]> git.gir.st - tmk_keyboard.git/blob - tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC408X/LPC407x_8x_177x_8x.h
git://git.gir.st / tmk_keyboard.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Squashed 'tmk_core/' changes from 7967731..b9e0ea0
[tmk_keyboard.git] / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_NXP / TARGET_LPC408X / LPC407x_8x_177x_8x.h
1 /****************************************************************************************************//**
2 * $Id$ LPC407x_8x_177x_8x.h 2012-04-25
3 *//**
4 * @file LPC407x_8x_177x_8x.h
5 *
6 * @brief CMSIS Cortex-M4 Cortex-M3 Peripheral Access Layer Header File for
7 * NXP LPC407x_8x_177x_8x.
8 * @version V0.7
9 * @date 20. June 2012
10 * @author NXP MCU SW Application Team
11 *
12 * Copyright(C) 2012, NXP Semiconductor
13 * All rights reserved.
14 *
15 ***********************************************************************
16 * Software that is described herein is for illustrative purposes only
17 * which provides customers with programming information regarding the
18 * products. This software is supplied "AS IS" without any warranties.
19 * NXP Semiconductors assumes no responsibility or liability for the
20 * use of the software, conveys no license or title under any patent,
21 * copyright, or mask work right to the product. NXP Semiconductors
22 * reserves the right to make changes in the software without
23 * notification. NXP Semiconductors also make no representation or
24 * warranty that such application will be suitable for the specified
25 * use without further testing or modification.
26 * Permission to use, copy, modify, and distribute this software and its
27 * documentation is hereby granted, under NXP Semiconductors'
28 * relevant copyright in the software, without fee, provided that it
29 * is used in conjunction with NXP Semiconductors microcontrollers. This
30 * copyright, permission, and disclaimer notice must appear in all copies of
31 * this code.
32 **********************************************************************/
33
34 #ifndef __LPC407x_8x_177x_8x_H__
35 #define __LPC407x_8x_177x_8x_H__
36
37 #if defined(__CORTEX_M4) && !defined(CORE_M4)
38 #define CORE_M4
39 #endif
40
41 // ##################
42 // Code Red - excluded extern "C" as unrequired
43 // ##################
44 #if 0
45 #ifdef __cplusplus
46 extern "C" {
47 #endif
48 #endif
49
50
51 /* ------------------------- Interrupt Number Definition ------------------------ */
52
53 typedef enum IRQn
54 {
55 /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
56 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
57 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
58 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
59 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
60 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
61 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
62 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
63 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
64 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
65 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
66
67 /****** LPC407x_8x_177x_8x Specific Interrupt Numbers *******************************************************/
68 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
69 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
70 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
71 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
72 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
73 UART0_IRQn = 5, /*!< UART0 Interrupt */
74 UART1_IRQn = 6, /*!< UART1 Interrupt */
75 UART2_IRQn = 7, /*!< UART2 Interrupt */
76 UART3_IRQn = 8, /*!< UART3 Interrupt */
77 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
78 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
79 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
80 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
81 Reserved0_IRQn = 13, /*!< Reserved */
82 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
83 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
84 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
85 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
86 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
87 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
88 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
89 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
90 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
91 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
92 USB_IRQn = 24, /*!< USB Interrupt */
93 CAN_IRQn = 25, /*!< CAN Interrupt */
94 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
95 I2S_IRQn = 27, /*!< I2S Interrupt */
96 ENET_IRQn = 28, /*!< Ethernet Interrupt */
97 MCI_IRQn = 29, /*!< SD/MMC card I/F Interrupt */
98 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
99 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
100 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
101 USBActivity_IRQn = 33, /*!< USB Activity interrupt */
102 CANActivity_IRQn = 34, /*!< CAN Activity interrupt */
103 UART4_IRQn = 35, /*!< UART4 Interrupt */
104 SSP2_IRQn = 36, /*!< SSP2 Interrupt */
105 LCD_IRQn = 37, /*!< LCD Interrupt */
106 GPIO_IRQn = 38, /*!< GPIO Interrupt */
107 PWM0_IRQn = 39, /*!< 39 PWM0 */
108 EEPROM_IRQn = 40, /*!< 40 EEPROM */
109 CMP0_IRQn = 41, /*!< 41 CMP0 */
110 CMP1_IRQn = 42 /*!< 42 CMP1 */
111 } IRQn_Type;
112
113 /* ================================================================================ */
114 /* ================ Processor and Core Peripheral Section ================ */
115 /* ================================================================================ */
116 #ifdef CORE_M4
117 /* ----------------Configuration of the cm4 Processor and Core Peripherals---------------- */
118 #define __CM4_REV 0x0000 /*!< Cortex-M4 Core Revision */
119 #define __MPU_PRESENT 1 /*!< MPU present or not */
120 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
121 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
122 #define __FPU_PRESENT 1 /*!< FPU present or not */
123
124
125 #include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
126 #else
127 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
128 #define __MPU_PRESENT 1 /*!< MPU present or not */
129 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
130 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
131
132
133 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
134
135 #endif
136
137 #include "system_LPC407x_8x_177x_8x.h" /*!< LPC408x_7x System */
138
139
140
141
142
143
144 /* ================================================================================ */
145 /* ================ Device Specific Peripheral Section ================ */
146 /* ================================================================================ */
147
148 #if defined ( __CC_ARM )
149 #pragma anon_unions
150 #endif
151
152 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
153 typedef struct /* Common Registers */
154 {
155 __I uint32_t IntStat;
156 __I uint32_t IntTCStat;
157 __O uint32_t IntTCClear;
158 __I uint32_t IntErrStat;
159 __O uint32_t IntErrClr;
160 __I uint32_t RawIntTCStat;
161 __I uint32_t RawIntErrStat;
162 __I uint32_t EnbldChns;
163 __IO uint32_t SoftBReq;
164 __IO uint32_t SoftSReq;
165 __IO uint32_t SoftLBReq;
166 __IO uint32_t SoftLSReq;
167 __IO uint32_t Config;
168 __IO uint32_t Sync;
169 } LPC_GPDMA_TypeDef;
170
171 typedef struct /* Channel Registers */
172 {
173 __IO uint32_t CSrcAddr;
174 __IO uint32_t CDestAddr;
175 __IO uint32_t CLLI;
176 __IO uint32_t CControl;
177 __IO uint32_t CConfig;
178 } LPC_GPDMACH_TypeDef;
179
180 /*------------- System Control (SC) ------------------------------------------*/
181 typedef struct
182 {
183 __IO uint32_t FLASHCFG; /*!< Offset: 0x000 (R/W) Flash Accelerator Configuration Register */
184 uint32_t RESERVED0[31];
185 __IO uint32_t PLL0CON; /*!< Offset: 0x080 (R/W) PLL0 Control Register */
186 __IO uint32_t PLL0CFG; /*!< Offset: 0x084 (R/W) PLL0 Configuration Register */
187 __I uint32_t PLL0STAT; /*!< Offset: 0x088 (R/ ) PLL0 Status Register */
188 __O uint32_t PLL0FEED; /*!< Offset: 0x08C ( /W) PLL0 Feed Register */
189 uint32_t RESERVED1[4];
190 __IO uint32_t PLL1CON; /*!< Offset: 0x0A0 (R/W) PLL1 Control Register */
191 __IO uint32_t PLL1CFG; /*!< Offset: 0x0A4 (R/W) PLL1 Configuration Register */
192 __I uint32_t PLL1STAT; /*!< Offset: 0x0A8 (R/ ) PLL1 Status Register */
193 __O uint32_t PLL1FEED; /*!< Offset: 0x0AC ( /W) PLL1 Feed Register */
194 uint32_t RESERVED2[4];
195 __IO uint32_t PCON; /*!< Offset: 0x0C0 (R/W) Power Control Register */
196 __IO uint32_t PCONP; /*!< Offset: 0x0C4 (R/W) Power Control for Peripherals Register */
197 __IO uint32_t PCONP1; /*!< Offset: 0x0C8 (R/W) Power Control for Peripherals Register */
198 uint32_t RESERVED3[13];
199 __IO uint32_t EMCCLKSEL; /*!< Offset: 0x100 (R/W) External Memory Controller Clock Selection Register */
200 __IO uint32_t CCLKSEL; /*!< Offset: 0x104 (R/W) CPU Clock Selection Register */
201 __IO uint32_t USBCLKSEL; /*!< Offset: 0x108 (R/W) USB Clock Selection Register */
202 __IO uint32_t CLKSRCSEL; /*!< Offset: 0x10C (R/W) Clock Source Select Register */
203 __IO uint32_t CANSLEEPCLR; /*!< Offset: 0x110 (R/W) CAN Sleep Clear Register */
204 __IO uint32_t CANWAKEFLAGS; /*!< Offset: 0x114 (R/W) CAN Wake-up Flags Register */
205 uint32_t RESERVED4[10];
206 __IO uint32_t EXTINT; /*!< Offset: 0x140 (R/W) External Interrupt Flag Register */
207 uint32_t RESERVED5[1];
208 __IO uint32_t EXTMODE; /*!< Offset: 0x148 (R/W) External Interrupt Mode Register */
209 __IO uint32_t EXTPOLAR; /*!< Offset: 0x14C (R/W) External Interrupt Polarity Register */
210 uint32_t RESERVED6[12];
211 __IO uint32_t RSID; /*!< Offset: 0x180 (R/W) Reset Source Identification Register */
212 uint32_t RESERVED7[7];
213 __IO uint32_t SCS; /*!< Offset: 0x1A0 (R/W) System Controls and Status Register */
214 __IO uint32_t IRCTRIM; /*!< Offset: 0x1A4 (R/W) Clock Dividers */
215 __IO uint32_t PCLKSEL; /*!< Offset: 0x1A8 (R/W) Peripheral Clock Selection Register */
216 uint32_t RESERVED8;
217 __IO uint32_t PBOOST; /*!< Offset: 0x1B0 (R/W) Power Boost control register */
218 __IO uint32_t SPIFICLKSEL;
219 __IO uint32_t LCD_CFG; /*!< Offset: 0x1B8 (R/W) LCD Configuration and clocking control Register */
220 uint32_t RESERVED10[1];
221 __IO uint32_t USBIntSt; /*!< Offset: 0x1C0 (R/W) USB Interrupt Status Register */
222 __IO uint32_t DMAREQSEL; /*!< Offset: 0x1C4 (R/W) DMA Request Select Register */
223 __IO uint32_t CLKOUTCFG; /*!< Offset: 0x1C8 (R/W) Clock Output Configuration Register */
224 __IO uint32_t RSTCON0; /*!< Offset: 0x1CC (R/W) RESET Control0 Register */
225 __IO uint32_t RSTCON1; /*!< Offset: 0x1D0 (R/W) RESET Control1 Register */
226 uint32_t RESERVED11[2];
227 __IO uint32_t EMCDLYCTL; /*!< Offset: 0x1DC (R/W) SDRAM programmable delays */
228 __IO uint32_t EMCCAL; /*!< Offset: 0x1E0 (R/W) Calibration of programmable delays */
229 } LPC_SC_TypeDef;
230 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
231 typedef struct
232 {
233 __IO uint32_t MAC1; /* MAC Registers */
234 __IO uint32_t MAC2;
235 __IO uint32_t IPGT;
236 __IO uint32_t IPGR;
237 __IO uint32_t CLRT;
238 __IO uint32_t MAXF;
239 __IO uint32_t SUPP;
240 __IO uint32_t TEST;
241 __IO uint32_t MCFG;
242 __IO uint32_t MCMD;
243 __IO uint32_t MADR;
244 __O uint32_t MWTD;
245 __I uint32_t MRDD;
246 __I uint32_t MIND;
247 uint32_t RESERVED0[2];
248 __IO uint32_t SA0;
249 __IO uint32_t SA1;
250 __IO uint32_t SA2;
251 uint32_t RESERVED1[45];
252 __IO uint32_t Command; /* Control Registers */
253 __I uint32_t Status;
254 __IO uint32_t RxDescriptor;
255 __IO uint32_t RxStatus;
256 __IO uint32_t RxDescriptorNumber;
257 __I uint32_t RxProduceIndex;
258 __IO uint32_t RxConsumeIndex;
259 __IO uint32_t TxDescriptor;
260 __IO uint32_t TxStatus;
261 __IO uint32_t TxDescriptorNumber;
262 __IO uint32_t TxProduceIndex;
263 __I uint32_t TxConsumeIndex;
264 uint32_t RESERVED2[10];
265 __I uint32_t TSV0;
266 __I uint32_t TSV1;
267 __I uint32_t RSV;
268 uint32_t RESERVED3[3];
269 __IO uint32_t FlowControlCounter;
270 __I uint32_t FlowControlStatus;
271 uint32_t RESERVED4[34];
272 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
273 __I uint32_t RxFilterWoLStatus;
274 __O uint32_t RxFilterWoLClear;
275 uint32_t RESERVED5;
276 __IO uint32_t HashFilterL;
277 __IO uint32_t HashFilterH;
278 uint32_t RESERVED6[882];
279 __I uint32_t IntStatus; /* Module Control Registers */
280 __IO uint32_t IntEnable;
281 __O uint32_t IntClear;
282 __O uint32_t IntSet;
283 uint32_t RESERVED7;
284 __IO uint32_t PowerDown;
285 uint32_t RESERVED8;
286 __IO uint32_t Module_ID;
287 } LPC_EMAC_TypeDef;
288
289 /*------------- LCD controller (LCD) -----------------------------------------*/
290 typedef struct
291 {
292 __IO uint32_t TIMH; /* LCD Registers */
293 __IO uint32_t TIMV;
294 __IO uint32_t POL;
295 __IO uint32_t LE;
296 __IO uint32_t UPBASE;
297 __IO uint32_t LPBASE;
298 __IO uint32_t CTRL;
299 __IO uint32_t INTMSK;
300 __I uint32_t INTRAW;
301 __I uint32_t INTSTAT;
302 __O uint32_t INTCLR;
303 __I uint32_t UPCURR;
304 __I uint32_t LPCURR;
305 uint32_t RESERVED0[115];
306 __IO uint32_t PAL[128];
307 uint32_t RESERVED1[256];
308 __IO uint32_t CRSR_IMG[256];
309 __IO uint32_t CRSR_CTRL;
310 __IO uint32_t CRSR_CFG;
311 __IO uint32_t CRSR_PAL0;
312 __IO uint32_t CRSR_PAL1;
313 __IO uint32_t CRSR_XY;
314 __IO uint32_t CRSR_CLIP;
315 uint32_t RESERVED2[2];
316 __IO uint32_t CRSR_INTMSK;
317 __O uint32_t CRSR_INTCLR;
318 __I uint32_t CRSR_INTRAW;
319 __I uint32_t CRSR_INTSTAT;
320 } LPC_LCD_TypeDef;
321
322 /*------------- Universal Serial Bus (USB) -----------------------------------*/
323 typedef struct
324 {
325 __I uint32_t Revision; /* USB Host Registers */
326 __IO uint32_t Control;
327 __IO uint32_t CommandStatus;
328 __IO uint32_t InterruptStatus;
329 __IO uint32_t InterruptEnable;
330 __IO uint32_t InterruptDisable;
331 __IO uint32_t HCCA;
332 __I uint32_t PeriodCurrentED;
333 __IO uint32_t ControlHeadED;
334 __IO uint32_t ControlCurrentED;
335 __IO uint32_t BulkHeadED;
336 __IO uint32_t BulkCurrentED;
337 __I uint32_t DoneHead;
338 __IO uint32_t FmInterval;
339 __I uint32_t FmRemaining;
340 __I uint32_t FmNumber;
341 __IO uint32_t PeriodicStart;
342 __IO uint32_t LSTreshold;
343 __IO uint32_t RhDescriptorA;
344 __IO uint32_t RhDescriptorB;
345 __IO uint32_t RhStatus;
346 __IO uint32_t RhPortStatus1;
347 __IO uint32_t RhPortStatus2;
348 uint32_t RESERVED0[40];
349 __I uint32_t Module_ID;
350
351 __I uint32_t IntSt; /* USB On-The-Go Registers */
352 __IO uint32_t IntEn;
353 __O uint32_t IntSet;
354 __O uint32_t IntClr;
355 __IO uint32_t StCtrl;
356 __IO uint32_t Tmr;
357 uint32_t RESERVED1[58];
358
359 __I uint32_t DevIntSt; /* USB Device Interrupt Registers */
360 __IO uint32_t DevIntEn;
361 __O uint32_t DevIntClr;
362 __O uint32_t DevIntSet;
363
364 __O uint32_t CmdCode; /* USB Device SIE Command Registers */
365 __I uint32_t CmdData;
366
367 __I uint32_t RxData; /* USB Device Transfer Registers */
368 __O uint32_t TxData;
369 __I uint32_t RxPLen;
370 __O uint32_t TxPLen;
371 __IO uint32_t Ctrl;
372 __O uint32_t DevIntPri;
373
374 __I uint32_t EpIntSt; /* USB Device Endpoint Interrupt Regs */
375 __IO uint32_t EpIntEn;
376 __O uint32_t EpIntClr;
377 __O uint32_t EpIntSet;
378 __O uint32_t EpIntPri;
379
380 __IO uint32_t ReEp; /* USB Device Endpoint Realization Reg*/
381 __O uint32_t EpInd;
382 __IO uint32_t MaxPSize;
383
384 __I uint32_t DMARSt; /* USB Device DMA Registers */
385 __O uint32_t DMARClr;
386 __O uint32_t DMARSet;
387 uint32_t RESERVED2[9];
388 __IO uint32_t UDCAH;
389 __I uint32_t EpDMASt;
390 __O uint32_t EpDMAEn;
391 __O uint32_t EpDMADis;
392 __I uint32_t DMAIntSt;
393 __IO uint32_t DMAIntEn;
394 uint32_t RESERVED3[2];
395 __I uint32_t EoTIntSt;
396 __O uint32_t EoTIntClr;
397 __O uint32_t EoTIntSet;
398 __I uint32_t NDDRIntSt;
399 __O uint32_t NDDRIntClr;
400 __O uint32_t NDDRIntSet;
401 __I uint32_t SysErrIntSt;
402 __O uint32_t SysErrIntClr;
403 __O uint32_t SysErrIntSet;
404 uint32_t RESERVED4[15];
405
406 union {
407 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
408 __O uint32_t I2C_TX;
409 };
410 __IO uint32_t I2C_STS;
411 __IO uint32_t I2C_CTL;
412 __IO uint32_t I2C_CLKHI;
413 __O uint32_t I2C_CLKLO;
414 uint32_t RESERVED5[824];
415
416 union {
417 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
418 __IO uint32_t OTGClkCtrl;
419 };
420 union {
421 __I uint32_t USBClkSt;
422 __I uint32_t OTGClkSt;
423 };
424 } LPC_USB_TypeDef;
425
426 /*------------- CRC Engine (CRC) -----------------------------------------*/
427 typedef struct
428 {
429 __IO uint32_t MODE;
430 __IO uint32_t SEED;
431 union {
432 __I uint32_t SUM;
433 struct {
434 __O uint32_t DATA;
435 } WR_DATA_DWORD;
436
437 struct {
438 __O uint16_t DATA;
439 uint16_t RESERVED;
440 }WR_DATA_WORD;
441
442 struct {
443 __O uint8_t DATA;
444 uint8_t RESERVED[3];
445 }WR_DATA_BYTE;
446 };
447 } LPC_CRC_TypeDef;
448 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
449 typedef struct
450 {
451 __IO uint32_t DIR;
452 uint32_t RESERVED0[3];
453 __IO uint32_t MASK;
454 __IO uint32_t PIN;
455 __IO uint32_t SET;
456 __O uint32_t CLR;
457 } LPC_GPIO_TypeDef;
458
459 typedef struct
460 {
461 __I uint32_t IntStatus;
462 __I uint32_t IO0IntStatR;
463 __I uint32_t IO0IntStatF;
464 __O uint32_t IO0IntClr;
465 __IO uint32_t IO0IntEnR;
466 __IO uint32_t IO0IntEnF;
467 uint32_t RESERVED0[3];
468 __I uint32_t IO2IntStatR;
469 __I uint32_t IO2IntStatF;
470 __O uint32_t IO2IntClr;
471 __IO uint32_t IO2IntEnR;
472 __IO uint32_t IO2IntEnF;
473 } LPC_GPIOINT_TypeDef;
474
475 /*------------- External Memory Controller (EMC) -----------------------------*/
476 typedef struct
477 {
478 __IO uint32_t Control;
479 __I uint32_t Status;
480 __IO uint32_t Config;
481 uint32_t RESERVED0[5];
482 __IO uint32_t DynamicControl;
483 __IO uint32_t DynamicRefresh;
484 __IO uint32_t DynamicReadConfig;
485 uint32_t RESERVED1[1];
486 __IO uint32_t DynamicRP;
487 __IO uint32_t DynamicRAS;
488 __IO uint32_t DynamicSREX;
489 __IO uint32_t DynamicAPR;
490 __IO uint32_t DynamicDAL;
491 __IO uint32_t DynamicWR;
492 __IO uint32_t DynamicRC;
493 __IO uint32_t DynamicRFC;
494 __IO uint32_t DynamicXSR;
495 __IO uint32_t DynamicRRD;
496 __IO uint32_t DynamicMRD;
497 uint32_t RESERVED2[9];
498 __IO uint32_t StaticExtendedWait;
499 uint32_t RESERVED3[31];
500 __IO uint32_t DynamicConfig0;
501 __IO uint32_t DynamicRasCas0;
502 uint32_t RESERVED4[6];
503 __IO uint32_t DynamicConfig1;
504 __IO uint32_t DynamicRasCas1;
505 uint32_t RESERVED5[6];
506 __IO uint32_t DynamicConfig2;
507 __IO uint32_t DynamicRasCas2;
508 uint32_t RESERVED6[6];
509 __IO uint32_t DynamicConfig3;
510 __IO uint32_t DynamicRasCas3;
511 uint32_t RESERVED7[38];
512 __IO uint32_t StaticConfig0;
513 __IO uint32_t StaticWaitWen0;
514 __IO uint32_t StaticWaitOen0;
515 __IO uint32_t StaticWaitRd0;
516 __IO uint32_t StaticWaitPage0;
517 __IO uint32_t StaticWaitWr0;
518 __IO uint32_t StaticWaitTurn0;
519 uint32_t RESERVED8[1];
520 __IO uint32_t StaticConfig1;
521 __IO uint32_t StaticWaitWen1;
522 __IO uint32_t StaticWaitOen1;
523 __IO uint32_t StaticWaitRd1;
524 __IO uint32_t StaticWaitPage1;
525 __IO uint32_t StaticWaitWr1;
526 __IO uint32_t StaticWaitTurn1;
527 uint32_t RESERVED9[1];
528 __IO uint32_t StaticConfig2;
529 __IO uint32_t StaticWaitWen2;
530 __IO uint32_t StaticWaitOen2;
531 __IO uint32_t StaticWaitRd2;
532 __IO uint32_t StaticWaitPage2;
533 __IO uint32_t StaticWaitWr2;
534 __IO uint32_t StaticWaitTurn2;
535 uint32_t RESERVED10[1];
536 __IO uint32_t StaticConfig3;
537 __IO uint32_t StaticWaitWen3;
538 __IO uint32_t StaticWaitOen3;
539 __IO uint32_t StaticWaitRd3;
540 __IO uint32_t StaticWaitPage3;
541 __IO uint32_t StaticWaitWr3;
542 __IO uint32_t StaticWaitTurn3;
543 } LPC_EMC_TypeDef;
544
545 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
546 typedef struct
547 {
548 __IO uint8_t MOD;
549 uint8_t RESERVED0[3];
550 __IO uint32_t TC;
551 __O uint8_t FEED;
552 uint8_t RESERVED1[3];
553 __I uint32_t TV;
554 uint32_t RESERVED2;
555 __IO uint32_t WARNINT;
556 __IO uint32_t WINDOW;
557 } LPC_WDT_TypeDef;
558
559 /*------------- Timer (TIM) --------------------------------------------------*/
560 typedef struct
561 {
562 __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */
563 __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */
564 __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */
565 __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */
566 __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */
567 __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */
568 __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */
569 __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */
570 __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */
571 __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */
572 __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */
573 __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */
574 __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */
575 uint32_t RESERVED0[2];
576 __IO uint32_t EMR; /*!< Offset: 0x03C External Match Register (R/W) */
577 uint32_t RESERVED1[12];
578 __IO uint32_t CTCR; /*!< Offset: 0x070 Count Control Register (R/W) */
579 } LPC_TIM_TypeDef;
580
581
582 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
583 typedef struct
584 {
585 __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */
586 __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */
587 __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */
588 __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */
589 __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */
590 __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */
591 __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */
592 __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */
593 __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */
594 __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */
595 __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */
596 __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */
597 __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */
598 __I uint32_t CR2; /*!< Offset: 0x034 Capture Register 2 (R/ ) */
599 __I uint32_t CR3; /*!< Offset: 0x038 Capture Register 3 (R/ ) */
600 uint32_t RESERVED0;
601 __IO uint32_t MR4; /*!< Offset: 0x040 Match Register 4 (R/W) */
602 __IO uint32_t MR5; /*!< Offset: 0x044 Match Register 5 (R/W) */
603 __IO uint32_t MR6; /*!< Offset: 0x048 Match Register 6 (R/W) */
604 __IO uint32_t PCR; /*!< Offset: 0x04C PWM Control Register (R/W) */
605 __IO uint32_t LER; /*!< Offset: 0x050 Load Enable Register (R/W) */
606 uint32_t RESERVED1[7];
607 __IO uint32_t CTCR; /*!< Offset: 0x070 Counter Control Register (R/W) */
608 } LPC_PWM_TypeDef;
609
610 /*------------- Universal Asynchronous Receiver Transmitter (UARTx) -----------*/
611 /* There are three types of UARTs on the chip:
612 (1) UART0,UART2, and UART3 are the standard UART.
613 (2) UART1 is the standard with modem capability.
614 (3) USART(UART4) is the sync/async UART with smart card capability.
615 More details can be found on the Users Manual. */
616
617 #if 0
618 typedef struct
619 {
620 union {
621 __I uint8_t RBR;
622 __O uint8_t THR;
623 __IO uint8_t DLL;
624 uint32_t RESERVED0;
625 };
626 union {
627 __IO uint8_t DLM;
628 __IO uint32_t IER;
629 };
630 union {
631 __I uint32_t IIR;
632 __O uint8_t FCR;
633 };
634 __IO uint8_t LCR;
635 uint8_t RESERVED1[7];
636 __I uint8_t LSR;
637 uint8_t RESERVED2[7];
638 __IO uint8_t SCR;
639 uint8_t RESERVED3[3];
640 __IO uint32_t ACR;
641 __IO uint8_t ICR;
642 uint8_t RESERVED4[3];
643 __IO uint8_t FDR;
644 uint8_t RESERVED5[7];
645 __IO uint8_t TER;
646 uint8_t RESERVED6[39];
647 __I uint8_t FIFOLVL;
648 } LPC_UART_TypeDef;
649 #else
650 typedef struct
651 {
652 union
653 {
654 __I uint8_t RBR;
655 __O uint8_t THR;
656 __IO uint8_t DLL;
657 uint32_t RESERVED0;
658 };
659 union
660 {
661 __IO uint8_t DLM;
662 __IO uint32_t IER;
663 };
664 union
665 {
666 __I uint32_t IIR;
667 __O uint8_t FCR;
668 };
669 __IO uint8_t LCR;
670 uint8_t RESERVED1[7];//Reserved
671 __I uint8_t LSR;
672 uint8_t RESERVED2[7];//Reserved
673 __IO uint8_t SCR;
674 uint8_t RESERVED3[3];//Reserved
675 __IO uint32_t ACR;
676 __IO uint8_t ICR;
677 uint8_t RESERVED4[3];//Reserved
678 __IO uint8_t FDR;
679 uint8_t RESERVED5[7];//Reserved
680 __IO uint8_t TER;
681 uint8_t RESERVED8[27];//Reserved
682 __IO uint8_t RS485CTRL;
683 uint8_t RESERVED9[3];//Reserved
684 __IO uint8_t ADRMATCH;
685 uint8_t RESERVED10[3];//Reserved
686 __IO uint8_t RS485DLY;
687 uint8_t RESERVED11[3];//Reserved
688 __I uint8_t FIFOLVL;
689 }LPC_UART_TypeDef;
690 #endif
691
692
693 typedef struct
694 {
695 union {
696 __I uint8_t RBR;
697 __O uint8_t THR;
698 __IO uint8_t DLL;
699 uint32_t RESERVED0;
700 };
701 union {
702 __IO uint8_t DLM;
703 __IO uint32_t IER;
704 };
705 union {
706 __I uint32_t IIR;
707 __O uint8_t FCR;
708 };
709 __IO uint8_t LCR;
710 uint8_t RESERVED1[3];
711 __IO uint8_t MCR;
712 uint8_t RESERVED2[3];
713 __I uint8_t LSR;
714 uint8_t RESERVED3[3];
715 __I uint8_t MSR;
716 uint8_t RESERVED4[3];
717 __IO uint8_t SCR;
718 uint8_t RESERVED5[3];
719 __IO uint32_t ACR;
720 uint32_t RESERVED6;
721 __IO uint32_t FDR;
722 uint32_t RESERVED7;
723 __IO uint8_t TER;
724 uint8_t RESERVED8[27];
725 __IO uint8_t RS485CTRL;
726 uint8_t RESERVED9[3];
727 __IO uint8_t ADRMATCH;
728 uint8_t RESERVED10[3];
729 __IO uint8_t RS485DLY;
730 uint8_t RESERVED11[3];
731 __I uint8_t FIFOLVL;
732 } LPC_UART1_TypeDef;
733
734 typedef struct
735 {
736 union {
737 __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */
738 __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */
739 __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */
740 };
741 union {
742 __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
743 __IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */
744 };
745 union {
746 __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */
747 __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */
748 };
749 __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */
750 __IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */
751 __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */
752 __I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */
753 __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */
754 __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
755 __IO uint32_t ICR; /*!< Offset: 0x024 irDA Control Register (R/W) */
756 __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */
757 __IO uint32_t OSR; /*!< Offset: 0x02C Over sampling Register (R/W) */
758 __O uint32_t POP; /*!< Offset: 0x030 NHP Pop Register (W) */
759 __IO uint32_t MODE; /*!< Offset: 0x034 NHP Mode selection Register (W) */
760 uint32_t RESERVED0[2];
761 __IO uint32_t HDEN; /*!< Offset: 0x040 Half duplex Enable Register (R/W) */
762 uint32_t RESERVED1;
763 __IO uint32_t SCI_CTRL; /*!< Offset: 0x048 Smart card Interface Control Register (R/W) */
764 __IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */
765 __IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */
766 __IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */
767 __IO uint32_t SYNCCTRL; /*!< Offset: 0x058 Synchronous Mode Control Register (R/W ) */
768 __IO uint32_t TER; /*!< Offset: 0x05C Transmit Enable Register (R/W) */
769 uint32_t RESERVED2[989];
770 __I uint32_t CFG; /*!< Offset: 0xFD4 Configuration Register (R) */
771 __O uint32_t INTCE; /*!< Offset: 0xFD8 Interrupt Clear Enable Register (W) */
772 __O uint32_t INTSE; /*!< Offset: 0xFDC Interrupt Set Enable Register (W) */
773 __I uint32_t INTS; /*!< Offset: 0xFE0 Interrupt Status Register (R) */
774 __I uint32_t INTE; /*!< Offset: 0xFE4 Interrupt Enable Register (R) */
775 __O uint32_t INTCS; /*!< Offset: 0xFE8 Interrupt Clear Status Register (W) */
776 __O uint32_t INTSS; /*!< Offset: 0xFEC Interrupt Set Status Register (W) */
777 uint32_t RESERVED3[3];
778 __I uint32_t MID; /*!< Offset: 0xFFC Module Identification Register (R) */
779 } LPC_UART4_TypeDef;
780 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
781 typedef struct
782 {
783 __IO uint32_t CONSET; /*!< Offset: 0x000 I2C Control Set Register (R/W) */
784 __I uint32_t STAT; /*!< Offset: 0x004 I2C Status Register (R/ ) */
785 __IO uint32_t DAT; /*!< Offset: 0x008 I2C Data Register (R/W) */
786 __IO uint32_t ADR0; /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */
787 __IO uint32_t SCLH; /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */
788 __IO uint32_t SCLL; /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */
789 __O uint32_t CONCLR; /*!< Offset: 0x018 I2C Control Clear Register ( /W) */
790 __IO uint32_t MMCTRL; /*!< Offset: 0x01C Monitor mode control register (R/W) */
791 __IO uint32_t ADR1; /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */
792 __IO uint32_t ADR2; /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */
793 __IO uint32_t ADR3; /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */
794 __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C Data buffer register ( /W) */
795 __IO uint32_t MASK0; /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */
796 __IO uint32_t MASK1; /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */
797 __IO uint32_t MASK2; /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */
798 __IO uint32_t MASK3; /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */
799 } LPC_I2C_TypeDef;
800
801 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
802 typedef struct
803 {
804 __IO uint8_t ILR;
805 uint8_t RESERVED0[7];
806 __IO uint8_t CCR;
807 uint8_t RESERVED1[3];
808 __IO uint8_t CIIR;
809 uint8_t RESERVED2[3];
810 __IO uint8_t AMR;
811 uint8_t RESERVED3[3];
812 __I uint32_t CTIME0;
813 __I uint32_t CTIME1;
814 __I uint32_t CTIME2;
815 __IO uint8_t SEC;
816 uint8_t RESERVED4[3];
817 __IO uint8_t MIN;
818 uint8_t RESERVED5[3];
819 __IO uint8_t HOUR;
820 uint8_t RESERVED6[3];
821 __IO uint8_t DOM;
822 uint8_t RESERVED7[3];
823 __IO uint8_t DOW;
824 uint8_t RESERVED8[3];
825 __IO uint16_t DOY;
826 uint16_t RESERVED9;
827 __IO uint8_t MONTH;
828 uint8_t RESERVED10[3];
829 __IO uint16_t YEAR;
830 uint16_t RESERVED11;
831 __IO uint32_t CALIBRATION;
832 __IO uint32_t GPREG0;
833 __IO uint32_t GPREG1;
834 __IO uint32_t GPREG2;
835 __IO uint32_t GPREG3;
836 __IO uint32_t GPREG4;
837 __IO uint8_t RTC_AUXEN;
838 uint8_t RESERVED12[3];
839 __IO uint8_t RTC_AUX;
840 uint8_t RESERVED13[3];
841 __IO uint8_t ALSEC;
842 uint8_t RESERVED14[3];
843 __IO uint8_t ALMIN;
844 uint8_t RESERVED15[3];
845 __IO uint8_t ALHOUR;
846 uint8_t RESERVED16[3];
847 __IO uint8_t ALDOM;
848 uint8_t RESERVED17[3];
849 __IO uint8_t ALDOW;
850 uint8_t RESERVED18[3];
851 __IO uint16_t ALDOY;
852 uint16_t RESERVED19;
853 __IO uint8_t ALMON;
854 uint8_t RESERVED20[3];
855 __IO uint16_t ALYEAR;
856 uint16_t RESERVED21;
857 __IO uint32_t ERSTATUS;
858 __IO uint32_t ERCONTROL;
859 __IO uint32_t ERCOUNTERS;
860 uint32_t RESERVED22;
861 __IO uint32_t ERFIRSTSTAMP0;
862 __IO uint32_t ERFIRSTSTAMP1;
863 __IO uint32_t ERFIRSTSTAMP2;
864 uint32_t RESERVED23;
865 __IO uint32_t ERLASTSTAMP0;
866 __IO uint32_t ERLASTSTAMP1;
867 __IO uint32_t ERLASTSTAMP2;
868 } LPC_RTC_TypeDef;
869
870
871
872 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
873 typedef struct
874 {
875 __IO uint32_t P0_0; /* 0x000 */
876 __IO uint32_t P0_1;
877 __IO uint32_t P0_2;
878 __IO uint32_t P0_3;
879 __IO uint32_t P0_4;
880 __IO uint32_t P0_5;
881 __IO uint32_t P0_6;
882 __IO uint32_t P0_7;
883
884 __IO uint32_t P0_8; /* 0x020 */
885 __IO uint32_t P0_9;
886 __IO uint32_t P0_10;
887 __IO uint32_t P0_11;
888 __IO uint32_t P0_12;
889 __IO uint32_t P0_13;
890 __IO uint32_t P0_14;
891 __IO uint32_t P0_15;
892
893 __IO uint32_t P0_16; /* 0x040 */
894 __IO uint32_t P0_17;
895 __IO uint32_t P0_18;
896 __IO uint32_t P0_19;
897 __IO uint32_t P0_20;
898 __IO uint32_t P0_21;
899 __IO uint32_t P0_22;
900 __IO uint32_t P0_23;
901
902 __IO uint32_t P0_24; /* 0x060 */
903 __IO uint32_t P0_25;
904 __IO uint32_t P0_26;
905 __IO uint32_t P0_27;
906 __IO uint32_t P0_28;
907 __IO uint32_t P0_29;
908 __IO uint32_t P0_30;
909 __IO uint32_t P0_31;
910
911 __IO uint32_t P1_0; /* 0x080 */
912 __IO uint32_t P1_1;
913 __IO uint32_t P1_2;
914 __IO uint32_t P1_3;
915 __IO uint32_t P1_4;
916 __IO uint32_t P1_5;
917 __IO uint32_t P1_6;
918 __IO uint32_t P1_7;
919
920 __IO uint32_t P1_8; /* 0x0A0 */
921 __IO uint32_t P1_9;
922 __IO uint32_t P1_10;
923 __IO uint32_t P1_11;
924 __IO uint32_t P1_12;
925 __IO uint32_t P1_13;
926 __IO uint32_t P1_14;
927 __IO uint32_t P1_15;
928
929 __IO uint32_t P1_16; /* 0x0C0 */
930 __IO uint32_t P1_17;
931 __IO uint32_t P1_18;
932 __IO uint32_t P1_19;
933 __IO uint32_t P1_20;
934 __IO uint32_t P1_21;
935 __IO uint32_t P1_22;
936 __IO uint32_t P1_23;
937
938 __IO uint32_t P1_24; /* 0x0E0 */
939 __IO uint32_t P1_25;
940 __IO uint32_t P1_26;
941 __IO uint32_t P1_27;
942 __IO uint32_t P1_28;
943 __IO uint32_t P1_29;
944 __IO uint32_t P1_30;
945 __IO uint32_t P1_31;
946
947 __IO uint32_t P2_0; /* 0x100 */
948 __IO uint32_t P2_1;
949 __IO uint32_t P2_2;
950 __IO uint32_t P2_3;
951 __IO uint32_t P2_4;
952 __IO uint32_t P2_5;
953 __IO uint32_t P2_6;
954 __IO uint32_t P2_7;
955
956 __IO uint32_t P2_8; /* 0x120 */
957 __IO uint32_t P2_9;
958 __IO uint32_t P2_10;
959 __IO uint32_t P2_11;
960 __IO uint32_t P2_12;
961 __IO uint32_t P2_13;
962 __IO uint32_t P2_14;
963 __IO uint32_t P2_15;
964
965 __IO uint32_t P2_16; /* 0x140 */
966 __IO uint32_t P2_17;
967 __IO uint32_t P2_18;
968 __IO uint32_t P2_19;
969 __IO uint32_t P2_20;
970 __IO uint32_t P2_21;
971 __IO uint32_t P2_22;
972 __IO uint32_t P2_23;
973
974 __IO uint32_t P2_24; /* 0x160 */
975 __IO uint32_t P2_25;
976 __IO uint32_t P2_26;
977 __IO uint32_t P2_27;
978 __IO uint32_t P2_28;
979 __IO uint32_t P2_29;
980 __IO uint32_t P2_30;
981 __IO uint32_t P2_31;
982
983 __IO uint32_t P3_0; /* 0x180 */
984 __IO uint32_t P3_1;
985 __IO uint32_t P3_2;
986 __IO uint32_t P3_3;
987 __IO uint32_t P3_4;
988 __IO uint32_t P3_5;
989 __IO uint32_t P3_6;
990 __IO uint32_t P3_7;
991
992 __IO uint32_t P3_8; /* 0x1A0 */
993 __IO uint32_t P3_9;
994 __IO uint32_t P3_10;
995 __IO uint32_t P3_11;
996 __IO uint32_t P3_12;
997 __IO uint32_t P3_13;
998 __IO uint32_t P3_14;
999 __IO uint32_t P3_15;
1000
1001 __IO uint32_t P3_16; /* 0x1C0 */
1002 __IO uint32_t P3_17;
1003 __IO uint32_t P3_18;
1004 __IO uint32_t P3_19;
1005 __IO uint32_t P3_20;
1006 __IO uint32_t P3_21;
1007 __IO uint32_t P3_22;
1008 __IO uint32_t P3_23;
1009
1010 __IO uint32_t P3_24; /* 0x1E0 */
1011 __IO uint32_t P3_25;
1012 __IO uint32_t P3_26;
1013 __IO uint32_t P3_27;
1014 __IO uint32_t P3_28;
1015 __IO uint32_t P3_29;
1016 __IO uint32_t P3_30;
1017 __IO uint32_t P3_31;
1018
1019 __IO uint32_t P4_0; /* 0x200 */
1020 __IO uint32_t P4_1;
1021 __IO uint32_t P4_2;
1022 __IO uint32_t P4_3;
1023 __IO uint32_t P4_4;
1024 __IO uint32_t P4_5;
1025 __IO uint32_t P4_6;
1026 __IO uint32_t P4_7;
1027
1028 __IO uint32_t P4_8; /* 0x220 */
1029 __IO uint32_t P4_9;
1030 __IO uint32_t P4_10;
1031 __IO uint32_t P4_11;
1032 __IO uint32_t P4_12;
1033 __IO uint32_t P4_13;
1034 __IO uint32_t P4_14;
1035 __IO uint32_t P4_15;
1036
1037 __IO uint32_t P4_16; /* 0x240 */
1038 __IO uint32_t P4_17;
1039 __IO uint32_t P4_18;
1040 __IO uint32_t P4_19;
1041 __IO uint32_t P4_20;
1042 __IO uint32_t P4_21;
1043 __IO uint32_t P4_22;
1044 __IO uint32_t P4_23;
1045
1046 __IO uint32_t P4_24; /* 0x260 */
1047 __IO uint32_t P4_25;
1048 __IO uint32_t P4_26;
1049 __IO uint32_t P4_27;
1050 __IO uint32_t P4_28;
1051 __IO uint32_t P4_29;
1052 __IO uint32_t P4_30;
1053 __IO uint32_t P4_31;
1054
1055 __IO uint32_t P5_0; /* 0x280 */
1056 __IO uint32_t P5_1;
1057 __IO uint32_t P5_2;
1058 __IO uint32_t P5_3;
1059 __IO uint32_t P5_4; /* 0x290 */
1060 } LPC_IOCON_TypeDef;
1061
1062
1063
1064
1065
1066
1067 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
1068 typedef struct
1069 {
1070 __IO uint32_t CR0; /*!< Offset: 0x000 Control Register 0 (R/W) */
1071 __IO uint32_t CR1; /*!< Offset: 0x004 Control Register 1 (R/W) */
1072 __IO uint32_t DR; /*!< Offset: 0x008 Data Register (R/W) */
1073 __I uint32_t SR; /*!< Offset: 0x00C Status Registe (R/ ) */
1074 __IO uint32_t CPSR; /*!< Offset: 0x010 Clock Prescale Register (R/W) */
1075 __IO uint32_t IMSC; /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */
1076 __IO uint32_t RIS; /*!< Offset: 0x018 Raw Interrupt Status Register (R/W) */
1077 __IO uint32_t MIS; /*!< Offset: 0x01C Masked Interrupt Status Register (R/W) */
1078 __IO uint32_t ICR; /*!< Offset: 0x020 SSPICR Interrupt Clear Register (R/W) */
1079 __IO uint32_t DMACR;
1080 } LPC_SSP_TypeDef;
1081
1082 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
1083 typedef struct
1084 {
1085 __IO uint32_t CR; /*!< Offset: 0x000 A/D Control Register (R/W) */
1086 __IO uint32_t GDR; /*!< Offset: 0x004 A/D Global Data Register (R/W) */
1087 uint32_t RESERVED0;
1088 __IO uint32_t INTEN; /*!< Offset: 0x00C A/D Interrupt Enable Register (R/W) */
1089 __IO uint32_t DR[8]; /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */
1090 __I uint32_t STAT; /*!< Offset: 0x030 A/D Status Register (R/ ) */
1091 __IO uint32_t ADTRM;
1092 } LPC_ADC_TypeDef;
1093
1094 /*------------- Controller Area Network (CAN) --------------------------------*/
1095 typedef struct
1096 {
1097 __IO uint32_t mask[512]; /* ID Masks */
1098 } LPC_CANAF_RAM_TypeDef;
1099
1100 typedef struct /* Acceptance Filter Registers */
1101 {
1102 ///Offset: 0x00000000 - Acceptance Filter Register
1103 __IO uint32_t AFMR;
1104
1105 ///Offset: 0x00000004 - Standard Frame Individual Start Address Register
1106 __IO uint32_t SFF_sa;
1107
1108 ///Offset: 0x00000008 - Standard Frame Group Start Address Register
1109 __IO uint32_t SFF_GRP_sa;
1110
1111 ///Offset: 0x0000000C - Extended Frame Start Address Register
1112 __IO uint32_t EFF_sa;
1113
1114 ///Offset: 0x00000010 - Extended Frame Group Start Address Register
1115 __IO uint32_t EFF_GRP_sa;
1116
1117 ///Offset: 0x00000014 - End of AF Tables register
1118 __IO uint32_t ENDofTable;
1119
1120 ///Offset: 0x00000018 - LUT Error Address register
1121 __I uint32_t LUTerrAd;
1122
1123 ///Offset: 0x0000001C - LUT Error Register
1124 __I uint32_t LUTerr;
1125
1126 ///Offset: 0x00000020 - CAN Central Transmit Status Register
1127 __IO uint32_t FCANIE;
1128
1129 ///Offset: 0x00000024 - FullCAN Interrupt and Capture registers 0
1130 __IO uint32_t FCANIC0;
1131
1132 ///Offset: 0x00000028 - FullCAN Interrupt and Capture registers 1
1133 __IO uint32_t FCANIC1;
1134 } LPC_CANAF_TypeDef;
1135
1136 typedef struct /* Central Registers */
1137 {
1138 __I uint32_t TxSR;
1139 __I uint32_t RxSR;
1140 __I uint32_t MSR;
1141 } LPC_CANCR_TypeDef;
1142
1143 typedef struct /* Controller Registers */
1144 {
1145 ///Offset: 0x00000000 - Controls the operating mode of the CAN Controller
1146 __IO uint32_t MOD;
1147
1148 ///Offset: 0x00000004 - Command bits that affect the state
1149 __O uint32_t CMR;
1150
1151 ///Offset: 0x00000008 - Global Controller Status and Error Counters
1152 __IO uint32_t GSR;
1153
1154 ///Offset: 0x0000000C - Interrupt status, Arbitration Lost Capture, Error Code Capture
1155 __I uint32_t ICR;
1156
1157 ///Offset: 0x00000010 - Interrupt Enable Register
1158 __IO uint32_t IER;
1159
1160 ///Offset: 0x00000014 - Bus Timing Register
1161 __IO uint32_t BTR;
1162
1163 ///Offset: 0x00000018 - Error Warning Limit
1164 __IO uint32_t EWL;
1165
1166 ///Offset: 0x0000001C - Status Register
1167 __I uint32_t SR;
1168
1169 ///Offset: 0x00000020 - Receive frame status
1170 __IO uint32_t RFS;
1171
1172 ///Offset: 0x00000024 - Received Identifier
1173 __IO uint32_t RID;
1174
1175 ///Offset: 0x00000028 - Received data bytes 1-4
1176 __IO uint32_t RDA;
1177
1178 ///Offset: 0x0000002C - Received data bytes 5-8
1179 __IO uint32_t RDB;
1180
1181 ///Offset: 0x00000030 - Transmit frame info (Tx Buffer 1)
1182 __IO uint32_t TFI1;
1183
1184 ///Offset: 0x00000034 - Transmit Identifier (Tx Buffer 1)
1185 __IO uint32_t TID1;
1186
1187 ///Offset: 0x00000038 - Transmit data bytes 1-4 (Tx Buffer 1)
1188 __IO uint32_t TDA1;
1189
1190 ///Offset: 0x0000003C - Transmit data bytes 5-8 (Tx Buffer 1)
1191 __IO uint32_t TDB1;
1192
1193 ///Offset: 0x00000040 - Transmit frame info (Tx Buffer 2)
1194 __IO uint32_t TFI2;
1195
1196 ///Offset: 0x00000044 - Transmit Identifier (Tx Buffer 2)
1197 __IO uint32_t TID2;
1198
1199 ///Offset: 0x00000048 - Transmit data bytes 1-4 (Tx Buffer 2)
1200 __IO uint32_t TDA2;
1201
1202 ///Offset: 0x0000004C - Transmit data bytes 5-8 (Tx Buffer 2)
1203 __IO uint32_t TDB2;
1204
1205 ///Offset: 0x00000050 - Transmit frame info (Tx Buffer 3)
1206 __IO uint32_t TFI3;
1207
1208 ///Offset: 0x00000054 - Transmit Identifier (Tx Buffer 3)
1209 __IO uint32_t TID3;
1210
1211 ///Offset: 0x00000058 - Transmit data bytes 1-4 (Tx Buffer 3)
1212 __IO uint32_t TDA3;
1213
1214 ///Offset: 0x0000005C - Transmit data bytes 5-8 (Tx Buffer 3)
1215 __IO uint32_t TDB3;
1216 } LPC_CAN_TypeDef;
1217
1218 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
1219 typedef struct
1220 {
1221 __IO uint32_t CR;
1222 __IO uint32_t CTRL;
1223 __IO uint32_t CNTVAL;
1224 } LPC_DAC_TypeDef;
1225
1226
1227 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
1228 typedef struct
1229 {
1230 __IO uint32_t DAO;
1231 __IO uint32_t DAI;
1232 __O uint32_t TXFIFO;
1233 __I uint32_t RXFIFO;
1234 __I uint32_t STATE;
1235 __IO uint32_t DMA1;
1236 __IO uint32_t DMA2;
1237 __IO uint32_t IRQ;
1238 __IO uint32_t TXRATE;
1239 __IO uint32_t RXRATE;
1240 __IO uint32_t TXBITRATE;
1241 __IO uint32_t RXBITRATE;
1242 __IO uint32_t TXMODE;
1243 __IO uint32_t RXMODE;
1244 } LPC_I2S_TypeDef;
1245
1246
1247
1248
1249
1250
1251 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
1252 typedef struct
1253 {
1254 __I uint32_t CON;
1255 __O uint32_t CON_SET;
1256 __O uint32_t CON_CLR;
1257 __I uint32_t CAPCON;
1258 __O uint32_t CAPCON_SET;
1259 __O uint32_t CAPCON_CLR;
1260 __IO uint32_t TC0;
1261 __IO uint32_t TC1;
1262 __IO uint32_t TC2;
1263 __IO uint32_t LIM0;
1264 __IO uint32_t LIM1;
1265 __IO uint32_t LIM2;
1266 __IO uint32_t MAT0;
1267 __IO uint32_t MAT1;
1268 __IO uint32_t MAT2;
1269 __IO uint32_t DT;
1270 __IO uint32_t CP;
1271 __IO uint32_t CAP0;
1272 __IO uint32_t CAP1;
1273 __IO uint32_t CAP2;
1274 __I uint32_t INTEN;
1275 __O uint32_t INTEN_SET;
1276 __O uint32_t INTEN_CLR;
1277 __I uint32_t CNTCON;
1278 __O uint32_t CNTCON_SET;
1279 __O uint32_t CNTCON_CLR;
1280 __I uint32_t INTF;
1281 __O uint32_t INTF_SET;
1282 __O uint32_t INTF_CLR;
1283 __O uint32_t CAP_CLR;
1284 } LPC_MCPWM_TypeDef;
1285
1286 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
1287 typedef struct
1288 {
1289 __O uint32_t CON;
1290 __I uint32_t STAT;
1291 __IO uint32_t CONF;
1292 __I uint32_t POS;
1293 __IO uint32_t MAXPOS;
1294 __IO uint32_t CMPOS0;
1295 __IO uint32_t CMPOS1;
1296 __IO uint32_t CMPOS2;
1297 __I uint32_t INXCNT;
1298 __IO uint32_t INXCMP0;
1299 __IO uint32_t LOAD;
1300 __I uint32_t TIME;
1301 __I uint32_t VEL;
1302 __I uint32_t CAP;
1303 __IO uint32_t VELCOMP;
1304 __IO uint32_t FILTERPHA;
1305 __IO uint32_t FILTERPHB;
1306 __IO uint32_t FILTERINX;
1307 __IO uint32_t WINDOW;
1308 __IO uint32_t INXCMP1;
1309 __IO uint32_t INXCMP2;
1310 uint32_t RESERVED0[993];
1311 __O uint32_t IEC;
1312 __O uint32_t IES;
1313 __I uint32_t INTSTAT;
1314 __I uint32_t IE;
1315 __O uint32_t CLR;
1316 __O uint32_t SET;
1317 } LPC_QEI_TypeDef;
1318
1319 /*------------- SD/MMC card Interface (MCI)-----------------------------------*/
1320 typedef struct
1321 {
1322 __IO uint32_t POWER;
1323 __IO uint32_t CLOCK;
1324 __IO uint32_t ARGUMENT;
1325 __IO uint32_t COMMAND;
1326 __I uint32_t RESP_CMD;
1327 __I uint32_t RESP0;
1328 __I uint32_t RESP1;
1329 __I uint32_t RESP2;
1330 __I uint32_t RESP3;
1331 __IO uint32_t DATATMR;
1332 __IO uint32_t DATALEN;
1333 __IO uint32_t DATACTRL;
1334 __I uint32_t DATACNT;
1335 __I uint32_t STATUS;
1336 __O uint32_t CLEAR;
1337 __IO uint32_t MASK0;
1338 uint32_t RESERVED0[2];
1339 __I uint32_t FIFOCNT;
1340 uint32_t RESERVED1[13];
1341 __IO uint32_t FIFO[16];
1342 } LPC_MCI_TypeDef;
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353 /*------------- EEPROM Controller (EEPROM) -----------------------------------*/
1354 typedef struct
1355 {
1356 __IO uint32_t CMD; /* 0x0080 */
1357 __IO uint32_t ADDR;
1358 __IO uint32_t WDATA;
1359 __IO uint32_t RDATA;
1360 __IO uint32_t WSTATE; /* 0x0090 */
1361 __IO uint32_t CLKDIV;
1362 __IO uint32_t PWRDWN; /* 0x0098 */
1363 uint32_t RESERVED0[975];
1364 __IO uint32_t INT_CLR_ENABLE; /* 0x0FD8 */
1365 __IO uint32_t INT_SET_ENABLE;
1366 __IO uint32_t INT_STATUS; /* 0x0FE0 */
1367 __IO uint32_t INT_ENABLE;
1368 __IO uint32_t INT_CLR_STATUS;
1369 __IO uint32_t INT_SET_STATUS;
1370 } LPC_EEPROM_TypeDef;
1371
1372
1373 /*------------- COMPARATOR ----------------------------------------------------*/
1374
1375 typedef struct { /*!< (@ 0x40020000) COMPARATOR Structure */
1376 __IO uint32_t CTRL; /*!< (@ 0x40020000) Comparator block control register */
1377 __IO uint32_t CTRL0; /*!< (@ 0x40020004) Comparator 0 control register */
1378 __IO uint32_t CTRL1; /*!< (@ 0x40020008) Comparator 1 control register */
1379 } LPC_COMPARATOR_Type;
1380
1381
1382 #if defined ( __CC_ARM )
1383 #pragma no_anon_unions
1384 #endif
1385
1386 /******************************************************************************/
1387 /* Peripheral memory map */
1388 /******************************************************************************/
1389 /* Base addresses */
1390 #define LPC_FLASH_BASE (0x00000000UL)
1391 #define LPC_RAM_BASE (0x10000000UL)
1392 #define LPC_PERI_RAM_BASE (0x20000000UL)
1393 #define LPC_APB0_BASE (0x40000000UL)
1394 #define LPC_APB1_BASE (0x40080000UL)
1395 #define LPC_AHBRAM1_BASE (0x20004000UL)
1396 #define LPC_AHB_BASE (0x20080000UL)
1397 #define LPC_CM3_BASE (0xE0000000UL)
1398
1399 /* APB0 peripherals */
1400 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
1401 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
1402 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
1403 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
1404 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
1405 #define LPC_PWM0_BASE (LPC_APB0_BASE + 0x14000)
1406 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
1407 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
1408 #define LPC_COMPARATOR_BASE (LPC_APB0_BASE + 0x20000)
1409 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
1410 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
1411 #define LPC_IOCON_BASE (LPC_APB0_BASE + 0x2C000)
1412 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
1413 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
1414 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
1415 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
1416 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
1417 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
1418 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
1419 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
1420
1421 /* APB1 peripherals */
1422 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
1423 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
1424 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
1425 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
1426 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
1427 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
1428 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
1429 #define LPC_UART4_BASE (LPC_APB1_BASE + 0x24000)
1430 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
1431 #define LPC_SSP2_BASE (LPC_APB1_BASE + 0x2C000)
1432 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
1433 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
1434 #define LPC_MCI_BASE (LPC_APB1_BASE + 0x40000)
1435 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
1436
1437 /* AHB peripherals */
1438 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x00000)
1439 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x00100)
1440 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x00120)
1441 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x00140)
1442 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x00160)
1443 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x00180)
1444 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x001A0)
1445 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x001C0)
1446 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x001E0)
1447 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x04000)
1448 #define LPC_LCD_BASE (LPC_AHB_BASE + 0x08000)
1449 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
1450 #define LPC_CRC_BASE (LPC_AHB_BASE + 0x10000)
1451 #define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x18000)
1452 #define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x18020)
1453 #define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x18040)
1454 #define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x18060)
1455 #define LPC_GPIO4_BASE (LPC_AHB_BASE + 0x18080)
1456 #define LPC_GPIO5_BASE (LPC_AHB_BASE + 0x180A0)
1457 #define LPC_EMC_BASE (LPC_AHB_BASE + 0x1C000)
1458
1459 #define LPC_EEPROM_BASE (LPC_FLASH_BASE+ 0x200080)
1460
1461
1462 /******************************************************************************/
1463 /* Peripheral declaration */
1464 /******************************************************************************/
1465 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
1466 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
1467 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
1468 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
1469 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
1470 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
1471 #define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE )
1472 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
1473 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
1474 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
1475 #define LPC_UART4 ((LPC_UART4_TypeDef *) LPC_UART4_BASE )
1476 #define LPC_PWM0 ((LPC_PWM_TypeDef *) LPC_PWM0_BASE )
1477 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
1478 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
1479 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
1480 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
1481 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
1482 #define LPC_COMPARATOR ((LPC_COMPARATOR_Type *) LPC_COMPARATOR_BASE)
1483 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
1484 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
1485 #define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
1486 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
1487 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
1488 #define LPC_SSP2 ((LPC_SSP_TypeDef *) LPC_SSP2_BASE )
1489 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
1490 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
1491 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
1492 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
1493 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
1494 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
1495 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
1496 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
1497 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
1498 #define LPC_MCI ((LPC_MCI_TypeDef *) LPC_MCI_BASE )
1499 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
1500 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
1501 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
1502 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
1503 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
1504 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
1505 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
1506 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
1507 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
1508 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
1509 #define LPC_LCD ((LPC_LCD_TypeDef *) LPC_LCD_BASE )
1510 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
1511 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
1512 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
1513 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
1514 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
1515 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
1516 #define LPC_GPIO5 ((LPC_GPIO_TypeDef *) LPC_GPIO5_BASE )
1517 #define LPC_EMC ((LPC_EMC_TypeDef *) LPC_EMC_BASE )
1518 #define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE )
1519 #define LPC_EEPROM ((LPC_EEPROM_TypeDef *) LPC_EEPROM_BASE )
1520
1521
1522
1523 #endif // __LPC407x_8x_177x_8x_H__
custom keymap for my minivan; forked from http://github.com/evangs/tmk_keyboard
Imprint / Impressum