1 ;/*****************************************************************************
2 ; * @file: startup_LPC8xx.s
3 ; * @purpose: CMSIS Cortex-M0+ Core Device Startup File
4 ; * for the NXP LPC8xx Device Series
6 ; * @date: 16. Aug. 2012
7 ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
9 ; * Copyright (C) 2012 ARM Limited. All rights reserved.
10 ; * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
11 ; * processor based microcontrollers. This file can be freely distributed
12 ; * within development tools that are supporting such ARM based processors.
14 ; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
15 ; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
16 ; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
17 ; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
18 ; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
20 ; *****************************************************************************/
23 ; <h> Stack Configuration
24 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
27 Stack_Size EQU 0x00000200
29 AREA STACK, NOINIT, READWRITE, ALIGN=3
32 Stack_Mem SPACE Stack_Size
33 __initial_sp EQU 0x10000400
36 ; <h> Heap Configuration
37 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
40 Heap_Size EQU 0x00000000
42 AREA HEAP, NOINIT, READWRITE, ALIGN=3
47 Heap_Mem SPACE Heap_Size
54 ; Vector Table Mapped to Address 0 at Reset
56 AREA RESET, DATA, READONLY
59 __Vectors DCD __initial_sp ; Top of Stack
60 DCD Reset_Handler ; Reset Handler
61 DCD NMI_Handler ; NMI Handler
62 DCD HardFault_Handler ; Hard Fault Handler
70 DCD SVC_Handler ; SVCall Handler
73 DCD PendSV_Handler ; PendSV Handler
74 DCD SysTick_Handler ; SysTick Handler
77 DCD SPI0_IRQHandler ; SPI0 controller
78 DCD SPI1_IRQHandler ; SPI1 controller
80 DCD UART0_IRQHandler ; UART0
81 DCD UART1_IRQHandler ; UART1
82 DCD UART2_IRQHandler ; UART2
85 DCD I2C_IRQHandler ; I2C controller
86 DCD SCT_IRQHandler ; Smart Counter Timer
87 DCD MRT_IRQHandler ; Multi-Rate Timer
88 DCD CMP_IRQHandler ; Comparator
89 DCD WDT_IRQHandler ; PIO1 (0:11)
90 DCD BOD_IRQHandler ; Brown Out Detect
92 DCD WKT_IRQHandler ; Wakeup timer
101 DCD PININT0_IRQHandler ; PIO INT0
102 DCD PININT1_IRQHandler ; PIO INT1
103 DCD PININT2_IRQHandler ; PIO INT2
104 DCD PININT3_IRQHandler ; PIO INT3
105 DCD PININT4_IRQHandler ; PIO INT4
106 DCD PININT5_IRQHandler ; PIO INT5
107 DCD PININT6_IRQHandler ; PIO INT6
108 DCD PININT7_IRQHandler ; PIO INT7
112 AREA |.ARM.__at_0x02FC|, CODE, READONLY
113 CRP_Key DCD 0xFFFFFFFF
117 AREA |.text|, CODE, READONLY
123 EXPORT Reset_Handler [WEAK]
133 ; Dummy Exception Handlers (infinite loops which can be modified)
134 ; now, under COMMON lpc8xx_nmi.c and lpc8xx_nmi.h, a real NMI handler is created if NMI is enabled
135 ; for particular peripheral.
137 ; EXPORT NMI_Handler [WEAK]
142 EXPORT HardFault_Handler [WEAK]
146 EXPORT SVC_Handler [WEAK]
150 EXPORT PendSV_Handler [WEAK]
154 EXPORT SysTick_Handler [WEAK]
160 EXPORT NMI_Handler [WEAK]
161 EXPORT SPI0_IRQHandler [WEAK]
162 EXPORT SPI1_IRQHandler [WEAK]
163 EXPORT UART0_IRQHandler [WEAK]
164 EXPORT UART1_IRQHandler [WEAK]
165 EXPORT UART2_IRQHandler [WEAK]
166 EXPORT I2C_IRQHandler [WEAK]
167 EXPORT SCT_IRQHandler [WEAK]
168 EXPORT MRT_IRQHandler [WEAK]
169 EXPORT CMP_IRQHandler [WEAK]
170 EXPORT WDT_IRQHandler [WEAK]
171 EXPORT BOD_IRQHandler [WEAK]
173 EXPORT WKT_IRQHandler [WEAK]
175 EXPORT PININT0_IRQHandler [WEAK]
176 EXPORT PININT1_IRQHandler [WEAK]
177 EXPORT PININT2_IRQHandler [WEAK]
178 EXPORT PININT3_IRQHandler [WEAK]
179 EXPORT PININT4_IRQHandler [WEAK]
180 EXPORT PININT5_IRQHandler [WEAK]
181 EXPORT PININT6_IRQHandler [WEAK]
182 EXPORT PININT7_IRQHandler [WEAK]