tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/system_LPC8xx.c

   1 /******************************************************************************
   2  * @file:    system_LPC8xx.c
   3  * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Source File
   4  *           for the NXP LPC8xx Device Series
   5  * @version: V1.0
   6  * @date:    16. Aug. 2012
   7  *----------------------------------------------------------------------------
   8  *
   9  * Copyright (C) 2012 ARM Limited. All rights reserved.
  10  *
  11  * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
  12  * processor based microcontrollers.  This file can be freely distributed
  13  * within development tools that are supporting such ARM based processors.
  14  *
  15  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  16  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
  17  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
  18  * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
  19  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
  20  *
  21  ******************************************************************************/
  22 #include <stdint.h>
  23 #include "LPC8xx.h"
  24
  25 /*
  26 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
  27 */
  28
  29 /*--------------------- Clock Configuration ----------------------------------
  30 //
  31 // <e> Clock Configuration
  32 //   <h> System Oscillator Control Register (SYSOSCCTRL)
  33 //     <o1.0>      BYPASS: System Oscillator Bypass Enable
  34 //                     <i> If enabled then PLL input (sys_osc_clk) is fed
  35 //                     <i> directly from XTALIN and XTALOUT pins.
  36 //     <o1.9>      FREQRANGE: System Oscillator Frequency Range
  37 //                     <i> Determines frequency range for Low-power oscillator.
  38 //                   <0=> 1 - 20 MHz
  39 //                   <1=> 15 - 25 MHz
  40 //   </h>
  41 //
  42 //   <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
  43 //     <o2.0..4>   DIVSEL: Select Divider for Fclkana
  44 //                     <i> wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL))
  45 //                   <0-31>
  46 //     <o2.5..8>   FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
  47 //                   <0=> Undefined
  48 //                   <1=> 0.5 MHz
  49 //                   <2=> 0.8 MHz
  50 //                   <3=> 1.1 MHz
  51 //                   <4=> 1.4 MHz
  52 //                   <5=> 1.6 MHz
  53 //                   <6=> 1.8 MHz
  54 //                   <7=> 2.0 MHz
  55 //                   <8=> 2.2 MHz
  56 //                   <9=> 2.4 MHz
  57 //                   <10=> 2.6 MHz
  58 //                   <11=> 2.7 MHz
  59 //                   <12=> 2.9 MHz
  60 //                   <13=> 3.1 MHz
  61 //                   <14=> 3.2 MHz
  62 //                   <15=> 3.4 MHz
  63 //   </h>
  64 //
  65 //   <h> System PLL Control Register (SYSPLLCTRL)
  66 //                   <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
  67 //                   <i> F_clkin must be in the range of  10 MHz to  25 MHz
  68 //                   <i> F_CCO   must be in the range of 156 MHz to 320 MHz
  69 //     <o3.0..4>   MSEL: Feedback Divider Selection
  70 //                     <i> M = MSEL + 1
  71 //                   <0-31>
  72 //     <o3.5..6>   PSEL: Post Divider Selection
  73 //                   <0=> P = 1
  74 //                   <1=> P = 2
  75 //                   <2=> P = 4
  76 //                   <3=> P = 8
  77 //   </h>
  78 //
  79 //   <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
  80 //     <o4.0..1>   SEL: System PLL Clock Source
  81 //                   <0=> IRC Oscillator
  82 //                   <1=> System Oscillator
  83 //                   <2=> Reserved
  84 //                   <3=> CLKIN pin
  85 //   </h>
  86 //
  87 //   <h> Main Clock Source Select Register (MAINCLKSEL)
  88 //     <o5.0..1>   SEL: Clock Source for Main Clock
  89 //                   <0=> IRC Oscillator
  90 //                   <1=> Input Clock to System PLL
  91 //                   <2=> WDT Oscillator
  92 //                   <3=> System PLL Clock Out
  93 //   </h>
  94 //
  95 //   <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
  96 //     <o6.0..7>   DIV: System AHB Clock Divider
  97 //                     <i> Divides main clock to provide system clock to core, memories, and peripherals.
  98 //                     <i> 0 = is disabled
  99 //                   <0-255>
 100 //   </h>
 101 // </e>
 102 */
 103 #define CLOCK_SETUP     1       // 1 == IRC: 2 == System Oscillator 12Mhz Xtal:
 104
 105 //Fixed to use PLL
 106 #if (CLOCK_SETUP == 1)
 107 //use PLL for IRC
 108         #define SYSOSCCTRL_Val        0x00000000              // Reset: 0x000
 109         #define WDTOSCCTRL_Val        0x00000000              // Reset: 0x000
 110         #define SYSPLLCTRL_Val        0x00000004              // Reset: 0x000  MSEL=4 => M=5; PSEL=0 => 2P=2; PLLCLKOUT = (12x5) = 60MHz
 111         #define SYSPLLCLKSEL_Val      0x00000000              // Reset: 0x000  Select IRC
 112         #define MAINCLKSEL_Val        0x00000003              // Reset: 0x000  MainClock = PLLCLKOUT
 113         #define SYSAHBCLKDIV_Val      0x00000002              // Reset: 0x001  DIV=2 => SYSTEMCORECLK = 60 / 2 = 30MHz
 114
 115 #elif (CLOCK_SETUP == 2)
 116 //use PLL for XTAL
 117         #define SYSOSCCTRL_Val        0x00000000              // Reset: 0x000
 118         #define WDTOSCCTRL_Val        0x00000000              // Reset: 0x000
 119         #define SYSPLLCTRL_Val        0x00000004              // Reset: 0x000 MSEL=4 => M=5; PSEL=0 => 2P=2; PLLCLKOUT = (12x5) = 60MHz
 120         #define SYSPLLCLKSEL_Val      0x00000001              // Reset: 0x000 Select XTAL
 121         #define MAINCLKSEL_Val        0x00000003              // Reset: 0x000 MainClock = PLLCLKOUT
 122         #define SYSAHBCLKDIV_Val      0x00000002              // Reset: 0x001 DIV=2 => SYSTEMCORECLK = 60 / 2 = 30MHz
 123 #endif
 124
 125 /*
 126 //-------- <<< end of configuration section >>> ------------------------------
 127 */
 128
 129 /*----------------------------------------------------------------------------
 130   Check the register settings
 131  *----------------------------------------------------------------------------*/
 132 #define CHECK_RANGE(val, min, max)                ((val < min) || (val > max))
 133 #define CHECK_RSVD(val, mask)                     (val & mask)
 134
 135 /* Clock Configuration -------------------------------------------------------*/
 136 #if (CHECK_RSVD((SYSOSCCTRL_Val),  ~0x00000003))
 137    #error "SYSOSCCTRL: Invalid values of reserved bits!"
 138 #endif
 139
 140 #if (CHECK_RSVD((WDTOSCCTRL_Val),  ~0x000001FF))
 141    #error "WDTOSCCTRL: Invalid values of reserved bits!"
 142 #endif
 143
 144 #if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
 145    #error "SYSPLLCLKSEL: Value out of range!"
 146 #endif
 147
 148 #if (CHECK_RSVD((SYSPLLCTRL_Val),  ~0x000001FF))
 149    #error "SYSPLLCTRL: Invalid values of reserved bits!"
 150 #endif
 151
 152 #if (CHECK_RSVD((MAINCLKSEL_Val),  ~0x00000003))
 153    #error "MAINCLKSEL: Invalid values of reserved bits!"
 154 #endif
 155
 156 #if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
 157    #error "SYSAHBCLKDIV: Value out of range!"
 158 #endif
 159
 160
 161 /*----------------------------------------------------------------------------
 162   DEFINES
 163  *----------------------------------------------------------------------------*/
 164
 165 /*----------------------------------------------------------------------------
 166   Define clocks
 167  *----------------------------------------------------------------------------*/
 168 #define __XTAL            (12000000UL)    /* Oscillator frequency             */
 169 #define __SYS_OSC_CLK     (    __XTAL)    /* Main oscillator frequency        */
 170 #define __IRC_OSC_CLK     (12000000UL)    /* Internal RC oscillator frequency */
 171 #define __CLKIN_CLK       (12000000UL)    /* CLKIN pin frequency              */
 172
 173
 174 #define __FREQSEL   ((WDTOSCCTRL_Val >> 5) & 0x0F)
 175 #define __DIVSEL   (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
 176
 177 #if (CLOCK_SETUP)                         /* Clock Setup              */
 178   #if  (__FREQSEL ==  0)
 179     #define __WDT_OSC_CLK        ( 0)                  /* undefined */
 180   #elif (__FREQSEL ==  1)
 181     #define __WDT_OSC_CLK        ( 500000 / __DIVSEL)
 182   #elif (__FREQSEL ==  2)
 183     #define __WDT_OSC_CLK        ( 800000 / __DIVSEL)
 184   #elif (__FREQSEL ==  3)
 185     #define __WDT_OSC_CLK        (1100000 / __DIVSEL)
 186   #elif (__FREQSEL ==  4)
 187     #define __WDT_OSC_CLK        (1400000 / __DIVSEL)
 188   #elif (__FREQSEL ==  5)
 189     #define __WDT_OSC_CLK        (1600000 / __DIVSEL)
 190   #elif (__FREQSEL ==  6)
 191     #define __WDT_OSC_CLK        (1800000 / __DIVSEL)
 192   #elif (__FREQSEL ==  7)
 193     #define __WDT_OSC_CLK        (2000000 / __DIVSEL)
 194   #elif (__FREQSEL ==  8)
 195     #define __WDT_OSC_CLK        (2200000 / __DIVSEL)
 196   #elif (__FREQSEL ==  9)
 197     #define __WDT_OSC_CLK        (2400000 / __DIVSEL)
 198   #elif (__FREQSEL == 10)
 199     #define __WDT_OSC_CLK        (2600000 / __DIVSEL)
 200   #elif (__FREQSEL == 11)
 201     #define __WDT_OSC_CLK        (2700000 / __DIVSEL)
 202   #elif (__FREQSEL == 12)
 203     #define __WDT_OSC_CLK        (2900000 / __DIVSEL)
 204   #elif (__FREQSEL == 13)
 205     #define __WDT_OSC_CLK        (3100000 / __DIVSEL)
 206   #elif (__FREQSEL == 14)
 207     #define __WDT_OSC_CLK        (3200000 / __DIVSEL)
 208   #else
 209     #define __WDT_OSC_CLK        (3400000 / __DIVSEL)
 210   #endif
 211
 212   /* sys_pllclkin calculation */
 213   #if   ((SYSPLLCLKSEL_Val & 0x03) == 0)
 214     #define __SYS_PLLCLKIN           (__IRC_OSC_CLK)
 215   #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
 216     #define __SYS_PLLCLKIN           (__SYS_OSC_CLK)
 217   #elif ((SYSPLLCLKSEL_Val & 0x03) == 3)
 218     #define __SYS_PLLCLKIN           (__CLKIN_CLK)
 219   #else
 220     #define __SYS_PLLCLKIN           (0)
 221   #endif
 222
 223   #define  __SYS_PLLCLKOUT         (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
 224
 225   /* main clock calculation */
 226   #if   ((MAINCLKSEL_Val & 0x03) == 0)
 227     #define __MAIN_CLOCK             (__IRC_OSC_CLK)
 228   #elif ((MAINCLKSEL_Val & 0x03) == 1)
 229     #define __MAIN_CLOCK             (__SYS_PLLCLKIN)
 230   #elif ((MAINCLKSEL_Val & 0x03) == 2)
 231     #if (__FREQSEL ==  0)
 232       #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
 233     #else
 234       #define __MAIN_CLOCK           (__WDT_OSC_CLK)
 235     #endif
 236   #elif ((MAINCLKSEL_Val & 0x03) == 3)
 237     #define __MAIN_CLOCK             (__SYS_PLLCLKOUT)
 238   #else
 239     #define __MAIN_CLOCK             (0)
 240   #endif
 241
 242   #define __SYSTEM_CLOCK             (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
 243
 244 #else
 245   #define __SYSTEM_CLOCK             (__IRC_OSC_CLK)
 246 #endif  // CLOCK_SETUP
 247
 248
 249 /*----------------------------------------------------------------------------
 250   Clock Variable definitions
 251  *----------------------------------------------------------------------------*/
 252 uint32_t MainClock = __MAIN_CLOCK;         /*!< Main Clock Frequency */
 253 uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
 254
 255 //Replaced SystemCoreClock with MainClock
 256 /*----------------------------------------------------------------------------
 257   Clock functions
 258  *----------------------------------------------------------------------------*/
 259 void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
 260 {
 261   uint32_t wdt_osc = 0;
 262
 263   /* Determine clock frequency according to clock register values             */
 264   switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
 265     case 0:  wdt_osc =       0; break;
 266     case 1:  wdt_osc =  500000; break;
 267     case 2:  wdt_osc =  800000; break;
 268     case 3:  wdt_osc = 1100000; break;
 269     case 4:  wdt_osc = 1400000; break;
 270     case 5:  wdt_osc = 1600000; break;
 271     case 6:  wdt_osc = 1800000; break;
 272     case 7:  wdt_osc = 2000000; break;
 273     case 8:  wdt_osc = 2200000; break;
 274     case 9:  wdt_osc = 2400000; break;
 275     case 10: wdt_osc = 2600000; break;
 276     case 11: wdt_osc = 2700000; break;
 277     case 12: wdt_osc = 2900000; break;
 278     case 13: wdt_osc = 3100000; break;
 279     case 14: wdt_osc = 3200000; break;
 280     case 15: wdt_osc = 3400000; break;
 281   }
 282   wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
 283
 284   switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
 285     case 0:                             /* Internal RC oscillator             */
 286       MainClock = __IRC_OSC_CLK;
 287       break;
 288     case 1:                             /* Input Clock to System PLL          */
 289       switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
 290           case 0:                       /* Internal RC oscillator             */
 291             MainClock = __IRC_OSC_CLK;
 292             break;
 293           case 1:                       /* System oscillator                  */
 294             MainClock = __SYS_OSC_CLK;
 295             break;
 296           case 2:                       /* Reserved                           */
 297             MainClock = 0;
 298             break;
 299           case 3:                       /* CLKIN pin                          */
 300             MainClock = __CLKIN_CLK;
 301             break;
 302       }
 303       break;
 304     case 2:                             /* WDT Oscillator                     */
 305       MainClock = wdt_osc;
 306       break;
 307     case 3:                             /* System PLL Clock Out               */
 308       switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
 309           case 0:                       /* Internal RC oscillator             */
 310             MainClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
 311             break;
 312           case 1:                       /* System oscillator                  */
 313             MainClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
 314             break;
 315           case 2:                       /* Reserved                           */
 316             MainClock = 0;
 317             break;
 318           case 3:                       /* CLKIN pin                          */
 319             MainClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
 320             break;
 321       }
 322       break;
 323   }
 324
 325   SystemCoreClock = MainClock / LPC_SYSCON->SYSAHBCLKDIV;
 326 }
 327
 328 /**
 329  * Initialize the system
 330  *
 331  * @param  none
 332  * @return none
 333  *
 334  * @brief  Setup the microcontroller system.
 335  *         Initialize the System.
 336  */
 337 void SystemInit (void) {
 338   volatile uint32_t i;
 339
 340   /* System clock to the IOCON & the SWM need to be enabled or
 341   most of the I/O related peripherals won't work. */
 342   LPC_SYSCON->SYSAHBCLKCTRL |= ( (0x1 << 7) | (0x1 << 18) );
 343
 344 #if (CLOCK_SETUP)                                 /* Clock Setup              */
 345
 346 #if ((SYSPLLCLKSEL_Val & 0x03) == 1)
 347   LPC_IOCON->PIO0_8 &= ~(0x3 << 3);
 348   LPC_IOCON->PIO0_9 &= ~(0x3 << 3);
 349   LPC_SWM->PINENABLE0 &= ~(0x3 << 4);
 350   LPC_SYSCON->PDRUNCFG     &= ~(0x1 << 5);        /* Power-up System Osc      */
 351   LPC_SYSCON->SYSOSCCTRL    = SYSOSCCTRL_Val;
 352   for (i = 0; i < 200; i++) __NOP();
 353 #endif
 354 #if ((SYSPLLCLKSEL_Val & 0x03) == 3)
 355   LPC_IOCON->PIO0_1 &= ~(0x3 << 3);
 356   LPC_SWM->PINENABLE0 &= ~(0x1 << 7);
 357   for (i = 0; i < 200; i++) __NOP();
 358 #endif
 359
 360   LPC_SYSCON->SYSPLLCLKSEL  = SYSPLLCLKSEL_Val;   /* Select PLL Input         */
 361   LPC_SYSCON->SYSPLLCLKUEN  = 0x01;               /* Update Clock Source      */
 362   while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01));     /* Wait Until Updated       */
 363 #if ((MAINCLKSEL_Val & 0x03) == 3)                /* Main Clock is PLL Out    */
 364   LPC_SYSCON->SYSPLLCTRL    = SYSPLLCTRL_Val;
 365   LPC_SYSCON->PDRUNCFG     &= ~(0x1 << 7);        /* Power-up SYSPLL          */
 366   while (!(LPC_SYSCON->SYSPLLSTAT & 0x01));           /* Wait Until PLL Locked    */
 367 #endif
 368
 369 #if (((MAINCLKSEL_Val & 0x03) == 2) )
 370   LPC_SYSCON->WDTOSCCTRL    = WDTOSCCTRL_Val;
 371   LPC_SYSCON->PDRUNCFG     &= ~(0x1 << 6);        /* Power-up WDT Clock       */
 372   for (i = 0; i < 200; i++) __NOP();
 373 #endif
 374
 375   LPC_SYSCON->MAINCLKSEL    = MAINCLKSEL_Val;     /* Select PLL Clock Output  */
 376   LPC_SYSCON->MAINCLKUEN    = 0x01;               /* Update MCLK Clock Source */
 377   while (!(LPC_SYSCON->MAINCLKUEN & 0x01));       /* Wait Until Updated       */
 378
 379   LPC_SYSCON->SYSAHBCLKDIV  = SYSAHBCLKDIV_Val;
 380 #endif
 381 }