tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_ARM/startup_LPC824.s

   1 /* File: startup_ARMCM0.S
   2  * Purpose: startup file for Cortex-M0 devices. Should use with
   3  *   GCC for ARM Embedded Processors
   4  * Version: V1.2
   5  * Date: 15 Nov 2011
   6  *
   7  * Copyright (c) 2011, ARM Limited
   8  * All rights reserved.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions are met:
  12     * Redistributions of source code must retain the above copyright
  13       notice, this list of conditions and the following disclaimer.
  14     * Redistributions in binary form must reproduce the above copyright
  15       notice, this list of conditions and the following disclaimer in the
  16       documentation and/or other materials provided with the distribution.
  17     * Neither the name of the ARM Limited nor the
  18       names of its contributors may be used to endorse or promote products
  19       derived from this software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  23  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  24  * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
  25  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  27  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  28  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  30  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32     .syntax unified
  33     .arch armv6-m
  34
  35 /* Memory Model
  36    The HEAP starts at the end of the DATA section and grows upward.
  37
  38    The STACK starts at the end of the RAM and grows downward.
  39
  40    The HEAP and stack STACK are only checked at compile time:
  41    (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
  42
  43    This is just a check for the bare minimum for the Heap+Stack area before
  44    aborting compilation, it is not the run time limit:
  45    Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
  46  */
  47     .section .stack
  48     .align 3
  49 #ifdef __STACK_SIZE
  50     .equ    Stack_Size, __STACK_SIZE
  51 #else
  52     .equ    Stack_Size, 0x80
  53 #endif
  54     .globl    __StackTop
  55     .globl    __StackLimit
  56 __StackLimit:
  57     .space    Stack_Size
  58     .size __StackLimit, . - __StackLimit
  59 __StackTop:
  60     .size __StackTop, . - __StackTop
  61
  62     .section .heap
  63     .align 3
  64 #ifdef __HEAP_SIZE
  65     .equ    Heap_Size, __HEAP_SIZE
  66 #else
  67     .equ    Heap_Size, 0x80
  68 #endif
  69     .globl    __HeapBase
  70     .globl    __HeapLimit
  71 __HeapBase:
  72     .space    Heap_Size
  73     .size __HeapBase, . - __HeapBase
  74 __HeapLimit:
  75     .size __HeapLimit, . - __HeapLimit
  76
  77     .section .isr_vector
  78     .align 2
  79     .globl __isr_vector
  80 __isr_vector:
  81     .long    __StackTop            /* Top of Stack */
  82     .long    Reset_Handler         /* Reset Handler */
  83     .long    NMI_Handler           /* NMI Handler */
  84     .long    HardFault_Handler     /* Hard Fault Handler */
  85     .long    0                     /* Reserved */
  86     .long    0                     /* Reserved */
  87     .long    0                     /* Reserved */
  88     .long    0                     /* Reserved */
  89     .long    0                     /* Reserved */
  90     .long    0                     /* Reserved */
  91     .long    0                     /* Reserved */
  92     .long    SVC_Handler           /* SVCall Handler */
  93     .long    0                     /* Reserved */
  94     .long    0                     /* Reserved */
  95     .long    PendSV_Handler        /* PendSV Handler */
  96     .long    SysTick_Handler       /* SysTick Handler */
  97
  98 /* LPC824 interrupts */
  99     .long    SPI0_IRQHandler                         // SPI0 controller
 100     .long    SPI1_IRQHandler                         // SPI1 controller
 101     .long    0                                       // Reserved
 102     .long    UART0_IRQHandler                        // UART0
 103     .long    UART1_IRQHandler                        // UART1
 104     .long    UART2_IRQHandler                        // UART2
 105     .long    0                                       // Reserved
 106     .long    I2C1_IRQHandler                         // I2C ch1 controller
 107     .long    I2C0_IRQHandler                         // I2C ch0 controller
 108     .long    SCT_IRQHandler                          // Smart Counter Timer
 109     .long    MRT_IRQHandler                          // Multi-Rate Timer
 110     .long    CMP_IRQHandler                          // Comparator
 111     .long    WDT_IRQHandler                          // PIO1 (0:11)
 112     .long    BOD_IRQHandler                          // Brown Out Detect
 113     .long    Flash_IRQHandler                        // Flash interrupt
 114     .long    WKT_IRQHandler                          // Wakeup timer
 115     .long    ADC_SEQA_IRQHandler                     // ADC sequence A completion
 116     .long    ADC_SEQB_IRQHandler                     // ADC sequence B completion
 117     .long    ADC_THCMP_IRQHandler                    // ADC threshold compare
 118     .long    ADC_OVR_IRQHandler                      // ADC overrun
 119     .long    DMA_IRQHandler                          // DMA interrupt
 120     .long    I2C2_IRQHandler                         // I2C2 controller
 121     .long    I2C3_IRQHandler                         // I2C3 controller
 122     .long    0                                       // Reserved
 123     .long    PININT0_IRQHandler                      // PIO INT0
 124     .long    PININT1_IRQHandler                      // PIO INT1
 125     .long    PININT2_IRQHandler                      // PIO INT2
 126     .long    PININT3_IRQHandler                      // PIO INT3
 127     .long    PININT4_IRQHandler                      // PIO INT4
 128     .long    PININT5_IRQHandler                      // PIO INT5
 129     .long    PININT6_IRQHandler                      // PIO INT6
 130     .long    PININT7_IRQHandler                      // PIO INT7
 131
 132     .size    __isr_vector, . - __isr_vector
 133
 134     .section .text.Reset_Handler
 135     .thumb
 136     .thumb_func
 137     .align 2
 138     .globl    Reset_Handler
 139     .type    Reset_Handler, %function
 140 Reset_Handler:
 141 /*     Loop to copy data from read only memory to RAM. The ranges
 142  *      of copy from/to are specified by following symbols evaluated in
 143  *      linker script.
 144  *      __etext: End of code section, i.e., begin of data sections to copy from.
 145  *      __data_start__/__data_end__: RAM address range that data should be
 146  *      copied to. Both must be aligned to 4 bytes boundary.  */
 147
 148     ldr    r1, =__etext
 149     ldr    r2, =__data_start__
 150     ldr    r3, =__data_end__
 151
 152     subs    r3, r2
 153     ble    .Lflash_to_ram_loop_end
 154
 155     movs    r4, 0
 156 .Lflash_to_ram_loop:
 157     ldr    r0, [r1,r4]
 158     str    r0, [r2,r4]
 159     adds    r4, 4
 160     cmp    r4, r3
 161     blt    .Lflash_to_ram_loop
 162 .Lflash_to_ram_loop_end:
 163
 164     ldr    r0, =SystemInit
 165     blx    r0
 166     ldr    r0, =_start
 167     bx    r0
 168     .pool
 169     .size Reset_Handler, . - Reset_Handler
 170
 171     .text
 172 /*    Macro to define default handlers. Default handler
 173  *    will be weak symbol and just dead loops. They can be
 174  *    overwritten by other handlers */
 175     .macro    def_default_handler    handler_name
 176     .align 1
 177     .thumb_func
 178     .weak    \handler_name
 179     .type    \handler_name, %function
 180 \handler_name :
 181     b    .
 182     .size    \handler_name, . - \handler_name
 183     .endm
 184
 185     def_default_handler     NMI_Handler
 186     def_default_handler     HardFault_Handler
 187     def_default_handler     SVC_Handler
 188     def_default_handler     PendSV_Handler
 189     def_default_handler     SysTick_Handler
 190     def_default_handler     Default_Handler
 191
 192     .macro    def_irq_default_handler    handler_name
 193     .weak     \handler_name
 194     .set      \handler_name, Default_Handler
 195     .endm
 196
 197     def_irq_default_handler    SPI0_IRQHandler
 198     def_irq_default_handler    SPI1_IRQHandler
 199     def_irq_default_handler    UART0_IRQHandler
 200     def_irq_default_handler    UART1_IRQHandler
 201     def_irq_default_handler    UART2_IRQHandler
 202     def_irq_default_handler    I2C0_IRQHandler
 203     def_irq_default_handler    I2C1_IRQHandler
 204     def_irq_default_handler    I2C2_IRQHandler
 205     def_irq_default_handler    I2C3_IRQHandler
 206     def_irq_default_handler    SCT_IRQHandler
 207     def_irq_default_handler    MRT_IRQHandler
 208     def_irq_default_handler    CMP_IRQHandler
 209     def_irq_default_handler    WDT_IRQHandler
 210     def_irq_default_handler    BOD_IRQHandler
 211     def_irq_default_handler    Flash_IRQHandler
 212     def_irq_default_handler    WKT_IRQHandler
 213     def_irq_default_handler    ADC_SEQA_IRQHandler
 214     def_irq_default_handler    ADC_SEQB_IRQHandler
 215     def_irq_default_handler    ADC_THCMP_IRQHandler
 216     def_irq_default_handler    ADC_OVR_IRQHandler
 217     def_irq_default_handler    DMA_IRQHandler
 218     def_irq_default_handler    PININT0_IRQHandler
 219     def_irq_default_handler    PININT1_IRQHandler
 220     def_irq_default_handler    PININT2_IRQHandler
 221     def_irq_default_handler    PININT3_IRQHandler
 222     def_irq_default_handler    PININT4_IRQHandler
 223     def_irq_default_handler    PININT5_IRQHandler
 224     def_irq_default_handler    PININT6_IRQHandler
 225     def_irq_default_handler    PININT7_IRQHandler
 226
 227     .end
 228