tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/system_LPC8xx.c

   1 /******************************************************************************
   2  * @file:    system_LPC8xx.c
   3  * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Source File
   4  *           for the NXP LPC8xx Device Series
   5  * @version: V1.0
   6  * @date:    16. Aug. 2012
   7  *----------------------------------------------------------------------------
   8  *
   9  * Copyright (C) 2012 ARM Limited. All rights reserved.
  10  *
  11  * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
  12  * processor based microcontrollers.  This file can be freely distributed
  13  * within development tools that are supporting such ARM based processors.
  14  *
  15  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  16  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
  17  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
  18  * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
  19  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
  20  *
  21  ******************************************************************************/
  22 #include <stdint.h>
  23 #include "LPC82x.h"
  24
  25 /*
  26 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
  27 */
  28
  29 /*--------------------- Clock Configuration ----------------------------------*/
  30 //
  31 // <e> Clock Configuration
  32 #define CLOCK_SETUP           1
  33 //   <h> System Oscillator Control Register (SYSOSCCTRL)
  34 //     <o.0>      BYPASS: System Oscillator Bypass Enable
  35 //                     <i> If enabled then PLL input (sys_osc_clk) is fed
  36 //                     <i> directly from XTALIN and XTALOUT pins.
  37 //     <o.1>      FREQRANGE: System Oscillator Frequency Range
  38 //                     <i> Determines frequency range for Low-power oscillator.
  39 //                   <0=> 1 - 20 MHz
  40 //                   <1=> 15 - 25 MHz
  41 //   </h>
  42 #define SYSOSCCTRL_Val        0x00000000              // Reset: 0x000
  43 //
  44 //   <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
  45 //     <o.0..4>   DIVSEL: Select Divider for Fclkana
  46 //                     <i> wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL))
  47 //                   <0-31>
  48 //     <o.5..8>   FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
  49 //                   <0=> Undefined
  50 //                   <1=> 0.6 MHz
  51 //                   <2=> 1.05 MHz
  52 //                   <3=> 1.4 MHz
  53 //                   <4=> 1.75 MHz
  54 //                   <5=> 2.1 MHz
  55 //                   <6=> 2.4 MHz
  56 //                   <7=> 2.7 MHz
  57 //                   <8=> 3.0 MHz
  58 //                   <9=> 3.25 MHz
  59 //                   <10=> 3.5 MHz
  60 //                   <11=> 3.75 MHz
  61 //                   <12=> 4.0 MHz
  62 //                   <13=> 4.2 MHz
  63 //                   <14=> 4.4 MHz
  64 //                   <15=> 4.6 MHz
  65 #define WDTOSCCTRL_Val        0x00000000              // Reset: 0x000
  66 //   </h>
  67 //   <h> System PLL Control Register (SYSPLLCTRL)
  68 //                   <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
  69 //                   <i> F_clkin must be in the range of  10 MHz to  25 MHz
  70 //                   <i> F_CCO   must be in the range of 156 MHz to 320 MHz
  71 //     <o.0..4>   MSEL: Feedback Divider Selection
  72 //                     <i> M = MSEL + 1
  73 //                   <0-31>
  74 //     <o.5..6>   PSEL: Post Divider Selection
  75 //                   <0=> P = 1
  76 //                   <1=> P = 2
  77 //                   <2=> P = 4
  78 //                   <3=> P = 8
  79 //   </h>
  80 #define SYSPLLCTRL_Val        0x00000024              // Reset: 0x000
  81 //
  82 //   <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
  83 //     <o.0..1>   SEL: System PLL Clock Source
  84 //                   <0=> IRC
  85 //                   <1=> Crystal Oscillator
  86 //                   <2=> Reserved
  87 //                   <3=> CLKIN. External clock input.
  88 //   </h>
  89 #define SYSPLLCLKSEL_Val      0x00000001              // Reset: 0x000
  90 //
  91 //   <h> Main Clock Source Select Register (MAINCLKSEL)
  92 //     <o.0..1>   SEL: Clock Source for Main Clock
  93 //                   <0=> IRC Oscillator
  94 //                   <1=> PLL input
  95 //                   <2=> Watchdog Oscillator
  96 //                   <3=> PLL output
  97 //   </h>
  98 #define MAINCLKSEL_Val        0x00000003              // Reset: 0x000
  99 //   <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
 100 //     <o.0..7>   DIV: System AHB Clock Divider
 101 //                     <i> Divides main clock to provide system clock to core, memories, and peripherals.
 102 //                     <i> 0 = is disabled
 103 //                   <0-255>
 104 //   </h>
 105 #define SYSAHBCLKDIV_Val      0x00000002              // Reset: 0x001
 106 // </e>
 107
 108 //#define CLOCK_SETUP     0     // 1 == IRC: 2 == System Oscillator 12Mhz Xtal:
 109
 110 /*
 111 #if (CLOCK_SETUP == 0)
 112         #define SYSOSCCTRL_Val        0x00000000              // Reset: 0x000
 113         #define WDTOSCCTRL_Val        0x00000024              // Reset: 0x000
 114         #define SYSPLLCTRL_Val        0x00000041              // Reset: 0x000
 115         #define SYSPLLCLKSEL_Val      0x00000003              // Reset: 0x000
 116         #define MAINCLKSEL_Val        0x00000000              // Reset: 0x000
 117         #define SYSAHBCLKDIV_Val      0x00000001              // Reset: 0x001
 118 #elif (CLOCK_SETUP == 2)
 119 //      #define SYSOSCCTRL_Val        0x00000000              // Reset: 0x000
 120         #define WDTOSCCTRL_Val        0x00000000              // Reset: 0x000
 121         #define SYSPLLCTRL_Val        0x00000040              // Reset: 0x000
 122         #define SYSPLLCLKSEL_Val      0x00000001              // Reset: 0x000
 123         #define MAINCLKSEL_Val        0x00000003              // Reset: 0x000
 124         #define SYSAHBCLKDIV_Val      0x00000001              // Reset: 0x001
 125 #endif
 126 */
 127
 128 /*
 129 //-------- <<< end of configuration section >>> ------------------------------
 130 */
 131
 132 /*----------------------------------------------------------------------------
 133   Check the register settings
 134  *----------------------------------------------------------------------------*/
 135 #define CHECK_RANGE(val, min, max)                ((val < min) || (val > max))
 136 #define CHECK_RSVD(val, mask)                     (val & mask)
 137
 138 /* Clock Configuration -------------------------------------------------------*/
 139 #if (CHECK_RSVD((SYSOSCCTRL_Val),  ~0x00000003))
 140    #error "SYSOSCCTRL: Invalid values of reserved bits!"
 141 #endif
 142
 143 #if (CHECK_RSVD((WDTOSCCTRL_Val),  ~0x000001FF))
 144    #error "WDTOSCCTRL: Invalid values of reserved bits!"
 145 #endif
 146
 147 #if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
 148    #error "SYSPLLCLKSEL: Value out of range!"
 149 #endif
 150
 151 #if (CHECK_RSVD((SYSPLLCTRL_Val),  ~0x000001FF))
 152    #error "SYSPLLCTRL: Invalid values of reserved bits!"
 153 #endif
 154
 155 #if (CHECK_RSVD((MAINCLKSEL_Val),  ~0x00000003))
 156    #error "MAINCLKSEL: Invalid values of reserved bits!"
 157 #endif
 158
 159 #if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
 160    #error "SYSAHBCLKDIV: Value out of range!"
 161 #endif
 162
 163
 164 /*----------------------------------------------------------------------------
 165   DEFINES
 166  *----------------------------------------------------------------------------*/
 167
 168 /*----------------------------------------------------------------------------
 169   Define clocks
 170  *----------------------------------------------------------------------------*/
 171 #define __XTAL            (12000000UL)    /* Oscillator frequency             */
 172 #define __SYS_OSC_CLK     (    __XTAL)    /* Main oscillator frequency        */
 173 #define __IRC_OSC_CLK     (12000000UL)    /* Internal RC oscillator frequency */
 174 #define __CLKIN_CLK       (12000000UL)    /* CLKIN pin frequency              */
 175
 176
 177 #define __FREQSEL   ((WDTOSCCTRL_Val >> 5) & 0x0F)
 178 #define __DIVSEL   (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
 179
 180 #if (CLOCK_SETUP)                         /* Clock Setup              */
 181   #if  (__FREQSEL ==  0)
 182     #define __WDT_OSC_CLK        ( 0)                  /* undefined */
 183   #elif (__FREQSEL ==  1)
 184     #define __WDT_OSC_CLK        ( 500000 / __DIVSEL)
 185   #elif (__FREQSEL ==  2)
 186     #define __WDT_OSC_CLK        ( 800000 / __DIVSEL)
 187   #elif (__FREQSEL ==  3)
 188     #define __WDT_OSC_CLK        (1100000 / __DIVSEL)
 189   #elif (__FREQSEL ==  4)
 190     #define __WDT_OSC_CLK        (1400000 / __DIVSEL)
 191   #elif (__FREQSEL ==  5)
 192     #define __WDT_OSC_CLK        (1600000 / __DIVSEL)
 193   #elif (__FREQSEL ==  6)
 194     #define __WDT_OSC_CLK        (1800000 / __DIVSEL)
 195   #elif (__FREQSEL ==  7)
 196     #define __WDT_OSC_CLK        (2000000 / __DIVSEL)
 197   #elif (__FREQSEL ==  8)
 198     #define __WDT_OSC_CLK        (2200000 / __DIVSEL)
 199   #elif (__FREQSEL ==  9)
 200     #define __WDT_OSC_CLK        (2400000 / __DIVSEL)
 201   #elif (__FREQSEL == 10)
 202     #define __WDT_OSC_CLK        (2600000 / __DIVSEL)
 203   #elif (__FREQSEL == 11)
 204     #define __WDT_OSC_CLK        (2700000 / __DIVSEL)
 205   #elif (__FREQSEL == 12)
 206     #define __WDT_OSC_CLK        (2900000 / __DIVSEL)
 207   #elif (__FREQSEL == 13)
 208     #define __WDT_OSC_CLK        (3100000 / __DIVSEL)
 209   #elif (__FREQSEL == 14)
 210     #define __WDT_OSC_CLK        (3200000 / __DIVSEL)
 211   #else
 212     #define __WDT_OSC_CLK        (3400000 / __DIVSEL)
 213   #endif
 214
 215   /* sys_pllclkin calculation */
 216   #if   ((SYSPLLCLKSEL_Val & 0x03) == 0)
 217     #define __SYS_PLLCLKIN           (__IRC_OSC_CLK)
 218   #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
 219     #define __SYS_PLLCLKIN           (__SYS_OSC_CLK)
 220   #elif ((SYSPLLCLKSEL_Val & 0x03) == 3)
 221     #define __SYS_PLLCLKIN           (__CLKIN_CLK)
 222   #else
 223     #define __SYS_PLLCLKIN           (0)
 224   #endif
 225
 226   #define  __SYS_PLLCLKOUT         (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
 227
 228   /* main clock calculation */
 229   #if   ((MAINCLKSEL_Val & 0x03) == 0)
 230     #define __MAIN_CLOCK             (__IRC_OSC_CLK)
 231   #elif ((MAINCLKSEL_Val & 0x03) == 1)
 232     #define __MAIN_CLOCK             (__SYS_PLLCLKIN)
 233   #elif ((MAINCLKSEL_Val & 0x03) == 2)
 234     #if (__FREQSEL ==  0)
 235       #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
 236     #else
 237       #define __MAIN_CLOCK           (__WDT_OSC_CLK)
 238     #endif
 239   #elif ((MAINCLKSEL_Val & 0x03) == 3)
 240     #define __MAIN_CLOCK             (__SYS_PLLCLKOUT)
 241   #else
 242     #define __MAIN_CLOCK             (0)
 243   #endif
 244
 245   #define __SYSTEM_CLOCK             (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
 246
 247 #else
 248   #define __SYSTEM_CLOCK             (__IRC_OSC_CLK)
 249 #endif  // CLOCK_SETUP
 250
 251
 252 /*----------------------------------------------------------------------------
 253   Clock Variable definitions
 254  *----------------------------------------------------------------------------*/
 255 uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
 256 uint32_t MainClock = __MAIN_CLOCK;         /*!< Main Clock Frequency */
 257
 258 /*----------------------------------------------------------------------------
 259   Clock functions
 260  *----------------------------------------------------------------------------*/
 261 void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
 262 {
 263   uint32_t wdt_osc = 0;
 264
 265   /* Determine clock frequency according to clock register values             */
 266   switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
 267     case 0:  wdt_osc =       0; break;
 268     case 1:  wdt_osc =  500000; break;
 269     case 2:  wdt_osc =  800000; break;
 270     case 3:  wdt_osc = 1100000; break;
 271     case 4:  wdt_osc = 1400000; break;
 272     case 5:  wdt_osc = 1600000; break;
 273     case 6:  wdt_osc = 1800000; break;
 274     case 7:  wdt_osc = 2000000; break;
 275     case 8:  wdt_osc = 2200000; break;
 276     case 9:  wdt_osc = 2400000; break;
 277     case 10: wdt_osc = 2600000; break;
 278     case 11: wdt_osc = 2700000; break;
 279     case 12: wdt_osc = 2900000; break;
 280     case 13: wdt_osc = 3100000; break;
 281     case 14: wdt_osc = 3200000; break;
 282     case 15: wdt_osc = 3400000; break;
 283   }
 284   wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
 285
 286   switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
 287     case 0:                             /* Internal RC oscillator             */
 288       SystemCoreClock = __IRC_OSC_CLK;
 289       break;
 290     case 1:                             /* Input Clock to System PLL          */
 291       switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
 292           case 0:                       /* Internal RC oscillator             */
 293             SystemCoreClock = __IRC_OSC_CLK;
 294             break;
 295           case 1:                       /* System oscillator                  */
 296             SystemCoreClock = __SYS_OSC_CLK;
 297             break;
 298           case 2:                       /* Reserved                           */
 299             SystemCoreClock = 0;
 300             break;
 301           case 3:                       /* CLKIN pin                          */
 302             SystemCoreClock = __CLKIN_CLK;
 303             break;
 304       }
 305       break;
 306     case 2:                             /* WDT Oscillator                     */
 307       SystemCoreClock = wdt_osc;
 308       break;
 309     case 3:                             /* System PLL Clock Out               */
 310       switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
 311           case 0:                       /* Internal RC oscillator             */
 312             SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
 313             break;
 314           case 1:                       /* System oscillator                  */
 315             SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
 316             break;
 317           case 2:                       /* Reserved                           */
 318             SystemCoreClock = 0;
 319             break;
 320           case 3:                       /* CLKIN pin                          */
 321             SystemCoreClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
 322             break;
 323       }
 324       break;
 325   }
 326
 327   SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
 328
 329 }
 330
 331 /**
 332  * Initialize the system
 333  *
 334  * @param  none
 335  * @return none
 336  *
 337  * @brief  Setup the microcontroller system.
 338  *         Initialize the System.
 339  */
 340 void SystemInit (void) {
 341   volatile uint32_t i;
 342
 343   /* System clock to the IOCON & the SWM need to be enabled or
 344   most of the I/O related peripherals won't work. */
 345   LPC_SYSCON->SYSAHBCLKCTRL |= ( (0x1 << 7) | (0x1 << 18) );
 346
 347 #if (CLOCK_SETUP)                                 /* Clock Setup              */
 348
 349 #if ((SYSPLLCLKSEL_Val & 0x03) == 1)
 350   LPC_IOCON->PIO0_8 &= ~(0x3 << 3);
 351   LPC_IOCON->PIO0_9 &= ~(0x3 << 3);
 352   LPC_SWM->PINENABLE0 &= ~(0x3 << 6);             /* XTALIN and XTALOUT       */
 353   LPC_SYSCON->PDRUNCFG     &= ~(0x1 << 5);        /* Power-up System Osc      */
 354   for (i = 0; i < 200; i++) __NOP();
 355   LPC_SYSCON->SYSOSCCTRL    = SYSOSCCTRL_Val;
 356 #endif
 357
 358 #if ((SYSPLLCLKSEL_Val & 0x03) == 3)
 359   LPC_IOCON->PIO0_1 &= ~(0x3 << 3);
 360   LPC_SWM->PINENABLE0 &= ~(0x1 << 9);             /* CLKIN                    */
 361   for (i = 0; i < 200; i++) __NOP();
 362 #endif
 363
 364   LPC_SYSCON->PDRUNCFG     &= ~(0x1 << 7);        /* Power-up System PLL      */
 365   LPC_SYSCON->SYSPLLCLKSEL  = SYSPLLCLKSEL_Val;   /* Select PLL Input         */
 366   LPC_SYSCON->SYSPLLCLKUEN = 0;
 367   LPC_SYSCON->SYSPLLCLKUEN = 1;                   /* Update Clock Source      */
 368   while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01));     /* Wait Until Updated       */
 369
 370 #if ((MAINCLKSEL_Val & 0x03) == 3)                /* Main Clock is PLL Out    */
 371   LPC_SYSCON->SYSPLLCTRL    = SYSPLLCTRL_Val;
 372   LPC_SYSCON->PDRUNCFG     &= ~(0x1 << 7);        /* Power-up SYSPLL          */
 373   while (!(LPC_SYSCON->SYSPLLSTAT & 0x01));           /* Wait Until PLL Locked    */
 374 #endif
 375
 376 #if (((MAINCLKSEL_Val & 0x03) == 2) )
 377   LPC_SYSCON->WDTOSCCTRL    = WDTOSCCTRL_Val;
 378   LPC_SYSCON->PDRUNCFG     &= ~(0x1 << 6);        /* Power-up WDT Clock       */
 379   for (i = 0; i < 200; i++) __NOP();
 380 #endif
 381
 382   LPC_SYSCON->MAINCLKSEL    = MAINCLKSEL_Val;     /* Select PLL Clock Output  */
 383   LPC_SYSCON->MAINCLKUEN    = 0;
 384   LPC_SYSCON->MAINCLKUEN    = 1;                  /* Update MCLK Clock Source */
 385   while (!(LPC_SYSCON->MAINCLKUEN & 0x01));       /* Wait Until Updated       */
 386
 387   LPC_SYSCON->SYSAHBCLKDIV  = SYSAHBCLKDIV_Val;
 388 #endif
 389 }