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git.gir.st - tmk_keyboard.git/blob - tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/gic.h
1 /**************************************************************************//**
3 * @brief Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File
9 ******************************************************************************/
10 /* Copyright (c) 2011 - 2013 ARM LIMITED
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 - Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 - Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 - Neither the name of ARM nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ---------------------------------------------------------------------------*/
40 /* IO definitions (access restrictions to peripheral registers) */
44 #define __I volatile /*!< Defines 'read only' permissions */
46 #define __I volatile const /*!< Defines 'read only' permissions */
48 #define __O volatile /*!< Defines 'write only' permissions */
49 #define __IO volatile /*!< Defines 'read / write' permissions */
51 /** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD)
58 uint32_t RESERVED0
[29];
59 __IO
uint32_t ICDISR
[32];
60 __IO
uint32_t ICDISER
[32];
61 __IO
uint32_t ICDICER
[32];
62 __IO
uint32_t ICDISPR
[32];
63 __IO
uint32_t ICDICPR
[32];
64 __I
uint32_t ICDABR
[32];
65 uint32_t RESERVED1
[32];
66 __IO
uint32_t ICDIPR
[256];
67 __IO
uint32_t ICDIPTR
[256];
68 __IO
uint32_t ICDICFR
[64];
69 uint32_t RESERVED2
[128];
70 __IO
uint32_t ICDSGIR
;
71 } GICDistributor_Type
;
73 /** \brief Structure type to access the Controller Interface (GICC)
77 __IO
uint32_t ICCICR
; // +0x000 - RW - CPU Interface Control Register
78 __IO
uint32_t ICCPMR
; // +0x004 - RW - Interrupt Priority Mask Register
79 __IO
uint32_t ICCBPR
; // +0x008 - RW - Binary Point Register
80 __I
uint32_t ICCIAR
; // +0x00C - RO - Interrupt Acknowledge Register
81 __IO
uint32_t ICCEOIR
; // +0x010 - WO - End of Interrupt Register
82 __I
uint32_t ICCRPR
; // +0x014 - RO - Running Priority Register
83 __I
uint32_t ICCHPIR
; // +0x018 - RO - Highest Pending Interrupt Register
84 __IO
uint32_t ICCABPR
; // +0x01C - RW - Aliased Binary Point Register
86 uint32_t RESERVED
[55];
88 __I
uint32_t ICCIIDR
; // +0x0FC - RO - CPU Interface Identification Register
93 /* ########################## GIC functions #################################### */
94 /** \brief Functions that manage interrupts via the GIC.
98 /** \brief Enable DistributorGICInterface->ICCICR |= 1; //enable interface
100 Enables the forwarding of pending interrupts to the CPU interfaces.
103 void GIC_EnableDistributor(void);
105 /** \brief Disable Distributor
107 Disables the forwarding of pending interrupts to the CPU interfaces.
110 void GIC_DisableDistributor(void);
112 /** \brief Provides information about the configuration of the GIC.
113 Provides information about the configuration of the GIC.
114 - whether the GIC implements the Security Extensions
115 - the maximum number of interrupt IDs that the GIC supports
116 - the number of CPU interfaces implemented
117 - if the GIC implements the Security Extensions, the maximum number of implemented Lockable Shared Peripheral Interrupts (LSPIs).
119 \return Distributor Information.
121 uint32_t GIC_DistributorInfo(void);
123 /** \brief Distributor Implementer Identification Register.
125 Distributor Implementer Identification Register
127 \return Implementer Information.
129 uint32_t GIC_DistributorImplementer(void);
131 /** \brief Set list of processors that the interrupt is sent to if it is asserted.
133 The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
134 This field stores the list of processors that the interrupt is sent to if it is asserted.
136 \param [in] IRQn Interrupt number.
137 \param [in] target CPU target
139 void GIC_SetTarget(IRQn_Type IRQn
, uint32_t cpu_target
);
141 /** \brief Get list of processors that the interrupt is sent to if it is asserted.
143 The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
144 This field stores the list of processors that the interrupt is sent to if it is asserted.
146 \param [in] IRQn Interrupt number.
147 \param [in] target CPU target
149 uint32_t GIC_GetTarget(IRQn_Type IRQn
);
151 /** \brief Enable Interface
153 Enables the signalling of interrupts to the target processors.
156 void GIC_EnableInterface(void);
158 /** \brief Disable Interface
160 Disables the signalling of interrupts to the target processors.
163 void GIC_DisableInterface(void);
165 /** \brief Acknowledge Interrupt
167 The function acknowledges the highest priority pending interrupt and returns its IRQ number.
169 \return Interrupt number
171 IRQn_Type
GIC_AcknowledgePending(void);
173 /** \brief End Interrupt
175 The function writes the end of interrupt register, indicating that handling of the interrupt is complete.
177 \param [in] IRQn Interrupt number.
179 void GIC_EndInterrupt(IRQn_Type IRQn
);
182 /** \brief Enable Interrupt
184 Set-enable bit for each interrupt supported by the GIC.
186 \param [in] IRQn External interrupt number.
188 void GIC_EnableIRQ(IRQn_Type IRQn
);
190 /** \brief Disable Interrupt
192 Clear-enable bit for each interrupt supported by the GIC.
194 \param [in] IRQn Number of the external interrupt to disable
196 void GIC_DisableIRQ(IRQn_Type IRQn
);
198 /** \brief Set Pending Interrupt
200 Set-pending bit for each interrupt supported by the GIC.
202 \param [in] IRQn Interrupt number.
204 void GIC_SetPendingIRQ(IRQn_Type IRQn
);
206 /** \brief Clear Pending Interrupt
208 Clear-pending bit for each interrupt supported by the GIC
210 \param [in] IRQn Number of the interrupt for clear pending
212 void GIC_ClearPendingIRQ(IRQn_Type IRQn
);
214 /** \brief Int_config field for each interrupt supported by the GIC.
216 This field identifies whether the corresponding interrupt is:
217 (1) edge-triggered or (0) level-sensitive
218 (1) 1-N model or (0) N-N model
220 \param [in] IRQn Interrupt number.
221 \param [in] edge_level (1) edge-triggered or (0) level-sensitive
222 \param [in] model (1) 1-N model or (0) N-N model
224 void GIC_SetLevelModel(IRQn_Type IRQn
, int8_t edge_level
, int8_t model
);
227 /** \brief Set Interrupt Priority
229 The function sets the priority of an interrupt.
231 \param [in] IRQn Interrupt number.
232 \param [in] priority Priority to set.
234 void GIC_SetPriority(IRQn_Type IRQn
, uint32_t priority
);
236 /** \brief Get Interrupt Priority
238 The function reads the priority of an interrupt.
240 \param [in] IRQn Interrupt number.
241 \return Interrupt Priority.
243 uint32_t GIC_GetPriority(IRQn_Type IRQn
);
245 /** \brief CPU Interface Priority Mask Register
247 The priority mask level for the CPU interface. If the priority of an interrupt is higher than the
248 value indicated by this field, the interface signals the interrupt to the processor.
252 void GIC_InterfacePriorityMask(uint32_t priority
);
254 /** \brief Set the binary point.
256 Set the point at which the priority value fields split into two parts, the group priority field and the subpriority field.
260 void GIC_SetBinaryPoint(uint32_t binary_point
);
262 /** \brief Get the binary point.
264 Get the point at which the priority value fields split into two parts, the group priority field and the subpriority field.
266 \return Binary point.
268 uint32_t GIC_GetBinaryPoint(uint32_t binary_point
);
270 /** \brief Get Interrupt state.
272 Get the interrupt state, whether pending and/or active
274 \return 0 - inactive, 1 - pending, 2 - active, 3 - pending and active
276 uint32_t GIC_GetIRQStatus(IRQn_Type IRQn
);
278 /** \brief Send Software Generated interrupt
280 Provides an interrupt priority filter. Only interrupts with higher priority than the value in this register can be signalled to the processor.
281 GIC_InterfacePriorityMask
282 \param [in] IRQn The Interrupt ID of the SGI.
283 \param [in] target_list CPUTargetList
284 \param [in] filter_list TargetListFilter
286 void GIC_SendSGI(IRQn_Type IRQn
, uint32_t target_list
, uint32_t filter_list
);
288 /** \brief API call to initialise the interrupt distributor
290 API call to initialise the interrupt distributor
293 void GIC_DistInit(void);
295 /** \brief API call to initialise the CPU interface
297 API call to initialise the CPU interface
300 void GIC_CPUInterfaceInit(void);
302 /** \brief API call to set the Interrupt Configuration Registers
304 API call to initialise the Interrupt Configuration Registers
307 void GIC_SetICDICFR (const uint32_t *ICDICFRn
);
309 /** \brief API call to Enable the GIC
311 API call to Enable the GIC
314 void GIC_Enable(void);