tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/pfv_iodefine.h

   1 /*******************************************************************************
   2 * DISCLAIMER
   3 * This software is supplied by Renesas Electronics Corporation and is only
   4 * intended for use with Renesas products. No other uses are authorized. This
   5 * software is owned by Renesas Electronics Corporation and is protected under
   6 * all applicable laws, including copyright laws.
   7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
   8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
   9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
  10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
  11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
  12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
  13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
  14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
  15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
  16 * Renesas reserves the right, without notice, to make changes to this software
  17 * and to discontinue the availability of this software. By using this software,
  18 * you agree to the additional terms and conditions found by accessing the
  19 * following link:
  20 * http://www.renesas.com/disclaimer*
  21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
  22 *******************************************************************************/
  23 /*******************************************************************************
  24 * File Name : pfv_iodefine.h
  25 * $Rev: $
  26 * $Date::                           $
  27 * Description : Definition of I/O Register (V1.00a)
  28 ******************************************************************************/
  29 #ifndef PFV_IODEFINE_H
  30 #define PFV_IODEFINE_H
  31 /* ->SEC M1.10.1 : Not magic number */
  32
  33 struct st_pfv
  34 {                                                          /* PFV              */
  35     volatile uint32_t  PFVCR;                                  /*  PFVCR           */
  36     volatile uint32_t  PFVICR;                                 /*  PFVICR          */
  37     volatile uint32_t  PFVISR;                                 /*  PFVISR          */
  38     volatile uint8_t   dummy1[20];                             /*                  */
  39 #define PFVID_COUNT 8
  40     volatile uint32_t  PFVID0;                                 /*  PFVID0          */
  41     volatile uint32_t  PFVID1;                                 /*  PFVID1          */
  42     volatile uint32_t  PFVID2;                                 /*  PFVID2          */
  43     volatile uint32_t  PFVID3;                                 /*  PFVID3          */
  44     volatile uint32_t  PFVID4;                                 /*  PFVID4          */
  45     volatile uint32_t  PFVID5;                                 /*  PFVID5          */
  46     volatile uint32_t  PFVID6;                                 /*  PFVID6          */
  47     volatile uint32_t  PFVID7;                                 /*  PFVID7          */
  48 #define PFVOD_COUNT 8
  49     volatile uint32_t  PFVOD0;                                 /*  PFVOD0          */
  50     volatile uint32_t  PFVOD1;                                 /*  PFVOD1          */
  51     volatile uint32_t  PFVOD2;                                 /*  PFVOD2          */
  52     volatile uint32_t  PFVOD3;                                 /*  PFVOD3          */
  53     volatile uint32_t  PFVOD4;                                 /*  PFVOD4          */
  54     volatile uint32_t  PFVOD5;                                 /*  PFVOD5          */
  55     volatile uint32_t  PFVOD6;                                 /*  PFVOD6          */
  56     volatile uint32_t  PFVOD7;                                 /*  PFVOD7          */
  57     volatile uint8_t   dummy2[4];                              /*                  */
  58     volatile uint32_t  PFVIFSR;                                /*  PFVIFSR         */
  59     volatile uint32_t  PFVOFSR;                                /*  PFVOFSR         */
  60     volatile uint32_t  PFVACR;                                 /*  PFVACR          */
  61     volatile uint32_t  PFV_MTX_MODE;                           /*  PFV_MTX_MODE    */
  62     volatile uint32_t  PFV_MTX_YG_ADJ0;                        /*  PFV_MTX_YG_ADJ0 */
  63     volatile uint32_t  PFV_MTX_YG_ADJ1;                        /*  PFV_MTX_YG_ADJ1 */
  64     volatile uint32_t  PFV_MTX_CBB_ADJ0;                       /*  PFV_MTX_CBB_ADJ0 */
  65     volatile uint32_t  PFV_MTX_CBB_ADJ1;                       /*  PFV_MTX_CBB_ADJ1 */
  66     volatile uint32_t  PFV_MTX_CRR_ADJ0;                       /*  PFV_MTX_CRR_ADJ0 */
  67     volatile uint32_t  PFV_MTX_CRR_ADJ1;                       /*  PFV_MTX_CRR_ADJ1 */
  68     volatile uint32_t  PFVSZR;                                 /*  PFVSZR          */
  69 };
  70
  71
  72 #define PFV0    (*(struct st_pfv     *)0xE8205000uL) /* PFV0 */
  73 #define PFV1    (*(struct st_pfv     *)0xE8205800uL) /* PFV1 */
  74
  75
  76 /* Start of channnel array defines of PFV */
  77
  78 /* Channnel array defines of PFV */
  79 /*(Sample) value = PFV[ channel ]->PFVCR; */
  80 #define PFV_COUNT  2
  81 #define PFV_ADDRESS_LIST \
  82 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
  83     &PFV0, &PFV1 \
  84 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
  85
  86 /* End of channnel array defines of PFV */
  87
  88
  89 #define PFV0PFVCR PFV0.PFVCR
  90 #define PFV0PFVICR PFV0.PFVICR
  91 #define PFV0PFVISR PFV0.PFVISR
  92 #define PFV0PFVID0 PFV0.PFVID0
  93 #define PFV0PFVID1 PFV0.PFVID1
  94 #define PFV0PFVID2 PFV0.PFVID2
  95 #define PFV0PFVID3 PFV0.PFVID3
  96 #define PFV0PFVID4 PFV0.PFVID4
  97 #define PFV0PFVID5 PFV0.PFVID5
  98 #define PFV0PFVID6 PFV0.PFVID6
  99 #define PFV0PFVID7 PFV0.PFVID7
 100 #define PFV0PFVOD0 PFV0.PFVOD0
 101 #define PFV0PFVOD1 PFV0.PFVOD1
 102 #define PFV0PFVOD2 PFV0.PFVOD2
 103 #define PFV0PFVOD3 PFV0.PFVOD3
 104 #define PFV0PFVOD4 PFV0.PFVOD4
 105 #define PFV0PFVOD5 PFV0.PFVOD5
 106 #define PFV0PFVOD6 PFV0.PFVOD6
 107 #define PFV0PFVOD7 PFV0.PFVOD7
 108 #define PFV0PFVIFSR PFV0.PFVIFSR
 109 #define PFV0PFVOFSR PFV0.PFVOFSR
 110 #define PFV0PFVACR PFV0.PFVACR
 111 #define PFV0PFV_MTX_MODE PFV0.PFV_MTX_MODE
 112 #define PFV0PFV_MTX_YG_ADJ0 PFV0.PFV_MTX_YG_ADJ0
 113 #define PFV0PFV_MTX_YG_ADJ1 PFV0.PFV_MTX_YG_ADJ1
 114 #define PFV0PFV_MTX_CBB_ADJ0 PFV0.PFV_MTX_CBB_ADJ0
 115 #define PFV0PFV_MTX_CBB_ADJ1 PFV0.PFV_MTX_CBB_ADJ1
 116 #define PFV0PFV_MTX_CRR_ADJ0 PFV0.PFV_MTX_CRR_ADJ0
 117 #define PFV0PFV_MTX_CRR_ADJ1 PFV0.PFV_MTX_CRR_ADJ1
 118 #define PFV0PFVSZR PFV0.PFVSZR
 119 #define PFV1PFVCR PFV1.PFVCR
 120 #define PFV1PFVICR PFV1.PFVICR
 121 #define PFV1PFVISR PFV1.PFVISR
 122 #define PFV1PFVID0 PFV1.PFVID0
 123 #define PFV1PFVID1 PFV1.PFVID1
 124 #define PFV1PFVID2 PFV1.PFVID2
 125 #define PFV1PFVID3 PFV1.PFVID3
 126 #define PFV1PFVID4 PFV1.PFVID4
 127 #define PFV1PFVID5 PFV1.PFVID5
 128 #define PFV1PFVID6 PFV1.PFVID6
 129 #define PFV1PFVID7 PFV1.PFVID7
 130 #define PFV1PFVOD0 PFV1.PFVOD0
 131 #define PFV1PFVOD1 PFV1.PFVOD1
 132 #define PFV1PFVOD2 PFV1.PFVOD2
 133 #define PFV1PFVOD3 PFV1.PFVOD3
 134 #define PFV1PFVOD4 PFV1.PFVOD4
 135 #define PFV1PFVOD5 PFV1.PFVOD5
 136 #define PFV1PFVOD6 PFV1.PFVOD6
 137 #define PFV1PFVOD7 PFV1.PFVOD7
 138 #define PFV1PFVIFSR PFV1.PFVIFSR
 139 #define PFV1PFVOFSR PFV1.PFVOFSR
 140 #define PFV1PFVACR PFV1.PFVACR
 141 #define PFV1PFV_MTX_MODE PFV1.PFV_MTX_MODE
 142 #define PFV1PFV_MTX_YG_ADJ0 PFV1.PFV_MTX_YG_ADJ0
 143 #define PFV1PFV_MTX_YG_ADJ1 PFV1.PFV_MTX_YG_ADJ1
 144 #define PFV1PFV_MTX_CBB_ADJ0 PFV1.PFV_MTX_CBB_ADJ0
 145 #define PFV1PFV_MTX_CBB_ADJ1 PFV1.PFV_MTX_CBB_ADJ1
 146 #define PFV1PFV_MTX_CRR_ADJ0 PFV1.PFV_MTX_CRR_ADJ0
 147 #define PFV1PFV_MTX_CRR_ADJ1 PFV1.PFV_MTX_CRR_ADJ1
 148 #define PFV1PFVSZR PFV1.PFVSZR
 149 /* <-SEC M1.10.1 */
 150 #endif