tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/rspi_iodefine.h

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  21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
  22 *******************************************************************************/
  23 /*******************************************************************************
  24 * File Name : rspi_iodefine.h
  25 * $Rev: $
  26 * $Date::                           $
  27 * Description : Definition of I/O Register (V1.00a)
  28 ******************************************************************************/
  29 #ifndef RSPI_IODEFINE_H
  30 #define RSPI_IODEFINE_H
  31 /* ->SEC M1.10.1 : Not magic number */
  32
  33 #include "reg32_t.h"
  34
  35 struct st_rspi
  36 {                                                          /* RSPI             */
  37     volatile uint8_t   SPCR;                                   /*  SPCR            */
  38     volatile uint8_t   SSLP;                                   /*  SSLP            */
  39     volatile uint8_t   SPPCR;                                  /*  SPPCR           */
  40     volatile uint8_t   SPSR;                                   /*  SPSR            */
  41     union reg32_t  SPDR;                          /*  SPDR            */
  42
  43     volatile uint8_t   SPSCR;                                  /*  SPSCR           */
  44     volatile uint8_t   SPSSR;                                  /*  SPSSR           */
  45     volatile uint8_t   SPBR;                                   /*  SPBR            */
  46     volatile uint8_t   SPDCR;                                  /*  SPDCR           */
  47     volatile uint8_t   SPCKD;                                  /*  SPCKD           */
  48     volatile uint8_t   SSLND;                                  /*  SSLND           */
  49     volatile uint8_t   SPND;                                   /*  SPND            */
  50     volatile uint8_t   dummy1[1];                              /*                  */
  51 #define SPCMD_COUNT 4
  52     volatile uint16_t SPCMD0;                                 /*  SPCMD0          */
  53     volatile uint16_t SPCMD1;                                 /*  SPCMD1          */
  54     volatile uint16_t SPCMD2;                                 /*  SPCMD2          */
  55     volatile uint16_t SPCMD3;                                 /*  SPCMD3          */
  56     volatile uint8_t   dummy2[8];                              /*                  */
  57     volatile uint8_t   SPBFCR;                                 /*  SPBFCR          */
  58     volatile uint8_t   dummy3[1];                              /*                  */
  59     volatile uint16_t SPBFDR;                                 /*  SPBFDR          */
  60 };
  61
  62
  63 #define RSPI0   (*(struct st_rspi    *)0xE800C800uL) /* RSPI0 */
  64 #define RSPI1   (*(struct st_rspi    *)0xE800D000uL) /* RSPI1 */
  65 #define RSPI2   (*(struct st_rspi    *)0xE800D800uL) /* RSPI2 */
  66 #define RSPI3   (*(struct st_rspi    *)0xE800E000uL) /* RSPI3 */
  67 #define RSPI4   (*(struct st_rspi    *)0xE800E800uL) /* RSPI4 */
  68
  69
  70 /* Start of channnel array defines of RSPI */
  71
  72 /* Channnel array defines of RSPI */
  73 /*(Sample) value = RSPI[ channel ]->SPCR; */
  74 #define RSPI_COUNT  5
  75 #define RSPI_ADDRESS_LIST \
  76 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
  77     &RSPI0, &RSPI1, &RSPI2, &RSPI3, &RSPI4 \
  78 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
  79
  80 /* End of channnel array defines of RSPI */
  81
  82
  83 #define SPCR_0 RSPI0.SPCR
  84 #define SSLP_0 RSPI0.SSLP
  85 #define SPPCR_0 RSPI0.SPPCR
  86 #define SPSR_0 RSPI0.SPSR
  87 #define SPDR_0   RSPI0.SPDR.UINT32
  88 #define SPDR_0L  RSPI0.SPDR.UINT16[L]
  89 #define SPDR_0H  RSPI0.SPDR.UINT16[H]
  90 #define SPDR_0LL RSPI0.SPDR.UINT8[LL]
  91 #define SPDR_0LH RSPI0.SPDR.UINT8[LH]
  92 #define SPDR_0HL RSPI0.SPDR.UINT8[HL]
  93 #define SPDR_0HH RSPI0.SPDR.UINT8[HH]
  94 #define SPSCR_0 RSPI0.SPSCR
  95 #define SPSSR_0 RSPI0.SPSSR
  96 #define SPBR_0 RSPI0.SPBR
  97 #define SPDCR_0 RSPI0.SPDCR
  98 #define SPCKD_0 RSPI0.SPCKD
  99 #define SSLND_0 RSPI0.SSLND
 100 #define SPND_0 RSPI0.SPND
 101 #define SPCMD0_0 RSPI0.SPCMD0
 102 #define SPCMD1_0 RSPI0.SPCMD1
 103 #define SPCMD2_0 RSPI0.SPCMD2
 104 #define SPCMD3_0 RSPI0.SPCMD3
 105 #define SPBFCR_0 RSPI0.SPBFCR
 106 #define SPBFDR_0 RSPI0.SPBFDR
 107 #define SPCR_1 RSPI1.SPCR
 108 #define SSLP_1 RSPI1.SSLP
 109 #define SPPCR_1 RSPI1.SPPCR
 110 #define SPSR_1 RSPI1.SPSR
 111 #define SPDR_1   RSPI1.SPDR.UINT32
 112 #define SPDR_1L  RSPI1.SPDR.UINT16[L]
 113 #define SPDR_1H  RSPI1.SPDR.UINT16[H]
 114 #define SPDR_1LL RSPI1.SPDR.UINT8[LL]
 115 #define SPDR_1LH RSPI1.SPDR.UINT8[LH]
 116 #define SPDR_1HL RSPI1.SPDR.UINT8[HL]
 117 #define SPDR_1HH RSPI1.SPDR.UINT8[HH]
 118 #define SPSCR_1 RSPI1.SPSCR
 119 #define SPSSR_1 RSPI1.SPSSR
 120 #define SPBR_1 RSPI1.SPBR
 121 #define SPDCR_1 RSPI1.SPDCR
 122 #define SPCKD_1 RSPI1.SPCKD
 123 #define SSLND_1 RSPI1.SSLND
 124 #define SPND_1 RSPI1.SPND
 125 #define SPCMD0_1 RSPI1.SPCMD0
 126 #define SPCMD1_1 RSPI1.SPCMD1
 127 #define SPCMD2_1 RSPI1.SPCMD2
 128 #define SPCMD3_1 RSPI1.SPCMD3
 129 #define SPBFCR_1 RSPI1.SPBFCR
 130 #define SPBFDR_1 RSPI1.SPBFDR
 131 #define SPCR_2 RSPI2.SPCR
 132 #define SSLP_2 RSPI2.SSLP
 133 #define SPPCR_2 RSPI2.SPPCR
 134 #define SPSR_2 RSPI2.SPSR
 135 #define SPDR_2   RSPI2.SPDR.UINT32
 136 #define SPDR_2L  RSPI2.SPDR.UINT16[L]
 137 #define SPDR_2H  RSPI2.SPDR.UINT16[H]
 138 #define SPDR_2LL RSPI2.SPDR.UINT8[LL]
 139 #define SPDR_2LH RSPI2.SPDR.UINT8[LH]
 140 #define SPDR_2HL RSPI2.SPDR.UINT8[HL]
 141 #define SPDR_2HH RSPI2.SPDR.UINT8[HH]
 142 #define SPSCR_2 RSPI2.SPSCR
 143 #define SPSSR_2 RSPI2.SPSSR
 144 #define SPBR_2 RSPI2.SPBR
 145 #define SPDCR_2 RSPI2.SPDCR
 146 #define SPCKD_2 RSPI2.SPCKD
 147 #define SSLND_2 RSPI2.SSLND
 148 #define SPND_2 RSPI2.SPND
 149 #define SPCMD0_2 RSPI2.SPCMD0
 150 #define SPCMD1_2 RSPI2.SPCMD1
 151 #define SPCMD2_2 RSPI2.SPCMD2
 152 #define SPCMD3_2 RSPI2.SPCMD3
 153 #define SPBFCR_2 RSPI2.SPBFCR
 154 #define SPBFDR_2 RSPI2.SPBFDR
 155 #define SPCR_3 RSPI3.SPCR
 156 #define SSLP_3 RSPI3.SSLP
 157 #define SPPCR_3 RSPI3.SPPCR
 158 #define SPSR_3 RSPI3.SPSR
 159 #define SPDR_3   RSPI3.SPDR.UINT32
 160 #define SPDR_3L  RSPI3.SPDR.UINT16[L]
 161 #define SPDR_3H  RSPI3.SPDR.UINT16[H]
 162 #define SPDR_3LL RSPI3.SPDR.UINT8[LL]
 163 #define SPDR_3LH RSPI3.SPDR.UINT8[LH]
 164 #define SPDR_3HL RSPI3.SPDR.UINT8[HL]
 165 #define SPDR_3HH RSPI3.SPDR.UINT8[HH]
 166 #define SPSCR_3 RSPI3.SPSCR
 167 #define SPSSR_3 RSPI3.SPSSR
 168 #define SPBR_3 RSPI3.SPBR
 169 #define SPDCR_3 RSPI3.SPDCR
 170 #define SPCKD_3 RSPI3.SPCKD
 171 #define SSLND_3 RSPI3.SSLND
 172 #define SPND_3 RSPI3.SPND
 173 #define SPCMD0_3 RSPI3.SPCMD0
 174 #define SPCMD1_3 RSPI3.SPCMD1
 175 #define SPCMD2_3 RSPI3.SPCMD2
 176 #define SPCMD3_3 RSPI3.SPCMD3
 177 #define SPBFCR_3 RSPI3.SPBFCR
 178 #define SPBFDR_3 RSPI3.SPBFDR
 179 #define SPCR_4 RSPI4.SPCR
 180 #define SSLP_4 RSPI4.SSLP
 181 #define SPPCR_4 RSPI4.SPPCR
 182 #define SPSR_4 RSPI4.SPSR
 183 #define SPDR_4   RSPI4.SPDR.UINT32
 184 #define SPDR_4L  RSPI4.SPDR.UINT16[L]
 185 #define SPDR_4H  RSPI4.SPDR.UINT16[H]
 186 #define SPDR_4LL RSPI4.SPDR.UINT8[LL]
 187 #define SPDR_4LH RSPI4.SPDR.UINT8[LH]
 188 #define SPDR_4HL RSPI4.SPDR.UINT8[HL]
 189 #define SPDR_4HH RSPI4.SPDR.UINT8[HH]
 190 #define SPSCR_4 RSPI4.SPSCR
 191 #define SPSSR_4 RSPI4.SPSSR
 192 #define SPBR_4 RSPI4.SPBR
 193 #define SPDCR_4 RSPI4.SPDCR
 194 #define SPCKD_4 RSPI4.SPCKD
 195 #define SSLND_4 RSPI4.SSLND
 196 #define SPND_4 RSPI4.SPND
 197 #define SPCMD0_4 RSPI4.SPCMD0
 198 #define SPCMD1_4 RSPI4.SPCMD1
 199 #define SPCMD2_4 RSPI4.SPCMD2
 200 #define SPCMD3_4 RSPI4.SPCMD3
 201 #define SPBFCR_4 RSPI4.SPBFCR
 202 #define SPBFDR_4 RSPI4.SPBFDR
 203 /* <-SEC M1.10.1 */
 204 #endif