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[tmk_keyboard.git] / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_STM / TARGET_STM32F0 / TARGET_DISCO_F051R8 / stm32f051x8.h
1 /**
2 ******************************************************************************
3 * @file stm32f051x8.h
4 * @author MCD Application Team
5 * @version V2.1.0
6 * @date 03-Oct-2014
7 * @brief CMSIS STM32F051x4/STM32F051x6/STM32F051x8 devices Peripheral Access
8 * Layer Header File.
9 *
10 * This file contains:
11 * - Data structures and the address mapping for all peripherals
12 * - Peripheral's registers declarations and bits definition
13 * - Macros to access peripheral\92s registers hardware
14 *
15 ******************************************************************************
16 * @attention
17 *
18 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
19 *
20 * Redistribution and use in source and binary forms, with or without modification,
21 * are permitted provided that the following conditions are met:
22 * 1. Redistributions of source code must retain the above copyright notice,
23 * this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright notice,
25 * this list of conditions and the following disclaimer in the documentation
26 * and/or other materials provided with the distribution.
27 * 3. Neither the name of STMicroelectronics nor the names of its contributors
28 * may be used to endorse or promote products derived from this software
29 * without specific prior written permission.
30 *
31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
32 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
34 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
37 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
38 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
39 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 *
42 ******************************************************************************
43 */
44
45 /** @addtogroup CMSIS_Device
46 * @{
47 */
48
49 /** @addtogroup stm32f051x8
50 * @{
51 */
52
53 #ifndef __STM32F051x8_H
54 #define __STM32F051x8_H
55
56 #ifdef __cplusplus
57 extern "C" {
58 #endif /* __cplusplus */
59
60 /** @addtogroup Configuration_section_for_CMSIS
61 * @{
62 */
63
64 /**
65 * @brief Configuration of the Cortex-M0 Processor and Core Peripherals
66 */
67 #define __CM0_REV 0 /*!< Core Revision r0p0 */
68 #define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
69 #define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
70 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
71
72 /**
73 * @}
74 */
75
76 /** @addtogroup Peripheral_interrupt_number_definition
77 * @{
78 */
79
80 /**
81 * @brief STM32F051x4/STM32F051x6/STM32F051x8 device Interrupt Number Definition
82 */
83 typedef enum
84 {
85 /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
86 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
87 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
88 SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
89 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
90 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
91
92 /****** STM32F051x4/STM32F051x6/STM32F051x8 specific Interrupt Numbers **************************************/
93 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
94 PVD_IRQn = 1, /*!< PVD Interrupt through EXTI Lines 16 */
95 RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */
96 FLASH_IRQn = 3, /*!< FLASH global Interrupt */
97 RCC_IRQn = 4, /*!< RCC global Interrupt */
98 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
99 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
100 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
101 TSC_IRQn = 8, /*!< Touch Sensing Controller Interrupts */
102 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
103 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
104 DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
105 ADC1_COMP_IRQn = 12, /*!< ADC1 and COMP interrupts (ADC interrupt combined with EXTI Lines 21 and 22 */
106 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
107 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
108 TIM2_IRQn = 15, /*!< TIM2 global Interrupt */
109 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
110 TIM6_DAC_IRQn = 17, /*!< TIM6 global and DAC channel underrun error Interrupts */
111 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
112 TIM15_IRQn = 20, /*!< TIM15 global Interrupt */
113 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
114 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
115 I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
116 I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */
117 SPI1_IRQn = 25, /*!< SPI1 global Interrupt */
118 SPI2_IRQn = 26, /*!< SPI2 global Interrupt */
119 USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
120 USART2_IRQn = 28, /*!< USART2 global Interrupt */
121 CEC_CAN_IRQn = 30 /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt */
122 } IRQn_Type;
123
124 /**
125 * @}
126 */
127
128 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
129 #include "system_stm32f0xx.h" /* STM32F0xx System Header */
130 #include <stdint.h>
131
132 /** @addtogroup Peripheral_registers_structures
133 * @{
134 */
135
136 /**
137 * @brief Analog to Digital Converter
138 */
139
140 typedef struct
141 {
142 __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
143 __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
144 __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
145 __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
146 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
147 __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
148 uint32_t RESERVED1; /*!< Reserved, 0x18 */
149 uint32_t RESERVED2; /*!< Reserved, 0x1C */
150 __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
151 uint32_t RESERVED3; /*!< Reserved, 0x24 */
152 __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
153 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
154 __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
155 }ADC_TypeDef;
156
157 typedef struct
158 {
159 __IO uint32_t CCR;
160 }ADC_Common_TypeDef;
161
162 /**
163 * @brief HDMI-CEC
164 */
165
166 typedef struct
167 {
168 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
169 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
170 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
171 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
172 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
173 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
174 }CEC_TypeDef;
175
176 /**
177 * @brief Comparator
178 */
179
180 typedef struct
181 {
182 __IO uint32_t CSR; /*!< Comparator 1 & 2 control Status register, Address offset: 0x00 */
183 }COMP1_2_TypeDef;
184
185 typedef struct
186 {
187 __IO uint16_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
188 }COMP_TypeDef;
189
190 /**
191 * @brief CRC calculation unit
192 */
193
194 typedef struct
195 {
196 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
197 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
198 uint8_t RESERVED0; /*!< Reserved, 0x05 */
199 uint16_t RESERVED1; /*!< Reserved, 0x06 */
200 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
201 uint32_t RESERVED2; /*!< Reserved, 0x0C */
202 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
203 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
204 }CRC_TypeDef;
205
206 /**
207 * @brief Digital to Analog Converter
208 */
209
210 typedef struct
211 {
212 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
213 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
214 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
215 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
216 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
217 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
218 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
219 }DAC_TypeDef;
220
221 /**
222 * @brief Debug MCU
223 */
224
225 typedef struct
226 {
227 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
228 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
229 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
230 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
231 }DBGMCU_TypeDef;
232
233 /**
234 * @brief DMA Controller
235 */
236
237 typedef struct
238 {
239 __IO uint32_t CCR; /*!< DMA channel x configuration register */
240 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
241 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
242 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
243 }DMA_Channel_TypeDef;
244
245 typedef struct
246 {
247 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
248 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
249 }DMA_TypeDef;
250
251 /**
252 * @brief External Interrupt/Event Controller
253 */
254
255 typedef struct
256 {
257 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
258 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
259 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
260 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
261 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
262 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
263 }EXTI_TypeDef;
264
265 /**
266 * @brief FLASH Registers
267 */
268 typedef struct
269 {
270 __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
271 __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
272 __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
273 __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
274 __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
275 __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
276 __IO uint32_t RESERVED; /*!< Reserved, 0x18 */
277 __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
278 __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
279 }FLASH_TypeDef;
280
281
282 /**
283 * @brief Option Bytes Registers
284 */
285 typedef struct
286 {
287 __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
288 __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
289 __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
290 __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
291 __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
292 __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
293 __IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */
294 __IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */
295 }OB_TypeDef;
296
297 /**
298 * @brief General Purpose I/O
299 */
300
301 typedef struct
302 {
303 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
304 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
305 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
306 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
307 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
308 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
309 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
310 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
311 __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
312 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
313 }GPIO_TypeDef;
314
315 /**
316 * @brief SysTem Configuration
317 */
318
319 typedef struct
320 {
321 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
322 uint32_t RESERVED; /*!< Reserved, 0x04 */
323 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
324 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
325 }SYSCFG_TypeDef;
326
327 /**
328 * @brief Inter-integrated Circuit Interface
329 */
330
331 typedef struct
332 {
333 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
334 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
335 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
336 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
337 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
338 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
339 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
340 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
341 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
342 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
343 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
344 }I2C_TypeDef;
345
346 /**
347 * @brief Independent WATCHDOG
348 */
349
350 typedef struct
351 {
352 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
353 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
354 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
355 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
356 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
357 }IWDG_TypeDef;
358
359 /**
360 * @brief Power Control
361 */
362
363 typedef struct
364 {
365 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
366 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
367 }PWR_TypeDef;
368
369 /**
370 * @brief Reset and Clock Control
371 */
372 typedef struct
373 {
374 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
375 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
376 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
377 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
378 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
379 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
380 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
381 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
382 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
383 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
384 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
385 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
386 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
387 __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
388 }RCC_TypeDef;
389
390 /**
391 * @brief Real-Time Clock
392 */
393
394 typedef struct
395 {
396 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
397 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
398 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
399 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
400 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
401 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
402 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */
403 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
404 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x20 */
405 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
406 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
407 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
408 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
409 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
410 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
411 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
412 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
413 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
414 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x48 */
415 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x4C */
416 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
417 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
418 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
419 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
420 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
421 }RTC_TypeDef;
422
423 /**
424 * @brief Serial Peripheral Interface
425 */
426
427 typedef struct
428 {
429 __IO uint16_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
430 uint16_t RESERVED0; /*!< Reserved, 0x02 */
431 __IO uint16_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
432 uint16_t RESERVED1; /*!< Reserved, 0x06 */
433 __IO uint16_t SR; /*!< SPI Status register, Address offset: 0x08 */
434 uint16_t RESERVED2; /*!< Reserved, 0x0A */
435 __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
436 uint16_t RESERVED3; /*!< Reserved, 0x0E */
437 __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
438 uint16_t RESERVED4; /*!< Reserved, 0x12 */
439 __IO uint16_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
440 uint16_t RESERVED5; /*!< Reserved, 0x16 */
441 __IO uint16_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
442 uint16_t RESERVED6; /*!< Reserved, 0x1A */
443 __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
444 uint16_t RESERVED7; /*!< Reserved, 0x1E */
445 __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
446 uint16_t RESERVED8; /*!< Reserved, 0x22 */
447 }SPI_TypeDef;
448
449 /**
450 * @brief TIM
451 */
452 typedef struct
453 {
454 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
455 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
456 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
457 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
458 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
459 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
460 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
461 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
462 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
463 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
464 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
465 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
466 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
467 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
468 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
469 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
470 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
471 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
472 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
473 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
474 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
475 }TIM_TypeDef;
476
477 /**
478 * @brief Touch Sensing Controller (TSC)
479 */
480 typedef struct
481 {
482 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
483 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
484 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
485 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
486 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
487 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
488 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
489 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
490 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
491 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
492 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
493 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
494 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
495 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
496 }TSC_TypeDef;
497
498 /**
499 * @brief Universal Synchronous Asynchronous Receiver Transmitter
500 */
501
502 typedef struct
503 {
504 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
505 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
506 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
507 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
508 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
509 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
510 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
511 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
512 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
513 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
514 uint16_t RESERVED1; /*!< Reserved, 0x26 */
515 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
516 uint16_t RESERVED2; /*!< Reserved, 0x2A */
517 }USART_TypeDef;
518
519 /**
520 * @brief Window WATCHDOG
521 */
522 typedef struct
523 {
524 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
525 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
526 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
527 }WWDG_TypeDef;
528
529 /**
530 * @}
531 */
532
533 /** @addtogroup Peripheral_memory_map
534 * @{
535 */
536
537 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
538 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
539 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
540
541 /*!< Peripheral memory map */
542 #define APBPERIPH_BASE PERIPH_BASE
543 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
544 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
545
546 #define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
547 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
548 #define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
549 #define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
550 #define RTC_BASE (APBPERIPH_BASE + 0x00002800)
551 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
552 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
553 #define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
554 #define USART2_BASE (APBPERIPH_BASE + 0x00004400)
555 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
556 #define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
557 #define PWR_BASE (APBPERIPH_BASE + 0x00007000)
558 #define DAC_BASE (APBPERIPH_BASE + 0x00007400)
559 #define CEC_BASE (APBPERIPH_BASE + 0x00007800)
560
561 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
562 #define COMP_BASE (APBPERIPH_BASE + 0x0001001C)
563 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
564 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
565 #define ADC_BASE (APBPERIPH_BASE + 0x00012708)
566 #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
567 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
568 #define USART1_BASE (APBPERIPH_BASE + 0x00013800)
569 #define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
570 #define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
571 #define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
572 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
573
574 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
575 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
576 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
577 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
578 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
579 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
580
581 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
582 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
583 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< FLASH Option Bytes base address */
584 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
585 #define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
586
587 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
588 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
589 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
590 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
591 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
592
593 /**
594 * @}
595 */
596
597 /** @addtogroup Peripheral_declaration
598 * @{
599 */
600
601 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
602 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
603 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
604 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
605 #define RTC ((RTC_TypeDef *) RTC_BASE)
606 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
607 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
608 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
609 #define USART2 ((USART_TypeDef *) USART2_BASE)
610 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
611 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
612 #define PWR ((PWR_TypeDef *) PWR_BASE)
613 #define DAC ((DAC_TypeDef *) DAC_BASE)
614 #define CEC ((CEC_TypeDef *) CEC_BASE)
615 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
616 #define COMP ((COMP1_2_TypeDef *) COMP_BASE)
617 #define COMP1 ((COMP_TypeDef *) COMP_BASE)
618 #define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000002))
619 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
620 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
621 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
622 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
623 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
624 #define USART1 ((USART_TypeDef *) USART1_BASE)
625 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
626 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
627 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
628 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
629 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
630 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
631 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
632 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
633 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
634 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
635 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
636 #define OB ((OB_TypeDef *) OB_BASE)
637 #define RCC ((RCC_TypeDef *) RCC_BASE)
638 #define CRC ((CRC_TypeDef *) CRC_BASE)
639 #define TSC ((TSC_TypeDef *) TSC_BASE)
640 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
641 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
642 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
643 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
644 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
645
646 /**
647 * @}
648 */
649
650 /** @addtogroup Exported_constants
651 * @{
652 */
653
654 /** @addtogroup Peripheral_Registers_Bits_Definition
655 * @{
656 */
657
658 /******************************************************************************/
659 /* Peripheral Registers Bits Definition */
660 /******************************************************************************/
661 /******************************************************************************/
662 /* */
663 /* Analog to Digital Converter (ADC) */
664 /* */
665 /******************************************************************************/
666 /******************** Bits definition for ADC_ISR register ******************/
667 #define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
668 #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
669 #define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
670 #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
671 #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
672 #define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
673
674 /* Old EOSEQ bit definition, maintained for legacy purpose */
675 #define ADC_ISR_EOS ADC_ISR_EOSEQ
676
677 /******************** Bits definition for ADC_IER register ******************/
678 #define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
679 #define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
680 #define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
681 #define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
682 #define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
683 #define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
684
685 /* Old EOSEQIE bit definition, maintained for legacy purpose */
686 #define ADC_IER_EOSIE ADC_IER_EOSEQIE
687
688 /******************** Bits definition for ADC_CR register *******************/
689 #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
690 #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
691 #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
692 #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
693 #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */
694
695 /******************* Bits definition for ADC_CFGR1 register *****************/
696 #define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
697 #define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
698 #define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
699 #define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
700 #define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
701 #define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
702 #define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
703 #define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
704 #define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
705 #define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
706 #define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
707 #define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
708 #define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
709 #define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
710 #define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
711 #define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
712 #define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
713 #define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
714 #define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
715 #define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
716 #define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
717 #define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
718 #define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
719 #define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
720 #define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
721 #define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
722 #define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
723
724 /* Old WAIT bit definition, maintained for legacy purpose */
725 #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
726
727 /******************* Bits definition for ADC_CFGR2 register *****************/
728 #define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< ADC clock mode */
729 #define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< ADC clocked by PCLK div4 */
730 #define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< ADC clocked by PCLK div2 */
731
732 /* Old bit definition, maintained for legacy purpose */
733 #define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /*!< ADC clocked by PCLK div4 */
734 #define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /*!< ADC clocked by PCLK div2 */
735
736 /****************** Bit definition for ADC_SMPR register ********************/
737 #define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMP[2:0] bits (Sampling time selection) */
738 #define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
739 #define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
740 #define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
741
742 /* Old bit definition, maintained for legacy purpose */
743 #define ADC_SMPR1_SMPR ADC_SMPR_SMP /*!< SMP[2:0] bits (Sampling time selection) */
744 #define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /*!< Bit 0 */
745 #define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /*!< Bit 1 */
746 #define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /*!< Bit 2 */
747
748 /******************* Bit definition for ADC_TR register ********************/
749 #define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
750 #define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
751
752 /* Old bit definition, maintained for legacy purpose */
753 #define ADC_HTR_HT ADC_TR_HT /*!< Analog watchdog high threshold */
754 #define ADC_LTR_LT ADC_TR_LT /*!< Analog watchdog low threshold */
755
756 /****************** Bit definition for ADC_CHSELR register ******************/
757 #define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
758 #define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
759 #define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
760 #define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
761 #define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
762 #define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
763 #define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
764 #define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
765 #define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
766 #define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
767 #define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
768 #define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
769 #define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
770 #define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
771 #define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
772 #define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
773 #define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
774 #define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
775 #define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
776
777 /******************** Bit definition for ADC_DR register ********************/
778 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
779
780 /******************* Bit definition for ADC_CCR register ********************/
781 #define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
782 #define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
783 #define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
784
785
786 /******************************************************************************/
787 /* */
788 /* HDMI-CEC (CEC) */
789 /* */
790 /******************************************************************************/
791
792 /******************* Bit definition for CEC_CR register *********************/
793 #define CEC_CR_CECEN ((uint32_t)0x00000001) /*!< CEC Enable */
794 #define CEC_CR_TXSOM ((uint32_t)0x00000002) /*!< CEC Tx Start Of Message */
795 #define CEC_CR_TXEOM ((uint32_t)0x00000004) /*!< CEC Tx End Of Message */
796
797 /******************* Bit definition for CEC_CFGR register *******************/
798 #define CEC_CFGR_SFT ((uint32_t)0x00000007) /*!< CEC Signal Free Time */
799 #define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /*!< CEC Tolerance */
800 #define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /*!< CEC Rx Stop */
801 #define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /*!< CEC Bit Rising Error generation */
802 #define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040) /*!< CEC Long Bit Period Error gener. */
803 #define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /*!< CEC Broadcast No Error generation */
804 #define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /*!< CEC Signal Free Time optional */
805 #define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /*!< CEC Own Address */
806 #define CEC_CFGR_LSTN ((uint32_t)0x80000000) /*!< CEC Listen mode */
807
808 /******************* Bit definition for CEC_TXDR register *******************/
809 #define CEC_TXDR_TXD ((uint32_t)0x000000FF) /*!< CEC Tx Data */
810
811 /******************* Bit definition for CEC_RXDR register *******************/
812 #define CEC_TXDR_RXD ((uint32_t)0x000000FF) /*!< CEC Rx Data */
813
814 /******************* Bit definition for CEC_ISR register ********************/
815 #define CEC_ISR_RXBR ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received */
816 #define CEC_ISR_RXEND ((uint32_t)0x00000002) /*!< CEC End Of Reception */
817 #define CEC_ISR_RXOVR ((uint32_t)0x00000004) /*!< CEC Rx-Overrun */
818 #define CEC_ISR_BRE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error */
819 #define CEC_ISR_SBPE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error */
820 #define CEC_ISR_LBPE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error */
821 #define CEC_ISR_RXACKE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge */
822 #define CEC_ISR_ARBLST ((uint32_t)0x00000080) /*!< CEC Arbitration Lost */
823 #define CEC_ISR_TXBR ((uint32_t)0x00000100) /*!< CEC Tx Byte Request */
824 #define CEC_ISR_TXEND ((uint32_t)0x00000200) /*!< CEC End of Transmission */
825 #define CEC_ISR_TXUDR ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun */
826 #define CEC_ISR_TXERR ((uint32_t)0x00000800) /*!< CEC Tx-Error */
827 #define CEC_ISR_TXACKE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge */
828
829 /******************* Bit definition for CEC_IER register ********************/
830 #define CEC_IER_RXBRIE ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received IT Enable */
831 #define CEC_IER_RXENDIE ((uint32_t)0x00000002) /*!< CEC End Of Reception IT Enable */
832 #define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /*!< CEC Rx-Overrun IT Enable */
833 #define CEC_IER_BREIE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error IT Enable */
834 #define CEC_IER_SBPEIE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error IT Enable*/
835 #define CEC_IER_LBPEIE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error IT Enable */
836 #define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge IT Enable */
837 #define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /*!< CEC Arbitration Lost IT Enable */
838 #define CEC_IER_TXBRIE ((uint32_t)0x00000100) /*!< CEC Tx Byte Request IT Enable */
839 #define CEC_IER_TXENDIE ((uint32_t)0x00000200) /*!< CEC End of Transmission IT Enable */
840 #define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun IT Enable */
841 #define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
842 #define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
843
844
845 /******************************************************************************/
846 /* */
847 /* Analog Comparators (COMP) */
848 /* */
849 /******************************************************************************/
850 /*********************** Bit definition for COMP_CSR register ***************/
851 /* COMP1 bits definition */
852 #define COMP_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
853 #define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< SW1 switch control */
854 #define COMP_CSR_COMP1MODE ((uint32_t)0x0000000C) /*!< COMP1 power mode */
855 #define COMP_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */
856 #define COMP_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */
857 #define COMP_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
858 #define COMP_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
859 #define COMP_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
860 #define COMP_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
861 #define COMP_CSR_COMP1OUTSEL ((uint32_t)0x00000700) /*!< COMP1 output select */
862 #define COMP_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000100) /*!< COMP1 output select bit 0 */
863 #define COMP_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000200) /*!< COMP1 output select bit 1 */
864 #define COMP_CSR_COMP1OUTSEL_2 ((uint32_t)0x00000400) /*!< COMP1 output select bit 2 */
865 #define COMP_CSR_COMP1POL ((uint32_t)0x00000800) /*!< COMP1 output polarity */
866 #define COMP_CSR_COMP1HYST ((uint32_t)0x00003000) /*!< COMP1 hysteresis */
867 #define COMP_CSR_COMP1HYST_0 ((uint32_t)0x00001000) /*!< COMP1 hysteresis bit 0 */
868 #define COMP_CSR_COMP1HYST_1 ((uint32_t)0x00002000) /*!< COMP1 hysteresis bit 1 */
869 #define COMP_CSR_COMP1OUT ((uint32_t)0x00004000) /*!< COMP1 output level */
870 #define COMP_CSR_COMP1LOCK ((uint32_t)0x00008000) /*!< COMP1 lock */
871 /* COMP2 bits definition */
872 #define COMP_CSR_COMP2EN ((uint32_t)0x00010000) /*!< COMP2 enable */
873 #define COMP_CSR_COMP2MODE ((uint32_t)0x000C0000) /*!< COMP2 power mode */
874 #define COMP_CSR_COMP2MODE_0 ((uint32_t)0x00040000) /*!< COMP2 power mode bit 0 */
875 #define COMP_CSR_COMP2MODE_1 ((uint32_t)0x00080000) /*!< COMP2 power mode bit 1 */
876 #define COMP_CSR_COMP2INSEL ((uint32_t)0x00700000) /*!< COMP2 inverting input select */
877 #define COMP_CSR_COMP2INSEL_0 ((uint32_t)0x00100000) /*!< COMP2 inverting input select bit 0 */
878 #define COMP_CSR_COMP2INSEL_1 ((uint32_t)0x00200000) /*!< COMP2 inverting input select bit 1 */
879 #define COMP_CSR_COMP2INSEL_2 ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 2 */
880 #define COMP_CSR_WNDWEN ((uint32_t)0x00800000) /*!< Comparators window mode enable */
881 #define COMP_CSR_COMP2OUTSEL ((uint32_t)0x07000000) /*!< COMP2 output select */
882 #define COMP_CSR_COMP2OUTSEL_0 ((uint32_t)0x01000000) /*!< COMP2 output select bit 0 */
883 #define COMP_CSR_COMP2OUTSEL_1 ((uint32_t)0x02000000) /*!< COMP2 output select bit 1 */
884 #define COMP_CSR_COMP2OUTSEL_2 ((uint32_t)0x04000000) /*!< COMP2 output select bit 2 */
885 #define COMP_CSR_COMP2POL ((uint32_t)0x08000000) /*!< COMP2 output polarity */
886 #define COMP_CSR_COMP2HYST ((uint32_t)0x30000000) /*!< COMP2 hysteresis */
887 #define COMP_CSR_COMP2HYST_0 ((uint32_t)0x10000000) /*!< COMP2 hysteresis bit 0 */
888 #define COMP_CSR_COMP2HYST_1 ((uint32_t)0x20000000) /*!< COMP2 hysteresis bit 1 */
889 #define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
890 #define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
891 /* COMPx bits definition */
892 #define COMP_CSR_COMPxEN ((uint16_t)0x0001) /*!< COMPx enable */
893 #define COMP_CSR_COMPxMODE ((uint16_t)0x000C) /*!< COMPx power mode */
894 #define COMP_CSR_COMPxMODE_0 ((uint16_t)0x0004) /*!< COMPx power mode bit 0 */
895 #define COMP_CSR_COMPxMODE_1 ((uint16_t)0x0008) /*!< COMPx power mode bit 1 */
896 #define COMP_CSR_COMPxINSEL ((uint16_t)0x0070) /*!< COMPx inverting input select */
897 #define COMP_CSR_COMPxINSEL_0 ((uint16_t)0x0010) /*!< COMPx inverting input select bit 0 */
898 #define COMP_CSR_COMPxINSEL_1 ((uint16_t)0x0020) /*!< COMPx inverting input select bit 1 */
899 #define COMP_CSR_COMPxINSEL_2 ((uint16_t)0x0040) /*!< COMPx inverting input select bit 2 */
900 #define COMP_CSR_COMPxOUTSEL ((uint16_t)0x0700) /*!< COMPx output select */
901 #define COMP_CSR_COMPxOUTSEL_0 ((uint16_t)0x0100) /*!< COMPx output select bit 0 */
902 #define COMP_CSR_COMPxOUTSEL_1 ((uint16_t)0x0200) /*!< COMPx output select bit 1 */
903 #define COMP_CSR_COMPxOUTSEL_2 ((uint16_t)0x0400) /*!< COMPx output select bit 2 */
904 #define COMP_CSR_COMPxPOL ((uint16_t)0x0800) /*!< COMPx output polarity */
905 #define COMP_CSR_COMPxHYST ((uint16_t)0x3000) /*!< COMPx hysteresis */
906 #define COMP_CSR_COMPxHYST_0 ((uint16_t)0x1000) /*!< COMPx hysteresis bit 0 */
907 #define COMP_CSR_COMPxHYST_1 ((uint16_t)0x2000) /*!< COMPx hysteresis bit 1 */
908 #define COMP_CSR_COMPxOUT ((uint16_t)0x4000) /*!< COMPx output level */
909 #define COMP_CSR_COMPxLOCK ((uint16_t)0x8000) /*!< COMPx lock */
910
911 /******************************************************************************/
912 /* */
913 /* CRC calculation unit (CRC) */
914 /* */
915 /******************************************************************************/
916 /******************* Bit definition for CRC_DR register *********************/
917 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
918
919 /******************* Bit definition for CRC_IDR register ********************/
920 #define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
921
922 /******************** Bit definition for CRC_CR register ********************/
923 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
924 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
925 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
926 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
927 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
928
929 /******************* Bit definition for CRC_INIT register *******************/
930 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
931
932
933 /******************************************************************************/
934 /* */
935 /* Digital to Analog Converter (DAC) */
936 /* */
937 /******************************************************************************/
938 /******************** Bit definition for DAC_CR register ********************/
939 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
940 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
941 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
942
943 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
944 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
945 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
946 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
947
948 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
949 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA Underrun Interrupt enable */
950
951
952 /***************** Bit definition for DAC_SWTRIGR register ******************/
953 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
954
955 /***************** Bit definition for DAC_DHR12R1 register ******************/
956 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
957
958 /***************** Bit definition for DAC_DHR12L1 register ******************/
959 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
960
961 /****************** Bit definition for DAC_DHR8R1 register ******************/
962 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
963
964 /***************** Bit definition for DAC_DHR12RD register ******************/
965 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
966
967 /***************** Bit definition for DAC_DHR12LD register ******************/
968 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
969
970 /****************** Bit definition for DAC_DHR8RD register ******************/
971 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
972
973 /******************* Bit definition for DAC_DOR1 register *******************/
974 #define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */
975
976 /******************** Bit definition for DAC_SR register ********************/
977 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
978
979
980 /******************************************************************************/
981 /* */
982 /* Debug MCU (DBGMCU) */
983 /* */
984 /******************************************************************************/
985
986 /**************** Bit definition for DBGMCU_IDCODE register *****************/
987 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
988
989 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
990 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
991 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
992 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
993 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
994 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
995 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
996 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
997 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
998 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
999 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
1000 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
1001 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
1002 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
1003 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
1004 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
1005 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
1006
1007 /****************** Bit definition for DBGMCU_CR register *******************/
1008 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
1009 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
1010
1011 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
1012 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
1013 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
1014 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted (not available on STM32F042 devices)*/
1015 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /*!< TIM14 counter stopped when core is halted */
1016 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
1017 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
1018 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
1019 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
1020
1021 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
1022 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /*!< TIM1 counter stopped when core is halted */
1023 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) /*!< TIM15 counter stopped when core is halted (not available on STM32F042 devices) */
1024 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /*!< TIM16 counter stopped when core is halted */
1025 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /*!< TIM17 counter stopped when core is halted */
1026
1027 /******************************************************************************/
1028 /* */
1029 /* DMA Controller (DMA) */
1030 /* */
1031 /******************************************************************************/
1032 /******************* Bit definition for DMA_ISR register ********************/
1033 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
1034 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
1035 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
1036 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
1037 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
1038 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
1039 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
1040 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
1041 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
1042 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
1043 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
1044 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
1045 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
1046 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
1047 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
1048 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
1049 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
1050 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
1051 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
1052 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
1053
1054 /******************* Bit definition for DMA_IFCR register *******************/
1055 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
1056 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
1057 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
1058 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
1059 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
1060 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
1061 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
1062 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
1063 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
1064 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
1065 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
1066 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
1067 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
1068 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
1069 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
1070 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
1071 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
1072 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
1073 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
1074 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
1075
1076 /******************* Bit definition for DMA_CCR register ********************/
1077 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
1078 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
1079 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
1080 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
1081 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
1082 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
1083 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
1084 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
1085
1086 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
1087 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
1088 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
1089
1090 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
1091 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
1092 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
1093
1094 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
1095 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
1096 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
1097
1098 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
1099
1100 /****************** Bit definition for DMA_CNDTR register *******************/
1101 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
1102
1103 /****************** Bit definition for DMA_CPAR register ********************/
1104 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
1105
1106 /****************** Bit definition for DMA_CMAR register ********************/
1107 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
1108
1109 /******************************************************************************/
1110 /* */
1111 /* External Interrupt/Event Controller (EXTI) */
1112 /* */
1113 /******************************************************************************/
1114 /******************* Bit definition for EXTI_IMR register *******************/
1115 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
1116 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
1117 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
1118 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
1119 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
1120 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
1121 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
1122 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
1123 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
1124 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
1125 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
1126 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
1127 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
1128 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
1129 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
1130 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
1131 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
1132 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
1133 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
1134 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
1135 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
1136 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
1137 #define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
1138 #define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
1139
1140 /****************** Bit definition for EXTI_EMR register ********************/
1141 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
1142 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
1143 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
1144 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
1145 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
1146 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
1147 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
1148 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
1149 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
1150 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
1151 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
1152 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
1153 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
1154 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
1155 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
1156 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
1157 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
1158 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
1159 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
1160 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
1161 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
1162 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
1163 #define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
1164 #define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
1165
1166 /******************* Bit definition for EXTI_RTSR register ******************/
1167 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
1168 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
1169 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
1170 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
1171 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
1172 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
1173 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
1174 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
1175 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
1176 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
1177 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
1178 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
1179 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
1180 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
1181 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
1182 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
1183 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
1184 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
1185 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
1186
1187 /******************* Bit definition for EXTI_FTSR register *******************/
1188 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
1189 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
1190 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
1191 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
1192 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
1193 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
1194 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
1195 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
1196 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
1197 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
1198 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
1199 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
1200 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
1201 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
1202 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
1203 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
1204 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
1205 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
1206 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
1207
1208 /******************* Bit definition for EXTI_SWIER register *******************/
1209 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
1210 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
1211 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
1212 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
1213 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
1214 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
1215 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
1216 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
1217 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
1218 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
1219 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
1220 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
1221 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
1222 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
1223 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
1224 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
1225 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
1226 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
1227 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
1228
1229 /****************** Bit definition for EXTI_PR register *********************/
1230 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
1231 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
1232 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
1233 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
1234 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
1235 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
1236 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
1237 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
1238 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
1239 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
1240 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
1241 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
1242 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
1243 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
1244 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
1245 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
1246 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
1247 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
1248 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
1249
1250 /******************************************************************************/
1251 /* */
1252 /* FLASH and Option Bytes Registers */
1253 /* */
1254 /******************************************************************************/
1255
1256 /******************* Bit definition for FLASH_ACR register ******************/
1257 #define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
1258
1259 #define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
1260 #define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
1261
1262 /****************** Bit definition for FLASH_KEYR register ******************/
1263 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
1264
1265 /***************** Bit definition for FLASH_OPTKEYR register ****************/
1266 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
1267
1268 /****************** FLASH Keys **********************************************/
1269 #define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
1270 #define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
1271 to unlock the write access to the FPEC. */
1272
1273 #define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
1274 #define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
1275 unlock the write access to the option byte block */
1276
1277 /****************** Bit definition for FLASH_SR register *******************/
1278 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
1279 #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
1280 #define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */
1281 #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
1282 #define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
1283
1284 /******************* Bit definition for FLASH_CR register *******************/
1285 #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
1286 #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
1287 #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
1288 #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
1289 #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
1290 #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
1291 #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
1292 #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
1293 #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
1294 #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
1295 #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< Option Bytes Loader Launch */
1296
1297 /******************* Bit definition for FLASH_AR register *******************/
1298 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
1299
1300 /****************** Bit definition for FLASH_OBR register *******************/
1301 #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
1302 #define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
1303 #define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
1304
1305 #define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */
1306 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
1307 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
1308 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
1309 #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
1310 #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
1311
1312 /* Old BOOT1 bit definition, maintained for legacy purpose */
1313 #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
1314
1315 /* Old OBR_VDDA bit definition, maintained for legacy purpose */
1316 #define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
1317
1318 /****************** Bit definition for FLASH_WRPR register ******************/
1319 #define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protect */
1320
1321 /*----------------------------------------------------------------------------*/
1322
1323 /****************** Bit definition for OB_RDP register **********************/
1324 #define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
1325 #define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
1326
1327 /****************** Bit definition for OB_USER register *********************/
1328 #define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
1329 #define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
1330
1331 /****************** Bit definition for OB_WRP0 register *********************/
1332 #define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
1333 #define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
1334
1335 /****************** Bit definition for OB_WRP1 register *********************/
1336 #define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
1337 #define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
1338
1339 /******************************************************************************/
1340 /* */
1341 /* General Purpose IOs (GPIO) */
1342 /* */
1343 /******************************************************************************/
1344 /******************* Bit definition for GPIO_MODER register *****************/
1345 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
1346 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
1347 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
1348 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
1349 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
1350 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
1351 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
1352 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
1353 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
1354 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
1355 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
1356 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
1357 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
1358 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
1359 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
1360 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
1361 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
1362 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
1363 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
1364 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
1365 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
1366 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
1367 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
1368 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
1369 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
1370 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
1371 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
1372 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
1373 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
1374 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
1375 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
1376 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
1377 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
1378 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
1379 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
1380 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
1381 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
1382 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
1383 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
1384 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
1385 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
1386 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
1387 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
1388 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
1389 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
1390 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
1391 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
1392 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
1393
1394 /****************** Bit definition for GPIO_OTYPER register *****************/
1395 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
1396 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
1397 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
1398 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
1399 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
1400 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
1401 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
1402 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
1403 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
1404 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
1405 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
1406 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
1407 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
1408 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
1409 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
1410 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
1411
1412 /**************** Bit definition for GPIO_OSPEEDR register ******************/
1413 #define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
1414 #define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
1415 #define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
1416 #define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
1417 #define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
1418 #define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
1419 #define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
1420 #define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
1421 #define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
1422 #define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
1423 #define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
1424 #define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
1425 #define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
1426 #define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
1427 #define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
1428 #define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
1429 #define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
1430 #define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
1431 #define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
1432 #define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
1433 #define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
1434 #define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
1435 #define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
1436 #define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
1437 #define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
1438 #define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
1439 #define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
1440 #define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
1441 #define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
1442 #define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
1443 #define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
1444 #define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
1445 #define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
1446 #define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
1447 #define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
1448 #define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
1449 #define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
1450 #define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
1451 #define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
1452 #define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
1453 #define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
1454 #define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
1455 #define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
1456 #define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
1457 #define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
1458 #define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
1459 #define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
1460 #define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
1461
1462 /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
1463 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
1464 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
1465 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
1466 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
1467 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
1468 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
1469 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
1470 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
1471 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
1472 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
1473 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
1474 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
1475 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
1476 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
1477 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
1478 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
1479 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
1480 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
1481 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
1482 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
1483 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
1484 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
1485 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
1486 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
1487 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
1488 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
1489 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
1490 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
1491 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
1492 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
1493 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
1494 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
1495 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
1496 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
1497 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
1498 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
1499 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
1500 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
1501 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
1502 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
1503 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
1504 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
1505 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
1506 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
1507 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
1508 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
1509 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
1510 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
1511
1512 /******************* Bit definition for GPIO_PUPDR register ******************/
1513 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
1514 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
1515 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
1516 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
1517 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
1518 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
1519 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
1520 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
1521 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
1522 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
1523 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
1524 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
1525 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
1526 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
1527 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
1528 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
1529 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
1530 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
1531 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
1532 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
1533 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
1534 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
1535 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
1536 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
1537 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
1538 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
1539 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
1540 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
1541 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
1542 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
1543 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
1544 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
1545 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
1546 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
1547 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
1548 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
1549 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
1550 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
1551 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
1552 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
1553 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
1554 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
1555 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
1556 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
1557 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
1558 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
1559 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
1560 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
1561
1562 /******************* Bit definition for GPIO_IDR register *******************/
1563 #define GPIO_IDR_0 ((uint32_t)0x00000001)
1564 #define GPIO_IDR_1 ((uint32_t)0x00000002)
1565 #define GPIO_IDR_2 ((uint32_t)0x00000004)
1566 #define GPIO_IDR_3 ((uint32_t)0x00000008)
1567 #define GPIO_IDR_4 ((uint32_t)0x00000010)
1568 #define GPIO_IDR_5 ((uint32_t)0x00000020)
1569 #define GPIO_IDR_6 ((uint32_t)0x00000040)
1570 #define GPIO_IDR_7 ((uint32_t)0x00000080)
1571 #define GPIO_IDR_8 ((uint32_t)0x00000100)
1572 #define GPIO_IDR_9 ((uint32_t)0x00000200)
1573 #define GPIO_IDR_10 ((uint32_t)0x00000400)
1574 #define GPIO_IDR_11 ((uint32_t)0x00000800)
1575 #define GPIO_IDR_12 ((uint32_t)0x00001000)
1576 #define GPIO_IDR_13 ((uint32_t)0x00002000)
1577 #define GPIO_IDR_14 ((uint32_t)0x00004000)
1578 #define GPIO_IDR_15 ((uint32_t)0x00008000)
1579
1580 /****************** Bit definition for GPIO_ODR register ********************/
1581 #define GPIO_ODR_0 ((uint32_t)0x00000001)
1582 #define GPIO_ODR_1 ((uint32_t)0x00000002)
1583 #define GPIO_ODR_2 ((uint32_t)0x00000004)
1584 #define GPIO_ODR_3 ((uint32_t)0x00000008)
1585 #define GPIO_ODR_4 ((uint32_t)0x00000010)
1586 #define GPIO_ODR_5 ((uint32_t)0x00000020)
1587 #define GPIO_ODR_6 ((uint32_t)0x00000040)
1588 #define GPIO_ODR_7 ((uint32_t)0x00000080)
1589 #define GPIO_ODR_8 ((uint32_t)0x00000100)
1590 #define GPIO_ODR_9 ((uint32_t)0x00000200)
1591 #define GPIO_ODR_10 ((uint32_t)0x00000400)
1592 #define GPIO_ODR_11 ((uint32_t)0x00000800)
1593 #define GPIO_ODR_12 ((uint32_t)0x00001000)
1594 #define GPIO_ODR_13 ((uint32_t)0x00002000)
1595 #define GPIO_ODR_14 ((uint32_t)0x00004000)
1596 #define GPIO_ODR_15 ((uint32_t)0x00008000)
1597
1598 /****************** Bit definition for GPIO_BSRR register ********************/
1599 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
1600 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
1601 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
1602 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
1603 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
1604 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
1605 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
1606 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
1607 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
1608 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
1609 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
1610 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
1611 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
1612 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
1613 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
1614 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
1615 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
1616 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
1617 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
1618 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
1619 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
1620 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
1621 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
1622 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
1623 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
1624 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
1625 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
1626 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
1627 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
1628 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
1629 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
1630 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
1631
1632 /****************** Bit definition for GPIO_LCKR register ********************/
1633 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
1634 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
1635 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
1636 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
1637 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
1638 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
1639 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
1640 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
1641 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
1642 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
1643 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
1644 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
1645 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
1646 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
1647 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
1648 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
1649 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
1650
1651 /****************** Bit definition for GPIO_AFRL register ********************/
1652 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
1653 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
1654 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
1655 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
1656 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
1657 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
1658 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
1659 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
1660
1661 /****************** Bit definition for GPIO_AFRH register ********************/
1662 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
1663 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
1664 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
1665 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
1666 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
1667 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
1668 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
1669 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
1670
1671 /****************** Bit definition for GPIO_BRR register *********************/
1672 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
1673 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
1674 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
1675 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
1676 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
1677 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
1678 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
1679 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
1680 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
1681 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
1682 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
1683 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
1684 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
1685 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
1686 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
1687 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
1688
1689 /******************************************************************************/
1690 /* */
1691 /* Inter-integrated Circuit Interface (I2C) */
1692 /* */
1693 /******************************************************************************/
1694
1695 /******************* Bit definition for I2C_CR1 register *******************/
1696 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
1697 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
1698 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
1699 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
1700 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
1701 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
1702 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
1703 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
1704 #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
1705 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
1706 #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
1707 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
1708 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
1709 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
1710 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
1711 #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
1712 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
1713 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
1714 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
1715 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
1716 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
1717
1718 /****************** Bit definition for I2C_CR2 register ********************/
1719 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
1720 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
1721 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
1722 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
1723 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
1724 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
1725 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
1726 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
1727 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
1728 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
1729 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
1730
1731 /******************* Bit definition for I2C_OAR1 register ******************/
1732 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
1733 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
1734 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
1735
1736 /******************* Bit definition for I2C_OAR2 register ******************/
1737 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
1738 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
1739 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
1740
1741 /******************* Bit definition for I2C_TIMINGR register ****************/
1742 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
1743 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
1744 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
1745 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
1746 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
1747
1748 /******************* Bit definition for I2C_TIMEOUTR register ****************/
1749 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
1750 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
1751 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
1752 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
1753 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
1754
1755 /****************** Bit definition for I2C_ISR register ********************/
1756 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
1757 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
1758 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
1759 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
1760 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
1761 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
1762 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
1763 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
1764 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
1765 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
1766 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
1767 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
1768 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
1769 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
1770 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
1771 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
1772 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
1773
1774 /****************** Bit definition for I2C_ICR register ********************/
1775 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
1776 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
1777 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
1778 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
1779 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
1780 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
1781 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
1782 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
1783 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
1784
1785 /****************** Bit definition for I2C_PECR register *******************/
1786 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
1787
1788 /****************** Bit definition for I2C_RXDR register *********************/
1789 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
1790
1791 /****************** Bit definition for I2C_TXDR register *******************/
1792 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
1793
1794 /*****************************************************************************/
1795 /* */
1796 /* Independent WATCHDOG (IWDG) */
1797 /* */
1798 /*****************************************************************************/
1799 /******************* Bit definition for IWDG_KR register *******************/
1800 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!< Key value (write only, read 0000h) */
1801
1802 /******************* Bit definition for IWDG_PR register *******************/
1803 #define IWDG_PR_PR ((uint32_t)0x07) /*!< PR[2:0] (Prescaler divider) */
1804 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!< Bit 0 */
1805 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!< Bit 1 */
1806 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!< Bit 2 */
1807
1808 /******************* Bit definition for IWDG_RLR register ******************/
1809 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!< Watchdog counter reload value */
1810
1811 /******************* Bit definition for IWDG_SR register *******************/
1812 #define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */
1813 #define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */
1814 #define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */
1815
1816 /******************* Bit definition for IWDG_KR register *******************/
1817 #define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */
1818
1819 /*****************************************************************************/
1820 /* */
1821 /* Power Control (PWR) */
1822 /* */
1823 /*****************************************************************************/
1824
1825 /******************** Bit definition for PWR_CR register *******************/
1826 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
1827 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
1828 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
1829 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
1830 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
1831
1832 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
1833 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
1834 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
1835 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
1836
1837 /*!< PVD level configuration */
1838 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
1839 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
1840 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
1841 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
1842 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
1843 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
1844 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
1845 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
1846
1847 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
1848
1849 /******************* Bit definition for PWR_CSR register *******************/
1850 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
1851 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
1852 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
1853 #define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
1854
1855 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
1856 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
1857
1858 /*****************************************************************************/
1859 /* */
1860 /* Reset and Clock Control */
1861 /* */
1862 /*****************************************************************************/
1863
1864 /******************** Bit definition for RCC_CR register *******************/
1865 #define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
1866 #define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
1867
1868 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
1869 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /*!<Bit 0 */
1870 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /*!<Bit 1 */
1871 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /*!<Bit 2 */
1872 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /*!<Bit 3 */
1873 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /*!<Bit 4 */
1874
1875 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
1876 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
1877 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
1878 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
1879 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
1880 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
1881 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
1882 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
1883 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /*!<Bit 7 */
1884
1885 #define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
1886 #define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
1887 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
1888 #define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
1889 #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
1890 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
1891
1892 /******************** Bit definition for RCC_CFGR register *****************/
1893 /*!< SW configuration */
1894 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
1895 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
1896 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
1897
1898 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
1899 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
1900 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
1901
1902 /*!< SWS configuration */
1903 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
1904 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
1905 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
1906
1907 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
1908 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
1909 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
1910
1911 /*!< HPRE configuration */
1912 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
1913 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
1914 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
1915 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
1916 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
1917
1918 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
1919 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
1920 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
1921 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
1922 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
1923 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
1924 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
1925 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
1926 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
1927
1928 /*!< PPRE configuration */
1929 #define RCC_CFGR_PPRE ((uint32_t)0x00000700) /*!< PRE[2:0] bits (APB prescaler) */
1930 #define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
1931 #define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
1932 #define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /*!< Bit 2 */
1933
1934 #define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
1935 #define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
1936 #define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
1937 #define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
1938 #define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
1939
1940 /*!< ADCPPRE configuration */
1941 #define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /*!< ADCPRE bit (ADC prescaler) */
1942
1943 #define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK divided by 2 */
1944 #define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK divided by 4 */
1945
1946 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
1947 #define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
1948 #define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
1949
1950 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
1951 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
1952 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
1953
1954 /*!< PLLMUL configuration */
1955 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
1956 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
1957 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
1958 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
1959 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
1960
1961 #define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
1962 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
1963 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
1964 #define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
1965 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
1966 #define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
1967 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
1968 #define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
1969 #define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
1970 #define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
1971 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
1972 #define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
1973 #define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
1974 #define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
1975 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
1976
1977 /*!< MCO configuration */
1978 #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
1979 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
1980 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
1981 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
1982
1983 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
1984 #define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /*!< HSI14 clock selected as MCO source */
1985 #define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
1986 #define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
1987 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
1988 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
1989 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
1990 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
1991
1992 /*!<****************** Bit definition for RCC_CIR register *****************/
1993 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
1994 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
1995 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
1996 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
1997 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
1998 #define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /*!< HSI14 Ready Interrupt flag */
1999 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
2000 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
2001 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
2002 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
2003 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
2004 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
2005 #define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /*!< HSI14 Ready Interrupt Enable */
2006 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
2007 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
2008 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
2009 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
2010 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
2011 #define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /*!< HSI14 Ready Interrupt Clear */
2012 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
2013
2014 /***************** Bit definition for RCC_APB2RSTR register ****************/
2015 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
2016 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /*!< ADC clock reset */
2017 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 clock reset */
2018 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
2019 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
2020 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 clock reset */
2021 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 clock reset */
2022 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 clock reset */
2023 #define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
2024
2025 /*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
2026 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
2027
2028 /***************** Bit definition for RCC_APB1RSTR register ****************/
2029 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 clock reset */
2030 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 clock reset */
2031 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 clock reset */
2032 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< Timer 14 clock reset */
2033 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
2034 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 clock reset */
2035 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 clock reset */
2036 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
2037 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 clock reset */
2038 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
2039 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC clock reset */
2040 #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC clock reset */
2041
2042 /****************** Bit definition for RCC_AHBENR register *****************/
2043 #define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
2044 #define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
2045 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
2046 #define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
2047 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
2048 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
2049 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
2050 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
2051 #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
2052 #define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS controller clock enable */
2053
2054 /* Old Bit definition maintained for legacy purpose */
2055 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
2056 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
2057
2058 /***************** Bit definition for RCC_APB2ENR register *****************/
2059 #define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /*!< SYSCFG and comparator clock enable */
2060 #define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
2061 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
2062 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
2063 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
2064 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
2065 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
2066 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
2067 #define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
2068
2069 /* Old Bit definition maintained for legacy purpose */
2070 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
2071 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
2072
2073 /***************** Bit definition for RCC_APB1ENR register *****************/
2074 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
2075 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
2076 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
2077 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< Timer 14 clock enable */
2078 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
2079 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
2080 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART2 clock enable */
2081 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
2082 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C2 clock enable */
2083 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
2084 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC clock enable */
2085 #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC clock enable */
2086
2087 /******************* Bit definition for RCC_BDCR register ******************/
2088 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
2089 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
2090 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
2091
2092 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
2093 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
2094 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
2095
2096 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
2097 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
2098 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
2099
2100 /*!< RTC configuration */
2101 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
2102 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
2103 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
2104 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
2105
2106 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
2107 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
2108
2109 /******************* Bit definition for RCC_CSR register *******************/
2110 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
2111 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
2112 #define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
2113 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
2114 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
2115 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
2116 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
2117 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
2118 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
2119 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
2120 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
2121
2122 /* Old Bit definition maintained for legacy purpose */
2123 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
2124
2125 /******************* Bit definition for RCC_AHBRSTR register ***************/
2126 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA clock reset */
2127 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB clock reset */
2128 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC clock reset */
2129 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD clock reset */
2130 #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF clock reset */
2131 #define RCC_AHBRSTR_TSCRST ((uint32_t)0x01000000) /*!< TS clock reset */
2132
2133 /* Old Bit definition maintained for legacy purpose */
2134 #define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */
2135
2136 /******************* Bit definition for RCC_CFGR2 register *****************/
2137 /*!< PREDIV configuration */
2138 #define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
2139 #define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
2140 #define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
2141 #define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
2142 #define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
2143
2144 #define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
2145 #define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
2146 #define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
2147 #define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
2148 #define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
2149 #define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
2150 #define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
2151 #define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
2152 #define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
2153 #define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
2154 #define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
2155 #define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
2156 #define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
2157 #define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
2158 #define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
2159 #define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
2160
2161 /******************* Bit definition for RCC_CFGR3 register *****************/
2162 /*!< USART1 Clock source selection */
2163 #define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
2164 #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
2165 #define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
2166
2167 #define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART1 clock source */
2168 #define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
2169 #define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
2170 #define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
2171
2172 /*!< I2C1 Clock source selection */
2173 #define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
2174
2175 #define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
2176 #define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
2177
2178 /*!< CEC Clock source selection */
2179 #define RCC_CFGR3_CECSW ((uint32_t)0x00000040) /*!< CECSW bits */
2180
2181 #define RCC_CFGR3_CECSW_HSI_DIV244 ((uint32_t)0x00000000) /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */
2182 #define RCC_CFGR3_CECSW_LSE ((uint32_t)0x00000040) /*!< LSE clock selected as HDMI CEC entry clock source */
2183
2184 /*!< USART2 Clock source selection */
2185 #define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
2186 #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
2187 #define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
2188
2189 #define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART2 clock source */
2190 #define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
2191 #define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
2192 #define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
2193
2194 /******************* Bit definition for RCC_CR2 register *******************/
2195 #define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */
2196 #define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */
2197 #define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /*!< Internal High Speed 14MHz clock disable */
2198 #define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /*!< Internal High Speed 14MHz clock trimming */
2199 #define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /*!< Internal High Speed 14MHz clock Calibration */
2200
2201 /*****************************************************************************/
2202 /* */
2203 /* Real-Time Clock (RTC) */
2204 /* */
2205 /*****************************************************************************/
2206 /******************** Bits definition for RTC_TR register ******************/
2207 #define RTC_TR_PM ((uint32_t)0x00400000)
2208 #define RTC_TR_HT ((uint32_t)0x00300000)
2209 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
2210 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
2211 #define RTC_TR_HU ((uint32_t)0x000F0000)
2212 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
2213 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
2214 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
2215 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
2216 #define RTC_TR_MNT ((uint32_t)0x00007000)
2217 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
2218 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
2219 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
2220 #define RTC_TR_MNU ((uint32_t)0x00000F00)
2221 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
2222 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
2223 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
2224 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
2225 #define RTC_TR_ST ((uint32_t)0x00000070)
2226 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
2227 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
2228 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
2229 #define RTC_TR_SU ((uint32_t)0x0000000F)
2230 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
2231 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
2232 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
2233 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
2234
2235 /******************** Bits definition for RTC_DR register ******************/
2236 #define RTC_DR_YT ((uint32_t)0x00F00000)
2237 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
2238 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
2239 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
2240 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
2241 #define RTC_DR_YU ((uint32_t)0x000F0000)
2242 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
2243 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
2244 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
2245 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
2246 #define RTC_DR_WDU ((uint32_t)0x0000E000)
2247 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
2248 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
2249 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
2250 #define RTC_DR_MT ((uint32_t)0x00001000)
2251 #define RTC_DR_MU ((uint32_t)0x00000F00)
2252 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
2253 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
2254 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
2255 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
2256 #define RTC_DR_DT ((uint32_t)0x00000030)
2257 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
2258 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
2259 #define RTC_DR_DU ((uint32_t)0x0000000F)
2260 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
2261 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
2262 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
2263 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
2264
2265 /******************** Bits definition for RTC_CR register ******************/
2266 #define RTC_CR_COE ((uint32_t)0x00800000)
2267 #define RTC_CR_OSEL ((uint32_t)0x00600000)
2268 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
2269 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
2270 #define RTC_CR_POL ((uint32_t)0x00100000)
2271 #define RTC_CR_COSEL ((uint32_t)0x00080000)
2272 #define RTC_CR_BCK ((uint32_t)0x00040000)
2273 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
2274 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
2275 #define RTC_CR_TSIE ((uint32_t)0x00008000)
2276 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
2277 #define RTC_CR_TSE ((uint32_t)0x00000800)
2278 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
2279 #define RTC_CR_FMT ((uint32_t)0x00000040)
2280 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
2281 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
2282 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
2283
2284 /******************** Bits definition for RTC_ISR register *****************/
2285 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
2286 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
2287 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
2288 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
2289 #define RTC_ISR_TSF ((uint32_t)0x00000800)
2290 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
2291 #define RTC_ISR_INIT ((uint32_t)0x00000080)
2292 #define RTC_ISR_INITF ((uint32_t)0x00000040)
2293 #define RTC_ISR_RSF ((uint32_t)0x00000020)
2294 #define RTC_ISR_INITS ((uint32_t)0x00000010)
2295 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
2296 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
2297
2298 /******************** Bits definition for RTC_PRER register ****************/
2299 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
2300 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
2301
2302 /******************** Bits definition for RTC_ALRMAR register **************/
2303 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
2304 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
2305 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
2306 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
2307 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
2308 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
2309 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
2310 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
2311 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
2312 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
2313 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
2314 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
2315 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
2316 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
2317 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
2318 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
2319 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
2320 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
2321 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
2322 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
2323 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
2324 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
2325 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
2326 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
2327 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
2328 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
2329 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
2330 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
2331 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
2332 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
2333 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
2334 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
2335 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
2336 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
2337 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
2338 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
2339 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
2340 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
2341 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
2342 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
2343
2344 /******************** Bits definition for RTC_WPR register *****************/
2345 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
2346
2347 /******************** Bits definition for RTC_SSR register *****************/
2348 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
2349
2350 /******************** Bits definition for RTC_SHIFTR register **************/
2351 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
2352 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
2353
2354 /******************** Bits definition for RTC_TSTR register ****************/
2355 #define RTC_TSTR_PM ((uint32_t)0x00400000)
2356 #define RTC_TSTR_HT ((uint32_t)0x00300000)
2357 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
2358 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
2359 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
2360 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
2361 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
2362 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
2363 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
2364 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
2365 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
2366 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
2367 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
2368 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
2369 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
2370 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
2371 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
2372 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
2373 #define RTC_TSTR_ST ((uint32_t)0x00000070)
2374 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
2375 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
2376 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
2377 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
2378 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
2379 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
2380 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
2381 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
2382
2383 /******************** Bits definition for RTC_TSDR register ****************/
2384 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
2385 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
2386 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
2387 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
2388 #define RTC_TSDR_MT ((uint32_t)0x00001000)
2389 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
2390 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
2391 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
2392 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
2393 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
2394 #define RTC_TSDR_DT ((uint32_t)0x00000030)
2395 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
2396 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
2397 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
2398 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
2399 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
2400 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
2401 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
2402
2403 /******************** Bits definition for RTC_TSSSR register ***************/
2404 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
2405
2406 /******************** Bits definition for RTC_CALR register ****************/
2407 #define RTC_CALR_CALP ((uint32_t)0x00008000)
2408 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
2409 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
2410 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
2411 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
2412 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
2413 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
2414 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
2415 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
2416 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
2417 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
2418 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
2419 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
2420
2421 /******************** Bits definition for RTC_TAFCR register ***************/
2422 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
2423 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
2424 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
2425 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
2426 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
2427 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
2428 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
2429 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
2430 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
2431 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
2432 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
2433 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
2434 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
2435 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
2436 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
2437 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
2438 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
2439 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
2440
2441 /******************** Bits definition for RTC_ALRMASSR register ************/
2442 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
2443 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
2444 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
2445 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
2446 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
2447 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
2448
2449 /******************** Bits definition for RTC_BKP0R register ***************/
2450 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
2451
2452 /******************** Bits definition for RTC_BKP1R register ***************/
2453 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
2454
2455 /******************** Bits definition for RTC_BKP2R register ***************/
2456 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
2457
2458 /******************** Bits definition for RTC_BKP3R register ***************/
2459 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
2460
2461 /******************** Bits definition for RTC_BKP4R register ***************/
2462 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
2463
2464 /******************** Number of backup registers ******************************/
2465 #define RTC_BKP_NUMBER ((uint32_t)0x00000005)
2466
2467 /*****************************************************************************/
2468 /* */
2469 /* Serial Peripheral Interface (SPI) */
2470 /* */
2471 /*****************************************************************************/
2472 /******************* Bit definition for SPI_CR1 register *******************/
2473 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
2474 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
2475 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
2476 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
2477 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
2478 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
2479 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
2480 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
2481 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
2482 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
2483 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
2484 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
2485 #define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
2486 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
2487 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
2488 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
2489 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
2490
2491 /******************* Bit definition for SPI_CR2 register *******************/
2492 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
2493 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
2494 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
2495 #define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
2496 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
2497 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
2498 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
2499 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
2500 #define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
2501 #define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
2502 #define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
2503 #define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
2504 #define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
2505 #define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
2506 #define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
2507 #define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
2508
2509 /******************** Bit definition for SPI_SR register *******************/
2510 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
2511 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
2512 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
2513 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
2514 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
2515 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
2516 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
2517 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
2518 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
2519 #define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
2520 #define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
2521 #define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
2522 #define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
2523 #define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
2524 #define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
2525
2526 /******************** Bit definition for SPI_DR register *******************/
2527 #define SPI_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data Register */
2528
2529 /******************* Bit definition for SPI_CRCPR register *****************/
2530 #define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFFFFFF) /*!< CRC polynomial register */
2531
2532 /****************** Bit definition for SPI_RXCRCR register *****************/
2533 #define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFFFFFF) /*!< Rx CRC Register */
2534
2535 /****************** Bit definition for SPI_TXCRCR register *****************/
2536 #define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFFFFFF) /*!< Tx CRC Register */
2537
2538 /****************** Bit definition for SPI_I2SCFGR register ****************/
2539 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
2540 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
2541 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
2542 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
2543 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
2544 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
2545 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
2546 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
2547 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
2548 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
2549 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
2550 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
2551 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
2552 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
2553
2554 /****************** Bit definition for SPI_I2SPR register ******************/
2555 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
2556 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
2557 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
2558
2559 /*****************************************************************************/
2560 /* */
2561 /* System Configuration (SYSCFG) */
2562 /* */
2563 /*****************************************************************************/
2564 /***************** Bit definition for SYSCFG_CFGR1 register ****************/
2565 #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
2566 #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
2567 #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
2568
2569 #define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00001F00) /*!< DMA remap mask */
2570 #define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
2571 #define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
2572 #define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
2573 #define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
2574 #define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
2575
2576 #define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
2577 #define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
2578 #define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
2579 #define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
2580
2581 /***************** Bit definition for SYSCFG_EXTICR1 register **************/
2582 #define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
2583 #define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
2584 #define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
2585 #define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
2586
2587 /**
2588 * @brief EXTI0 configuration
2589 */
2590 #define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
2591 #define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
2592 #define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
2593 #define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
2594 #define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
2595
2596 /**
2597 * @brief EXTI1 configuration
2598 */
2599 #define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
2600 #define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
2601 #define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
2602 #define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
2603 #define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
2604
2605 /**
2606 * @brief EXTI2 configuration
2607 */
2608 #define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
2609 #define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
2610 #define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
2611 #define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
2612 #define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
2613
2614 /**
2615 * @brief EXTI3 configuration
2616 */
2617 #define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
2618 #define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
2619 #define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
2620 #define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
2621 #define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
2622
2623 /***************** Bit definition for SYSCFG_EXTICR2 register **************/
2624 #define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
2625 #define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
2626 #define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
2627 #define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
2628
2629 /**
2630 * @brief EXTI4 configuration
2631 */
2632 #define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
2633 #define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
2634 #define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
2635 #define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
2636 #define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
2637
2638 /**
2639 * @brief EXTI5 configuration
2640 */
2641 #define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
2642 #define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
2643 #define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
2644 #define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
2645 #define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
2646
2647 /**
2648 * @brief EXTI6 configuration
2649 */
2650 #define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
2651 #define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
2652 #define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
2653 #define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
2654 #define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
2655
2656 /**
2657 * @brief EXTI7 configuration
2658 */
2659 #define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
2660 #define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
2661 #define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
2662 #define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
2663 #define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
2664
2665 /***************** Bit definition for SYSCFG_EXTICR3 register **************/
2666 #define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
2667 #define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
2668 #define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
2669 #define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
2670
2671 /**
2672 * @brief EXTI8 configuration
2673 */
2674 #define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
2675 #define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
2676 #define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
2677 #define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
2678 #define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */
2679
2680 /**
2681 * @brief EXTI9 configuration
2682 */
2683 #define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
2684 #define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
2685 #define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
2686 #define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
2687 #define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
2688
2689 /**
2690 * @brief EXTI10 configuration
2691 */
2692 #define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
2693 #define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
2694 #define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
2695 #define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
2696 #define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
2697
2698 /**
2699 * @brief EXTI11 configuration
2700 */
2701 #define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
2702 #define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
2703 #define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
2704 #define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
2705 #define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */
2706
2707 /***************** Bit definition for SYSCFG_EXTICR4 register **************/
2708 #define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
2709 #define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
2710 #define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
2711 #define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
2712
2713 /**
2714 * @brief EXTI12 configuration
2715 */
2716 #define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
2717 #define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
2718 #define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
2719 #define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
2720 #define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */
2721
2722 /**
2723 * @brief EXTI13 configuration
2724 */
2725 #define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
2726 #define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
2727 #define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
2728 #define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
2729 #define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */
2730
2731 /**
2732 * @brief EXTI14 configuration
2733 */
2734 #define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
2735 #define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
2736 #define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
2737 #define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
2738 #define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */
2739
2740 /**
2741 * @brief EXTI15 configuration
2742 */
2743 #define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
2744 #define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
2745 #define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
2746 #define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
2747 #define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */
2748
2749 /***************** Bit definition for SYSCFG_CFGR2 register ****************/
2750 #define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
2751 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
2752 #define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
2753 #define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
2754 #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
2755
2756 /*****************************************************************************/
2757 /* */
2758 /* Timers (TIM) */
2759 /* */
2760 /*****************************************************************************/
2761 /******************* Bit definition for TIM_CR1 register *******************/
2762 #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
2763 #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
2764 #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
2765 #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
2766 #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
2767
2768 #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
2769 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
2770 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
2771
2772 #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
2773
2774 #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
2775 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
2776 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
2777
2778 /******************* Bit definition for TIM_CR2 register *******************/
2779 #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
2780 #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
2781 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
2782
2783 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
2784 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
2785 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
2786 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
2787
2788 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
2789 #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
2790 #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
2791 #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
2792 #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
2793 #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
2794 #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
2795 #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
2796
2797 /******************* Bit definition for TIM_SMCR register ******************/
2798 #define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
2799 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
2800 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
2801 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
2802
2803 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
2804
2805 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
2806 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
2807 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
2808 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
2809
2810 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
2811
2812 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
2813 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
2814 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
2815 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
2816 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
2817
2818 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
2819 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
2820 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
2821
2822 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
2823 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
2824
2825 /******************* Bit definition for TIM_DIER register ******************/
2826 #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
2827 #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
2828 #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
2829 #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
2830 #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
2831 #define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
2832 #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
2833 #define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
2834 #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
2835 #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
2836 #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
2837 #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
2838 #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
2839 #define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
2840 #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
2841
2842 /******************** Bit definition for TIM_SR register *******************/
2843 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
2844 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
2845 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
2846 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
2847 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
2848 #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
2849 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
2850 #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
2851 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
2852 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
2853 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
2854 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
2855
2856 /******************* Bit definition for TIM_EGR register *******************/
2857 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
2858 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
2859 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
2860 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
2861 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
2862 #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
2863 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
2864 #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
2865
2866 /****************** Bit definition for TIM_CCMR1 register ******************/
2867 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
2868 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
2869 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
2870
2871 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
2872 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
2873
2874 #define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
2875 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
2876 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
2877 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
2878
2879 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
2880
2881 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
2882 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
2883 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
2884
2885 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
2886 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
2887
2888 #define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
2889 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
2890 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
2891 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
2892
2893 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
2894
2895 /*---------------------------------------------------------------------------*/
2896
2897 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
2898 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
2899 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
2900
2901 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
2902 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
2903 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
2904 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
2905 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
2906
2907 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
2908 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
2909 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
2910
2911 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
2912 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
2913 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
2914 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
2915 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
2916
2917 /****************** Bit definition for TIM_CCMR2 register ******************/
2918 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
2919 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
2920 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
2921
2922 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
2923 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
2924
2925 #define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
2926 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
2927 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
2928 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
2929
2930 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
2931
2932 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
2933 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
2934 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
2935
2936 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
2937 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
2938
2939 #define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
2940 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
2941 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
2942 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
2943
2944 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
2945
2946 /*---------------------------------------------------------------------------*/
2947
2948 #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
2949 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
2950 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
2951
2952 #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
2953 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
2954 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
2955 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
2956 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
2957
2958 #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
2959 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
2960 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
2961
2962 #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
2963 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
2964 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
2965 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
2966 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
2967
2968 /******************* Bit definition for TIM_CCER register ******************/
2969 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
2970 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
2971 #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
2972 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
2973 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
2974 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
2975 #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
2976 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
2977 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
2978 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
2979 #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
2980 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
2981 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
2982 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
2983 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
2984
2985 /******************* Bit definition for TIM_CNT register *******************/
2986 #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
2987
2988 /******************* Bit definition for TIM_PSC register *******************/
2989 #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
2990
2991 /******************* Bit definition for TIM_ARR register *******************/
2992 #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
2993
2994 /******************* Bit definition for TIM_RCR register *******************/
2995 #define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
2996
2997 /******************* Bit definition for TIM_CCR1 register ******************/
2998 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
2999
3000 /******************* Bit definition for TIM_CCR2 register ******************/
3001 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
3002
3003 /******************* Bit definition for TIM_CCR3 register ******************/
3004 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
3005
3006 /******************* Bit definition for TIM_CCR4 register ******************/
3007 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
3008
3009 /******************* Bit definition for TIM_BDTR register ******************/
3010 #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
3011 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3012 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3013 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3014 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3015 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
3016 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
3017 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
3018 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
3019
3020 #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
3021 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3022 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3023
3024 #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
3025 #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
3026 #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
3027 #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
3028 #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
3029 #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
3030
3031 /******************* Bit definition for TIM_DCR register *******************/
3032 #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
3033 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3034 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3035 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
3036 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
3037 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
3038
3039 #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
3040 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
3041 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
3042 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
3043 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
3044 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
3045
3046 /******************* Bit definition for TIM_DMAR register ******************/
3047 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
3048
3049 /******************* Bit definition for TIM14_OR register ********************/
3050 #define TIM14_OR_TI1_RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
3051 #define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
3052 #define TIM14_OR_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
3053
3054 /******************************************************************************/
3055 /* */
3056 /* Touch Sensing Controller (TSC) */
3057 /* */
3058 /******************************************************************************/
3059 /******************* Bit definition for TSC_CR register *********************/
3060 #define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */
3061 #define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */
3062 #define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */
3063 #define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */
3064 #define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */
3065
3066 #define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */
3067 #define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */
3068 #define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */
3069 #define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */
3070
3071 #define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
3072 #define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
3073 #define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
3074 #define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
3075
3076 #define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */
3077 #define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */
3078
3079 #define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
3080 #define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
3081 #define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
3082 #define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */
3083 #define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */
3084 #define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */
3085 #define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */
3086 #define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */
3087
3088 #define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
3089 #define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
3090 #define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
3091 #define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
3092 #define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
3093
3094 #define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
3095 #define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */
3096 #define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */
3097 #define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */
3098 #define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */
3099
3100 /******************* Bit definition for TSC_IER register ********************/
3101 #define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */
3102 #define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */
3103
3104 /******************* Bit definition for TSC_ICR register ********************/
3105 #define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */
3106 #define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */
3107
3108 /******************* Bit definition for TSC_ISR register ********************/
3109 #define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */
3110 #define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */
3111
3112 /******************* Bit definition for TSC_IOHCR register ******************/
3113 #define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
3114 #define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
3115 #define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
3116 #define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
3117 #define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
3118 #define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
3119 #define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
3120 #define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
3121 #define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
3122 #define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
3123 #define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
3124 #define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
3125 #define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
3126 #define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
3127 #define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
3128 #define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
3129 #define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
3130 #define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
3131 #define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
3132 #define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
3133 #define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
3134 #define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
3135 #define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
3136 #define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
3137 #define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
3138 #define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
3139 #define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
3140 #define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
3141 #define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
3142 #define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
3143 #define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
3144 #define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
3145
3146 /******************* Bit definition for TSC_IOASCR register *****************/
3147 #define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */
3148 #define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */
3149 #define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */
3150 #define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */
3151 #define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */
3152 #define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */
3153 #define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */
3154 #define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */
3155 #define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */
3156 #define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */
3157 #define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */
3158 #define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */
3159 #define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */
3160 #define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */
3161 #define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */
3162 #define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */
3163 #define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */
3164 #define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */
3165 #define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */
3166 #define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */
3167 #define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */
3168 #define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */
3169 #define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */
3170 #define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */
3171 #define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */
3172 #define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */
3173 #define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */
3174 #define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */
3175 #define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */
3176 #define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */
3177 #define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */
3178 #define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */
3179
3180 /******************* Bit definition for TSC_IOSCR register ******************/
3181 #define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */
3182 #define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */
3183 #define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */
3184 #define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */
3185 #define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */
3186 #define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */
3187 #define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */
3188 #define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */
3189 #define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */
3190 #define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */
3191 #define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */
3192 #define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */
3193 #define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */
3194 #define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */
3195 #define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */
3196 #define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */
3197 #define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */
3198 #define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */
3199 #define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */
3200 #define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */
3201 #define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */
3202 #define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */
3203 #define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */
3204 #define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */
3205 #define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */
3206 #define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */
3207 #define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */
3208 #define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */
3209 #define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */
3210 #define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */
3211 #define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */
3212 #define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */
3213
3214 /******************* Bit definition for TSC_IOCCR register ******************/
3215 #define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */
3216 #define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */
3217 #define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */
3218 #define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */
3219 #define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */
3220 #define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */
3221 #define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */
3222 #define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */
3223 #define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */
3224 #define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */
3225 #define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */
3226 #define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */
3227 #define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */
3228 #define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */
3229 #define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */
3230 #define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */
3231 #define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */
3232 #define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */
3233 #define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */
3234 #define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */
3235 #define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */
3236 #define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */
3237 #define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */
3238 #define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */
3239 #define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */
3240 #define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */
3241 #define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */
3242 #define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */
3243 #define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */
3244 #define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */
3245 #define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */
3246 #define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */
3247
3248 /******************* Bit definition for TSC_IOGCSR register *****************/
3249 #define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */
3250 #define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */
3251 #define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */
3252 #define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */
3253 #define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */
3254 #define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */
3255 #define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */
3256 #define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */
3257 #define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */
3258 #define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */
3259 #define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */
3260 #define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */
3261 #define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */
3262 #define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */
3263 #define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */
3264 #define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */
3265
3266 /******************* Bit definition for TSC_IOGXCR register *****************/
3267 #define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */
3268
3269 /******************************************************************************/
3270 /* */
3271 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
3272 /* */
3273 /******************************************************************************/
3274 /****************** Bit definition for USART_CR1 register *******************/
3275 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
3276 #define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
3277 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
3278 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
3279 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
3280 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
3281 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
3282 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
3283 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
3284 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
3285 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
3286 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
3287 #define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
3288 #define USART_CR1_M ((uint32_t)0x00001000) /*!< SmartCard Length */
3289 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
3290 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
3291 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
3292 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
3293 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
3294 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
3295 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
3296 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
3297 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
3298 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
3299 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
3300 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
3301 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
3302 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
3303 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
3304 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
3305 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
3306
3307 /****************** Bit definition for USART_CR2 register *******************/
3308 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
3309 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
3310 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
3311 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
3312 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
3313 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
3314 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
3315 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
3316 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
3317 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
3318 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
3319 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
3320 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
3321 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
3322 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
3323 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
3324 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
3325 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
3326 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
3327 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
3328 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
3329 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
3330
3331 /****************** Bit definition for USART_CR3 register *******************/
3332 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
3333 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
3334 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
3335 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
3336 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
3337 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
3338 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
3339 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
3340 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
3341 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
3342 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
3343 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
3344 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
3345 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
3346 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
3347 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
3348 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
3349 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
3350 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
3351 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
3352 #define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
3353 #define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
3354 #define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
3355 #define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
3356
3357 /****************** Bit definition for USART_BRR register *******************/
3358 #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
3359 #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
3360
3361 /****************** Bit definition for USART_GTPR register ******************/
3362 #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
3363 #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
3364
3365
3366 /******************* Bit definition for USART_RTOR register *****************/
3367 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
3368 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
3369
3370 /******************* Bit definition for USART_RQR register ******************/
3371 #define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
3372 #define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
3373 #define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
3374 #define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
3375 #define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
3376
3377 /******************* Bit definition for USART_ISR register ******************/
3378 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
3379 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
3380 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
3381 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
3382 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
3383 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
3384 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
3385 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
3386 #define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
3387 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
3388 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
3389 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
3390 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
3391 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
3392 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
3393 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
3394 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
3395 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
3396 #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
3397 #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
3398 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
3399 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
3400
3401 /******************* Bit definition for USART_ICR register ******************/
3402 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
3403 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
3404 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
3405 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
3406 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
3407 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
3408 #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
3409 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
3410 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
3411 #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
3412 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
3413 #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
3414
3415 /******************* Bit definition for USART_RDR register ******************/
3416 #define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
3417
3418 /******************* Bit definition for USART_TDR register ******************/
3419 #define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
3420
3421 /******************************************************************************/
3422 /* */
3423 /* Window WATCHDOG (WWDG) */
3424 /* */
3425 /******************************************************************************/
3426 /******************* Bit definition for WWDG_CR register ********************/
3427 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
3428 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
3429 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
3430 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
3431 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
3432 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
3433 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
3434 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
3435
3436 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
3437
3438 /******************* Bit definition for WWDG_CFR register *******************/
3439 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
3440 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
3441 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
3442 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
3443 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
3444 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
3445 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
3446 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
3447
3448 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
3449 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
3450 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
3451
3452 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
3453
3454 /******************* Bit definition for WWDG_SR register ********************/
3455 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
3456
3457 /**
3458 * @}
3459 */
3460
3461 /**
3462 * @}
3463 */
3464
3465
3466 /** @addtogroup Exported_macro
3467 * @{
3468 */
3469
3470 /****************************** ADC Instances *********************************/
3471 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
3472
3473 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
3474
3475 /****************************** COMP Instances *********************************/
3476 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
3477 ((INSTANCE) == COMP2))
3478
3479 #define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) ((INSTANCE) == COMP1)
3480
3481 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
3482
3483 /****************************** CEC Instances *********************************/
3484 #define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
3485
3486 /****************************** CRC Instances *********************************/
3487 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
3488
3489 /******************************* DAC Instances ********************************/
3490 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
3491
3492 /******************************* DMA Instances ******************************/
3493 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
3494 ((INSTANCE) == DMA1_Channel2) || \
3495 ((INSTANCE) == DMA1_Channel3) || \
3496 ((INSTANCE) == DMA1_Channel4) || \
3497 ((INSTANCE) == DMA1_Channel5))
3498
3499 /****************************** GPIO Instances ********************************/
3500 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
3501 ((INSTANCE) == GPIOB) || \
3502 ((INSTANCE) == GPIOC) || \
3503 ((INSTANCE) == GPIOD) || \
3504 ((INSTANCE) == GPIOF))
3505
3506 /****************************** GPIO Lock Instances ****************************/
3507 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
3508 ((INSTANCE) == GPIOB))
3509
3510 /****************************** I2C Instances *********************************/
3511 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
3512 ((INSTANCE) == I2C2))
3513
3514 /****************************** I2S Instances *********************************/
3515 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
3516 ((INSTANCE) == SPI2))
3517
3518 /****************************** IWDG Instances ********************************/
3519 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
3520
3521 /****************************** RTC Instances *********************************/
3522 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
3523
3524 /****************************** SMBUS Instances *********************************/
3525 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
3526
3527 /****************************** SPI Instances *********************************/
3528 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
3529 ((INSTANCE) == SPI2))
3530
3531 /****************************** TIM Instances *********************************/
3532 #define IS_TIM_INSTANCE(INSTANCE)\
3533 (((INSTANCE) == TIM1) || \
3534 ((INSTANCE) == TIM2) || \
3535 ((INSTANCE) == TIM3) || \
3536 ((INSTANCE) == TIM6) || \
3537 ((INSTANCE) == TIM14) || \
3538 ((INSTANCE) == TIM15) || \
3539 ((INSTANCE) == TIM16) || \
3540 ((INSTANCE) == TIM17))
3541
3542 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
3543 (((INSTANCE) == TIM1) || \
3544 ((INSTANCE) == TIM2) || \
3545 ((INSTANCE) == TIM3) || \
3546 ((INSTANCE) == TIM14) || \
3547 ((INSTANCE) == TIM15) || \
3548 ((INSTANCE) == TIM16) || \
3549 ((INSTANCE) == TIM17))
3550
3551 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
3552 (((INSTANCE) == TIM1) || \
3553 ((INSTANCE) == TIM2) || \
3554 ((INSTANCE) == TIM3) || \
3555 ((INSTANCE) == TIM15))
3556
3557 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
3558 (((INSTANCE) == TIM1) || \
3559 ((INSTANCE) == TIM2) || \
3560 ((INSTANCE) == TIM3))
3561
3562 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
3563 (((INSTANCE) == TIM1) || \
3564 ((INSTANCE) == TIM2) || \
3565 ((INSTANCE) == TIM3))
3566
3567 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
3568 (((INSTANCE) == TIM1) || \
3569 ((INSTANCE) == TIM2) || \
3570 ((INSTANCE) == TIM3))
3571
3572 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
3573 (((INSTANCE) == TIM1) || \
3574 ((INSTANCE) == TIM2) || \
3575 ((INSTANCE) == TIM3))
3576
3577 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
3578 (((INSTANCE) == TIM1) || \
3579 ((INSTANCE) == TIM2) || \
3580 ((INSTANCE) == TIM3) || \
3581 ((INSTANCE) == TIM15))
3582
3583 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
3584 (((INSTANCE) == TIM1) || \
3585 ((INSTANCE) == TIM2) || \
3586 ((INSTANCE) == TIM3) || \
3587 ((INSTANCE) == TIM15))
3588
3589 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
3590 (((INSTANCE) == TIM1) || \
3591 ((INSTANCE) == TIM2) || \
3592 ((INSTANCE) == TIM3))
3593
3594 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
3595 (((INSTANCE) == TIM1) || \
3596 ((INSTANCE) == TIM2) || \
3597 ((INSTANCE) == TIM3))
3598
3599 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
3600 (((INSTANCE) == TIM1))
3601
3602 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
3603 (((INSTANCE) == TIM1) || \
3604 ((INSTANCE) == TIM2) || \
3605 ((INSTANCE) == TIM3))
3606
3607 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
3608 (((INSTANCE) == TIM1) || \
3609 ((INSTANCE) == TIM2) || \
3610 ((INSTANCE) == TIM3) || \
3611 ((INSTANCE) == TIM6) || \
3612 ((INSTANCE) == TIM15))
3613
3614 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
3615 (((INSTANCE) == TIM1) || \
3616 ((INSTANCE) == TIM2) || \
3617 ((INSTANCE) == TIM3) || \
3618 ((INSTANCE) == TIM15))
3619
3620 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
3621 ((INSTANCE) == TIM2)
3622
3623 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
3624 (((INSTANCE) == TIM1) || \
3625 ((INSTANCE) == TIM2) || \
3626 ((INSTANCE) == TIM3) || \
3627 ((INSTANCE) == TIM15) || \
3628 ((INSTANCE) == TIM16) || \
3629 ((INSTANCE) == TIM17))
3630
3631 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
3632 (((INSTANCE) == TIM1) || \
3633 ((INSTANCE) == TIM15) || \
3634 ((INSTANCE) == TIM16) || \
3635 ((INSTANCE) == TIM17))
3636
3637 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
3638 ((((INSTANCE) == TIM1) && \
3639 (((CHANNEL) == TIM_CHANNEL_1) || \
3640 ((CHANNEL) == TIM_CHANNEL_2) || \
3641 ((CHANNEL) == TIM_CHANNEL_3) || \
3642 ((CHANNEL) == TIM_CHANNEL_4))) \
3643 || \
3644 (((INSTANCE) == TIM2) && \
3645 (((CHANNEL) == TIM_CHANNEL_1) || \
3646 ((CHANNEL) == TIM_CHANNEL_2) || \
3647 ((CHANNEL) == TIM_CHANNEL_3) || \
3648 ((CHANNEL) == TIM_CHANNEL_4))) \
3649 || \
3650 (((INSTANCE) == TIM3) && \
3651 (((CHANNEL) == TIM_CHANNEL_1) || \
3652 ((CHANNEL) == TIM_CHANNEL_2) || \
3653 ((CHANNEL) == TIM_CHANNEL_3) || \
3654 ((CHANNEL) == TIM_CHANNEL_4))) \
3655 || \
3656 (((INSTANCE) == TIM14) && \
3657 (((CHANNEL) == TIM_CHANNEL_1))) \
3658 || \
3659 (((INSTANCE) == TIM15) && \
3660 (((CHANNEL) == TIM_CHANNEL_1) || \
3661 ((CHANNEL) == TIM_CHANNEL_2))) \
3662 || \
3663 (((INSTANCE) == TIM16) && \
3664 (((CHANNEL) == TIM_CHANNEL_1))) \
3665 || \
3666 (((INSTANCE) == TIM17) && \
3667 (((CHANNEL) == TIM_CHANNEL_1))))
3668
3669 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
3670 ((((INSTANCE) == TIM1) && \
3671 (((CHANNEL) == TIM_CHANNEL_1) || \
3672 ((CHANNEL) == TIM_CHANNEL_2) || \
3673 ((CHANNEL) == TIM_CHANNEL_3))) \
3674 || \
3675 (((INSTANCE) == TIM15) && \
3676 ((CHANNEL) == TIM_CHANNEL_1)) \
3677 || \
3678 (((INSTANCE) == TIM16) && \
3679 ((CHANNEL) == TIM_CHANNEL_1)) \
3680 || \
3681 (((INSTANCE) == TIM17) && \
3682 ((CHANNEL) == TIM_CHANNEL_1)))
3683
3684 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
3685 (((INSTANCE) == TIM1) || \
3686 ((INSTANCE) == TIM2) || \
3687 ((INSTANCE) == TIM3))
3688
3689 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
3690 (((INSTANCE) == TIM1) || \
3691 ((INSTANCE) == TIM15) || \
3692 ((INSTANCE) == TIM16) || \
3693 ((INSTANCE) == TIM17))
3694
3695 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
3696 (((INSTANCE) == TIM1) || \
3697 ((INSTANCE) == TIM2) || \
3698 ((INSTANCE) == TIM3) || \
3699 ((INSTANCE) == TIM14) || \
3700 ((INSTANCE) == TIM15) || \
3701 ((INSTANCE) == TIM16) || \
3702 ((INSTANCE) == TIM17))
3703
3704 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
3705 (((INSTANCE) == TIM1) || \
3706 ((INSTANCE) == TIM2) || \
3707 ((INSTANCE) == TIM3) || \
3708 ((INSTANCE) == TIM6) || \
3709 ((INSTANCE) == TIM15) || \
3710 ((INSTANCE) == TIM16) || \
3711 ((INSTANCE) == TIM17))
3712
3713 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
3714 (((INSTANCE) == TIM1) || \
3715 ((INSTANCE) == TIM2) || \
3716 ((INSTANCE) == TIM3) || \
3717 ((INSTANCE) == TIM15) || \
3718 ((INSTANCE) == TIM16) || \
3719 ((INSTANCE) == TIM17))
3720
3721 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
3722 (((INSTANCE) == TIM1) || \
3723 ((INSTANCE) == TIM15) || \
3724 ((INSTANCE) == TIM16) || \
3725 ((INSTANCE) == TIM17))
3726
3727 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
3728 ((INSTANCE) == TIM14)
3729
3730 /****************************** TSC Instances *********************************/
3731 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
3732
3733 /*********************** UART Instances : IRDA mode ***************************/
3734 #define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
3735
3736 /********************* UART Instances : Smard card mode ***********************/
3737 #define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
3738
3739 /******************** USART Instances : Synchronous mode **********************/
3740 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
3741 ((INSTANCE) == USART2))
3742
3743 /******************** USART Instances : auto Baud rate detection **************/
3744 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
3745
3746 /******************** UART Instances : Asynchronous mode **********************/
3747 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
3748 ((INSTANCE) == USART2))
3749
3750 /******************** UART Instances : Half-Duplex mode **********************/
3751 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
3752 ((INSTANCE) == USART2))
3753
3754 /****************** UART Instances : Hardware Flow control ********************/
3755 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
3756 ((INSTANCE) == USART2))
3757
3758 /****************** UART Instances : LIN mode ********************/
3759 #define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
3760
3761 /****************** UART Instances : wakeup from stop mode ********************/
3762 #define IS_UART_WAKEUP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
3763
3764 /****************** UART Instances : Auto Baud Rate detection ********************/
3765 #define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
3766
3767 /****************** UART Instances : Driver enable detection ********************/
3768 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
3769 ((INSTANCE) == USART2))
3770
3771 /****************************** WWDG Instances ********************************/
3772 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
3773
3774 /**
3775 * @}
3776 */
3777
3778
3779 /******************************************************************************/
3780 /* For a painless codes migration between the STM32F0xx device product */
3781 /* lines, the aliases defined below are put in place to overcome the */
3782 /* differences in the interrupt handlers and IRQn definitions. */
3783 /* No need to update developed interrupt code when moving across */
3784 /* product lines within the same STM32F0 Family */
3785 /******************************************************************************/
3786
3787 /* Aliases for __IRQn */
3788 #define PVD_VDDIO2_IRQn PVD_IRQn
3789 #define RCC_CRS_IRQn RCC_IRQn
3790 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
3791 #define ADC1_IRQn ADC1_COMP_IRQn
3792 #define TIM6_IRQn TIM6_DAC_IRQn
3793
3794 /* Aliases for __IRQHandler */
3795 #define PVD_VDDIO2_IRQHandler PVD_IRQHandler
3796 #define RCC_CRS_IRQHandler RCC_IRQHandler
3797 #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
3798 #define ADC1_IRQHandler ADC1_COMP_IRQHandler
3799 #define TIM6_IRQHandler TIM6_DAC_IRQHandler
3800
3801 #ifdef __cplusplus
3802 }
3803 #endif /* __cplusplus */
3804
3805 #endif /* __STM32F051x8_H */
3806
3807 /**
3808 * @}
3809 */
3810
3811 /**
3812 * @}
3813 */
3814
3815 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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