tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/system_stm32f0xx.c

   1 /**
   2   ******************************************************************************
   3   * @file    system_stm32f0xx.c
   4   * @author  MCD Application Team
   5   * @version V2.2.0
   6   * @date    05-December-2014
   7   * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
   8   *
   9   * 1. This file provides two functions and one global variable to be called from
  10   *    user application:
  11   *      - SystemInit(): This function is called at startup just after reset and
  12   *                      before branch to main program. This call is made inside
  13   *                      the "startup_stm32f0xx.s" file.
  14   *
  15   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
  16   *                                  by the user application to setup the SysTick
  17   *                                  timer or configure other parameters.
  18   *
  19   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
  20   *                                 be called whenever the core clock is changed
  21   *                                 during program execution.
  22   *
  23   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
  24   *    Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
  25   *    configure the system clock before to branch to main program.
  26   *
  27   * 3. This file configures the system clock as follows:
  28   *=============================================================================
  29   * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
  30   *                                    | (external 8 MHz clock) | (internal 48 MHz)
  31   *                                    | 2- PLL_HSE_XTAL        |
  32   *                                    | (external 8 MHz xtal)  |
  33   *-----------------------------------------------------------------------------
  34   * SYSCLK(MHz)                        | 48                     | 48
  35   *-----------------------------------------------------------------------------
  36   * AHBCLK (MHz)                       | 48                     | 48
  37   *-----------------------------------------------------------------------------
  38   * APB1CLK (MHz)                      | 48                     | 48
  39   *-----------------------------------------------------------------------------
  40   * USB capable (48 MHz precise clock) | YES                    | YES
  41   *=============================================================================
  42   ******************************************************************************
  43   * @attention
  44   *
  45   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  46   *
  47   * Redistribution and use in source and binary forms, with or without modification,
  48   * are permitted provided that the following conditions are met:
  49   *   1. Redistributions of source code must retain the above copyright notice,
  50   *      this list of conditions and the following disclaimer.
  51   *   2. Redistributions in binary form must reproduce the above copyright notice,
  52   *      this list of conditions and the following disclaimer in the documentation
  53   *      and/or other materials provided with the distribution.
  54   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  55   *      may be used to endorse or promote products derived from this software
  56   *      without specific prior written permission.
  57   *
  58   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  59   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  60   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  61   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  62   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  63   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  64   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  65   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  66   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  67   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  68   *
  69   ******************************************************************************
  70   */
  71
  72 /** @addtogroup CMSIS
  73   * @{
  74   */
  75
  76 /** @addtogroup stm32f0xx_system
  77   * @{
  78   */
  79
  80 /** @addtogroup STM32F0xx_System_Private_Includes
  81   * @{
  82   */
  83
  84 #include "stm32f0xx.h"
  85 #include "hal_tick.h"
  86
  87 /**
  88   * @}
  89   */
  90
  91 /** @addtogroup STM32F0xx_System_Private_TypesDefinitions
  92   * @{
  93   */
  94
  95 /**
  96   * @}
  97   */
  98
  99 /** @addtogroup STM32F0xx_System_Private_Defines
 100   * @{
 101   */
 102 #if !defined  (HSE_VALUE)
 103   #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
 104                                                 This value can be provided and adapted by the user application. */
 105 #endif /* HSE_VALUE */
 106
 107 #if !defined  (HSI_VALUE)
 108   #define HSI_VALUE    ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
 109                                                 This value can be provided and adapted by the user application. */
 110 #endif /* HSI_VALUE */
 111 /**
 112   * @}
 113   */
 114
 115 /** @addtogroup STM32F0xx_System_Private_Macros
 116   * @{
 117   */
 118
 119 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
 120 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
 121 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
 122
 123 /**
 124   * @}
 125   */
 126
 127 /** @addtogroup STM32F0xx_System_Private_Variables
 128   * @{
 129   */
 130   /* This variable is updated in three ways:
 131       1) by calling CMSIS function SystemCoreClockUpdate()
 132       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
 133       3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
 134          Note: If you use this function to configure the system clock there is no need to
 135                call the 2 first functions listed above, since SystemCoreClock variable is
 136                updated automatically.
 137   */
 138 uint32_t SystemCoreClock = 48000000;
 139
 140 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 141
 142 /**
 143   * @}
 144   */
 145
 146 /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
 147   * @{
 148   */
 149
 150 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
 151 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
 152 #endif
 153
 154 uint8_t SetSysClock_PLL_HSI(void);
 155
 156 /**
 157   * @}
 158   */
 159
 160 /** @addtogroup STM32F0xx_System_Private_Functions
 161   * @{
 162   */
 163
 164 extern int NVIC_vtor_remap;
 165
 166 /**
 167   * @brief  Setup the microcontroller system.
 168   *         Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
 169   * @param  None
 170   * @retval None
 171   */
 172 void SystemInit(void)
 173 {
 174   /* Reset the RCC clock configuration to the default reset state ------------*/
 175   /* Set HSION bit */
 176   RCC->CR |= (uint32_t)0x00000001;
 177
 178 #if defined (STM32F051x8) || defined (STM32F058x8)
 179   /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
 180   RCC->CFGR &= (uint32_t)0xF8FFB80C;
 181 #else
 182   /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
 183   RCC->CFGR &= (uint32_t)0x08FFB80C;
 184 #endif /* STM32F051x8 or STM32F058x8 */
 185
 186   /* Reset HSEON, CSSON and PLLON bits */
 187   RCC->CR &= (uint32_t)0xFEF6FFFF;
 188
 189   /* Reset HSEBYP bit */
 190   RCC->CR &= (uint32_t)0xFFFBFFFF;
 191
 192   /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
 193   RCC->CFGR &= (uint32_t)0xFFC0FFFF;
 194
 195   /* Reset PREDIV[3:0] bits */
 196   RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
 197
 198 #if defined (STM32F072xB) || defined (STM32F078xB)
 199   /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
 200   RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
 201 #elif defined (STM32F071xB)
 202   /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
 203   RCC->CFGR3 &= (uint32_t)0xFFFFCEAC;
 204 #elif defined (STM32F091xC) || defined (STM32F098xx)
 205   /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
 206   RCC->CFGR3 &= (uint32_t)0xFFF0FEAC;
 207 #elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
 208   /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
 209   RCC->CFGR3 &= (uint32_t)0xFFFFFEEC;
 210 #elif defined (STM32F051x8) || defined (STM32F058xx)
 211   /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
 212   RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
 213 #elif defined (STM32F042x6) || defined (STM32F048xx)
 214   /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
 215   RCC->CFGR3 &= (uint32_t)0xFFFFFE2C;
 216 #elif defined (STM32F070x6) || defined (STM32F070xB)
 217   /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
 218   RCC->CFGR3 &= (uint32_t)0xFFFFFE6C;
 219   /* Set default USB clock to PLLCLK, since there is no HSI48 */
 220   RCC->CFGR3 |= (uint32_t)0x00000080;
 221 #else
 222  #warning "No target selected"
 223 #endif
 224
 225   /* Reset HSI14 bit */
 226   RCC->CR2 &= (uint32_t)0xFFFFFFFE;
 227
 228   /* Disable all interrupts */
 229   RCC->CIR = 0x00000000;
 230
 231   /* Configure the Cube driver */
 232   SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
 233   NVIC_vtor_remap = 0; // Because it is not cleared the first time we enter in NVIC_SetVector()
 234   HAL_Init();
 235
 236   /* Configure the System clock source, PLL Multiplier and Divider factors,
 237      AHB/APBx prescalers and Flash settings */
 238   SetSysClock();
 239
 240   /* Reset the timer to avoid issues after the RAM initialization */
 241   TIM_MST_RESET_ON;
 242   TIM_MST_RESET_OFF;
 243 }
 244
 245 /**
 246    * @brief  Update SystemCoreClock variable according to Clock Register Values.
 247   *         The SystemCoreClock variable contains the core clock (HCLK), it can
 248   *         be used by the user application to setup the SysTick timer or configure
 249   *         other parameters.
 250   *
 251   * @note   Each time the core clock (HCLK) changes, this function must be called
 252   *         to update SystemCoreClock variable value. Otherwise, any configuration
 253   *         based on this variable will be incorrect.
 254   *
 255   * @note   - The system frequency computed by this function is not the real
 256   *           frequency in the chip. It is calculated based on the predefined
 257   *           constant and the selected clock source:
 258   *
 259   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
 260   *
 261   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
 262   *
 263   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
 264   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
 265   *
 266   *         (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
 267   *             8 MHz) but the real value may vary depending on the variations
 268   *             in voltage and temperature.
 269   *
 270   *         (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
 271   *              8 MHz), user has to ensure that HSE_VALUE is same as the real
 272   *              frequency of the crystal used. Otherwise, this function may
 273   *              have wrong result.
 274   *
 275   *         - The result of this function could be not correct when using fractional
 276   *           value for HSE crystal.
 277   *
 278   * @param  None
 279   * @retval None
 280   */
 281 void SystemCoreClockUpdate (void)
 282 {
 283   uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
 284
 285   /* Get SYSCLK source -------------------------------------------------------*/
 286   tmp = RCC->CFGR & RCC_CFGR_SWS;
 287
 288   switch (tmp)
 289   {
 290     case RCC_CFGR_SWS_HSI:  /* HSI used as system clock */
 291       SystemCoreClock = HSI_VALUE;
 292       break;
 293     case RCC_CFGR_SWS_HSE:  /* HSE used as system clock */
 294       SystemCoreClock = HSE_VALUE;
 295       break;
 296     case RCC_CFGR_SWS_PLL:  /* PLL used as system clock */
 297       /* Get PLL clock source and multiplication factor ----------------------*/
 298       pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
 299       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
 300       pllmull = ( pllmull >> 18) + 2;
 301       predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
 302
 303       if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
 304       {
 305         /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
 306         SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
 307       }
 308 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
 309       else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
 310       {
 311         /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
 312         SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
 313       }
 314 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
 315       else
 316       {
 317 #if defined(STM32F042x6) || defined(STM32F048xx)  || defined(STM32F070x6) || \
 318     defined(STM32F078xx) || defined(STM32F071xB)  || defined(STM32F072xB) || defined(STM32F070xB) || \
 319     defined(STM32F091xC) || defined(STM32F098xx)  || defined(STM32F030xC)
 320         /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
 321         SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
 322 #else
 323         /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
 324         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
 325 #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
 326           STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
 327           STM32F091xC || STM32F098xx || STM32F030xC */
 328       }
 329       break;
 330     default: /* HSI used as system clock */
 331       SystemCoreClock = HSI_VALUE;
 332       break;
 333   }
 334   /* Compute HCLK clock frequency ----------------*/
 335   /* Get HCLK prescaler */
 336   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
 337   /* HCLK clock frequency */
 338   SystemCoreClock >>= tmp;
 339 }
 340
 341 /**
 342   * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
 343   *               AHB/APBx prescalers and Flash settings
 344   * @note   This function should be called only once the RCC clock configuration
 345   *         is reset to the default reset state (done in SystemInit() function).
 346   * @param  None
 347   * @retval None
 348   */
 349 void SetSysClock(void)
 350 {
 351   /* 1- Try to start with HSE and external clock */
 352 #if USE_PLL_HSE_EXTC != 0
 353   if (SetSysClock_PLL_HSE(1) == 0)
 354 #endif
 355   {
 356     /* 2- If fail try to start with HSE and external xtal */
 357     #if USE_PLL_HSE_XTAL != 0
 358     if (SetSysClock_PLL_HSE(0) == 0)
 359     #endif
 360     {
 361       /* 3- If fail start with HSI clock */
 362       if (SetSysClock_PLL_HSI() == 0)
 363       {
 364         while(1)
 365         {
 366           // [TODO] Put something here to tell the user that a problem occured...
 367         }
 368       }
 369     }
 370   }
 371
 372   // Output clock on MCO pin(PA8) for debugging purpose
 373   //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz
 374 }
 375
 376 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
 377 /******************************************************************************/
 378 /*            PLL (clocked by HSE) used as System clock source                */
 379 /******************************************************************************/
 380 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
 381 {
 382   RCC_ClkInitTypeDef RCC_ClkInitStruct;
 383   RCC_OscInitTypeDef RCC_OscInitStruct;
 384
 385   // Select HSE oscillator as PLL source
 386   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
 387   if (bypass == 0) {
 388       RCC_OscInitStruct.HSEState   = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
 389   } else {
 390       RCC_OscInitStruct.HSEState   = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
 391   }
 392   RCC_OscInitStruct.HSI48State     = RCC_HSI48_ON;
 393   RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
 394   RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSE;
 395   RCC_OscInitStruct.PLL.PREDIV     = RCC_PREDIV_DIV2;
 396   RCC_OscInitStruct.PLL.PLLMUL     = RCC_PLL_MUL12;
 397   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
 398       return 0; // FAIL
 399   }
 400
 401   // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
 402   RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
 403   RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
 404   RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
 405   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
 406   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
 407       return 0; // FAIL
 408   }
 409
 410   // Output clock on MCO pin(PA8) for debugging purpose
 411   //if (bypass == 0)
 412   //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
 413   //else
 414   //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV4); // 2 MHz with ST-Link MCO
 415
 416   return 1; // OK
 417 }
 418 #endif
 419
 420 /******************************************************************************/
 421 /*            PLL (clocked by HSI) used as System clock source                */
 422 /******************************************************************************/
 423 uint8_t SetSysClock_PLL_HSI(void)
 424 {
 425   RCC_ClkInitTypeDef RCC_ClkInitStruct;
 426   RCC_OscInitTypeDef RCC_OscInitStruct;
 427
 428   // Select HSI48 oscillator as PLL source
 429   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48;
 430   RCC_OscInitStruct.HSI48State     = RCC_HSI48_ON;
 431   RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
 432   RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSI48;
 433   RCC_OscInitStruct.PLL.PREDIV     = RCC_PREDIV_DIV2;
 434   RCC_OscInitStruct.PLL.PLLMUL     = RCC_PLL_MUL2;
 435   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
 436       return 0; // FAIL
 437   }
 438
 439   // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
 440   RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
 441   RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
 442   RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 48 MHz
 443   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 48 MHz
 444   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
 445       return 0; // FAIL
 446   }
 447
 448   // Output clock on MCO1 pin(PA8) for debugging purpose
 449   //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI48, RCC_MCO_DIV1); // 48 MHz
 450
 451   return 1; // OK
 452 }
 453
 454 /**
 455   * @}
 456   */
 457
 458 /**
 459   * @}
 460   */
 461
 462 /**
 463   * @}
 464   */
 465
 466 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 467