]> git.gir.st - tmk_keyboard.git/blob - tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_ARM_STD/startup_stm32f091rc.s
Squashed 'tmk_core/' changes from 7967731..b9e0ea0
[tmk_keyboard.git] / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_STM / TARGET_STM32F0 / TARGET_NUCLEO_F091RC / TOOLCHAIN_ARM_STD / startup_stm32f091rc.s
1 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
2 ;* File Name : startup_stm32f091xc.s
3 ;* Author : MCD Application Team
4 ;* Version : V2.1.0
5 ;* Date : 03-Oct-2014
6 ;* Description : STM32F091xc/STM32F098xc devices vector table for MDK-ARM_STD toolchain.
7 ;* This module performs:
8 ;* - Set the initial SP
9 ;* - Set the initial PC == Reset_Handler
10 ;* - Set the vector table entries with the exceptions ISR address
11 ;* - Branches to __main in the C library (which eventually
12 ;* calls main()).
13 ;* After Reset the CortexM0 processor is in Thread mode,
14 ;* priority is Privileged, and the Stack is set to Main.
15 ;* <<< Use Configuration Wizard in Context Menu >>>
16 ;*******************************************************************************
17 ;
18 ;* Redistribution and use in source and binary forms, with or without modification,
19 ;* are permitted provided that the following conditions are met:
20 ;* 1. Redistributions of source code must retain the above copyright notice,
21 ;* this list of conditions and the following disclaimer.
22 ;* 2. Redistributions in binary form must reproduce the above copyright notice,
23 ;* this list of conditions and the following disclaimer in the documentation
24 ;* and/or other materials provided with the distribution.
25 ;* 3. Neither the name of STMicroelectronics nor the names of its contributors
26 ;* may be used to endorse or promote products derived from this software
27 ;* without specific prior written permission.
28 ;*
29 ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
30 ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31 ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
32 ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
33 ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
35 ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
36 ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
37 ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 ;
40 ;*******************************************************************************
41
42 __initial_sp EQU 0x20008000 ; Top of RAM (32KB)
43
44 PRESERVE8
45 THUMB
46
47
48 ; Vector Table Mapped to Address 0 at Reset
49 AREA RESET, DATA, READONLY
50 EXPORT __Vectors
51 EXPORT __Vectors_End
52 EXPORT __Vectors_Size
53
54 __Vectors DCD __initial_sp ; Top of Stack
55 DCD Reset_Handler ; Reset Handler
56 DCD NMI_Handler ; NMI Handler
57 DCD HardFault_Handler ; Hard Fault Handler
58 DCD 0 ; Reserved
59 DCD 0 ; Reserved
60 DCD 0 ; Reserved
61 DCD 0 ; Reserved
62 DCD 0 ; Reserved
63 DCD 0 ; Reserved
64 DCD 0 ; Reserved
65 DCD SVC_Handler ; SVCall Handler
66 DCD 0 ; Reserved
67 DCD 0 ; Reserved
68 DCD PendSV_Handler ; PendSV Handler
69 DCD SysTick_Handler ; SysTick Handler
70
71 ; External Interrupts
72 DCD WWDG_IRQHandler ; Window Watchdog
73 DCD PVD_VDDIO2_IRQHandler ; PVD through EXTI Line detect
74 DCD RTC_IRQHandler ; RTC through EXTI Line
75 DCD FLASH_IRQHandler ; FLASH
76 DCD RCC_CRS_IRQHandler ; RCC and CRS
77 DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
78 DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
79 DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
80 DCD TSC_IRQHandler ; TS
81 DCD DMA1_Ch1_IRQHandler ; DMA1 Channel 1
82 DCD DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler ; DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2
83 DCD DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler ; DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5
84 DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
85 DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
86 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
87 DCD TIM2_IRQHandler ; TIM2
88 DCD TIM3_IRQHandler ; TIM3
89 DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
90 DCD TIM7_IRQHandler ; TIM7
91 DCD TIM14_IRQHandler ; TIM14
92 DCD TIM15_IRQHandler ; TIM15
93 DCD TIM16_IRQHandler ; TIM16
94 DCD TIM17_IRQHandler ; TIM17
95 DCD I2C1_IRQHandler ; I2C1
96 DCD I2C2_IRQHandler ; I2C2
97 DCD SPI1_IRQHandler ; SPI1
98 DCD SPI2_IRQHandler ; SPI2
99 DCD USART1_IRQHandler ; USART1
100 DCD USART2_IRQHandler ; USART2
101 DCD USART3_8_IRQHandler ; USART3, USART4, USART5, USART6, USART7, USART8
102 DCD CEC_CAN_IRQHandler ; CEC and CAN
103
104 __Vectors_End
105
106 __Vectors_Size EQU __Vectors_End - __Vectors
107
108 AREA |.text|, CODE, READONLY
109
110 ; Reset handler routine
111 Reset_Handler PROC
112 EXPORT Reset_Handler [WEAK]
113 IMPORT __main
114 IMPORT SystemInit
115 LDR R0, =SystemInit
116 BLX R0
117 LDR R0, =__main
118 BX R0
119 ENDP
120
121 ; Dummy Exception Handlers (infinite loops which can be modified)
122
123 NMI_Handler PROC
124 EXPORT NMI_Handler [WEAK]
125 B .
126 ENDP
127 HardFault_Handler\
128 PROC
129 EXPORT HardFault_Handler [WEAK]
130 B .
131 ENDP
132 SVC_Handler PROC
133 EXPORT SVC_Handler [WEAK]
134 B .
135 ENDP
136 PendSV_Handler PROC
137 EXPORT PendSV_Handler [WEAK]
138 B .
139 ENDP
140 SysTick_Handler PROC
141 EXPORT SysTick_Handler [WEAK]
142 B .
143 ENDP
144
145 Default_Handler PROC
146
147 EXPORT WWDG_IRQHandler [WEAK]
148 EXPORT PVD_VDDIO2_IRQHandler [WEAK]
149 EXPORT RTC_IRQHandler [WEAK]
150 EXPORT FLASH_IRQHandler [WEAK]
151 EXPORT RCC_CRS_IRQHandler [WEAK]
152 EXPORT EXTI0_1_IRQHandler [WEAK]
153 EXPORT EXTI2_3_IRQHandler [WEAK]
154 EXPORT EXTI4_15_IRQHandler [WEAK]
155 EXPORT TSC_IRQHandler [WEAK]
156 EXPORT DMA1_Ch1_IRQHandler [WEAK]
157 EXPORT DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler [WEAK]
158 EXPORT DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler [WEAK]
159 EXPORT ADC1_COMP_IRQHandler [WEAK]
160 EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
161 EXPORT TIM1_CC_IRQHandler [WEAK]
162 EXPORT TIM2_IRQHandler [WEAK]
163 EXPORT TIM3_IRQHandler [WEAK]
164 EXPORT TIM6_DAC_IRQHandler [WEAK]
165 EXPORT TIM7_IRQHandler [WEAK]
166 EXPORT TIM14_IRQHandler [WEAK]
167 EXPORT TIM15_IRQHandler [WEAK]
168 EXPORT TIM16_IRQHandler [WEAK]
169 EXPORT TIM17_IRQHandler [WEAK]
170 EXPORT I2C1_IRQHandler [WEAK]
171 EXPORT I2C2_IRQHandler [WEAK]
172 EXPORT SPI1_IRQHandler [WEAK]
173 EXPORT SPI2_IRQHandler [WEAK]
174 EXPORT USART1_IRQHandler [WEAK]
175 EXPORT USART2_IRQHandler [WEAK]
176 EXPORT USART3_8_IRQHandler [WEAK]
177 EXPORT CEC_CAN_IRQHandler [WEAK]
178
179
180 WWDG_IRQHandler
181 PVD_VDDIO2_IRQHandler
182 RTC_IRQHandler
183 FLASH_IRQHandler
184 RCC_CRS_IRQHandler
185 EXTI0_1_IRQHandler
186 EXTI2_3_IRQHandler
187 EXTI4_15_IRQHandler
188 TSC_IRQHandler
189 DMA1_Ch1_IRQHandler
190 DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
191 DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
192 ADC1_COMP_IRQHandler
193 TIM1_BRK_UP_TRG_COM_IRQHandler
194 TIM1_CC_IRQHandler
195 TIM2_IRQHandler
196 TIM3_IRQHandler
197 TIM6_DAC_IRQHandler
198 TIM7_IRQHandler
199 TIM14_IRQHandler
200 TIM15_IRQHandler
201 TIM16_IRQHandler
202 TIM17_IRQHandler
203 I2C1_IRQHandler
204 I2C2_IRQHandler
205 SPI1_IRQHandler
206 SPI2_IRQHandler
207 USART1_IRQHandler
208 USART2_IRQHandler
209 USART3_8_IRQHandler
210 CEC_CAN_IRQHandler
211
212 B .
213
214 ENDP
215
216 ALIGN
217 END
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