tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f0xx_hal.h
   4   * @author  MCD Application Team
   5   * @version V1.2.0
   6   * @date    11-December-2014
   7   * @brief   This file contains all the functions prototypes for the HAL
   8   *          module driver.
   9   ******************************************************************************
  10   * @attention
  11   *
  12   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  13   *
  14   * Redistribution and use in source and binary forms, with or without modification,
  15   * are permitted provided that the following conditions are met:
  16   *   1. Redistributions of source code must retain the above copyright notice,
  17   *      this list of conditions and the following disclaimer.
  18   *   2. Redistributions in binary form must reproduce the above copyright notice,
  19   *      this list of conditions and the following disclaimer in the documentation
  20   *      and/or other materials provided with the distribution.
  21   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  22   *      may be used to endorse or promote products derived from this software
  23   *      without specific prior written permission.
  24   *
  25   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  26   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  27   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  28   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  29   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  30   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  31   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  32   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  33   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  34   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35   *
  36   ******************************************************************************
  37   */
  38
  39 /* Define to prevent recursive inclusion -------------------------------------*/
  40 #ifndef __STM32F0xx_HAL_H
  41 #define __STM32F0xx_HAL_H
  42
  43 #ifdef __cplusplus
  44  extern "C" {
  45 #endif
  46
  47 /* Includes ------------------------------------------------------------------*/
  48 #include "stm32f0xx_hal_conf.h"
  49
  50 /** @addtogroup STM32F0xx_HAL_Driver
  51   * @{
  52   */
  53
  54 /** @addtogroup HAL
  55   * @{
  56   */
  57
  58 /* Exported types ------------------------------------------------------------*/
  59 /* Exported constants --------------------------------------------------------*/
  60 /** @defgroup HAL_Exported_Constants HAL Exported Constants
  61   * @{
  62   */
  63
  64 #if defined(SYSCFG_CFGR1_DMA_RMP)
  65 /** @defgroup HAL_DMA_remapping HAL DMA remapping
  66   *        Elements values convention: 0xYYYYYYYY
  67   *           - YYYYYYYY  : Position in the SYSCFG register CFGR1
  68   * @{
  69   */
  70 #define HAL_REMAPDMA_ADC_DMA_CH2         ((uint32_t)SYSCFG_CFGR1_ADC_DMA_RMP) /*!< ADC DMA remap
  71                                                                          0: No remap (ADC DMA requests mapped on DMA channel 1
  72                                                                          1: Remap (ADC DMA requests mapped on DMA channel 2 */
  73 #define HAL_REMAPDMA_USART1_TX_DMA_CH4   ((uint32_t)SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1 TX DMA remap
  74                                                                          0: No remap (USART1_TX DMA request mapped on DMA channel 2
  75                                                                          1: Remap (USART1_TX DMA request mapped on DMA channel 4 */
  76 #define HAL_REMAPDMA_USART1_RX_DMA_CH5   ((uint32_t)SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1 RX DMA remap
  77                                                                          0: No remap (USART1_RX DMA request mapped on DMA channel 3
  78                                                                          1: Remap (USART1_RX DMA request mapped on DMA channel 5 */
  79 #define HAL_REMAPDMA_TIM16_DMA_CH4       ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16 DMA request remap
  80                                                                          0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3)
  81                                                                          1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4) */
  82 #define HAL_REMAPDMA_TIM17_DMA_CH2       ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17 DMA request remap
  83                                                                          0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1
  84                                                                          1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) */
  85
  86 #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx)
  87 #define HAL_REMAPDMA_TIM16_DMA_CH6       ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16 alternate DMA request remapping bit. Available on STM32F07x devices only
  88                                                                          0: No alternate remap (TIM16 DMA requestsmapped according to TIM16_DMA_RMP bit)
  89                                                                          1: Alternate remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6) */
  90 #define HAL_REMAPDMA_TIM17_DMA_CH7       ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17 alternate DMA request remapping bit. Available on STM32F07x devices only
  91                                                                          0: No alternate remap (TIM17 DMA requestsmapped according to TIM17_DMA_RMP bit)
  92                                                                          1: Alternate remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7) */
  93 #define HAL_REMAPDMA_SPI2_DMA_CH67       ((uint32_t)SYSCFG_CFGR1_SPI2_DMA_RMP) /*!< SPI2 DMA request remapping bit. Available on STM32F07x devices only.
  94                                                                          0: No remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively)
  95                                                                          1: 1: Remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */
  96 #define HAL_REMAPDMA_USART2_DMA_CH67     ((uint32_t)SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2 DMA request remapping bit. Available on STM32F07x devices only.
  97                                                                          0: No remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively)
  98                                                                          1: 1: Remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */
  99 #define HAL_REMAPDMA_USART3_DMA_CH32     ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F07x devices only.
 100                                                                          0: No remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively)
 101                                                                          1: 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */
 102 #define HAL_REMAPDMA_I2C1_DMA_CH76       ((uint32_t)SYSCFG_CFGR1_I2C1_DMA_RMP) /*!< I2C1 DMA request remapping bit. Available on STM32F07x devices only.
 103                                                                          0: No remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively)
 104                                                                          1: Remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively) */
 105 #define HAL_REMAPDMA_TIM1_DMA_CH6        ((uint32_t)SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1 DMA request remapping bit. Available on STM32F07x devices only.
 106                                                                          0: No remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively)
 107                                                                          1: Remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */
 108 #define HAL_REMAPDMA_TIM2_DMA_CH7        ((uint32_t)SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2 DMA request remapping bit. Available on STM32F07x devices only.
 109                                                                          0: No remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively)
 110                                                                          1: Remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */
 111 #define HAL_REMAPDMA_TIM3_DMA_CH6        ((uint32_t)SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3 DMA request remapping bit. Available on STM32F07x devices only.
 112                                                                          0: No remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4)
 113                                                                          1: Remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6) */
 114 #endif
 115
 116 #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx)
 117 #define IS_HAL_REMAPDMA(RMP) (((RMP) == HAL_REMAPDMA_ADC_DMA_CH2)        || \
 118                               ((RMP) == HAL_REMAPDMA_USART1_TX_DMA_CH4) || \
 119                               ((RMP) == HAL_REMAPDMA_USART1_RX_DMA_CH5) || \
 120                               ((RMP) == HAL_REMAPDMA_TIM16_DMA_CH4)     || \
 121                               ((RMP) == HAL_REMAPDMA_TIM17_DMA_CH2)     || \
 122                               ((RMP) == HAL_REMAPDMA_TIM16_DMA_CH6)     || \
 123                               ((RMP) == HAL_REMAPDMA_TIM17_DMA_CH7)     || \
 124                               ((RMP) == HAL_REMAPDMA_SPI2_DMA_CH67)     || \
 125                               ((RMP) == HAL_REMAPDMA_USART2_DMA_CH67)   || \
 126                               ((RMP) == HAL_REMAPDMA_USART3_DMA_CH32)   || \
 127                               ((RMP) == HAL_REMAPDMA_I2C1_DMA_CH76)     || \
 128                               ((RMP) == HAL_REMAPDMA_TIM1_DMA_CH6)      || \
 129                               ((RMP) == HAL_REMAPDMA_TIM2_DMA_CH7)      || \
 130                               ((RMP) == HAL_REMAPDMA_TIM3_DMA_CH6))
 131 #else
 132 #define IS_HAL_REMAPDMA(RMP) (((RMP) == HAL_REMAPDMA_ADC_DMA_CH2)       || \
 133                               ((RMP) == HAL_REMAPDMA_USART1_TX_DMA_CH4) || \
 134                               ((RMP) == HAL_REMAPDMA_USART1_RX_DMA_CH5) || \
 135                               ((RMP) == HAL_REMAPDMA_TIM16_DMA_CH4)     || \
 136                               ((RMP) == HAL_REMAPDMA_TIM17_DMA_CH2))
 137 #endif
 138 /**
 139   * @}
 140   */
 141 #endif /* SYSCFG_CFGR1_DMA_RMP */
 142
 143 #if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
 144 /** @defgroup HAL_Pin_remapping HAL Pin remapping
 145   * @{
 146   */
 147 #define HAL_REMAP_PA11_PA12                 (SYSCFG_CFGR1_PA11_PA12_RMP)  /*!< PA11 and PA12 remapping bit for small packages (28 and 20 pins).
 148                                                                            0: No remap (pin pair PA9/10 mapped on the pins)
 149                                                                            1: Remap (pin pair PA11/12 mapped instead of PA9/10) */
 150
 151 #define IS_HAL_REMAP_PIN(RMP) ((RMP) == HAL_REMAP_PA11_PA12)
 152 /**
 153   * @}
 154   */
 155 #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
 156
 157 #if defined(STM32F091xC) || defined(STM32F098xx)
 158 /** @defgroup HAL_IRDA_ENV_SEL HAL IRDA Enveloppe Selection
 159   * @note Applicable on STM32F09x
 160   * @{
 161   */
 162 #define HAL_SYSCFG_IRDA_ENV_SEL_TIM16     (SYSCFG_CFGR1_IRDA_ENV_SEL_0 & SYSCFG_CFGR1_IRDA_ENV_SEL_1)    /* 00: Timer16 is selected as IRDA Modulation enveloppe source */
 163 #define HAL_SYSCFG_IRDA_ENV_SEL_USART1    (SYSCFG_CFGR1_IRDA_ENV_SEL_0)  /* 01: USART1 is selected as IRDA Modulation enveloppe source */
 164 #define HAL_SYSCFG_IRDA_ENV_SEL_USART4    (SYSCFG_CFGR1_IRDA_ENV_SEL_1)  /* 10: USART4 is selected as IRDA Modulation enveloppe source */
 165
 166 #define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL)   (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16)   || \
 167                                            ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1)   || \
 168                                            ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4))
 169 /**
 170   * @}
 171   */
 172 #endif /* STM32F091xC || STM32F098xx */
 173
 174
 175 /** @defgroup HAL_FastModePlus_I2C HAL FastModePlus I2C
 176   * @{
 177   */
 178 #if defined(SYSCFG_CFGR1_I2C_FMP_PB6)
 179 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6     (SYSCFG_CFGR1_I2C_FMP_PB6)  /*!< Fast Mode Plus (FM+) driving capability activation on the pad
 180                                                                          0: PB6 pin operates in standard mode
 181                                                                          1: I2C FM+ mode enabled on PB6 pin, and the Speed control is bypassed */
 182 #endif /* SYSCFG_CFGR1_I2C_FMP_PB6 */
 183
 184 #if defined(SYSCFG_CFGR1_I2C_FMP_PB7)
 185 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7     (SYSCFG_CFGR1_I2C_FMP_PB7)  /*!< Fast Mode Plus (FM+) driving capability activation on the pad
 186                                                                          0: PB7 pin operates in standard mode
 187                                                                          1: I2C FM+ mode enabled on PB7 pin, and the Speed control is bypassed */
 188 #endif /* SYSCFG_CFGR1_I2C_FMP_PB7 */
 189
 190 #if defined(SYSCFG_CFGR1_I2C_FMP_PB8)
 191 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8     (SYSCFG_CFGR1_I2C_FMP_PB8)  /*!< Fast Mode Plus (FM+) driving capability activation on the pad
 192                                                                          0: PB8 pin operates in standard mode
 193                                                                          1: I2C FM+ mode enabled on PB8 pin, and the Speed control is bypassed */
 194 #endif /* SYSCFG_CFGR1_I2C_FMP_PB8 */
 195
 196 #if defined(SYSCFG_CFGR1_I2C_FMP_PB9)
 197 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9     (SYSCFG_CFGR1_I2C_FMP_PB9)  /*!< Fast Mode Plus (FM+) driving capability activation on the pad
 198                                                                          0: PB9 pin operates in standard mode
 199                                                                          1: I2C FM+ mode enabled on PB9 pin, and the Speed control is bypassed */
 200 #endif /* SYSCFG_CFGR1_I2C_FMP_PB9 */
 201
 202 #if defined(SYSCFG_CFGR1_I2C_FMP_I2C1)
 203 #define HAL_SYSCFG_FASTMODEPLUS_I2C1        (SYSCFG_CFGR1_I2C_FMP_I2C1)  /*!< I2C1 fast mode Plus driving capability activation
 204                                                                          0: FM+ mode is not enabled on I2C1 pins selected through AF selection bits
 205                                                                          1: FM+ mode is enabled on I2C1 pins selected through AF selection bits */
 206 #endif /* SYSCFG_CFGR1_I2C_FMP_I2C1 */
 207
 208 #if defined(SYSCFG_CFGR1_I2C_FMP_I2C2)
 209 #define HAL_SYSCFG_FASTMODEPLUS_I2C2        (SYSCFG_CFGR1_I2C_FMP_I2C2)  /*!< I2C2 fast mode Plus driving capability activation
 210                                                                          0: FM+ mode is not enabled on I2C2 pins selected through AF selection bits
 211                                                                          1: FM+ mode is enabled on I2C2 pins selected through AF selection bits */
 212 #endif /* SYSCFG_CFGR1_I2C_FMP_I2C2 */
 213
 214 #if defined(SYSCFG_CFGR1_I2C_FMP_PA9)
 215 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9    (SYSCFG_CFGR1_I2C_FMP_PA9)  /*!< Fast Mode Plus (FM+) driving capability activation on the pad
 216                                                                          0: PA9 pin operates in standard mode
 217                                                                          1: FM+ mode is enabled on PA9 pin, and the Speed control is bypassed */
 218 #endif /* SYSCFG_CFGR1_I2C_FMP_PA9 */
 219
 220 #if defined(SYSCFG_CFGR1_I2C_FMP_PA10)
 221 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10   (SYSCFG_CFGR1_I2C_FMP_PA10)  /*!< Fast Mode Plus (FM+) driving capability activation on the pad
 222                                                                          0: PA10 pin operates in standard mode
 223                                                                          1: FM+ mode is enabled on PA10 pin, and the Speed control is bypassed */
 224 #endif /* SYSCFG_CFGR1_I2C_FMP_PA10 */
 225
 226 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx)
 227 #define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) (((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C1)      || \
 228                                                    ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C2)      || \
 229                                                    ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PA9)   || \
 230                                                    ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PA10)  || \
 231                                                    ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6)   || \
 232                                                    ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7)   || \
 233                                                    ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8)   || \
 234                                                    ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9))
 235 #elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
 236 #define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) (((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C1)      || \
 237                                                    ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C2)      || \
 238                                                    ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6)   || \
 239                                                    ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7)   || \
 240                                                    ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8)   || \
 241                                                    ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9))
 242 #elif defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || defined(STM32F070xB) || defined(STM32F030x6)
 243 #define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) (((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C1)      || \
 244                                                    ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PA9)   || \
 245                                                    ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PA10)  || \
 246                                                    ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6)   || \
 247                                                    ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7)   || \
 248                                                    ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8)   || \
 249                                                    ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9))
 250 #else
 251 #define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) (((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6)   || \
 252                                                    ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7)   || \
 253                                                    ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8)   || \
 254                                                    ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9))
 255 #endif
 256
 257 /**
 258   * @}
 259   */
 260
 261 #if defined(STM32F091xC) || defined (STM32F098xx)
 262 /** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper
 263   * @brief ISR Wrapper
 264   * @note applicable on STM32F09x
 265   * @{
 266   */
 267 #define HAL_SYSCFG_ITLINE0                           ((uint32_t) 0x00000000) /*!< Internal define for macro handling */
 268 #define HAL_SYSCFG_ITLINE1                           ((uint32_t) 0x00000001) /*!< Internal define for macro handling */
 269 #define HAL_SYSCFG_ITLINE2                           ((uint32_t) 0x00000002) /*!< Internal define for macro handling */
 270 #define HAL_SYSCFG_ITLINE3                           ((uint32_t) 0x00000003) /*!< Internal define for macro handling */
 271 #define HAL_SYSCFG_ITLINE4                           ((uint32_t) 0x00000004) /*!< Internal define for macro handling */
 272 #define HAL_SYSCFG_ITLINE5                           ((uint32_t) 0x00000005) /*!< Internal define for macro handling */
 273 #define HAL_SYSCFG_ITLINE6                           ((uint32_t) 0x00000006) /*!< Internal define for macro handling */
 274 #define HAL_SYSCFG_ITLINE7                           ((uint32_t) 0x00000007) /*!< Internal define for macro handling */
 275 #define HAL_SYSCFG_ITLINE8                           ((uint32_t) 0x00000008) /*!< Internal define for macro handling */
 276 #define HAL_SYSCFG_ITLINE9                           ((uint32_t) 0x00000009) /*!< Internal define for macro handling */
 277 #define HAL_SYSCFG_ITLINE10                          ((uint32_t) 0x0000000A) /*!< Internal define for macro handling */
 278 #define HAL_SYSCFG_ITLINE11                          ((uint32_t) 0x0000000B) /*!< Internal define for macro handling */
 279 #define HAL_SYSCFG_ITLINE12                          ((uint32_t) 0x0000000C) /*!< Internal define for macro handling */
 280 #define HAL_SYSCFG_ITLINE13                          ((uint32_t) 0x0000000D) /*!< Internal define for macro handling */
 281 #define HAL_SYSCFG_ITLINE14                          ((uint32_t) 0x0000000E) /*!< Internal define for macro handling */
 282 #define HAL_SYSCFG_ITLINE15                          ((uint32_t) 0x0000000F) /*!< Internal define for macro handling */
 283 #define HAL_SYSCFG_ITLINE16                          ((uint32_t) 0x00000010) /*!< Internal define for macro handling */
 284 #define HAL_SYSCFG_ITLINE17                          ((uint32_t) 0x00000011) /*!< Internal define for macro handling */
 285 #define HAL_SYSCFG_ITLINE18                          ((uint32_t) 0x00000012) /*!< Internal define for macro handling */
 286 #define HAL_SYSCFG_ITLINE19                          ((uint32_t) 0x00000013) /*!< Internal define for macro handling */
 287 #define HAL_SYSCFG_ITLINE20                          ((uint32_t) 0x00000014) /*!< Internal define for macro handling */
 288 #define HAL_SYSCFG_ITLINE21                          ((uint32_t) 0x00000015) /*!< Internal define for macro handling */
 289 #define HAL_SYSCFG_ITLINE22                          ((uint32_t) 0x00000016) /*!< Internal define for macro handling */
 290 #define HAL_SYSCFG_ITLINE23                          ((uint32_t) 0x00000017) /*!< Internal define for macro handling */
 291 #define HAL_SYSCFG_ITLINE24                          ((uint32_t) 0x00000018) /*!< Internal define for macro handling */
 292 #define HAL_SYSCFG_ITLINE25                          ((uint32_t) 0x00000019) /*!< Internal define for macro handling */
 293 #define HAL_SYSCFG_ITLINE26                          ((uint32_t) 0x0000001A) /*!< Internal define for macro handling */
 294 #define HAL_SYSCFG_ITLINE27                          ((uint32_t) 0x0000001B) /*!< Internal define for macro handling */
 295 #define HAL_SYSCFG_ITLINE28                          ((uint32_t) 0x0000001C) /*!< Internal define for macro handling */
 296 #define HAL_SYSCFG_ITLINE29                          ((uint32_t) 0x0000001D) /*!< Internal define for macro handling */
 297 #define HAL_SYSCFG_ITLINE30                          ((uint32_t) 0x0000001E) /*!< Internal define for macro handling */
 298 #define HAL_SYSCFG_ITLINE31                          ((uint32_t) 0x0000001F) /*!< Internal define for macro handling */
 299
 300 #define HAL_ITLINE_EWDG           ((uint32_t) ((HAL_SYSCFG_ITLINE0 << 0x18) | SYSCFG_ITLINE0_SR_EWDG)) /*!< EWDG has expired .... */
 301 #if defined(STM32F091xC)
 302 #define HAL_ITLINE_PVDOUT         ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18) | SYSCFG_ITLINE1_SR_PVDOUT)) /*!< Power voltage detection Interrupt .... */
 303 #endif
 304 #define HAL_ITLINE_VDDIO2         ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18) | SYSCFG_ITLINE1_SR_VDDIO2)) /*!< VDDIO2 Interrupt .... */
 305 #define HAL_ITLINE_RTC_WAKEUP     ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_WAKEUP)) /*!< RTC WAKEUP -> exti[20] Interrupt */
 306 #define HAL_ITLINE_RTC_TSTAMP     ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_TSTAMP)) /*!< RTC Time Stamp -> exti[19] interrupt */
 307 #define HAL_ITLINE_RTC_ALRA       ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_ALRA)) /*!< RTC Alarm -> exti[17] interrupt .... */
 308 #define HAL_ITLINE_FLASH_ITF      ((uint32_t) ((HAL_SYSCFG_ITLINE3 << 0x18) | SYSCFG_ITLINE3_SR_FLASH_ITF)) /*!< Flash ITF Interrupt */
 309 #define HAL_ITLINE_CRS            ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18) | SYSCFG_ITLINE4_SR_CRS)) /*!< CRS Interrupt */
 310 #define HAL_ITLINE_CLK_CTRL       ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18) | SYSCFG_ITLINE4_SR_CLK_CTRL)) /*!< CLK Control Interrupt */
 311 #define HAL_ITLINE_EXTI0          ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18) | SYSCFG_ITLINE5_SR_EXTI0)) /*!< External Interrupt 0 */
 312 #define HAL_ITLINE_EXTI1          ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18) | SYSCFG_ITLINE5_SR_EXTI1)) /*!< External Interrupt 1 */
 313 #define HAL_ITLINE_EXTI2          ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18) | SYSCFG_ITLINE6_SR_EXTI2)) /*!< External Interrupt 2 */
 314 #define HAL_ITLINE_EXTI3          ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18) | SYSCFG_ITLINE6_SR_EXTI3)) /*!< External Interrupt 3 */
 315 #define HAL_ITLINE_EXTI4          ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI4)) /*!< EXTI4 Interrupt */
 316 #define HAL_ITLINE_EXTI5          ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI5)) /*!< EXTI5 Interrupt */
 317 #define HAL_ITLINE_EXTI6          ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI6)) /*!< EXTI6 Interrupt */
 318 #define HAL_ITLINE_EXTI7          ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI7)) /*!< EXTI7 Interrupt */
 319 #define HAL_ITLINE_EXTI8          ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI8)) /*!< EXTI8 Interrupt */
 320 #define HAL_ITLINE_EXTI9          ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI9)) /*!< EXTI9 Interrupt */
 321 #define HAL_ITLINE_EXTI10         ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI10)) /*!< EXTI10 Interrupt */
 322 #define HAL_ITLINE_EXTI11         ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI11)) /*!< EXTI11 Interrupt */
 323 #define HAL_ITLINE_EXTI12         ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI12)) /*!< EXTI12 Interrupt */
 324 #define HAL_ITLINE_EXTI13         ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI13)) /*!< EXTI13 Interrupt */
 325 #define HAL_ITLINE_EXTI14         ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI14)) /*!< EXTI14 Interrupt */
 326 #define HAL_ITLINE_EXTI15         ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI15)) /*!< EXTI15 Interrupt */
 327 #define HAL_ITLINE_TSC_EOA        ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18) | SYSCFG_ITLINE8_SR_TSC_EOA)) /*!< Touch control EOA Interrupt */
 328 #define HAL_ITLINE_TSC_MCE        ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18) | SYSCFG_ITLINE8_SR_TSC_MCE)) /*!< Touch control MCE Interrupt */
 329 #define HAL_ITLINE_DMA1_CH1       ((uint32_t) ((HAL_SYSCFG_ITLINE9 << 0x18) | SYSCFG_ITLINE9_SR_DMA1_CH1)) /*!< DMA1 Channel 1 Interrupt */
 330 #define HAL_ITLINE_DMA1_CH2       ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA1_CH2)) /*!< DMA1 Channel 2 Interrupt */
 331 #define HAL_ITLINE_DMA1_CH3       ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA1_CH3)) /*!< DMA1 Channel 3 Interrupt */
 332 #define HAL_ITLINE_DMA2_CH1       ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA2_CH1)) /*!< DMA2 Channel 1 Interrupt */
 333 #define HAL_ITLINE_DMA2_CH2       ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA2_CH2)) /*!< DMA2 Channel 2 Interrupt */
 334 #define HAL_ITLINE_DMA1_CH4       ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH4)) /*!< DMA1 Channel 4 Interrupt */
 335 #define HAL_ITLINE_DMA1_CH5       ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH5)) /*!< DMA1 Channel 5 Interrupt */
 336 #define HAL_ITLINE_DMA1_CH6       ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH6)) /*!< DMA1 Channel 6 Interrupt */
 337 #define HAL_ITLINE_DMA1_CH7       ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH7)) /*!< DMA1 Channel 7 Interrupt */
 338 #define HAL_ITLINE_DMA2_CH3       ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH3)) /*!< DMA2 Channel 3 Interrupt */
 339 #define HAL_ITLINE_DMA2_CH4       ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH4)) /*!< DMA2 Channel 4 Interrupt */
 340 #define HAL_ITLINE_DMA2_CH5       ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH5)) /*!< DMA2 Channel 5 Interrupt */
 341 #define HAL_ITLINE_ADC            ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_ADC)) /*!< ADC Interrupt */
 342 #define HAL_ITLINE_COMP1          ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_COMP1)) /*!< COMP1 Interrupt -> exti[21] */
 343 #define HAL_ITLINE_COMP2          ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_COMP2)) /*!< COMP2 Interrupt -> exti[21] */
 344 #define HAL_ITLINE_TIM1_BRK       ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_BRK)) /*!< TIM1 BRK Interrupt */
 345 #define HAL_ITLINE_TIM1_UPD       ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_UPD)) /*!< TIM1 UPD Interrupt */
 346 #define HAL_ITLINE_TIM1_TRG       ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_TRG)) /*!< TIM1 TRG Interrupt */
 347 #define HAL_ITLINE_TIM1_CCU       ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_CCU)) /*!< TIM1 CCU Interrupt */
 348 #define HAL_ITLINE_TIM1_CC        ((uint32_t) ((HAL_SYSCFG_ITLINE14 << 0x18) | SYSCFG_ITLINE14_SR_TIM1_CC)) /*!< TIM1 CC Interrupt */
 349 #define HAL_ITLINE_TIM2           ((uint32_t) ((HAL_SYSCFG_ITLINE15 << 0x18) | SYSCFG_ITLINE15_SR_TIM2_GLB)) /*!< TIM2 Interrupt */
 350 #define HAL_ITLINE_TIM3           ((uint32_t) ((HAL_SYSCFG_ITLINE16 << 0x18) | SYSCFG_ITLINE16_SR_TIM3_GLB)) /*!< TIM3 Interrupt */
 351 #define HAL_ITLINE_DAC            ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18) | SYSCFG_ITLINE17_SR_DAC)) /*!< DAC Interrupt */
 352 #define HAL_ITLINE_TIM6           ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18) | SYSCFG_ITLINE17_SR_TIM6_GLB)) /*!< TIM6 Interrupt */
 353 #define HAL_ITLINE_TIM7           ((uint32_t) ((HAL_SYSCFG_ITLINE18 << 0x18) | SYSCFG_ITLINE18_SR_TIM7_GLB)) /*!< TIM7 Interrupt */
 354 #define HAL_ITLINE_TIM14          ((uint32_t) ((HAL_SYSCFG_ITLINE19 << 0x18) | SYSCFG_ITLINE19_SR_TIM14_GLB)) /*!< TIM14 Interrupt */
 355 #define HAL_ITLINE_TIM15          ((uint32_t) ((HAL_SYSCFG_ITLINE20 << 0x18) | SYSCFG_ITLINE20_SR_TIM15_GLB)) /*!< TIM15 Interrupt */
 356 #define HAL_ITLINE_TIM16          ((uint32_t) ((HAL_SYSCFG_ITLINE21 << 0x18) | SYSCFG_ITLINE21_SR_TIM16_GLB)) /*!< TIM16 Interrupt */
 357 #define HAL_ITLINE_TIM17          ((uint32_t) ((HAL_SYSCFG_ITLINE22 << 0x18) | SYSCFG_ITLINE22_SR_TIM17_GLB)) /*!< TIM17 Interrupt */
 358 #define HAL_ITLINE_I2C1           ((uint32_t) ((HAL_SYSCFG_ITLINE23 << 0x18) | SYSCFG_ITLINE23_SR_I2C1_GLB)) /*!< I2C1 Interrupt -> exti[23] */
 359 #define HAL_ITLINE_I2C2           ((uint32_t) ((HAL_SYSCFG_ITLINE24 << 0x18) | SYSCFG_ITLINE24_SR_I2C2_GLB)) /*!< I2C2 Interrupt */
 360 #define HAL_ITLINE_SPI1           ((uint32_t) ((HAL_SYSCFG_ITLINE25 << 0x18) | SYSCFG_ITLINE25_SR_SPI1)) /*!< I2C1 Interrupt -> exti[23] */
 361 #define HAL_ITLINE_SPI2           ((uint32_t) ((HAL_SYSCFG_ITLINE26 << 0x18) | SYSCFG_ITLINE26_SR_SPI2)) /*!< SPI1 Interrupt */
 362 #define HAL_ITLINE_USART1         ((uint32_t) ((HAL_SYSCFG_ITLINE27 << 0x18) | SYSCFG_ITLINE27_SR_USART1_GLB)) /*!< USART1 GLB Interrupt -> exti[25] */
 363 #define HAL_ITLINE_USART2         ((uint32_t) ((HAL_SYSCFG_ITLINE28 << 0x18) | SYSCFG_ITLINE28_SR_USART2_GLB)) /*!< USART2 GLB Interrupt -> exti[26] */
 364 #define HAL_ITLINE_USART3         ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART3_GLB)) /*!< USART3 Interrupt .... */
 365 #define HAL_ITLINE_USART4         ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART4_GLB)) /*!< USART4 Interrupt .... */
 366 #define HAL_ITLINE_USART5         ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART5_GLB)) /*!< USART5 Interrupt .... */
 367 #define HAL_ITLINE_USART6         ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART6_GLB)) /*!< USART6 Interrupt .... */
 368 #define HAL_ITLINE_USART7         ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART7_GLB)) /*!< USART7 Interrupt .... */
 369 #define HAL_ITLINE_USART8         ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART8_GLB)) /*!< USART8 Interrupt .... */
 370 #define HAL_ITLINE_CAN            ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18) | SYSCFG_ITLINE30_SR_CAN)) /*!< CAN Interrupt */
 371 #define HAL_ITLINE_CEC            ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18) | SYSCFG_ITLINE30_SR_CEC)) /*!< CEC Interrupt -> exti[27] */
 372 /**
 373   * @}
 374   */
 375 #endif /* STM32F091xC || STM32F098xx */
 376
 377 /**
 378   * @}
 379   */
 380
 381 /* Exported macros -----------------------------------------------------------*/
 382 /** @defgroup HAL_Exported_Macros HAL Exported Macros
 383   * @{
 384   */
 385
 386 /** @defgroup HAL_Freeze_Unfreeze_Peripherals HAL Freeze Unfreeze Peripherals
 387   * @brief  Freeze/Unfreeze Peripherals in Debug mode
 388   * @{
 389   */
 390
 391 #if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
 392 #define __HAL_FREEZE_CAN_DBGMCU()            (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP))
 393 #define __HAL_UNFREEZE_CAN_DBGMCU()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP))
 394 #endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */
 395
 396 #if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP)
 397 #define __HAL_FREEZE_RTC_DBGMCU()            (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
 398 #define __HAL_UNFREEZE_RTC_DBGMCU()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
 399 #endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */
 400
 401 #if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
 402 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
 403 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
 404 #endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */
 405
 406 #if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP)
 407 #define __HAL_FREEZE_IWDG_DBGMCU()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
 408 #define __HAL_UNFREEZE_IWDG_DBGMCU()         (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
 409 #endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */
 410
 411 #if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP)
 412 #define __HAL_FREEZE_WWDG_DBGMCU()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
 413 #define __HAL_UNFREEZE_WWDG_DBGMCU()         (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
 414 #endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */
 415
 416 #if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
 417 #define __HAL_FREEZE_TIM2_DBGMCU()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
 418 #define __HAL_UNFREEZE_TIM2_DBGMCU()         (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
 419 #endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
 420
 421 #if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
 422 #define __HAL_FREEZE_TIM3_DBGMCU()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
 423 #define __HAL_UNFREEZE_TIM3_DBGMCU()         (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
 424 #endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
 425
 426 #if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
 427 #define __HAL_FREEZE_TIM6_DBGMCU()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
 428 #define __HAL_UNFREEZE_TIM6_DBGMCU()         (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
 429 #endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
 430
 431 #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
 432 #define __HAL_FREEZE_TIM7_DBGMCU()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
 433 #define __HAL_UNFREEZE_TIM7_DBGMCU()         (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
 434 #endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
 435
 436 #if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
 437 #define __HAL_FREEZE_TIM14_DBGMCU()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
 438 #define __HAL_UNFREEZE_TIM14_DBGMCU()        (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
 439 #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
 440
 441 #if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
 442 #define __HAL_FREEZE_TIM1_DBGMCU()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
 443 #define __HAL_UNFREEZE_TIM1_DBGMCU()         (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
 444 #endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */
 445
 446 #if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
 447 #define __HAL_FREEZE_TIM15_DBGMCU()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP))
 448 #define __HAL_UNFREEZE_TIM15_DBGMCU()        (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP))
 449 #endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */
 450
 451 #if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP)
 452 #define __HAL_FREEZE_TIM16_DBGMCU()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP))
 453 #define __HAL_UNFREEZE_TIM16_DBGMCU()        (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP))
 454 #endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */
 455
 456 #if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP)
 457 #define __HAL_FREEZE_TIM17_DBGMCU()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP))
 458 #define __HAL_UNFREEZE_TIM17_DBGMCU()        (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP))
 459 #endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */
 460
 461 /**
 462   * @}
 463   */
 464
 465 /** @defgroup Memory_Mapping_Selection Memory Mapping Selection
 466   * @{
 467   */
 468 #if defined(SYSCFG_CFGR1_MEM_MODE)
 469 /** @brief  Main Flash memory mapped at 0x00000000
 470   */
 471 #define __HAL_REMAPMEMORY_FLASH()        (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE))
 472 #endif /* SYSCFG_CFGR1_MEM_MODE */
 473
 474 #if defined(SYSCFG_CFGR1_MEM_MODE_0)
 475 /** @brief  System Flash memory mapped at 0x00000000
 476   */
 477 #define __HAL_REMAPMEMORY_SYSTEMFLASH()  do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
 478                                              SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0;  \
 479                                             }while(0)
 480 #endif /* SYSCFG_CFGR1_MEM_MODE_0 */
 481
 482 #if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1)
 483 /** @brief  Embedded SRAM mapped at 0x00000000
 484   */
 485 #define __HAL_REMAPMEMORY_SRAM()         do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
 486                                              SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \
 487                                             }while(0)
 488 #endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */
 489 /**
 490   * @}
 491   */
 492
 493 #if defined(SYSCFG_CFGR1_DMA_RMP)
 494 /** @defgroup HAL_DMA_remap HAL DMA remap
 495   * @brief  DMA remapping enable/disable macros
 496   * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_remapping
 497   * @{
 498   */
 499 #define __HAL_REMAPDMA_CHANNEL_ENABLE(__DMA_REMAP__)   do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__)));                  \
 500                                                            SYSCFG->CFGR1 |= (__DMA_REMAP__);                                \
 501                                                          }while(0)
 502 #define __HAL_REMAPDMA_CHANNEL_DISABLE(__DMA_REMAP__)  do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__)));                  \
 503                                                            SYSCFG->CFGR1 &= ~(__DMA_REMAP__);                               \
 504                                                          }while(0)
 505 /**
 506   * @}
 507   */
 508 #endif /* SYSCFG_CFGR1_DMA_RMP */
 509
 510 #if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
 511 /** @defgroup HAL_Pin_remap HAL Pin remap
 512   * @brief  Pin remapping enable/disable macros
 513   * @param __PIN_REMAP__: This parameter can be a value of @ref HAL_Pin_remapping
 514   * @{
 515   */
 516 #define __HAL_REMAP_PIN_ENABLE(__PIN_REMAP__)          do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__)));                 \
 517                                                            SYSCFG->CFGR1 |= (__PIN_REMAP__);                                \
 518                                                          }while(0)
 519 #define __HAL_REMAP_PIN_DISABLE(__PIN_REMAP__)         do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__)));                 \
 520                                                            SYSCFG->CFGR1 &= ~(__PIN_REMAP__);                               \
 521                                                          }while(0)
 522 /**
 523   * @}
 524   */
 525 #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
 526
 527 /** @defgroup HAL_Fast_mode_plus_driving_cap HAL Fast mode plus driving cap
 528   * @brief  Fast mode Plus driving capability enable/disable macros
 529   * @param __FASTMODEPLUS__: This parameter can be a value of @ref HAL_FastModePlus_I2C
 530   * @{
 531   */
 532 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG((__FASTMODEPLUS__))); \
 533                                                                 SYSCFG->CFGR1 |= (__FASTMODEPLUS__);                                 \
 534                                                                }while(0)
 535
 536 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG((__FASTMODEPLUS__))); \
 537                                                                 SYSCFG->CFGR1 &= ~(__FASTMODEPLUS__);                                \
 538                                                                }while(0)
 539 /**
 540   * @}
 541   */
 542
 543 #if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
 544 /** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
 545   * @{
 546   */
 547 /** @brief  SYSCFG Break Lockup lock
 548   *         Enables and locks the connection of Cortex-M0 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input
 549   * @note   The selected configuration is locked and can be unlocked by system reset
 550   */
 551 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()   do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
 552                                                SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK;    \
 553                                               }while(0)
 554 /**
 555   * @}
 556   */
 557 #endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
 558
 559 #if defined(SYSCFG_CFGR2_PVD_LOCK)
 560 /** @defgroup PVD_Lock_Enable PVD Lock
 561   * @{
 562   */
 563 /** @brief  SYSCFG Break PVD lock
 564   *         Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
 565   * @note   The selected configuration is locked and can be unlocked by system reset
 566   */
 567 #define __HAL_SYSCFG_BREAK_PVD_LOCK()      do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
 568                                                SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK;    \
 569                                               }while(0)
 570 /**
 571   * @}
 572   */
 573 #endif /* SYSCFG_CFGR2_PVD_LOCK */
 574
 575 #if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
 576 /** @defgroup SRAM_Parity_Lock SRAM Parity Lock
 577   * @{
 578   */
 579 /** @brief  SYSCFG Break SRAM PARITY lock
 580   *         Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17
 581   * @note   The selected configuration is locked and can be unlocked by system reset
 582   */
 583 #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \
 584                                                  SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK;    \
 585                                                 }while(0)
 586 /**
 587   * @}
 588   */
 589 #endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
 590
 591 #if defined(SYSCFG_CFGR2_SRAM_PEF)
 592 /** @defgroup HAL_SYSCFG_Parity_check_on_RAM HAL SYSCFG Parity check on RAM
 593   * @brief  Parity check on RAM disable macro
 594   * @note   Disabling the parity check on RAM locks the configuration bit.
 595   *         To re-enable the parity check on RAM perform a system reset.
 596   * @{
 597   */
 598 #define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE()   (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PEF)
 599 /**
 600   * @}
 601   */
 602 #endif /* SYSCFG_CFGR2_SRAM_PEF */
 603
 604
 605 #if defined(STM32F091xC) || defined (STM32F098xx)
 606 /** @defgroup HAL_ISR_wrapper_check HAL ISR wrapper check
 607   * @brief  ISR wrapper check
 608   * @note This feature is applicable on STM32F09x
 609   * @note Allow to determine interrupt source per line.
 610   * @{
 611   */
 612 #define __HAL_GET_PENDING_IT(__SOURCE__)       (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18)] & ((__SOURCE__) & 0x00FFFFFF))
 613 /**
 614   * @}
 615   */
 616 #endif /* (STM32F091xC) || defined (STM32F098xx)*/
 617
 618 #if defined(STM32F091xC) || defined (STM32F098xx)
 619 /** @defgroup HAL_SYSCFG_IRDA_modulation_envelope_selection HAL SYSCFG IRDA modulation envelope selection
 620   * @brief  selection of the modulation envelope signal macro, using bits [7:6] of SYS_CTRL(CFGR1) register
 621   * @note This feature is applicable on STM32F09x
 622   * @param __SOURCE__: This parameter can be a value of @ref HAL_IRDA_ENV_SEL
 623   * @{
 624   */
 625 #define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__)  do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__))); \
 626                                                          SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_IRDA_ENV_SEL); \
 627                                                          SYSCFG->CFGR1 |= (__SOURCE__);    \
 628                                                         }while(0)
 629
 630 #define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION()  ((SYSCFG->CFGR1) & 0x000000C0)
 631 /**
 632   * @}
 633   */
 634 #endif /* (STM32F091xC) || defined (STM32F098xx)*/
 635
 636 /**
 637   * @}
 638   */
 639 /* Exported functions --------------------------------------------------------*/
 640 /** @addtogroup HAL_Exported_Functions HAL Exported Functions
 641   * @{
 642   */
 643
 644 /** @addtogroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
 645  *  @brief    Initialization and de-initialization functions
 646   * @{
 647   */
 648 /* Initialization and de-initialization functions  ******************************/
 649 HAL_StatusTypeDef HAL_Init(void);
 650 HAL_StatusTypeDef HAL_DeInit(void);
 651 void              HAL_MspInit(void);
 652 void              HAL_MspDeInit(void);
 653 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
 654 /**
 655   * @}
 656   */
 657
 658 /** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions
 659  *  @brief    HAL Control functions
 660   * @{
 661   */
 662 /* Peripheral Control functions  **********************************************/
 663 void              HAL_IncTick(void);
 664 void              HAL_Delay(__IO uint32_t Delay);
 665 uint32_t          HAL_GetTick(void);
 666 void              HAL_SuspendTick(void);
 667 void              HAL_ResumeTick(void);
 668 uint32_t          HAL_GetHalVersion(void);
 669 uint32_t          HAL_GetREVID(void);
 670 uint32_t          HAL_GetDEVID(void);
 671 void              HAL_EnableDBGStopMode(void);
 672 void              HAL_DisableDBGStopMode(void);
 673 void              HAL_EnableDBGStandbyMode(void);
 674 void              HAL_DisableDBGStandbyMode(void);
 675 /**
 676   * @}
 677   */
 678
 679 /**
 680   * @}
 681   */
 682
 683 /**
 684   * @}
 685   */
 686
 687 /**
 688   * @}
 689   */
 690
 691 #ifdef __cplusplus
 692 }
 693 #endif
 694
 695 #endif /* __STM32F0xx_HAL_H */
 696
 697 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/