tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_i2s.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f0xx_hal_i2s.c
   4   * @author  MCD Application Team
   5   * @version V1.2.0
   6   * @date    11-December-2014
   7   * @brief   I2S HAL module driver.
   8   *          This file provides firmware functions to manage the following
   9   *          functionalities of the Integrated Interchip Sound (I2S) peripheral:
  10   *           + Initialization and de-initialization functions
  11   *           + IO operation functions
  12   *           + Peripheral State and Errors functions
  13   @verbatim
  14  ===============================================================================
  15                   ##### How to use this driver #####
  16  ===============================================================================
  17  [..]
  18     The I2S HAL driver can be used as follow:
  19
  20     (#) Declare a I2S_HandleTypeDef handle structure.
  21     (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
  22         (##) Enable the SPIx interface clock.
  23         (##) I2S pins configuration:
  24             (+++) Enable the clock for the I2S GPIOs.
  25             (+++) Configure these I2S pins as alternate function pull-up.
  26         (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
  27              and HAL_I2S_Receive_IT() APIs).
  28             (+++) Configure the I2Sx interrupt priority.
  29             (+++) Enable the NVIC I2S IRQ handle.
  30         (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
  31              and HAL_I2S_Receive_DMA() APIs:
  32             (+++) Declare a DMA handle structure for the Tx/Rx Channel.
  33             (+++) Enable the DMAx interface clock.
  34             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
  35             (+++) Configure the DMA Tx/Rx Channel.
  36             (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle.
  37             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
  38                   DMA Tx/Rx Channel.
  39
  40    (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
  41        using HAL_I2S_Init() function.
  42
  43    -@- The specific I2S interrupts (Transmission complete interrupt,
  44        RXNE interrupt and Error Interrupts) will be managed using the macros
  45        __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
  46    -@- Make sure that either:
  47        (+@) External clock source is configured after setting correctly
  48             the define constant EXTERNAL_CLOCK_VALUE in the stm32f0xx_hal_conf.h file.
  49
  50     (#) Three mode of operations are available within this driver :
  51
  52    *** Polling mode IO operation ***
  53    =================================
  54    [..]
  55      (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
  56      (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
  57
  58    *** Interrupt mode IO operation ***
  59    ===================================
  60    [..]
  61      (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
  62      (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
  63          add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
  64      (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
  65          add his own code by customization of function pointer HAL_I2S_TxCpltCallback
  66      (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
  67      (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
  68          add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
  69      (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
  70          add his own code by customization of function pointer HAL_I2S_RxCpltCallback
  71      (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
  72          add his own code by customization of function pointer HAL_I2S_ErrorCallback
  73
  74    *** DMA mode IO operation ***
  75    ==============================
  76    [..]
  77      (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
  78      (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
  79          add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
  80      (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
  81          add his own code by customization of function pointer HAL_I2S_TxCpltCallback
  82      (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
  83      (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
  84          add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
  85      (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
  86          add his own code by customization of function pointer HAL_I2S_RxCpltCallback
  87      (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
  88          add his own code by customization of function pointer HAL_I2S_ErrorCallback
  89      (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
  90      (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
  91      (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
  92
  93    *** I2S HAL driver macros list ***
  94    =============================================
  95    [..]
  96      Below the list of most used macros in I2S HAL driver.
  97
  98       (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
  99       (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
 100       (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
 101       (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
 102       (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
 103
 104     [..]
 105       (@) You can refer to the I2S HAL driver header file for more useful macros
 106
 107   @endverbatim
 108   ******************************************************************************
 109   * @attention
 110   *
 111   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
 112   *
 113   * Redistribution and use in source and binary forms, with or without modification,
 114   * are permitted provided that the following conditions are met:
 115   *   1. Redistributions of source code must retain the above copyright notice,
 116   *      this list of conditions and the following disclaimer.
 117   *   2. Redistributions in binary form must reproduce the above copyright notice,
 118   *      this list of conditions and the following disclaimer in the documentation
 119   *      and/or other materials provided with the distribution.
 120   *   3. Neither the name of STMicroelectronics nor the names of its contributors
 121   *      may be used to endorse or promote products derived from this software
 122   *      without specific prior written permission.
 123   *
 124   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 125   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 126   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 127   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 128   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 129   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 130   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 131   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 132   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 133   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 134   *
 135   ******************************************************************************
 136   */
 137
 138 /* Includes ------------------------------------------------------------------*/
 139 #include "stm32f0xx_hal.h"
 140
 141 #ifdef HAL_I2S_MODULE_ENABLED
 142
 143 #if defined(STM32F031x6) || defined(STM32F038xx) || \
 144     defined(STM32F051x8) || defined(STM32F058xx) || \
 145     defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
 146     defined(STM32F042x6) || defined(STM32F048xx) || \
 147     defined(STM32F091xC) || defined(STM32F098xx)
 148
 149 /** @addtogroup STM32F0xx_HAL_Driver
 150   * @{
 151   */
 152
 153 /** @defgroup I2S I2S HAL module driver
 154   * @brief I2S HAL module driver
 155   * @{
 156   */
 157
 158 /* Private typedef -----------------------------------------------------------*/
 159 /* Private define ------------------------------------------------------------*/
 160 /* Private macro -------------------------------------------------------------*/
 161 /* Private variables ---------------------------------------------------------*/
 162 /* Private function prototypes -----------------------------------------------*/
 163 /** @defgroup I2S_Private_Functions I2S Private Functions
 164   * @{
 165   */
 166 static void               I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
 167 static void               I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
 168 static void               I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
 169 static void               I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
 170 static void               I2S_DMAError(DMA_HandleTypeDef *hdma);
 171 static void               I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
 172 static void               I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
 173 static HAL_StatusTypeDef  I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout);
 174 /**
 175   * @}
 176   */
 177
 178 /* Exported functions ---------------------------------------------------------*/
 179
 180 /** @defgroup I2S_Exported_Functions I2S Exported Functions
 181   * @{
 182   */
 183
 184 /** @defgroup  I2S_Exported_Functions_Group1 Initialization and de-initialization functions
 185   *  @brief    Initialization and Configuration functions
 186   *
 187 @verbatim
 188  ===============================================================================
 189               ##### Initialization and de-initialization functions #####
 190  ===============================================================================
 191     [..]  This subsection provides a set of functions allowing to initialize and
 192           de-initialiaze the I2Sx peripheral in simplex mode:
 193
 194       (+) User must Implement HAL_I2S_MspInit() function in which he configures
 195           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
 196
 197       (+) Call the function HAL_I2S_Init() to configure the selected device with
 198           the selected configuration:
 199         (++) Mode
 200         (++) Standard
 201         (++) Data Format
 202         (++) MCLK Output
 203         (++) Audio frequency
 204         (++) Polarity
 205
 206      (+) Call the function HAL_I2S_DeInit() to restore the default configuration
 207          of the selected I2Sx periperal.
 208   @endverbatim
 209   * @{
 210   */
 211
 212 /**
 213   * @brief Initializes the I2S according to the specified parameters
 214   *         in the I2S_InitTypeDef and create the associated handle.
 215   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 216   *         the configuration information for I2S module
 217   * @retval HAL status
 218   */
 219 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
 220 {
 221   uint32_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
 222   uint32_t tmp = 0, i2sclk = 0;
 223
 224   /* Check the I2S handle allocation */
 225   if(hi2s == NULL)
 226   {
 227     return HAL_ERROR;
 228   }
 229
 230   /* Check the I2S parameters */
 231   assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
 232   assert_param(IS_I2S_MODE(hi2s->Init.Mode));
 233   assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
 234   assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
 235   assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
 236   assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
 237   assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
 238
 239   if(hi2s->State == HAL_I2S_STATE_RESET)
 240   {
 241     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
 242     HAL_I2S_MspInit(hi2s);
 243   }
 244
 245   hi2s->State = HAL_I2S_STATE_BUSY;
 246
 247   /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/
 248   /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
 249   hi2s->Instance->I2SCFGR &= (uint16_t)(~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
 250                                           SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
 251                                           SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
 252   hi2s->Instance->I2SPR = 0x0002;
 253
 254   /* Get the I2SCFGR register value */
 255   tmpreg = hi2s->Instance->I2SCFGR;
 256
 257   /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
 258   if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)
 259   {
 260     i2sodd = (uint16_t)0;
 261     i2sdiv = (uint16_t)2;
 262   }
 263   /* If the requested audio frequency is not the default, compute the prescaler */
 264   else
 265   {
 266     /* Check the frame length (For the Prescaler computing) *******************/
 267     if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
 268     {
 269       /* Packet length is 16 bits */
 270       packetlength = 1;
 271     }
 272     else
 273     {
 274       /* Packet length is 32 bits */
 275       packetlength = 2;
 276     }
 277
 278     /* Get I2S source Clock frequency  ****************************************/
 279     i2sclk = HAL_RCC_GetSysClockFreq();
 280
 281     /* Compute the Real divider depending on the MCLK output state, with a floating point */
 282     if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
 283     {
 284       /* MCLK output is enabled */
 285       tmp = (uint32_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);
 286     }
 287     else
 288     {
 289       /* MCLK output is disabled */
 290       tmp = (uint32_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);
 291     }
 292
 293     /* Remove the flatting point */
 294     tmp = tmp / 10;
 295
 296     /* Check the parity of the divider */
 297     i2sodd = (uint32_t)(tmp & (uint32_t)1);
 298
 299     /* Compute the i2sdiv prescaler */
 300     i2sdiv = (uint32_t)((tmp - i2sodd) / 2);
 301
 302     /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
 303     i2sodd = (uint32_t) (i2sodd << 8);
 304   }
 305
 306   /* Test if the divider is 1 or 0 or greater than 0xFF */
 307   if((i2sdiv < 2) || (i2sdiv > 0xFF))
 308   {
 309     /* Set the default values */
 310     i2sdiv = 2;
 311     i2sodd = 0;
 312   }
 313
 314   /* Write to SPIx I2SPR register the computed value */
 315   hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
 316
 317   /* Configure the I2S with the I2S_InitStruct values */
 318   tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
 319
 320   /* Write to SPIx I2SCFGR */
 321   hi2s->Instance->I2SCFGR = tmpreg;
 322
 323   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
 324   hi2s->State= HAL_I2S_STATE_READY;
 325
 326   return HAL_OK;
 327 }
 328
 329 /**
 330   * @brief DeInitializes the I2S peripheral
 331   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 332   *         the configuration information for I2S module
 333   * @retval HAL status
 334   */
 335 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
 336 {
 337   /* Check the I2S handle allocation */
 338   if(hi2s == NULL)
 339   {
 340     return HAL_ERROR;
 341   }
 342
 343   /* Check the parameters */
 344   assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
 345
 346   hi2s->State = HAL_I2S_STATE_BUSY;
 347
 348   /* Disable the I2S Peripheral Clock */
 349   __HAL_I2S_DISABLE(hi2s);
 350
 351   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
 352   HAL_I2S_MspDeInit(hi2s);
 353
 354   hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
 355   hi2s->State = HAL_I2S_STATE_RESET;
 356
 357   /* Release Lock */
 358   __HAL_UNLOCK(hi2s);
 359
 360   return HAL_OK;
 361 }
 362
 363 /**
 364   * @brief I2S MSP Init
 365   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 366   *         the configuration information for I2S module
 367   * @retval None
 368   */
 369  __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
 370 {
 371   /* NOTE : This function Should not be modified, when the callback is needed,
 372             the HAL_I2S_MspInit could be implemented in the user file
 373    */
 374 }
 375
 376 /**
 377   * @brief I2S MSP DeInit
 378   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 379   *         the configuration information for I2S module
 380   * @retval None
 381   */
 382  __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
 383 {
 384   /* NOTE : This function Should not be modified, when the callback is needed,
 385             the HAL_I2S_MspDeInit could be implemented in the user file
 386    */
 387 }
 388
 389 /**
 390   * @}
 391   */
 392
 393 /** @defgroup I2S_Exported_Functions_Group2 IO operation functions
 394   *  @brief Data transfers functions
 395   *
 396 @verbatim
 397  ===============================================================================
 398                       ##### IO operation functions #####
 399  ===============================================================================
 400     [..]
 401     This subsection provides a set of functions allowing to manage the I2S data
 402     transfers.
 403
 404     (#) There are two modes of transfer:
 405        (++) Blocking mode : The communication is performed in the polling mode.
 406             The status of all data processing is returned by the same function
 407             after finishing transfer.
 408        (++) No-Blocking mode : The communication is performed using Interrupts
 409             or DMA. These functions return the status of the transfer startup.
 410             The end of the data processing will be indicated through the
 411             dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
 412             using DMA mode.
 413
 414     (#) Blocking mode functions are :
 415         (++) HAL_I2S_Transmit()
 416         (++) HAL_I2S_Receive()
 417
 418     (#) No-Blocking mode functions with Interrupt are :
 419         (++) HAL_I2S_Transmit_IT()
 420         (++) HAL_I2S_Receive_IT()
 421
 422     (#) No-Blocking mode functions with DMA are :
 423         (++) HAL_I2S_Transmit_DMA()
 424         (++) HAL_I2S_Receive_DMA()
 425
 426     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
 427         (++) HAL_I2S_TxCpltCallback()
 428         (++) HAL_I2S_RxCpltCallback()
 429         (++) HAL_I2S_ErrorCallback()
 430
 431 @endverbatim
 432   * @{
 433   */
 434
 435 /**
 436   * @brief Transmit an amount of data in blocking mode
 437   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 438   *         the configuration information for I2S module
 439   * @param pData: a 16-bit pointer to data buffer.
 440   * @param Size: number of data sample to be sent:
 441   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
 442   *       configuration phase, the Size parameter means the number of 16-bit data length
 443   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
 444   *       the Size parameter means the number of 16-bit data length.
 445   * @param  Timeout: Timeout duration
 446   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
 447   *       between Master and Slave(example: audio streaming).
 448   * @retval HAL status
 449   */
 450 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
 451 {
 452   if((pData == NULL ) || (Size == 0))
 453   {
 454     return  HAL_ERROR;
 455   }
 456
 457   /* Process Locked */
 458   __HAL_LOCK(hi2s);
 459
 460   if(hi2s->State == HAL_I2S_STATE_READY)
 461   {
 462     if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
 463       ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
 464     {
 465       hi2s->TxXferSize = (Size << 1);
 466       hi2s->TxXferCount = (Size << 1);
 467     }
 468     else
 469     {
 470       hi2s->TxXferSize = Size;
 471       hi2s->TxXferCount = Size;
 472     }
 473
 474     /* Set state and reset error code */
 475     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
 476     hi2s->State = HAL_I2S_STATE_BUSY_TX;
 477     hi2s->pTxBuffPtr = pData;
 478
 479     /* Check if the I2S is already enabled */
 480     if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
 481     {
 482       /* Enable I2S peripheral */
 483       __HAL_I2S_ENABLE(hi2s);
 484     }
 485
 486     while(hi2s->TxXferCount > 0)
 487     {
 488       /* Wait until TXE flag is set */
 489       if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
 490       {
 491         return HAL_TIMEOUT;
 492       }
 493       hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
 494       hi2s->TxXferCount--;
 495     }
 496
 497     /* Wait until TXE flag is set, to confirm the end of the transcation */
 498     if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
 499     {
 500       return HAL_TIMEOUT;
 501     }
 502     /* Wait until Busy flag is reset */
 503     if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
 504     {
 505       return HAL_TIMEOUT;
 506     }
 507
 508     hi2s->State = HAL_I2S_STATE_READY;
 509
 510     /* Process Unlocked */
 511     __HAL_UNLOCK(hi2s);
 512
 513     return HAL_OK;
 514   }
 515   else
 516   {
 517     /* Process Unlocked */
 518     __HAL_UNLOCK(hi2s);
 519     return HAL_BUSY;
 520   }
 521 }
 522
 523 /**
 524   * @brief Receive an amount of data in blocking mode
 525   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 526   *         the configuration information for I2S module
 527   * @param pData: a 16-bit pointer to data buffer.
 528   * @param Size: number of data sample to be sent:
 529   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
 530   *       configuration phase, the Size parameter means the number of 16-bit data length
 531   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
 532   *       the Size parameter means the number of 16-bit data length.
 533   * @param Timeout: Timeout duration
 534   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
 535   *       between Master and Slave(example: audio streaming).
 536   * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
 537   *       in continouse way and as the I2S is not disabled at the end of the I2S transaction.
 538   * @retval HAL status
 539   */
 540 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
 541 {
 542   if((pData == NULL ) || (Size == 0))
 543   {
 544     return  HAL_ERROR;
 545   }
 546
 547   /* Process Locked */
 548   __HAL_LOCK(hi2s);
 549
 550   if(hi2s->State == HAL_I2S_STATE_READY)
 551   {
 552     if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
 553       ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
 554     {
 555       hi2s->RxXferSize = (Size << 1);
 556       hi2s->RxXferCount = (Size << 1);
 557     }
 558     else
 559     {
 560       hi2s->RxXferSize = Size;
 561       hi2s->RxXferCount = Size;
 562     }
 563
 564     /* Set state and reset error code */
 565     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
 566     hi2s->State = HAL_I2S_STATE_BUSY_RX;
 567     hi2s->pRxBuffPtr = pData;
 568
 569     /* Check if the I2S is already enabled */
 570     if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
 571     {
 572       /* Enable I2S peripheral */
 573       __HAL_I2S_ENABLE(hi2s);
 574     }
 575
 576     /* Receive data */
 577     while(hi2s->RxXferCount > 0)
 578     {
 579       /* Wait until RXNE flag is set */
 580       if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
 581       {
 582         return HAL_TIMEOUT;
 583       }
 584
 585       (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
 586       hi2s->RxXferCount--;
 587     }
 588
 589     hi2s->State = HAL_I2S_STATE_READY;
 590
 591     /* Process Unlocked */
 592     __HAL_UNLOCK(hi2s);
 593
 594     return HAL_OK;
 595   }
 596   else
 597   {
 598     /* Process Unlocked */
 599     __HAL_UNLOCK(hi2s);
 600     return HAL_BUSY;
 601   }
 602 }
 603
 604 /**
 605   * @brief Transmit an amount of data in non-blocking mode with Interrupt
 606   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 607   *         the configuration information for I2S module
 608   * @param pData: a 16-bit pointer to data buffer.
 609   * @param Size: number of data sample to be sent:
 610   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
 611   *       configuration phase, the Size parameter means the number of 16-bit data length
 612   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
 613   *       the Size parameter means the number of 16-bit data length.
 614   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
 615   *       between Master and Slave(example: audio streaming).
 616   * @retval HAL status
 617   */
 618 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
 619 {
 620   if((pData == NULL) || (Size == 0))
 621   {
 622     return  HAL_ERROR;
 623   }
 624
 625   /* Process Locked */
 626   __HAL_LOCK(hi2s);
 627
 628   if(hi2s->State == HAL_I2S_STATE_READY)
 629   {
 630     hi2s->pTxBuffPtr = pData;
 631     hi2s->State = HAL_I2S_STATE_BUSY_TX;
 632     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
 633
 634     if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
 635       ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
 636     {
 637       hi2s->TxXferSize = (Size << 1);
 638       hi2s->TxXferCount = (Size << 1);
 639     }
 640     else
 641     {
 642       hi2s->TxXferSize = Size;
 643       hi2s->TxXferCount = Size;
 644     }
 645
 646     /* Enable TXE and ERR interrupt */
 647     __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
 648
 649     /* Check if the I2S is already enabled */
 650     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
 651     {
 652       /* Enable I2S peripheral */
 653       __HAL_I2S_ENABLE(hi2s);
 654     }
 655
 656     /* Process Unlocked */
 657     __HAL_UNLOCK(hi2s);
 658
 659     return HAL_OK;
 660   }
 661   else
 662   {
 663     /* Process Unlocked */
 664     __HAL_UNLOCK(hi2s);
 665     return HAL_BUSY;
 666   }
 667 }
 668
 669 /**
 670   * @brief Receive an amount of data in non-blocking mode with Interrupt
 671   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 672   *         the configuration information for I2S module
 673   * @param pData: a 16-bit pointer to the Receive data buffer.
 674   * @param Size: number of data sample to be sent:
 675   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
 676   *       configuration phase, the Size parameter means the number of 16-bit data length
 677   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
 678   *       the Size parameter means the number of 16-bit data length.
 679   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
 680   *       between Master and Slave(example: audio streaming).
 681   * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
 682   * between Master and Slave otherwise the I2S interrupt should be optimized.
 683   * @retval HAL status
 684   */
 685 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
 686 {
 687     if((pData == NULL) || (Size == 0))
 688     {
 689       return  HAL_ERROR;
 690     }
 691
 692   /* Process Locked */
 693   __HAL_LOCK(hi2s);
 694
 695   if(hi2s->State == HAL_I2S_STATE_READY)
 696   {
 697     hi2s->pRxBuffPtr = pData;
 698     hi2s->State = HAL_I2S_STATE_BUSY_RX;
 699     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
 700
 701     if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
 702       ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
 703     {
 704       hi2s->RxXferSize = (Size << 1);
 705       hi2s->RxXferCount = (Size << 1);
 706     }
 707     else
 708     {
 709       hi2s->RxXferSize = Size;
 710       hi2s->RxXferCount = Size;
 711     }
 712
 713     /* Enable TXE and ERR interrupt */
 714     __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
 715
 716     /* Check if the I2S is already enabled */
 717     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
 718     {
 719       /* Enable I2S peripheral */
 720       __HAL_I2S_ENABLE(hi2s);
 721     }
 722
 723     /* Process Unlocked */
 724     __HAL_UNLOCK(hi2s);
 725
 726     return HAL_OK;
 727   }
 728   else
 729   {
 730     /* Process Unlocked */
 731     __HAL_UNLOCK(hi2s);
 732     return HAL_BUSY;
 733   }
 734 }
 735
 736 /**
 737   * @brief Transmit an amount of data in non-blocking mode with DMA
 738   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 739   *         the configuration information for I2S module
 740   * @param pData: a 16-bit pointer to the Transmit data buffer.
 741   * @param Size: number of data sample to be sent:
 742   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
 743   *       configuration phase, the Size parameter means the number of 16-bit data length
 744   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
 745   *       the Size parameter means the number of 16-bit data length.
 746   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
 747   *       between Master and Slave(example: audio streaming).
 748   * @retval HAL status
 749   */
 750 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
 751 {
 752   if((pData == NULL) || (Size == 0))
 753   {
 754     return  HAL_ERROR;
 755   }
 756
 757   /* Process Locked */
 758   __HAL_LOCK(hi2s);
 759
 760   if(hi2s->State == HAL_I2S_STATE_READY)
 761   {
 762     hi2s->pTxBuffPtr = pData;
 763     hi2s->State = HAL_I2S_STATE_BUSY_TX;
 764     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
 765
 766     if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
 767       ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
 768     {
 769       hi2s->TxXferSize = (Size << 1);
 770       hi2s->TxXferCount = (Size << 1);
 771     }
 772     else
 773     {
 774       hi2s->TxXferSize = Size;
 775       hi2s->TxXferCount = Size;
 776     }
 777
 778     /* Set the I2S Tx DMA Half transfert complete callback */
 779     hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
 780
 781     /* Set the I2S Tx DMA transfert complete callback */
 782     hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
 783
 784     /* Set the DMA error callback */
 785     hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
 786
 787     /* Enable the Tx DMA Channel */
 788     HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
 789
 790     /* Check if the I2S is already enabled */
 791     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
 792     {
 793       /* Enable I2S peripheral */
 794       __HAL_I2S_ENABLE(hi2s);
 795     }
 796
 797     /* Check if the I2S Tx request is already enabled */
 798     if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN)
 799     {
 800       /* Enable Tx DMA Request */
 801       hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
 802     }
 803
 804     /* Process Unlocked */
 805     __HAL_UNLOCK(hi2s);
 806
 807     return HAL_OK;
 808   }
 809   else
 810   {
 811     /* Process Unlocked */
 812     __HAL_UNLOCK(hi2s);
 813     return HAL_BUSY;
 814   }
 815 }
 816
 817 /**
 818   * @brief Receive an amount of data in non-blocking mode with DMA
 819   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 820   *         the configuration information for I2S module
 821   * @param pData: a 16-bit pointer to the Receive data buffer.
 822   * @param Size: number of data sample to be sent:
 823   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
 824   *       configuration phase, the Size parameter means the number of 16-bit data length
 825   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
 826   *       the Size parameter means the number of 16-bit data length.
 827   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
 828   *       between Master and Slave(example: audio streaming).
 829   * @retval HAL status
 830   */
 831 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
 832 {
 833   if((pData == NULL) || (Size == 0))
 834   {
 835     return  HAL_ERROR;
 836   }
 837
 838   /* Process Locked */
 839   __HAL_LOCK(hi2s);
 840
 841   if(hi2s->State == HAL_I2S_STATE_READY)
 842   {
 843     hi2s->pRxBuffPtr = pData;
 844     hi2s->State = HAL_I2S_STATE_BUSY_RX;
 845     hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
 846
 847     if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
 848       ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
 849     {
 850       hi2s->RxXferSize = (Size << 1);
 851       hi2s->RxXferCount = (Size << 1);
 852     }
 853     else
 854     {
 855       hi2s->RxXferSize = Size;
 856       hi2s->RxXferCount = Size;
 857     }
 858
 859
 860     /* Set the I2S Rx DMA Half transfert complete callback */
 861     hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
 862
 863     /* Set the I2S Rx DMA transfert complete callback */
 864     hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
 865
 866     /* Set the DMA error callback */
 867     hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
 868
 869     /* Check if Master Receiver mode is selected */
 870     if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
 871     {
 872       /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
 873       access to the SPI_SR register. */
 874       __HAL_I2S_CLEAR_OVRFLAG(hi2s);
 875     }
 876
 877     /* Enable the Rx DMA Channel */
 878     HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize);
 879
 880     /* Check if the I2S is already enabled */
 881     if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
 882     {
 883       /* Enable I2S peripheral */
 884       __HAL_I2S_ENABLE(hi2s);
 885     }
 886
 887      /* Check if the I2S Rx request is already enabled */
 888     if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN)
 889     {
 890       /* Enable Rx DMA Request */
 891       hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
 892     }
 893
 894     /* Process Unlocked */
 895     __HAL_UNLOCK(hi2s);
 896
 897     return HAL_OK;
 898   }
 899   else
 900   {
 901     /* Process Unlocked */
 902     __HAL_UNLOCK(hi2s);
 903     return HAL_BUSY;
 904   }
 905 }
 906
 907 /**
 908   * @brief Pauses the audio stream playing from the Media.
 909   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 910   *         the configuration information for I2S module
 911   * @retval HAL status
 912   */
 913 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
 914 {
 915   /* Process Locked */
 916   __HAL_LOCK(hi2s);
 917
 918   if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
 919   {
 920     /* Disable the I2S DMA Tx request */
 921     hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_TXDMAEN);
 922   }
 923   else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
 924   {
 925     /* Disable the I2S DMA Rx request */
 926     hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_RXDMAEN);
 927   }
 928
 929   /* Process Unlocked */
 930   __HAL_UNLOCK(hi2s);
 931
 932   return HAL_OK;
 933 }
 934
 935 /**
 936   * @brief Resumes the audio stream playing from the Media.
 937   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 938   *         the configuration information for I2S module
 939   * @retval HAL status
 940   */
 941 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
 942 {
 943   /* Process Locked */
 944   __HAL_LOCK(hi2s);
 945
 946   if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
 947   {
 948     /* Enable the I2S DMA Tx request */
 949     hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
 950   }
 951   else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
 952   {
 953     /* Enable the I2S DMA Rx request */
 954     hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
 955   }
 956
 957   /* If the I2S peripheral is still not enabled, enable it */
 958   if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0)
 959   {
 960     /* Enable I2S peripheral */
 961     __HAL_I2S_ENABLE(hi2s);
 962   }
 963
 964   /* Process Unlocked */
 965   __HAL_UNLOCK(hi2s);
 966
 967   return HAL_OK;
 968 }
 969
 970 /**
 971   * @brief Resumes the audio stream playing from the Media.
 972   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
 973   *         the configuration information for I2S module
 974   * @retval HAL status
 975   */
 976 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
 977 {
 978   /* Process Locked */
 979   __HAL_LOCK(hi2s);
 980
 981   /* Disable the I2S Tx/Rx DMA requests */
 982   hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_TXDMAEN);
 983   hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_RXDMAEN);
 984
 985   /* Disable the I2S DMA channel */
 986   __HAL_DMA_DISABLE(hi2s->hdmatx);
 987   __HAL_DMA_DISABLE(hi2s->hdmarx);
 988
 989   /* Abort the I2S DMA tx channel */
 990   if(hi2s->hdmatx != NULL)
 991   {
 992     HAL_DMA_Abort(hi2s->hdmatx);
 993   }
 994   /* Abort the I2S DMA rx channel */
 995   if(hi2s->hdmarx != NULL)
 996   {
 997     HAL_DMA_Abort(hi2s->hdmarx);
 998   }
 999
1000   /* Disable I2S peripheral */
1001   __HAL_I2S_DISABLE(hi2s);
1002
1003   hi2s->State = HAL_I2S_STATE_READY;
1004
1005   /* Process Unlocked */
1006   __HAL_UNLOCK(hi2s);
1007
1008   return HAL_OK;
1009 }
1010
1011 /**
1012   * @brief  This function handles I2S interrupt request.
1013   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
1014   *         the configuration information for I2S module
1015   * @retval None
1016   */
1017 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
1018 {
1019   uint32_t i2ssr = hi2s->Instance->SR;
1020
1021   /* I2S in mode Receiver ------------------------------------------------*/
1022   if(((i2ssr & I2S_FLAG_OVR) != I2S_FLAG_OVR) &&
1023      ((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
1024   {
1025     I2S_Receive_IT(hi2s);
1026     return;
1027   }
1028
1029   /* I2S in mode Tramitter -----------------------------------------------*/
1030   if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
1031   {
1032     I2S_Transmit_IT(hi2s);
1033     return;
1034   }
1035
1036   /* I2S Overrun error interrupt occured ---------------------------------*/
1037   if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
1038   {
1039     /* Disable RXNE and ERR interrupt */
1040     __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
1041
1042     /* Set the I2S State ready */
1043     hi2s->State = HAL_I2S_STATE_READY;
1044
1045     /* Set the error code and execute error callback*/
1046     hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
1047     HAL_I2S_ErrorCallback(hi2s);
1048   }
1049
1050   /* I2S Underrun error interrupt occured --------------------------------*/
1051   if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET))
1052   {
1053     /* Disable TXE and ERR interrupt */
1054     __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
1055
1056     /* Set the I2S State ready */
1057     hi2s->State = HAL_I2S_STATE_READY;
1058
1059     /* Set the error code and execute error callback*/
1060     hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
1061     HAL_I2S_ErrorCallback(hi2s);
1062   }
1063 }
1064
1065 /**
1066   * @brief Tx Transfer Half completed callbacks
1067   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
1068   *         the configuration information for I2S module
1069   * @retval None
1070   */
1071  __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
1072 {
1073   /* NOTE : This function Should not be modified, when the callback is needed,
1074             the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
1075    */
1076 }
1077
1078 /**
1079   * @brief Tx Transfer completed callbacks
1080   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
1081   *         the configuration information for I2S module
1082   * @retval None
1083   */
1084  __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
1085 {
1086   /* NOTE : This function Should not be modified, when the callback is needed,
1087             the HAL_I2S_TxCpltCallback could be implemented in the user file
1088    */
1089 }
1090
1091 /**
1092   * @brief Rx Transfer half completed callbacks
1093   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
1094   *         the configuration information for I2S module
1095   * @retval None
1096   */
1097 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
1098 {
1099   /* NOTE : This function Should not be modified, when the callback is needed,
1100             the HAL_I2S_RxCpltCallback could be implemented in the user file
1101    */
1102 }
1103
1104 /**
1105   * @brief Rx Transfer completed callbacks
1106   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
1107   *         the configuration information for I2S module
1108   * @retval None
1109   */
1110 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
1111 {
1112   /* NOTE : This function Should not be modified, when the callback is needed,
1113             the HAL_I2S_RxCpltCallback could be implemented in the user file
1114    */
1115 }
1116
1117 /**
1118   * @brief I2S error callbacks
1119   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
1120   *         the configuration information for I2S module
1121   * @retval None
1122   */
1123  __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
1124 {
1125   /* NOTE : This function Should not be modified, when the callback is needed,
1126             the HAL_I2S_ErrorCallback could be implemented in the user file
1127    */
1128 }
1129
1130 /**
1131   * @}
1132   */
1133
1134 /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
1135   *  @brief   Peripheral State functions
1136   *
1137 @verbatim
1138  ===============================================================================
1139                       ##### Peripheral State and Errors functions #####
1140  ===============================================================================
1141     [..]
1142     This subsection permits to get in run-time the status of the peripheral
1143     and the data flow.
1144
1145 @endverbatim
1146   * @{
1147   */
1148
1149 /**
1150   * @brief  Return the I2S state
1151   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
1152   *         the configuration information for I2S module
1153   * @retval HAL state
1154   */
1155 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
1156 {
1157   return hi2s->State;
1158 }
1159
1160 /**
1161   * @brief  Return the I2S error code
1162   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
1163   *         the configuration information for I2S module
1164   * @retval I2S Error Code
1165   */
1166 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
1167 {
1168   return hi2s->ErrorCode;
1169 }
1170 /**
1171   * @}
1172   */
1173
1174 /**
1175   * @}
1176   */
1177
1178 /** @addtogroup I2S_Private_Functions I2S Private Functions
1179   * @{
1180   */
1181 /**
1182   * @brief DMA I2S transmit process complete callback
1183   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
1184   *                the configuration information for the specified DMA module.
1185   * @retval None
1186   */
1187 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
1188 {
1189   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
1190
1191   if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
1192   {
1193     /* Disable Tx DMA Request */
1194     hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_TXDMAEN);
1195
1196     hi2s->TxXferCount = 0;
1197     hi2s->State = HAL_I2S_STATE_READY;
1198   }
1199   HAL_I2S_TxCpltCallback(hi2s);
1200 }
1201
1202 /**
1203   * @brief DMA I2S transmit process half complete callback
1204   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
1205   *                the configuration information for the specified DMA module.
1206   * @retval None
1207   */
1208 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
1209 {
1210   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
1211
1212   HAL_I2S_TxHalfCpltCallback(hi2s);
1213 }
1214
1215 /**
1216   * @brief DMA I2S receive process complete callback
1217   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
1218   *                the configuration information for the specified DMA module.
1219   * @retval None
1220   */
1221 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
1222 {
1223   I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
1224
1225   if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
1226   {
1227     /* Disable Rx DMA Request */
1228     hi2s->Instance->CR2 &= (uint16_t)(~SPI_CR2_RXDMAEN);
1229     hi2s->RxXferCount = 0;
1230     hi2s->State = HAL_I2S_STATE_READY;
1231   }
1232   HAL_I2S_RxCpltCallback(hi2s);
1233 }
1234
1235 /**
1236   * @brief DMA I2S receive process half complete callback
1237   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
1238   *                the configuration information for the specified DMA module.
1239   * @retval None
1240   */
1241 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
1242 {
1243   I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
1244
1245   HAL_I2S_RxHalfCpltCallback(hi2s);
1246 }
1247
1248 /**
1249   * @brief DMA I2S communication error callback
1250   * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
1251   *                the configuration information for the specified DMA module.
1252   * @retval None
1253   */
1254 static void I2S_DMAError(DMA_HandleTypeDef *hdma)
1255 {
1256   I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
1257
1258   /* Disable Rx and Tx DMA Request */
1259   hi2s->Instance->CR2 &= (uint16_t)(~(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
1260   hi2s->TxXferCount = 0;
1261   hi2s->RxXferCount = 0;
1262
1263   hi2s->State= HAL_I2S_STATE_READY;
1264
1265   /* Set the error code and execute error callback*/
1266   hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;
1267   HAL_I2S_ErrorCallback(hi2s);
1268 }
1269
1270 /**
1271   * @brief Transmit an amount of data in non-blocking mode with Interrupt
1272   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
1273   *         the configuration information for I2S module
1274   * @retval None
1275   */
1276 static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
1277 {
1278   /* Transmit data */
1279   hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
1280   hi2s->TxXferCount--;
1281
1282   if(hi2s->TxXferCount == 0)
1283   {
1284     /* Disable TXE and ERR interrupt */
1285     __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
1286
1287     hi2s->State = HAL_I2S_STATE_READY;
1288     HAL_I2S_TxCpltCallback(hi2s);
1289   }
1290 }
1291
1292 /**
1293 * @brief Receive an amount of data in non-blocking mode with Interrupt
1294 * @param hi2s: I2S handle
1295   * @retval None
1296 */
1297 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
1298 {
1299   /* Receive data */
1300   (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
1301   hi2s->RxXferCount--;
1302
1303   if(hi2s->RxXferCount == 0)
1304   {
1305     /* Disable RXNE and ERR interrupt */
1306     __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
1307
1308     hi2s->State = HAL_I2S_STATE_READY;
1309     HAL_I2S_RxCpltCallback(hi2s);
1310   }
1311 }
1312
1313
1314 /**
1315   * @brief This function handles I2S Communication Timeout.
1316   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
1317   *         the configuration information for I2S module
1318   * @param Flag: Flag checked
1319   * @param State: Value of the flag expected
1320   * @param Timeout: Duration of the timeout
1321   * @retval HAL status
1322   */
1323 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout)
1324 {
1325   uint32_t tickstart = HAL_GetTick();
1326
1327   /* Wait until flag is set */
1328   if(State == RESET)
1329   {
1330     while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
1331     {
1332       if(Timeout != HAL_MAX_DELAY)
1333       {
1334         if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
1335         {
1336           /* Set the I2S State ready */
1337           hi2s->State= HAL_I2S_STATE_READY;
1338
1339           /* Process Unlocked */
1340           __HAL_UNLOCK(hi2s);
1341
1342           return HAL_TIMEOUT;
1343         }
1344       }
1345     }
1346   }
1347   else
1348   {
1349     while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
1350     {
1351       if(Timeout != HAL_MAX_DELAY)
1352       {
1353         if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
1354         {
1355           /* Set the I2S State ready */
1356           hi2s->State= HAL_I2S_STATE_READY;
1357
1358           /* Process Unlocked */
1359           __HAL_UNLOCK(hi2s);
1360
1361           return HAL_TIMEOUT;
1362         }
1363       }
1364     }
1365   }
1366   return HAL_OK;
1367 }
1368
1369 /**
1370   * @}
1371   */
1372
1373 /**
1374   * @}
1375   */
1376
1377 /**
1378   * @}
1379   */
1380
1381 #endif /* defined(STM32F031x6) || defined(STM32F038xx) || */
1382        /* defined(STM32F051x8) || defined(STM32F058xx) || */
1383        /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || */
1384        /* defined(STM32F042x6) || defined(STM32F048xx) || */
1385        /* defined(STM32F091xC) || defined(STM32F098xx) */
1386
1387 #endif /* HAL_I2S_MODULE_ENABLED */
1388
1389 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/