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[tmk_keyboard.git] / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_STM / TARGET_STM32F0 / stm32f0xx_hal_rcc.h
1 /**
2 ******************************************************************************
3 * @file stm32f0xx_hal_rcc.h
4 * @author MCD Application Team
5 * @version V1.2.0
6 * @date 11-December-2014
7 * @brief Header file of RCC HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F0xx_HAL_RCC_H
40 #define __STM32F0xx_HAL_RCC_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f0xx_hal_def.h"
48
49 /** @addtogroup STM32F0xx_HAL_Driver
50 * @{
51 */
52
53 /** @addtogroup RCC
54 * @{
55 */
56
57 /* Exported types ------------------------------------------------------------*/
58
59 /** @defgroup RCC_Exported_Types RCC Exported Types
60 * @{
61 */
62
63 /**
64 * @brief RCC PLL configuration structure definition
65 */
66 typedef struct
67 {
68 uint32_t PLLState; /*!< PLLState: The new state of the PLL.
69 This parameter can be a value of @ref RCC_PLL_Config */
70
71 uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
72 This parameter must be a value of @ref RCC_PLL_Clock_Source */
73
74 uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
75 This parameter must be a value of @ref RCC_PLL_Prediv_Factor */
76
77 uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
78 This parameter must be a value of @ref RCC_PLL_Multiplication_Factor */
79
80 }RCC_PLLInitTypeDef;
81
82 /**
83 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
84 */
85 typedef struct
86 {
87 uint32_t OscillatorType; /*!< The Oscillators to be configured.
88 This parameter can be a value of @ref RCC_Oscillator_Type */
89
90 uint32_t HSEState; /*!< The new state of the HSE.
91 This parameter can be a value of @ref RCC_HSE_Config */
92
93 uint32_t LSEState; /*!< The new state of the LSE.
94 This parameter can be a value of @ref RCC_LSE_Config */
95
96 uint32_t HSIState; /*!< The new state of the HSI.
97 This parameter can be a value of @ref RCC_HSI_Config */
98
99 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
100 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
101
102 uint32_t HSI14State; /*!< The new state of the HSI14.
103 This parameter can be a value of @ref RCC_HSI14_Config */
104
105 uint32_t HSI14CalibrationValue; /*!< The HSI14 calibration trimming value (default is RCC_HSI14CALIBRATION_DEFAULT).
106 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
107
108 uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32F07x, STM32F0x2 and STM32F09x devices).
109 This parameter can be a value of @ref RCCEx_HSI48_Config */
110
111 uint32_t LSIState; /*!< The new state of the LSI.
112 This parameter can be a value of @ref RCC_LSI_Config */
113
114 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
115
116 }RCC_OscInitTypeDef;
117
118 /**
119 * @brief RCC System, AHB and APB busses clock configuration structure definition
120 */
121 typedef struct
122 {
123 uint32_t ClockType; /*!< The clock to be configured.
124 This parameter can be a value of @ref RCC_System_Clock_Type */
125
126 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
127 This parameter can be a value of @ref RCC_System_Clock_Source */
128
129 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
130 This parameter can be a value of @ref RCC_AHB_Clock_Source */
131
132 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
133 This parameter can be a value of @ref RCC_APB1_Clock_Source */
134
135 }RCC_ClkInitTypeDef;
136
137 /**
138 * @}
139 */
140
141 /* Exported constants --------------------------------------------------------*/
142 /** @defgroup RCC_Exported_Constants RCC Exported Constants
143 * @{
144 */
145
146 /** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
147 * @brief RCC registers bit address in the alias region
148 * @{
149 */
150 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
151 /* --- CR Register ---*/
152 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
153 /* --- CFGR Register ---*/
154 #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x04)
155 /* --- CIR Register ---*/
156 #define RCC_CIR_OFFSET (RCC_OFFSET + 0x08)
157 /* --- BDCR Register ---*/
158 #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x20)
159 /* --- CSR Register ---*/
160 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x24)
161 /* --- CR2 Register ---*/
162 #define RCC_CR2_OFFSET (RCC_OFFSET + 0x34)
163
164 /* CR register byte 2 (Bits[23:16]) base address */
165 #define RCC_CR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CR_OFFSET + 0x02)
166
167 /* CIR register byte 1 (Bits[15:8]) base address */
168 #define RCC_CIR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x01)
169
170 /* CIR register byte 2 (Bits[23:16]) base address */
171 #define RCC_CIR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x02)
172
173 /* CSR register byte 1 (Bits[15:8]) base address */
174 #define RCC_CSR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CSR_OFFSET + 0x01)
175
176 /* BDCR register byte 0 (Bits[7:0] base address */
177 #define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
178
179 #define RCC_CFGR_PLLMUL_BITNUMBER 18
180 #define RCC_CFGR2_PREDIV_BITNUMBER 0
181
182 /**
183 * @}
184 */
185
186 /** @defgroup RCC_Timeout RCC Timeout
187 * @{
188 */
189 /* LSE state change timeout */
190 #define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
191
192 /* Disable Backup domain write protection state change timeout */
193 #define DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
194 /**
195 * @}
196 */
197
198 /** @defgroup RCC_Oscillator_Type RCC Oscillator Type
199 * @{
200 */
201 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
202 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
203 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
204 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
205 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
206 #define RCC_OSCILLATORTYPE_HSI14 ((uint32_t)0x00000010)
207 #define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
208
209 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) || \
210 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
211 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
212 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
213 (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
214 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) || \
215 (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
216 /**
217 * @}
218 */
219
220 /** @defgroup RCC_HSE_Config RCC HSE Config
221 * @{
222 */
223 #define RCC_HSE_OFF ((uint8_t)0x00)
224 #define RCC_HSE_ON ((uint8_t)0x01)
225 #define RCC_HSE_BYPASS ((uint8_t)0x05)
226
227 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
228 ((HSE) == RCC_HSE_BYPASS))
229 /**
230 * @}
231 */
232
233 /** @defgroup RCC_LSE_Config RCC_LSE_Config
234 * @{
235 */
236 #define RCC_LSE_OFF ((uint8_t)0x00)
237 #define RCC_LSE_ON ((uint8_t)0x01)
238 #define RCC_LSE_BYPASS ((uint8_t)0x05)
239
240 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
241 ((LSE) == RCC_LSE_BYPASS))
242 /**
243 * @}
244 */
245
246 /** @defgroup RCC_HSI_Config RCC HSI Config
247 * @{
248 */
249 #define RCC_HSI_OFF ((uint8_t)0x00)
250 #define RCC_HSI_ON ((uint8_t)0x01)
251
252 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
253
254 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
255 /**
256 * @}
257 */
258
259 /** @defgroup RCC_HSI14_Config RCC HSI14 Config
260 * @{
261 */
262 #define RCC_HSI14_OFF ((uint32_t)0x00)
263 #define RCC_HSI14_ON RCC_CR2_HSI14ON
264 #define RCC_HSI14_ADC_CONTROL (~RCC_CR2_HSI14DIS)
265
266 #define IS_RCC_HSI14(HSI14) (((HSI14) == RCC_HSI14_OFF) || ((HSI14) == RCC_HSI14_ON) || ((HSI14) == RCC_HSI14_ADC_CONTROL))
267
268 #define RCC_HSI14CALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI14 calibration trimming value */
269 /**
270 * @}
271 */
272
273 /** @defgroup RCC_LSI_Config RCC LSI Config
274 * @{
275 */
276 #define RCC_LSI_OFF ((uint8_t)0x00)
277 #define RCC_LSI_ON ((uint8_t)0x01)
278
279 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
280 /**
281 * @}
282 */
283
284 /** @defgroup RCC_PLL_Config RCC PLL Config
285 * @{
286 */
287 #define RCC_PLL_NONE ((uint8_t)0x00)
288 #define RCC_PLL_OFF ((uint8_t)0x01)
289 #define RCC_PLL_ON ((uint8_t)0x02)
290
291 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
292 /**
293 * @}
294 */
295
296 /** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor
297 * @{
298 */
299 #define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
300 #define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
301 #define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
302 #define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
303 #define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
304 #define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
305 #define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
306 #define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
307 #define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
308 #define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
309 #define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
310 #define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
311 #define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
312 #define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
313 #define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
314 #define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
315
316 #define IS_RCC_PREDIV(PREDIV) (((PREDIV) == RCC_PREDIV_DIV1) || ((PREDIV) == RCC_PREDIV_DIV2) || \
317 ((PREDIV) == RCC_PREDIV_DIV3) || ((PREDIV) == RCC_PREDIV_DIV4) || \
318 ((PREDIV) == RCC_PREDIV_DIV5) || ((PREDIV) == RCC_PREDIV_DIV6) || \
319 ((PREDIV) == RCC_PREDIV_DIV7) || ((PREDIV) == RCC_PREDIV_DIV8) || \
320 ((PREDIV) == RCC_PREDIV_DIV9) || ((PREDIV) == RCC_PREDIV_DIV10) || \
321 ((PREDIV) == RCC_PREDIV_DIV11) || ((PREDIV) == RCC_PREDIV_DIV12) || \
322 ((PREDIV) == RCC_PREDIV_DIV13) || ((PREDIV) == RCC_PREDIV_DIV14) || \
323 ((PREDIV) == RCC_PREDIV_DIV15) || ((PREDIV) == RCC_PREDIV_DIV16))
324 /**
325 * @}
326 */
327
328 /** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
329 * @{
330 */
331 #define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2
332 #define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
333 #define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
334 #define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5
335 #define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
336 #define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7
337 #define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
338 #define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9
339 #define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10
340 #define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11
341 #define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
342 #define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13
343 #define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14
344 #define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
345 #define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
346
347 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLL_MUL2) || ((MUL) == RCC_PLL_MUL3) || \
348 ((MUL) == RCC_PLL_MUL4) || ((MUL) == RCC_PLL_MUL5) || \
349 ((MUL) == RCC_PLL_MUL6) || ((MUL) == RCC_PLL_MUL7) || \
350 ((MUL) == RCC_PLL_MUL8) || ((MUL) == RCC_PLL_MUL9) || \
351 ((MUL) == RCC_PLL_MUL10) || ((MUL) == RCC_PLL_MUL11) || \
352 ((MUL) == RCC_PLL_MUL12) || ((MUL) == RCC_PLL_MUL13) || \
353 ((MUL) == RCC_PLL_MUL14) || ((MUL) == RCC_PLL_MUL15) || \
354 ((MUL) == RCC_PLL_MUL16))
355 /**
356 * @}
357 */
358
359 /** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source
360 * @{
361 */
362 #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV
363 /**
364 * @}
365 */
366
367 /** @defgroup RCC_System_Clock_Type RCC System Clock Type
368 * @{
369 */
370 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
371 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
372 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
373
374 #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
375 (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
376 (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1))
377 /**
378 * @}
379 */
380
381 /** @defgroup RCC_System_Clock_Source RCC System Clock Source
382 * @{
383 */
384 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
385 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
386 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
387 /**
388 * @}
389 */
390
391 /** @defgroup RCC_System_Clock_Source_Status RCC System Clock Source Status
392 * @{
393 */
394 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
395 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
396 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
397 /**
398 * @}
399 */
400
401 /** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
402 * @{
403 */
404 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
405 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
406 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
407 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
408 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
409 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
410 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
411 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
412 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
413
414 #define IS_RCC_SYSCLK_DIV(DIV) (((DIV) == RCC_SYSCLK_DIV1) || ((DIV) == RCC_SYSCLK_DIV2) || \
415 ((DIV) == RCC_SYSCLK_DIV4) || ((DIV) == RCC_SYSCLK_DIV8) || \
416 ((DIV) == RCC_SYSCLK_DIV16) || ((DIV) == RCC_SYSCLK_DIV64) || \
417 ((DIV) == RCC_SYSCLK_DIV128) || ((DIV) == RCC_SYSCLK_DIV256) || \
418 ((DIV) == RCC_SYSCLK_DIV512))
419 /**
420 * @}
421 */
422
423 /** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source
424 * @{
425 */
426 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE_DIV1
427 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE_DIV2
428 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE_DIV4
429 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE_DIV8
430 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE_DIV16
431
432 #define IS_RCC_HCLK_DIV(DIV) (((DIV) == RCC_HCLK_DIV1) || ((DIV) == RCC_HCLK_DIV2) || \
433 ((DIV) == RCC_HCLK_DIV4) || ((DIV) == RCC_HCLK_DIV8) || \
434 ((DIV) == RCC_HCLK_DIV16))
435 /**
436 * @}
437 */
438
439 /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
440 * @{
441 */
442 #define RCC_RTCCLKSOURCE_NONE RCC_BDCR_RTCSEL_NOCLOCK
443 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE
444 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI
445 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE
446
447 #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_NONE) || \
448 ((SOURCE) == RCC_RTCCLKSOURCE_LSE) || \
449 ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \
450 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32))
451 /**
452 * @}
453 */
454
455 /** @defgroup RCC_USART1_Clock_Source RCC USART1 Clock Source
456 * @{
457 */
458 #define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK
459 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
460 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
461 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
462
463 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \
464 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
465 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
466 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
467 /**
468 * @}
469 */
470
471 /** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source
472 * @{
473 */
474 #define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
475 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK
476
477 #define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_HSI) || \
478 ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK))
479 /**
480 * @}
481 */
482
483 /** @defgroup RCC_MCOx_Index RCC MCOx Index
484 * @{
485 */
486 #define RCC_MCO ((uint32_t)0x00000000)
487
488 #define IS_RCC_MCO(MCOx) ((MCOx) == RCC_MCO)
489 /**
490 * @}
491 */
492
493 /** @defgroup RCC_MCO_Clock_Source RCC MCO Clock Source
494 * @{
495 */
496 #define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK
497 #define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI
498 #define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE
499 #define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
500 #define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI
501 #define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE
502 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
503 #define RCC_MCOSOURCE_HSI14 RCC_CFGR_MCO_HSI14
504 /**
505 * @}
506 */
507
508 /** @defgroup RCC_Interrupt RCC Interrupt
509 * @{
510 */
511 #define RCC_IT_LSIRDY ((uint8_t)0x01)
512 #define RCC_IT_LSERDY ((uint8_t)0x02)
513 #define RCC_IT_HSIRDY ((uint8_t)0x04)
514 #define RCC_IT_HSERDY ((uint8_t)0x08)
515 #define RCC_IT_PLLRDY ((uint8_t)0x10)
516 #define RCC_IT_HSI14 ((uint8_t)0x20)
517 #define RCC_IT_CSS ((uint8_t)0x80)
518 /**
519 * @}
520 */
521
522 /** @defgroup RCC_Flag RCC Flag
523 * Elements values convention: 0XXYYYYYb
524 * - YYYYY : Flag position in the register
525 * - XX : Register index
526 * - 00: CR register
527 * - 01: CR2 register
528 * - 10: BDCR register
529 * - 11: CSR register
530 * @{
531 */
532 #define CR_REG_INDEX 0
533 #define CR2_REG_INDEX 1
534 #define BDCR_REG_INDEX 2
535 #define CSR_REG_INDEX 3
536
537 /* Flags in the CR register */
538 #define RCC_CR_HSIRDY_BitNumber 1
539 #define RCC_CR_HSERDY_BitNumber 17
540 #define RCC_CR_PLLRDY_BitNumber 25
541
542 #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSIRDY_BitNumber))
543 #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_HSERDY_BitNumber))
544 #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | RCC_CR_PLLRDY_BitNumber))
545
546 /* Flags in the CR2 register */
547 #define RCC_CR2_HSI14RDY_BitNumber 1
548
549 #define RCC_FLAG_HSI14RDY ((uint8_t)((CR2_REG_INDEX << 5) | RCC_CR2_HSI14RDY_BitNumber))
550
551 /* Flags in the BDCR register */
552 #define RCC_BDCR_LSERDY_BitNumber 1
553
554 #define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) | RCC_BDCR_LSERDY_BitNumber))
555
556 /* Flags in the CSR register */
557 #define RCC_CSR_LSIRDY_BitNumber 1
558 #define RCC_CSR_V18PWRRSTF_BitNumber 23
559 #define RCC_CSR_RMVF_BitNumber 24
560 #define RCC_CSR_OBLRSTF_BitNumber 25
561 #define RCC_CSR_PINRSTF_BitNumber 26
562 #define RCC_CSR_PORRSTF_BitNumber 27
563 #define RCC_CSR_SFTRSTF_BitNumber 28
564 #define RCC_CSR_IWDGRSTF_BitNumber 29
565 #define RCC_CSR_WWDGRSTF_BitNumber 30
566 #define RCC_CSR_LPWRRSTF_BitNumber 31
567
568 #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSIRDY_BitNumber))
569 #define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LSIRDY_BitNumber))
570 #define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_RMVF_BitNumber))
571 #define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_OBLRSTF_BitNumber))
572 #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_PINRSTF_BitNumber))
573 #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_PORRSTF_BitNumber))
574 #define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_SFTRSTF_BitNumber))
575 #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_IWDGRSTF_BitNumber))
576 #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_WWDGRSTF_BitNumber))
577 #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | RCC_CSR_LPWRRSTF_BitNumber))
578 /**
579 * @}
580 */
581
582 /** @defgroup RCC_Calibration_values RCC Calibration values
583 * @{
584 */
585 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
586
587 /**
588 * @}
589 */
590
591 /** @addtogroup RCC_Timeout
592 * @{
593 */
594
595 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
596 #define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
597 #define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
598 #define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
599 #define HSI14_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
600 #define HSI48_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
601 #define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
602 #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
603
604 /**
605 * @}
606 */
607
608 /**
609 * @}
610 */
611
612 /* Exported macro ------------------------------------------------------------*/
613
614 /** @defgroup RCC_Exported_Macros RCC Exported Macros
615 * @{
616 */
617
618 /** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable
619 * @brief Enable or disable the AHB peripheral clock.
620 * @note After reset, the peripheral clock (used for registers read/write access)
621 * is disabled and the application software has to enable this clock before
622 * using it.
623 * @{
624 */
625 #define __GPIOA_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOAEN))
626 #define __GPIOB_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOBEN))
627 #define __GPIOC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOCEN))
628 #define __GPIOF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOFEN))
629 #define __CRC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_CRCEN))
630 #define __DMA1_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA1EN))
631 #define __SRAM_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_SRAMEN))
632 #define __FLITF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_FLITFEN))
633
634 #define __GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
635 #define __GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
636 #define __GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
637 #define __GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
638 #define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
639 #define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
640 #define __SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
641 #define __FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
642 /**
643 * @}
644 */
645
646 /** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable
647 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
648 * @note After reset, the peripheral clock (used for registers read/write access)
649 * is disabled and the application software has to enable this clock before
650 * using it.
651 * @{
652 */
653 #define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
654 #define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
655 #define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
656 #define __I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
657 #define __PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN))
658
659 #define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
660 #define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
661 #define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
662 #define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
663 #define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
664 /**
665 * @}
666 */
667
668 /** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable
669 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
670 * @note After reset, the peripheral clock (used for registers read/write access)
671 * is disabled and the application software has to enable this clock before
672 * using it.
673 * @{
674 */
675 #define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN))
676 #define __ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN))
677 #define __TIM1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM1EN))
678 #define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
679 #define __TIM16_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM16EN))
680 #define __TIM17_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM17EN))
681 #define __USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN))
682 #define __DBGMCU_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_DBGMCUEN))
683
684 #define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
685 #define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
686 #define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
687 #define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
688 #define __TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
689 #define __TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
690 #define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
691 #define __DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DBGMCUEN))
692 /**
693 * @}
694 */
695
696 /** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset
697 * @brief Force or release AHB peripheral reset.
698 * @{
699 */
700 #define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
701 #define __GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
702 #define __GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
703 #define __GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
704 #define __GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
705
706 #define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
707 #define __GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
708 #define __GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
709 #define __GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
710 #define __GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
711 /**
712 * @}
713 */
714
715 /** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset
716 * @brief Force or release APB1 peripheral reset.
717 * @{
718 */
719 #define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
720 #define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
721 #define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
722 #define __WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
723 #define __I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
724 #define __PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
725
726 #define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
727 #define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
728 #define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
729 #define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
730 #define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
731 #define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
732 /**
733 * @}
734 */
735
736 /** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset
737 * @brief Force or release APB2 peripheral reset.
738 * @{
739 */
740 #define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
741 #define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
742 #define __ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
743 #define __TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
744 #define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
745 #define __USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
746 #define __TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
747 #define __TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
748 #define __DBGMCU_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DBGMCURST))
749
750 #define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
751 #define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
752 #define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
753 #define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
754 #define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
755 #define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
756 #define __TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
757 #define __TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
758 #define __DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DBGMCURST))
759 /**
760 * @}
761 */
762
763 /** @defgroup RCC_HSI_Configuration RCC HSI Configuration
764 * @{
765 */
766
767 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
768 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
769 * It is used (enabled by hardware) as system clock source after startup
770 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
771 * of the HSE used directly or indirectly as system clock (if the Clock
772 * Security System CSS is enabled).
773 * @note HSI can not be stopped if it is used as system clock source. In this case,
774 * you have to select another source of the system clock then stop the HSI.
775 * @note After enabling the HSI, the application software should wait on HSIRDY
776 * flag to be set indicating that HSI clock is stable and can be used as
777 * system clock source.
778 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
779 * clock cycles.
780 */
781 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
782 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
783
784 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
785 * @note The calibration is used to compensate for the variations in voltage
786 * and temperature that influence the frequency of the internal HSI RC.
787 * @param __HSICalibrationValue__: specifies the calibration trimming value
788 * (default is RCC_HSICALIBRATION_DEFAULT).
789 * This parameter must be a number between 0 and 0x1F.
790 */
791 #define RCC_CR_HSITRIM_BitNumber 3
792 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \
793 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_BitNumber)
794 /**
795 * @}
796 */
797
798 /** @defgroup RCC_LSI_Configuration RCC LSI Configuration
799 * @{
800 */
801
802 /** @brief Macro to enable or disable the Internal Low Speed oscillator (LSI).
803 * @note After enabling the LSI, the application software should wait on
804 * LSIRDY flag to be set indicating that LSI clock is stable and can
805 * be used to clock the IWDG and/or the RTC.
806 * @note LSI can not be disabled if the IWDG is running.
807 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
808 * clock cycles.
809 */
810 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
811 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
812 /**
813 * @}
814 */
815
816 /** @defgroup RCC_HSE_Configuration RCC HSE Configuration
817 * @{
818 */
819
820 /**
821 * @brief Macro to configure the External High Speed oscillator (HSE).
822 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
823 * software should wait on HSERDY flag to be set indicating that HSE clock
824 * is stable and can be used to clock the PLL and/or system clock.
825 * @note HSE state can not be changed if it is used directly or through the
826 * PLL as system clock. In this case, you have to select another source
827 * of the system clock then change the HSE state (ex. disable it).
828 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
829 * @note This function reset the CSSON bit, so if the Clock security system(CSS)
830 * was previously enabled you have to enable it again after calling this
831 * function.
832 * @param __STATE__: specifies the new state of the HSE.
833 * This parameter can be one of the following values:
834 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
835 * 6 HSE oscillator clock cycles.
836 * @arg RCC_HSE_ON: turn ON the HSE oscillator
837 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
838 */
839 #define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *)RCC_CR_BYTE2_ADDRESS = (__STATE__))
840
841 /**
842 * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
843 * @note Predivision factor can not be changed if PLL is used as system clock
844 * In this case, you have to select another source of the system clock, disable the PLL and
845 * then change the HSE predivision factor.
846 * @param __HSEPredivValue__: specifies the division value applied to HSE.
847 * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
848 */
849 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSEPredivValue__) \
850 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSEPredivValue__))
851 /**
852 * @}
853 */
854
855 /** @defgroup RCC_LSE_Configuration RCC LSE Configuration
856 * @{
857 */
858 /**
859 * @brief Macro to configure the External Low Speed oscillator (LSE).
860 * @note As the LSE is in the Backup domain and write access is denied to
861 * this domain after reset, you have to enable write access using
862 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
863 * (to be done once after reset).
864 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
865 * software should wait on LSERDY flag to be set indicating that LSE clock
866 * is stable and can be used to clock the RTC.
867 * @param __STATE__: specifies the new state of the LSE.
868 * This parameter can be one of the following values:
869 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
870 * 6 LSE oscillator clock cycles.
871 * @arg RCC_LSE_ON: turn ON the LSE oscillator
872 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock
873 */
874 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
875 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEON|RCC_BDCR_LSEBYP, (uint32_t)(__STATE__))
876 /**
877 * @}
878 */
879
880 /** @defgroup RCC_HSI14_Configuration RCC_HSI14_Configuration
881 * @{
882 */
883
884 /** @brief Macros to enable or disable the Internal 14Mhz High Speed oscillator (HSI14).
885 * @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes.
886 * @note HSI14 can not be stopped if it is used as system clock source. In this case,
887 * you have to select another source of the system clock then stop the HSI14.
888 * @note After enabling the HSI14 with __HAL_RCC_HSI14_ENABLE(), the application software
889 * should wait on HSI14RDY flag to be set indicating that HSI clock is stable and can be
890 * used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
891 * @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator
892 * clock cycles.
893 */
894 #define __HAL_RCC_HSI14_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14ON)
895 #define __HAL_RCC_HSI14_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON)
896
897 /** @brief macros to Enable or Disable the Internal 14Mhz High Speed oscillator (HSI14) usage by ADC.
898 */
899 #define __HAL_RCC_HSI14ADC_ENABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
900 #define __HAL_RCC_HSI14ADC_DISABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
901
902 /** @brief Macro to adjust the Internal 14Mhz High Speed oscillator (HSI) calibration value.
903 * @note The calibration is used to compensate for the variations in voltage
904 * and temperature that influence the frequency of the internal HSI14 RC.
905 * @param __HSI14CalibrationValue__: specifies the calibration trimming value
906 * (default is RCC_HSI14CALIBRATION_DEFAULT).
907 * This parameter must be a number between 0 and 0x1F.
908 */
909 #define RCC_CR2_HSI14TRIM_BitNumber 3
910 #define __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(__HSI14CalibrationValue__) \
911 MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, (uint32_t)(__HSI14CalibrationValue__) << RCC_CR2_HSI14TRIM_BitNumber)
912 /**
913 * @}
914 */
915
916 /** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config
917 * @{
918 */
919
920 /** @brief Macro to configure the USART1 clock (USART1CLK).
921 * @param __USART1CLKSource__: specifies the USART1 clock source.
922 * This parameter can be one of the following values:
923 * @arg RCC_USART1CLKSOURCE_PCLK1: PCLK1 selected as USART1 clock
924 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
925 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
926 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
927 */
928 #define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \
929 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSource__))
930
931 /** @brief Macro to get the USART1 clock source.
932 * @retval The clock source can be one of the following values:
933 * @arg RCC_USART1CLKSOURCE_PCLK1: PCLK1 selected as USART1 clock
934 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
935 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
936 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
937 */
938 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
939 /**
940 * @}
941 */
942
943 /** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config
944 * @{
945 */
946
947 /** @brief Macro to configure the I2C1 clock (I2C1CLK).
948 * @param __I2C1CLKSource__: specifies the I2C1 clock source.
949 * This parameter can be one of the following values:
950 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
951 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
952 */
953 #define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \
954 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSource__))
955
956 /** @brief Macro to get the I2C1 clock source.
957 * @retval The clock source can be one of the following values:
958 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
959 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
960 */
961 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
962 /**
963 * @}
964 */
965
966 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
967 * @{
968 */
969 /** @brief Macros to enable or disable the the RTC clock.
970 * @note These macros must be used only after the RTC clock source was selected.
971 */
972 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
973 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
974
975 /** @brief Macro to configure the RTC clock (RTCCLK).
976 * @note As the RTC clock configuration bits are in the Backup domain and write
977 * access is denied to this domain after reset, you have to enable write
978 * access using the Power Backup Access macro before to configure
979 * the RTC clock source (to be done once after reset).
980 * @note Once the RTC clock is configured it can't be changed unless the
981 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
982 * a Power On Reset (POR).
983 * @param __RTCCLKSource__: specifies the RTC clock source.
984 * This parameter can be one of the following values:
985 * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock
986 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
987 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
988 * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32
989 *
990 * @note If the LSE is used as RTC clock source, the RTC continues to
991 * work in STOP and STANDBY modes, and can be used as wakeup source.
992 * However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
993 * the RTC cannot be used in STOP and STANDBY modes.
994 * @note The system must always be configured so as to get a PCLK frequency greater than or
995 * equal to the RTCCLK frequency for a proper operation of the RTC.
996 */
997 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) \
998 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (uint32_t)(__RTCCLKSource__))
999
1000 /** @brief Macro to get the RTC clock source.
1001 * @retval The clock source can be one of the following values:
1002 * @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock
1003 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
1004 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
1005 * @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 selected as RTC clock
1006 */
1007 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
1008 /**
1009 * @}
1010 */
1011
1012 /** @defgroup RCC_Force_Release_Backup RCC Force Release Backup
1013 * @{
1014 */
1015
1016 /** @brief Macro to force or release the Backup domain reset.
1017 * @note These macros reset the RTC peripheral (including the backup registers)
1018 * and the RTC clock source selection in RCC_CSR register.
1019 * @note The BKPSRAM is not affected by this reset.
1020 */
1021 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
1022 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
1023 /**
1024 * @}
1025 */
1026
1027 /** @defgroup RCC_PLL_Configuration RCC PLL Configuration
1028 * @{
1029 */
1030
1031 /** @brief Macro to enable or disable the PLL.
1032 * @note After enabling the PLL, the application software should wait on
1033 * PLLRDY flag to be set indicating that PLL clock is stable and can
1034 * be used as system clock source.
1035 * @note The PLL can not be disabled if it is used as system clock source
1036 * @note The PLL is disabled by hardware when entering STOP and STANDBY modes.
1037 */
1038 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
1039 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
1040
1041 /** @brief Macro to configure the PLL clock source, multiplication and division factors.
1042 * @note This macro must be used only when the PLL is disabled.
1043 *
1044 * @param __RCC_PLLSource__: specifies the PLL entry clock source.
1045 * This parameter can be one of the following values:
1046 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
1047 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
1048 * @param __PREDIV__: specifies the predivider factor for PLL VCO input clock
1049 * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
1050 * @param __PLLMUL__: specifies the multiplication factor for PLL VCO input clock
1051 * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
1052 *
1053 */
1054 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \
1055 do { \
1056 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
1057 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__))); \
1058 } while(0)
1059 /**
1060 * @}
1061 */
1062
1063 /** @defgroup RCC_Get_Clock_source RCC Get Clock source
1064 * @{
1065 */
1066
1067 /** @brief Macro to get the clock source used as system clock.
1068 * @retval The clock source used as system clock.
1069 * The returned value can be one of the following value:
1070 * @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock
1071 * @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock
1072 * @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock
1073 */
1074 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)))
1075
1076 /** @brief Macro to get the oscillator used as PLL clock source.
1077 * @retval The oscillator used as PLL clock source. The returned value can be one
1078 * of the following:
1079 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
1080 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
1081 */
1082 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
1083 /**
1084 * @}
1085 */
1086
1087 /** @defgroup RCC_Flags_Interrupts_Management RCC Flags Interrupts Management
1088 * @brief macros to manage the specified RCC Flags and interrupts.
1089 * @{
1090 */
1091
1092 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to enable
1093 * the selected interrupts.).
1094 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
1095 * This parameter can be any combination of the following values:
1096 * @arg RCC_IT_LSIRDY: LSI ready interrupt enable
1097 * @arg RCC_IT_LSERDY: LSE ready interrupt enable
1098 * @arg RCC_IT_HSIRDY: HSI ready interrupt enable
1099 * @arg RCC_IT_HSERDY: HSE ready interrupt enable
1100 * @arg RCC_IT_PLLRDY: PLL ready interrupt enable
1101 * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
1102 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
1103 */
1104 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
1105
1106 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to disable
1107 * the selected interrupts.).
1108 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
1109 * This parameter can be any combination of the following values:
1110 * @arg RCC_IT_LSIRDY: LSI ready interrupt enable
1111 * @arg RCC_IT_LSERDY: LSE ready interrupt enable
1112 * @arg RCC_IT_HSIRDY: HSI ready interrupt enable
1113 * @arg RCC_IT_HSERDY: HSE ready interrupt enable
1114 * @arg RCC_IT_PLLRDY: PLL ready interrupt enable
1115 * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
1116 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
1117 */
1118 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *)RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
1119
1120 /** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16]
1121 * bits to clear the selected interrupt pending bits.
1122 * @param __IT__: specifies the interrupt pending bit to clear.
1123 * This parameter can be any combination of the following values:
1124 * @arg RCC_IT_LSIRDY: LSI ready interrupt clear
1125 * @arg RCC_IT_LSERDY: LSE ready interrupt clear
1126 * @arg RCC_IT_HSIRDY: HSI ready interrupt clear
1127 * @arg RCC_IT_HSERDY: HSE ready interrupt clear
1128 * @arg RCC_IT_PLLRDY: PLL ready interrupt clear
1129 * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt clear
1130 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt clear (only applicable to STM32F0X2 USB devices)
1131 * @arg RCC_IT_CSS: Clock Security System interrupt clear
1132 */
1133 #define __HAL_RCC_CLEAR_IT(__IT__) (*(__IO uint8_t *)RCC_CIR_BYTE2_ADDRESS = (__IT__))
1134
1135 /** @brief Check the RCC's interrupt has occurred or not.
1136 * @param __IT__: specifies the RCC interrupt source to check.
1137 * This parameter can be one of the following values:
1138 * @arg RCC_IT_LSIRDY: LSI ready interrupt flag
1139 * @arg RCC_IT_LSERDY: LSE ready interrupt flag
1140 * @arg RCC_IT_HSIRDY: HSI ready interrupt flag
1141 * @arg RCC_IT_HSERDY: HSE ready interrupt flag
1142 * @arg RCC_IT_PLLRDY: PLL ready interrupt flag
1143 * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt flag
1144 * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt flag (only applicable to STM32F0X2 USB devices)
1145 * @arg RCC_IT_CSS: Clock Security System interrupt flag
1146 * @retval The new state of __IT__ (TRUE or FALSE).
1147 */
1148 #define __HAL_RCC_GET_IT(__IT__) ((RCC->CIR & (__IT__)) == (__IT__))
1149
1150 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
1151 * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
1152 */
1153 #define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF)
1154
1155 /** @brief Check RCC flag is set or not.
1156 * @param __FLAG__: specifies the flag to check.
1157 * This parameter can be one of the following values:
1158 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
1159 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
1160 * @arg RCC_FLAG_PLLRDY: PLL clock ready
1161 * @arg RCC_FLAG_HSI14RDY: HSI14 oscillator clock ready
1162 * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready (only applicable to STM32F0X2 USB devices)
1163 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
1164 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
1165 * @arg RCC_FLAG_OBLRST: Option Byte Load reset
1166 * @arg RCC_FLAG_PINRST: Pin reset
1167 * @arg RCC_FLAG_PORRST: POR/PDR reset
1168 * @arg RCC_FLAG_SFTRST: Software reset
1169 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
1170 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
1171 * @arg RCC_FLAG_LPWRRST: Low Power reset
1172 * @retval The new state of __FLAG__ (TRUE or FALSE).
1173 */
1174 #define RCC_FLAG_MASK ((uint8_t)0x1F)
1175 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : \
1176 (((__FLAG__) >> 5) == CR2_REG_INDEX)? RCC->CR2 : \
1177 (((__FLAG__) >> 5) == BDCR_REG_INDEX) ? RCC->BDCR : \
1178 RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
1179
1180
1181
1182 /**
1183 * @}
1184 */
1185
1186 /**
1187 * @}
1188 */
1189
1190 /* Include RCC HAL Extension module */
1191 #include "stm32f0xx_hal_rcc_ex.h"
1192
1193 /* Exported functions --------------------------------------------------------*/
1194
1195 /** @addtogroup RCC_Exported_Functions
1196 * @{
1197 */
1198
1199 /** @addtogroup RCC_Exported_Functions_Group1
1200 * @{
1201 */
1202
1203 /* Initialization and de-initialization functions ***************************/
1204 void HAL_RCC_DeInit(void);
1205 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1206 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
1207
1208 /**
1209 * @}
1210 */
1211
1212 /** @addtogroup RCC_Exported_Functions_Group2
1213 * @{
1214 */
1215
1216 /* Peripheral Control functions *********************************************/
1217 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
1218 void HAL_RCC_EnableCSS(void);
1219 void HAL_RCC_DisableCSS(void);
1220 uint32_t HAL_RCC_GetSysClockFreq(void);
1221 uint32_t HAL_RCC_GetHCLKFreq(void);
1222 uint32_t HAL_RCC_GetPCLK1Freq(void);
1223 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1224 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
1225
1226 /* CSS NMI IRQ handler */
1227 void HAL_RCC_NMI_IRQHandler(void);
1228
1229 /* User Callbacks in non blocking mode (IT mode) */
1230 void HAL_RCC_CCSCallback(void);
1231
1232 /**
1233 * @}
1234 */
1235
1236 /**
1237 * @}
1238 */
1239
1240 /**
1241 * @}
1242 */
1243
1244 /**
1245 * @}
1246 */
1247
1248 #ifdef __cplusplus
1249 }
1250 #endif
1251
1252 #endif /* __STM32F0xx_HAL_RCC_H */
1253
1254 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1255
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