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1 /**
2 ******************************************************************************
3 * @file stm32f0xx_hal_tim.h
4 * @author MCD Application Team
5 * @version V1.2.0
6 * @date 11-December-2014
7 * @brief Header file of TIM HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F0xx_HAL_TIM_H
40 #define __STM32F0xx_HAL_TIM_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f0xx_hal_def.h"
48
49 /** @addtogroup STM32F0xx_HAL_Driver
50 * @{
51 */
52
53 /** @addtogroup TIM
54 * @{
55 */
56
57 /* Exported types ------------------------------------------------------------*/
58 /** @defgroup TIM_Exported_Types TIM Exported Types
59 * @{
60 */
61
62 /**
63 * @brief TIM Time base Configuration Structure definition
64 */
65 typedef struct
66 {
67 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
68 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
69
70 uint32_t CounterMode; /*!< Specifies the counter mode.
71 This parameter can be a value of @ref TIM_Counter_Mode */
72
73 uint32_t Period; /*!< Specifies the period value to be loaded into the active
74 Auto-Reload Register at the next update event.
75 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
76
77 uint32_t ClockDivision; /*!< Specifies the clock division.
78 This parameter can be a value of @ref TIM_ClockDivision */
79
80 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
81 reaches zero, an update event is generated and counting restarts
82 from the RCR value (N).
83 This means in PWM mode that (N+1) corresponds to:
84 - the number of PWM periods in edge-aligned mode
85 - the number of half PWM period in center-aligned mode
86 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
87 @note This parameter is valid only for TIM1 and TIM8. */
88 } TIM_Base_InitTypeDef;
89
90 /**
91 * @brief TIM Output Compare Configuration Structure definition
92 */
93 typedef struct
94 {
95 uint32_t OCMode; /*!< Specifies the TIM mode.
96 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
97
98 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
99 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
100
101 uint32_t OCPolarity; /*!< Specifies the output polarity.
102 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
103
104 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
105 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
106 @note This parameter is valid only for TIM1 and TIM8. */
107
108 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
109 This parameter can be a value of @ref TIM_Output_Fast_State
110 @note This parameter is valid only in PWM1 and PWM2 mode. */
111
112
113 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
114 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
115 @note This parameter is valid only for TIM1 and TIM8. */
116
117 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
118 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
119 @note This parameter is valid only for TIM1 and TIM8. */
120 } TIM_OC_InitTypeDef;
121
122 /**
123 * @brief TIM One Pulse Mode Configuration Structure definition
124 */
125 typedef struct
126 {
127 uint32_t OCMode; /*!< Specifies the TIM mode.
128 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
129
130 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
131 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
132
133 uint32_t OCPolarity; /*!< Specifies the output polarity.
134 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
135
136 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
137 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
138 @note This parameter is valid only for TIM1 and TIM8. */
139
140 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
141 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
142 @note This parameter is valid only for TIM1 and TIM8. */
143
144 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
145 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
146 @note This parameter is valid only for TIM1 and TIM8. */
147
148 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
149 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
150
151 uint32_t ICSelection; /*!< Specifies the input.
152 This parameter can be a value of @ref TIM_Input_Capture_Selection */
153
154 uint32_t ICFilter; /*!< Specifies the input capture filter.
155 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
156 } TIM_OnePulse_InitTypeDef;
157
158
159 /**
160 * @brief TIM Input Capture Configuration Structure definition
161 */
162 typedef struct
163 {
164 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
165 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
166
167 uint32_t ICSelection; /*!< Specifies the input.
168 This parameter can be a value of @ref TIM_Input_Capture_Selection */
169
170 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
171 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
172
173 uint32_t ICFilter; /*!< Specifies the input capture filter.
174 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
175 } TIM_IC_InitTypeDef;
176
177 /**
178 * @brief TIM Encoder Configuration Structure definition
179 */
180 typedef struct
181 {
182 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
183 This parameter can be a value of @ref TIM_Encoder_Mode */
184
185 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
186 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
187
188 uint32_t IC1Selection; /*!< Specifies the input.
189 This parameter can be a value of @ref TIM_Input_Capture_Selection */
190
191 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
192 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
193
194 uint32_t IC1Filter; /*!< Specifies the input capture filter.
195 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
196
197 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
198 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
199
200 uint32_t IC2Selection; /*!< Specifies the input.
201 This parameter can be a value of @ref TIM_Input_Capture_Selection */
202
203 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
204 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
205
206 uint32_t IC2Filter; /*!< Specifies the input capture filter.
207 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
208 } TIM_Encoder_InitTypeDef;
209
210
211 /**
212 * @brief Clock Configuration Handle Structure definition
213 */
214 typedef struct
215 {
216 uint32_t ClockSource; /*!< TIM clock sources
217 This parameter can be a value of @ref TIM_Clock_Source */
218 uint32_t ClockPolarity; /*!< TIM clock polarity
219 This parameter can be a value of @ref TIM_Clock_Polarity */
220 uint32_t ClockPrescaler; /*!< TIM clock prescaler
221 This parameter can be a value of @ref TIM_Clock_Prescaler */
222 uint32_t ClockFilter; /*!< TIM clock filter
223 This parameter can be a value of @ref TIM_Clock_Filter */
224 }TIM_ClockConfigTypeDef;
225
226 /**
227 * @brief Clear Input Configuration Handle Structure definition
228 */
229 typedef struct
230 {
231 uint32_t ClearInputState; /*!< TIM clear Input state
232 This parameter can be ENABLE or DISABLE */
233 uint32_t ClearInputSource; /*!< TIM clear Input sources
234 This parameter can be a value of @ref TIM_ClearInput_Source */
235 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
236 This parameter can be a value of @ref TIM_ClearInput_Polarity */
237 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
238 This parameter can be a value of @ref TIM_ClearInput_Prescaler */
239 uint32_t ClearInputFilter; /*!< TIM Clear Input filter
240 This parameter can be a value of @ref TIM_ClearInput_Filter */
241 }TIM_ClearInputConfigTypeDef;
242
243 /**
244 * @brief TIM Slave configuration Structure definition
245 */
246 typedef struct {
247 uint32_t SlaveMode; /*!< Slave mode selection
248 This parameter can be a value of @ref TIM_Slave_Mode */
249 uint32_t InputTrigger; /*!< Input Trigger source
250 This parameter can be a value of @ref TIM_Trigger_Selection */
251 uint32_t TriggerPolarity; /*!< Input Trigger polarity
252 This parameter can be a value of @ref TIM_Trigger_Polarity */
253 uint32_t TriggerPrescaler; /*!< Input trigger prescaler
254 This parameter can be a value of @ref TIM_Trigger_Prescaler */
255 uint32_t TriggerFilter; /*!< Input trigger filter
256 This parameter can be a value of @ref TIM_Trigger_Filter */
257
258 }TIM_SlaveConfigTypeDef;
259
260 /**
261 * @brief HAL State structures definition
262 */
263 typedef enum
264 {
265 HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */
266 HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
267 HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
268 HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
269 HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
270 }HAL_TIM_StateTypeDef;
271
272 /**
273 * @brief HAL Active channel structures definition
274 */
275 typedef enum
276 {
277 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */
278 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */
279 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */
280 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */
281 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
282 }HAL_TIM_ActiveChannel;
283
284 /**
285 * @brief TIM Time Base Handle Structure definition
286 */
287 typedef struct
288 {
289 TIM_TypeDef *Instance; /*!< Register base address */
290 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
291 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
292 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
293 This array is accessed by a @ref TIM_DMA_Handle_index */
294 HAL_LockTypeDef Lock; /*!< Locking object */
295 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
296 }TIM_HandleTypeDef;
297
298 /**
299 * @}
300 */
301
302 /* Exported constants --------------------------------------------------------*/
303 /** @defgroup TIM_Exported_Constants TIM Exported Constants
304 * @{
305 */
306
307 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
308 * @{
309 */
310 #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */
311 #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
312 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
313 /**
314 * @}
315 */
316
317 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
318 * @{
319 */
320 #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
321 #define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */
322 /**
323 * @}
324 */
325
326 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
327 * @{
328 */
329 #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */
330 #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
331 #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
332 #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
333 /**
334 * @}
335 */
336
337 /** @defgroup TIM_Counter_Mode TIM Counter Mode
338 * @{
339 */
340
341 #define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
342 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
343 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
344 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
345 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
346
347 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
348 ((MODE) == TIM_COUNTERMODE_DOWN) || \
349 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
350 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
351 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
352 /**
353 * @}
354 */
355
356 /** @defgroup TIM_ClockDivision TIM Clock Division
357 * @{
358 */
359
360 #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
361 #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
362 #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
363
364 #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
365 ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
366 ((DIV) == TIM_CLOCKDIVISION_DIV4))
367 /**
368 * @}
369 */
370
371 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare & PWM modes
372 * @{
373 */
374
375 #define TIM_OCMODE_TIMING ((uint32_t)0x0000)
376 #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
377 #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
378 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
379 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
380 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
381 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
382 #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
383
384 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
385 ((MODE) == TIM_OCMODE_PWM2))
386
387 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
388 ((MODE) == TIM_OCMODE_ACTIVE) || \
389 ((MODE) == TIM_OCMODE_INACTIVE) || \
390 ((MODE) == TIM_OCMODE_TOGGLE) || \
391 ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
392 ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
393 /**
394 * @}
395 */
396
397 /** @defgroup TIM_Output_Compare_State TIM Output Compare State
398 * @{
399 */
400
401 #define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
402 #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
403
404 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
405 ((STATE) == TIM_OUTPUTSTATE_ENABLE))
406 /**
407 * @}
408 */
409 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
410 * @{
411 */
412 #define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
413 #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
414
415 #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
416 ((STATE) == TIM_OCFAST_ENABLE))
417 /**
418 * @}
419 */
420 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
421 * @{
422 */
423
424 #define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
425 #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
426
427 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
428 ((STATE) == TIM_OUTPUTNSTATE_ENABLE))
429 /**
430 * @}
431 */
432
433 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
434 * @{
435 */
436
437 #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
438 #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
439
440 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
441 ((POLARITY) == TIM_OCPOLARITY_LOW))
442 /**
443 * @}
444 */
445
446 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
447 * @{
448 */
449
450 #define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
451 #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
452
453 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
454 ((POLARITY) == TIM_OCNPOLARITY_LOW))
455 /**
456 * @}
457 */
458
459 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
460 * @{
461 */
462
463 #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
464 #define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
465 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
466 ((STATE) == TIM_OCIDLESTATE_RESET))
467 /**
468 * @}
469 */
470
471 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
472 * @{
473 */
474
475 #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
476 #define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
477 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
478 ((STATE) == TIM_OCNIDLESTATE_RESET))
479 /**
480 * @}
481 */
482
483 /** @defgroup TIM_Channel TIM Channel
484 * @{
485 */
486 #define TIM_CHANNEL_1 ((uint32_t)0x0000)
487 #define TIM_CHANNEL_2 ((uint32_t)0x0004)
488 #define TIM_CHANNEL_3 ((uint32_t)0x0008)
489 #define TIM_CHANNEL_4 ((uint32_t)0x000C)
490 #define TIM_CHANNEL_ALL ((uint32_t)0x0018)
491
492 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
493 ((CHANNEL) == TIM_CHANNEL_2) || \
494 ((CHANNEL) == TIM_CHANNEL_3) || \
495 ((CHANNEL) == TIM_CHANNEL_4) || \
496 ((CHANNEL) == TIM_CHANNEL_ALL))
497
498 #define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
499 ((CHANNEL) == TIM_CHANNEL_2))
500
501 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
502 ((CHANNEL) == TIM_CHANNEL_2))
503
504 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
505 ((CHANNEL) == TIM_CHANNEL_2) || \
506 ((CHANNEL) == TIM_CHANNEL_3))
507 /**
508 * @}
509 */
510
511 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
512 * @{
513 */
514
515 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
516 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
517 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
518
519 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
520 ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
521 ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
522 /**
523 * @}
524 */
525
526 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
527 * @{
528 */
529
530 #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
531 connected to IC1, IC2, IC3 or IC4, respectively */
532 #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
533 connected to IC2, IC1, IC4 or IC3, respectively */
534 #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
535
536 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
537 ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
538 ((SELECTION) == TIM_ICSELECTION_TRC))
539 /**
540 * @}
541 */
542
543 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
544 * @{
545 */
546
547 #define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */
548 #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
549 #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
550 #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
551
552 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
553 ((PRESCALER) == TIM_ICPSC_DIV2) || \
554 ((PRESCALER) == TIM_ICPSC_DIV4) || \
555 ((PRESCALER) == TIM_ICPSC_DIV8))
556 /**
557 * @}
558 */
559
560 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
561 * @{
562 */
563
564 #define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
565 #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
566
567 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
568 ((MODE) == TIM_OPMODE_REPETITIVE))
569 /**
570 * @}
571 */
572 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
573 * @{
574 */
575 #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
576 #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
577 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
578
579 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
580 ((MODE) == TIM_ENCODERMODE_TI2) || \
581 ((MODE) == TIM_ENCODERMODE_TI12))
582 /**
583 * @}
584 */
585 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition
586 * @{
587 */
588 #define TIM_IT_UPDATE (TIM_DIER_UIE)
589 #define TIM_IT_CC1 (TIM_DIER_CC1IE)
590 #define TIM_IT_CC2 (TIM_DIER_CC2IE)
591 #define TIM_IT_CC3 (TIM_DIER_CC3IE)
592 #define TIM_IT_CC4 (TIM_DIER_CC4IE)
593 #define TIM_IT_COM (TIM_DIER_COMIE)
594 #define TIM_IT_TRIGGER (TIM_DIER_TIE)
595 #define TIM_IT_BREAK (TIM_DIER_BIE)
596 /**
597 * @}
598 */
599
600 /** @defgroup TIM_COMMUTATION TIM Commutation
601 * @{
602 */
603 #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
604 #define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
605
606 /**
607 * @}
608 */
609 /** @defgroup TIM_DMA_sources TIM DMA Sources
610 * @{
611 */
612
613 #define TIM_DMA_UPDATE (TIM_DIER_UDE)
614 #define TIM_DMA_CC1 (TIM_DIER_CC1DE)
615 #define TIM_DMA_CC2 (TIM_DIER_CC2DE)
616 #define TIM_DMA_CC3 (TIM_DIER_CC3DE)
617 #define TIM_DMA_CC4 (TIM_DIER_CC4DE)
618 #define TIM_DMA_COM (TIM_DIER_COMDE)
619 #define TIM_DMA_TRIGGER (TIM_DIER_TDE)
620
621 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
622 /**
623 * @}
624 */
625
626 /** @defgroup TIM_Event_Source TIM Event Source
627 * @{
628 */
629 #define TIM_EventSource_Update TIM_EGR_UG
630 #define TIM_EventSource_CC1 TIM_EGR_CC1G
631 #define TIM_EventSource_CC2 TIM_EGR_CC2G
632 #define TIM_EventSource_CC3 TIM_EGR_CC3G
633 #define TIM_EventSource_CC4 TIM_EGR_CC4G
634 #define TIM_EventSource_COM TIM_EGR_COMG
635 #define TIM_EventSource_Trigger TIM_EGR_TG
636 #define TIM_EventSource_Break TIM_EGR_BG
637
638 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
639 /**
640 * @}
641 */
642
643 /** @defgroup TIM_Flag_definition TIM Flag Definition
644 * @{
645 */
646
647 #define TIM_FLAG_UPDATE (TIM_SR_UIF)
648 #define TIM_FLAG_CC1 (TIM_SR_CC1IF)
649 #define TIM_FLAG_CC2 (TIM_SR_CC2IF)
650 #define TIM_FLAG_CC3 (TIM_SR_CC3IF)
651 #define TIM_FLAG_CC4 (TIM_SR_CC4IF)
652 #define TIM_FLAG_COM (TIM_SR_COMIF)
653 #define TIM_FLAG_TRIGGER (TIM_SR_TIF)
654 #define TIM_FLAG_BREAK (TIM_SR_BIF)
655 #define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
656 #define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
657 #define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
658 #define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
659
660 #define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) || \
661 ((FLAG) == TIM_FLAG_CC1) || \
662 ((FLAG) == TIM_FLAG_CC2) || \
663 ((FLAG) == TIM_FLAG_CC3) || \
664 ((FLAG) == TIM_FLAG_CC4) || \
665 ((FLAG) == TIM_FLAG_COM) || \
666 ((FLAG) == TIM_FLAG_TRIGGER) || \
667 ((FLAG) == TIM_FLAG_BREAK) || \
668 ((FLAG) == TIM_FLAG_CC1OF) || \
669 ((FLAG) == TIM_FLAG_CC2OF) || \
670 ((FLAG) == TIM_FLAG_CC3OF) || \
671 ((FLAG) == TIM_FLAG_CC4OF))
672 /**
673 * @}
674 */
675
676 /** @defgroup TIM_Clock_Source TIM Clock Source
677 * @{
678 */
679 #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
680 #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
681 #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
682 #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
683 #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
684 #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
685 #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
686 #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
687 #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
688 #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
689
690 #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
691 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
692 ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
693 ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
694 ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
695 ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
696 ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
697 ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
698 ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
699 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
700 /**
701 * @}
702 */
703
704 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
705 * @{
706 */
707 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
708 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
709 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
710 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
711 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
712
713 #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
714 ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
715 ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
716 ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
717 ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
718 /**
719 * @}
720 */
721 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
722 * @{
723 */
724 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
725 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
726 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
727 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
728
729 #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
730 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
731 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
732 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
733 /**
734 * @}
735 */
736 /** @defgroup TIM_Clock_Filter TIM Clock Filter
737 * @{
738 */
739
740 #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
741 /**
742 * @}
743 */
744
745 /** @defgroup TIM_ClearInput_Source TIM ClearInput Source
746 * @{
747 */
748 #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
749 #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
750
751 #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
752 ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
753 /**
754 * @}
755 */
756
757 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
758 * @{
759 */
760 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
761 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
762
763
764 #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
765 ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
766 /**
767 * @}
768 */
769
770 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
771 * @{
772 */
773 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
774 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
775 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
776 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
777
778 #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
779 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
780 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
781 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
782 /**
783 * @}
784 */
785
786 /** @defgroup TIM_ClearInput_Filter TIM Clear Input Filter
787 * @{
788 */
789
790 #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
791 /**
792 * @}
793 */
794
795 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM Off-state Selection for Run Mode
796 * @{
797 */
798 #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
799 #define TIM_OSSR_DISABLE ((uint32_t)0x0000)
800
801 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
802 ((STATE) == TIM_OSSR_DISABLE))
803 /**
804 * @}
805 */
806
807 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM Off-state Selection for Idle Mode
808 * @{
809 */
810 #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
811 #define TIM_OSSI_DISABLE ((uint32_t)0x0000)
812
813 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
814 ((STATE) == TIM_OSSI_DISABLE))
815 /**
816 * @}
817 */
818 /** @defgroup TIM_Lock_level TIM Lock Configuration
819 * @{
820 */
821 #define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
822 #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
823 #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
824 #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
825
826 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
827 ((LEVEL) == TIM_LOCKLEVEL_1) || \
828 ((LEVEL) == TIM_LOCKLEVEL_2) || \
829 ((LEVEL) == TIM_LOCKLEVEL_3))
830 /**
831 * @}
832 */
833 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
834 * @{
835 */
836 #define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
837 #define TIM_BREAK_DISABLE ((uint32_t)0x0000)
838
839 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
840 ((STATE) == TIM_BREAK_DISABLE))
841 /**
842 * @}
843 */
844 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity
845 * @{
846 */
847 #define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
848 #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
849
850 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
851 ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
852 /**
853 * @}
854 */
855 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
856 * @{
857 */
858 #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
859 #define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
860
861 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
862 ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
863 /**
864 * @}
865 */
866
867 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
868 * @{
869 */
870 #define TIM_TRGO_RESET ((uint32_t)0x0000)
871 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
872 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
873 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
874 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
875 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
876 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
877 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
878
879 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
880 ((SOURCE) == TIM_TRGO_ENABLE) || \
881 ((SOURCE) == TIM_TRGO_UPDATE) || \
882 ((SOURCE) == TIM_TRGO_OC1) || \
883 ((SOURCE) == TIM_TRGO_OC1REF) || \
884 ((SOURCE) == TIM_TRGO_OC2REF) || \
885 ((SOURCE) == TIM_TRGO_OC3REF) || \
886 ((SOURCE) == TIM_TRGO_OC4REF))
887
888
889 /**
890 * @}
891 */
892
893 /** @defgroup TIM_Slave_Mode TIM Slave Mode
894 * @{
895 */
896
897 #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
898 #define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
899 #define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
900 #define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
901 #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
902
903 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
904 ((MODE) == TIM_SLAVEMODE_GATED) || \
905 ((MODE) == TIM_SLAVEMODE_RESET) || \
906 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
907 ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
908 /**
909 * @}
910 */
911
912 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
913 * @{
914 */
915
916 #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
917 #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
918
919 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
920 ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
921 /**
922 * @}
923 */
924 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
925 * @{
926 */
927
928 #define TIM_TS_ITR0 ((uint32_t)0x0000)
929 #define TIM_TS_ITR1 ((uint32_t)0x0010)
930 #define TIM_TS_ITR2 ((uint32_t)0x0020)
931 #define TIM_TS_ITR3 ((uint32_t)0x0030)
932 #define TIM_TS_TI1F_ED ((uint32_t)0x0040)
933 #define TIM_TS_TI1FP1 ((uint32_t)0x0050)
934 #define TIM_TS_TI2FP2 ((uint32_t)0x0060)
935 #define TIM_TS_ETRF ((uint32_t)0x0070)
936 #define TIM_TS_NONE ((uint32_t)0xFFFF)
937
938 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
939 ((SELECTION) == TIM_TS_ITR1) || \
940 ((SELECTION) == TIM_TS_ITR2) || \
941 ((SELECTION) == TIM_TS_ITR3) || \
942 ((SELECTION) == TIM_TS_TI1F_ED) || \
943 ((SELECTION) == TIM_TS_TI1FP1) || \
944 ((SELECTION) == TIM_TS_TI2FP2) || \
945 ((SELECTION) == TIM_TS_ETRF))
946
947 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
948 ((SELECTION) == TIM_TS_ITR1) || \
949 ((SELECTION) == TIM_TS_ITR2) || \
950 ((SELECTION) == TIM_TS_ITR3))
951
952 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
953 ((SELECTION) == TIM_TS_ITR1) || \
954 ((SELECTION) == TIM_TS_ITR2) || \
955 ((SELECTION) == TIM_TS_ITR3) || \
956 ((SELECTION) == TIM_TS_NONE))
957 /**
958 * @}
959 */
960
961 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
962 * @{
963 */
964 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
965 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
966 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
967 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
968 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
969
970 #define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
971 ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
972 ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
973 ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
974 ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
975 /**
976 * @}
977 */
978
979 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
980 * @{
981 */
982 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
983 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
984 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
985 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
986
987 #define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
988 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
989 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
990 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
991 /**
992 * @}
993 */
994
995 /** @defgroup TIM_Trigger_Filter TIM Trigger Filter
996 * @{
997 */
998
999 #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
1000 /**
1001 * @}
1002 */
1003
1004 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
1005 * @{
1006 */
1007
1008 #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
1009 #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
1010
1011 #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
1012 ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
1013
1014 /**
1015 * @}
1016 */
1017
1018 /** @defgroup TIM_DMA_Base_address TIM DMA Base address
1019 * @{
1020 */
1021 #define TIM_DMABase_CR1 (0x00000000)
1022 #define TIM_DMABase_CR2 (0x00000001)
1023 #define TIM_DMABase_SMCR (0x00000002)
1024 #define TIM_DMABase_DIER (0x00000003)
1025 #define TIM_DMABase_SR (0x00000004)
1026 #define TIM_DMABase_EGR (0x00000005)
1027 #define TIM_DMABase_CCMR1 (0x00000006)
1028 #define TIM_DMABase_CCMR2 (0x00000007)
1029 #define TIM_DMABase_CCER (0x00000008)
1030 #define TIM_DMABase_CNT (0x00000009)
1031 #define TIM_DMABase_PSC (0x0000000A)
1032 #define TIM_DMABase_ARR (0x0000000B)
1033 #define TIM_DMABase_RCR (0x0000000C)
1034 #define TIM_DMABase_CCR1 (0x0000000D)
1035 #define TIM_DMABase_CCR2 (0x0000000E)
1036 #define TIM_DMABase_CCR3 (0x0000000F)
1037 #define TIM_DMABase_CCR4 (0x00000010)
1038 #define TIM_DMABase_BDTR (0x00000011)
1039 #define TIM_DMABase_DCR (0x00000012)
1040 #define TIM_DMABase_OR (0x00000013)
1041
1042 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
1043 ((BASE) == TIM_DMABase_CR2) || \
1044 ((BASE) == TIM_DMABase_SMCR) || \
1045 ((BASE) == TIM_DMABase_DIER) || \
1046 ((BASE) == TIM_DMABase_SR) || \
1047 ((BASE) == TIM_DMABase_EGR) || \
1048 ((BASE) == TIM_DMABase_CCMR1) || \
1049 ((BASE) == TIM_DMABase_CCMR2) || \
1050 ((BASE) == TIM_DMABase_CCER) || \
1051 ((BASE) == TIM_DMABase_CNT) || \
1052 ((BASE) == TIM_DMABase_PSC) || \
1053 ((BASE) == TIM_DMABase_ARR) || \
1054 ((BASE) == TIM_DMABase_RCR) || \
1055 ((BASE) == TIM_DMABase_CCR1) || \
1056 ((BASE) == TIM_DMABase_CCR2) || \
1057 ((BASE) == TIM_DMABase_CCR3) || \
1058 ((BASE) == TIM_DMABase_CCR4) || \
1059 ((BASE) == TIM_DMABase_BDTR) || \
1060 ((BASE) == TIM_DMABase_DCR) || \
1061 ((BASE) == TIM_DMABase_OR))
1062 /**
1063 * @}
1064 */
1065
1066 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
1067 * @{
1068 */
1069
1070 #define TIM_DMABurstLength_1Transfer (0x00000000)
1071 #define TIM_DMABurstLength_2Transfers (0x00000100)
1072 #define TIM_DMABurstLength_3Transfers (0x00000200)
1073 #define TIM_DMABurstLength_4Transfers (0x00000300)
1074 #define TIM_DMABurstLength_5Transfers (0x00000400)
1075 #define TIM_DMABurstLength_6Transfers (0x00000500)
1076 #define TIM_DMABurstLength_7Transfers (0x00000600)
1077 #define TIM_DMABurstLength_8Transfers (0x00000700)
1078 #define TIM_DMABurstLength_9Transfers (0x00000800)
1079 #define TIM_DMABurstLength_10Transfers (0x00000900)
1080 #define TIM_DMABurstLength_11Transfers (0x00000A00)
1081 #define TIM_DMABurstLength_12Transfers (0x00000B00)
1082 #define TIM_DMABurstLength_13Transfers (0x00000C00)
1083 #define TIM_DMABurstLength_14Transfers (0x00000D00)
1084 #define TIM_DMABurstLength_15Transfers (0x00000E00)
1085 #define TIM_DMABurstLength_16Transfers (0x00000F00)
1086 #define TIM_DMABurstLength_17Transfers (0x00001000)
1087 #define TIM_DMABurstLength_18Transfers (0x00001100)
1088
1089 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
1090 ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
1091 ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
1092 ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
1093 ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
1094 ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
1095 ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
1096 ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
1097 ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
1098 ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
1099 ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
1100 ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
1101 ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
1102 ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
1103 ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
1104 ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
1105 ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
1106 ((LENGTH) == TIM_DMABurstLength_18Transfers))
1107 /**
1108 * @}
1109 */
1110
1111 /** @defgroup TIM_Input_Capture_Filer_Value TIM Input Capture Value
1112 * @{
1113 */
1114
1115 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
1116 /**
1117 * @}
1118 */
1119
1120 /** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
1121 * @{
1122 */
1123 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */
1124 #define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
1125 #define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
1126 #define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
1127 #define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
1128 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */
1129 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */
1130 /**
1131 * @}
1132 */
1133
1134 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State
1135 * @{
1136 */
1137 #define TIM_CCx_ENABLE ((uint32_t)0x0001)
1138 #define TIM_CCx_DISABLE ((uint32_t)0x0000)
1139 #define TIM_CCxN_ENABLE ((uint32_t)0x0004)
1140 #define TIM_CCxN_DISABLE ((uint32_t)0x0000)
1141 /**
1142 * @}
1143 */
1144
1145 /**
1146 * @}
1147 */
1148
1149 /* Exported macros -----------------------------------------------------------*/
1150 /** @defgroup TIM_Exported_Macros TIM Exported Macros
1151 * @{
1152 */
1153
1154 /** @brief Reset TIM handle state
1155 * @param __HANDLE__: TIM handle.
1156 * @retval None
1157 */
1158 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
1159
1160 /**
1161 * @brief Enable the TIM peripheral.
1162 * @param __HANDLE__: TIM handle
1163 * @retval None
1164 */
1165 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
1166
1167 /**
1168 * @brief Enable the TIM main Output.
1169 * @param __HANDLE__: TIM handle
1170 * @retval None
1171 */
1172 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
1173
1174 /**
1175 * @brief Disable the TIM peripheral.
1176 * @param __HANDLE__: TIM handle
1177 * @retval None
1178 */
1179 #define __HAL_TIM_DISABLE(__HANDLE__) \
1180 do { \
1181 if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
1182 { \
1183 if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
1184 { \
1185 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
1186 } \
1187 } \
1188 } while(0)
1189 /* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
1190 channels have been disabled */
1191 /**
1192 * @brief Disable the TIM main Output.
1193 * @param __HANDLE__: TIM handle
1194 * @retval None
1195 */
1196 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
1197 do { \
1198 if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
1199 { \
1200 if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
1201 { \
1202 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
1203 } \
1204 } \
1205 } while(0)
1206
1207 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
1208 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
1209 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
1210 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
1211 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
1212 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
1213
1214 #define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
1215 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
1216
1217 #define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
1218 #define __HAL_TIM_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
1219
1220 #define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \
1221 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
1222 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
1223 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
1224 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
1225
1226 #define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \
1227 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
1228 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
1229 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
1230 ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
1231
1232 /**
1233 * @brief Sets the TIM Capture Compare Register value on runtime without
1234 * calling another time ConfigChannel function.
1235 * @param __HANDLE__: TIM handle.
1236 * @param __CHANNEL__ : TIM Channels to be configured.
1237 * This parameter can be one of the following values:
1238 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1239 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1240 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1241 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1242 * @param __COMPARE__: specifies the Capture Compare register new value.
1243 * @retval None
1244 */
1245 #define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
1246 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
1247
1248 /**
1249 * @brief Gets the TIM Capture Compare Register value on runtime
1250 * @param __HANDLE__: TIM handle.
1251 * @param __CHANNEL__ : TIM Channel associated with the capture compare register
1252 * This parameter can be one of the following values:
1253 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
1254 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
1255 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
1256 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
1257 * @retval None
1258 */
1259 #define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \
1260 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
1261
1262 /**
1263 * @brief Sets the TIM Counter Register value on runtime.
1264 * @param __HANDLE__: TIM handle.
1265 * @param __COUNTER__: specifies the Counter register new value.
1266 * @retval None
1267 */
1268 #define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
1269
1270 /**
1271 * @brief Gets the TIM Counter Register value on runtime.
1272 * @param __HANDLE__: TIM handle.
1273 * @retval None
1274 */
1275 #define __HAL_TIM_GetCounter(__HANDLE__) \
1276 ((__HANDLE__)->Instance->CNT)
1277
1278 /**
1279 * @brief Sets the TIM Autoreload Register value on runtime without calling
1280 * another time any Init function.
1281 * @param __HANDLE__: TIM handle.
1282 * @param __AUTORELOAD__: specifies the Counter register new value.
1283 * @retval None
1284 */
1285 #define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \
1286 do{ \
1287 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
1288 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
1289 } while(0)
1290
1291 /**
1292 * @brief Gets the TIM Autoreload Register value on runtime
1293 * @param __HANDLE__: TIM handle.
1294 * @retval None
1295 */
1296 #define __HAL_TIM_GetAutoreload(__HANDLE__) \
1297 ((__HANDLE__)->Instance->ARR)
1298
1299 /**
1300 * @brief Sets the TIM Clock Division value on runtime without calling
1301 * another time any Init function.
1302 * @param __HANDLE__: TIM handle.
1303 * @param __CKD__: specifies the clock division value.
1304 * This parameter can be one of the following value:
1305 * @arg TIM_CLOCKDIVISION_DIV1
1306 * @arg TIM_CLOCKDIVISION_DIV2
1307 * @arg TIM_CLOCKDIVISION_DIV4
1308 * @retval None
1309 */
1310 #define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \
1311 do{ \
1312 (__HANDLE__)->Instance->CR1 &= ~TIM_CR1_CKD; \
1313 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
1314 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
1315 } while(0)
1316
1317 /**
1318 * @brief Gets the TIM Clock Division value on runtime
1319 * @param __HANDLE__: TIM handle.
1320 * @retval None
1321 */
1322 #define __HAL_TIM_GetClockDivision(__HANDLE__) \
1323 ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
1324
1325 /**
1326 * @brief Sets the TIM Input Capture prescaler on runtime without calling
1327 * another time HAL_TIM_IC_ConfigChannel() function.
1328 * @param __HANDLE__: TIM handle.
1329 * @param __CHANNEL__ : TIM Channels to be configured.
1330 * This parameter can be one of the following values:
1331 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1332 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1333 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1334 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1335 * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
1336 * This parameter can be one of the following values:
1337 * @arg TIM_ICPSC_DIV1: no prescaler
1338 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1339 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1340 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1341 * @retval None
1342 */
1343 #define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \
1344 do{ \
1345 __HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \
1346 __HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
1347 } while(0)
1348
1349 /**
1350 * @brief Gets the TIM Input Capture prescaler on runtime
1351 * @param __HANDLE__: TIM handle.
1352 * @param __CHANNEL__: TIM Channels to be configured.
1353 * This parameter can be one of the following values:
1354 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
1355 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
1356 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
1357 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
1358 * @retval None
1359 */
1360 #define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \
1361 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
1362 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
1363 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
1364 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
1365
1366 /**
1367 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
1368 * @param __HANDLE__: TIM handle.
1369 * @note When the USR bit of the TIMx_CR1 register is set, only counter
1370 * overflow/underflow generates an update interrupt or DMA request (if
1371 * enabled)
1372 * @retval None
1373 */
1374 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
1375 ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
1376
1377 /**
1378 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
1379 * @param __HANDLE__: TIM handle.
1380 * @note When the USR bit of the TIMx_CR1 register is reset, any of the
1381 * following events generate an update interrupt or DMA request (if
1382 * enabled):
1383 * (+) Counter overflow/underflow
1384 * (+) Setting the UG bit
1385 * (+) Update generation through the slave mode controller
1386 * @retval None
1387 */
1388 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
1389 ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
1390
1391 /**
1392 * @}
1393 */
1394
1395 /* Include TIM HAL Extension module */
1396 #include "stm32f0xx_hal_tim_ex.h"
1397
1398 /* Exported functions --------------------------------------------------------*/
1399 /** @addtogroup TIM_Exported_Functions TIM Exported Functions
1400 * @{
1401 */
1402
1403 /** @addtogroup TIM_Exported_Functions_Group1 Time Base functions
1404 * @brief Time Base functions
1405 * @{
1406 */
1407 /* Time Base functions ********************************************************/
1408 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
1409 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
1410 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
1411 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
1412 /* Blocking mode: Polling */
1413 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
1414 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
1415 /* Non-Blocking mode: Interrupt */
1416 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
1417 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
1418 /* Non-Blocking mode: DMA */
1419 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
1420 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
1421 /**
1422 * @}
1423 */
1424
1425 /** @addtogroup TIM_Exported_Functions_Group2 Time Output Compare functions
1426 * @brief Time Output Compare functions
1427 * @{
1428 */
1429 /* Timer Output Compare functions **********************************************/
1430 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
1431 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
1432 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
1433 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
1434 /* Blocking mode: Polling */
1435 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1436 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1437 /* Non-Blocking mode: Interrupt */
1438 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1439 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1440 /* Non-Blocking mode: DMA */
1441 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1442 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1443 /**
1444 * @}
1445 */
1446
1447 /** @addtogroup TIM_Exported_Functions_Group3 Time PWM functions
1448 * @brief Time PWM functions
1449 * @{
1450 */
1451 /* Timer PWM functions *********************************************************/
1452 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
1453 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
1454 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
1455 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
1456 /* Blocking mode: Polling */
1457 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1458 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1459 /* Non-Blocking mode: Interrupt */
1460 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1461 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1462 /* Non-Blocking mode: DMA */
1463 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1464 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1465 /**
1466 * @}
1467 */
1468
1469 /** @addtogroup TIM_Exported_Functions_Group4 Time Input Capture functions
1470 * @brief Time Input Capture functions
1471 * @{
1472 */
1473 /* Timer Input Capture functions ***********************************************/
1474 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
1475 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
1476 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
1477 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
1478 /* Blocking mode: Polling */
1479 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1480 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1481 /* Non-Blocking mode: Interrupt */
1482 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1483 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1484 /* Non-Blocking mode: DMA */
1485 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1486 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1487 /**
1488 * @}
1489 */
1490
1491 /** @addtogroup TIM_Exported_Functions_Group5 Time One Pulse functions
1492 * @brief Time One Pulse functions
1493 * @{
1494 */
1495 /* Timer One Pulse functions ***************************************************/
1496 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
1497 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
1498 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
1499 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
1500 /* Blocking mode: Polling */
1501 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1502 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1503 /* Non-Blocking mode: Interrupt */
1504 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1505 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1506 /**
1507 * @}
1508 */
1509
1510 /** @addtogroup TIM_Exported_Functions_Group6 Time Encoder functions
1511 * @brief Time Encoder functions
1512 * @{
1513 */
1514 /* Timer Encoder functions *****************************************************/
1515 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
1516 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
1517 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
1518 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
1519 /* Blocking mode: Polling */
1520 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1521 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1522 /* Non-Blocking mode: Interrupt */
1523 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1524 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1525 /* Non-Blocking mode: DMA */
1526 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
1527 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1528 /**
1529 * @}
1530 */
1531
1532 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
1533 * @brief IRQ handler management
1534 * @{
1535 */
1536 /* Interrupt Handler functions **********************************************/
1537 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
1538 /**
1539 * @}
1540 */
1541
1542 /** @addtogroup TIM_Exported_Functions_Group8 Peripheral Control functions
1543 * @brief Peripheral Control functions
1544 * @{
1545 */
1546 /* Control functions *********************************************************/
1547 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
1548 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
1549 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
1550 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
1551 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
1552 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
1553 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
1554 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
1555 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
1556 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
1557 uint32_t *BurstBuffer, uint32_t BurstLength);
1558 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
1559 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
1560 uint32_t *BurstBuffer, uint32_t BurstLength);
1561 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
1562 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
1563 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
1564 /**
1565 * @}
1566 */
1567
1568 /** @addtogroup TIM_Exported_Functions_Group9
1569 * @brief TIM Callbacks functions
1570 * @{
1571 */
1572 /* Callback in non blocking modes (Interrupt and DMA) *************************/
1573 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
1574 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
1575 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
1576 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
1577 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
1578 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
1579 /**
1580 * @}
1581 */
1582
1583 /** @addtogroup TIM_Exported_Functions_Group10
1584 * @brief Peripheral State functions
1585 * @{
1586 */
1587 /* Peripheral State functions **************************************************/
1588 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
1589 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
1590 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
1591 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
1592 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
1593 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
1594 /**
1595 * @}
1596 */
1597
1598 /**
1599 * @}
1600 */
1601
1602 /* Private Macros -----------------------------------------------------------*/
1603 /** @defgroup TIM_Private_Macros TIM Private Macros
1604 * @{
1605 */
1606 /* The counter of a timer instance is disabled only if all the CCx and CCxN
1607 channels have been disabled */
1608 #define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
1609 #define CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
1610 /**
1611 * @}
1612 */
1613
1614 /* Private Functions --------------------------------------------------------*/
1615 /** @addtogroup TIM_Private_Functions
1616 * @{
1617 */
1618 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
1619 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
1620 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
1621 void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
1622 void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
1623 void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
1624 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
1625
1626 /**
1627 * @}
1628 */
1629
1630 /**
1631 * @}
1632 */
1633
1634 /**
1635 * @}
1636 */
1637
1638 #ifdef __cplusplus
1639 }
1640 #endif
1641
1642 #endif /* __STM32F0xx_HAL_TIM_H */
1643
1644 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1645
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