tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/stm32f100xb.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f100xb.h
   4   * @author  MCD Application Team
   5   * @version V4.0.0
   6   * @date    16-December-2014
   7   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
   8   *          This file contains all the peripheral register's definitions, bits
   9   *          definitions and memory mapping for STM32F1xx devices.
  10   *
  11   *          This file contains:
  12   *           - Data structures and the address mapping for all peripherals
  13   *           - Peripheral's registers declarations and bits definition
  14   *           - Macros to access peripheral\92s registers hardware
  15   *
  16   ******************************************************************************
  17   * @attention
  18   *
  19   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  20   *
  21   * Redistribution and use in source and binary forms, with or without modification,
  22   * are permitted provided that the following conditions are met:
  23   *   1. Redistributions of source code must retain the above copyright notice,
  24   *      this list of conditions and the following disclaimer.
  25   *   2. Redistributions in binary form must reproduce the above copyright notice,
  26   *      this list of conditions and the following disclaimer in the documentation
  27   *      and/or other materials provided with the distribution.
  28   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  29   *      may be used to endorse or promote products derived from this software
  30   *      without specific prior written permission.
  31   *
  32   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  33   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  34   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  36   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  37   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  38   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  39   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  40   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  41   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42   *
  43   ******************************************************************************
  44   */
  45
  46
  47 /** @addtogroup CMSIS
  48   * @{
  49   */
  50
  51 /** @addtogroup stm32f100xb
  52   * @{
  53   */
  54
  55 #ifndef __STM32F100xB_H
  56 #define __STM32F100xB_H
  57
  58 #ifdef __cplusplus
  59  extern "C" {
  60 #endif
  61
  62 /** @addtogroup Configuration_section_for_CMSIS
  63   * @{
  64   */
  65 /**
  66   * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
  67  */
  68  #define __MPU_PRESENT             0      /*!< Other STM32 devices does not provide an MPU  */
  69 #define __CM3_REV                 0x0200  /*!< Core Revision r2p0                           */
  70 #define __NVIC_PRIO_BITS          4       /*!< STM32 uses 4 Bits for the Priority Levels    */
  71 #define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used */
  72
  73 /**
  74   * @}
  75   */
  76
  77 /** @addtogroup Peripheral_interrupt_number_definition
  78   * @{
  79   */
  80
  81 /**
  82  * @brief STM32F10x Interrupt Number Definition, according to the selected device
  83  *        in @ref Library_configuration_section
  84  */
  85
  86  /*!< Interrupt Number Definition */
  87 typedef enum
  88 {
  89 /******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
  90   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                             */
  91   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt              */
  92   BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                      */
  93   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                    */
  94   SVCall_IRQn                 = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                       */
  95   DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                 */
  96   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                       */
  97   SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                   */
  98
  99 /******  STM32 specific Interrupt Numbers *********************************************************/
 100   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                            */
 101   PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt            */
 102   TAMPER_IRQn                 = 2,      /*!< Tamper Interrupt                                     */
 103   RTC_IRQn                    = 3,      /*!< RTC global Interrupt                                 */
 104   FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                               */
 105   RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                 */
 106   EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                 */
 107   EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                 */
 108   EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                 */
 109   EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                 */
 110   EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                 */
 111   DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                      */
 112   DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                      */
 113   DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                      */
 114   DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                      */
 115   DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                      */
 116   DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                      */
 117   DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                      */
 118   ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                */
 119   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */
 120   TIM1_BRK_TIM15_IRQn         = 24,     /*!< TIM1 Break and TIM15 Interrupts                      */
 121   TIM1_UP_TIM16_IRQn          = 25,     /*!< TIM1 Update and TIM16 Interrupts                     */
 122   TIM1_TRG_COM_TIM17_IRQn     = 26,     /*!< TIM1 Trigger and Commutation and TIM17 Interrupt     */
 123   TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */
 124   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */
 125   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */
 126   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */
 127   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */
 128   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */
 129   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */
 130   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */
 131   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */
 132   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */
 133   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */
 134   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */
 135   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */
 136   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */
 137   RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */
 138   CEC_IRQn                    = 42,     /*!< HDMI-CEC Interrupt                                   */
 139   TIM6_DAC_IRQn               = 54,     /*!< TIM6 and DAC underrun Interrupt                      */
 140   TIM7_IRQn                   = 55,     /*!< TIM7 global Interrupt                                */
 141 } IRQn_Type;
 142
 143
 144 /**
 145   * @}
 146   */
 147
 148 #include "core_cm3.h"
 149 #include "system_stm32f1xx.h"
 150 #include <stdint.h>
 151
 152 /** @addtogroup Peripheral_registers_structures
 153   * @{
 154   */
 155
 156 /**
 157   * @brief Analog to Digital Converter
 158   */
 159
 160 typedef struct
 161 {
 162   __IO uint32_t SR;
 163   __IO uint32_t CR1;
 164   __IO uint32_t CR2;
 165   __IO uint32_t SMPR1;
 166   __IO uint32_t SMPR2;
 167   __IO uint32_t JOFR1;
 168   __IO uint32_t JOFR2;
 169   __IO uint32_t JOFR3;
 170   __IO uint32_t JOFR4;
 171   __IO uint32_t HTR;
 172   __IO uint32_t LTR;
 173   __IO uint32_t SQR1;
 174   __IO uint32_t SQR2;
 175   __IO uint32_t SQR3;
 176   __IO uint32_t JSQR;
 177   __IO uint32_t JDR1;
 178   __IO uint32_t JDR2;
 179   __IO uint32_t JDR3;
 180   __IO uint32_t JDR4;
 181   __IO uint32_t DR;
 182 } ADC_TypeDef;
 183
 184 /**
 185   * @brief Backup Registers
 186   */
 187
 188 typedef struct
 189 {
 190   uint32_t  RESERVED0;
 191   __IO uint32_t DR1;
 192   __IO uint32_t DR2;
 193   __IO uint32_t DR3;
 194   __IO uint32_t DR4;
 195   __IO uint32_t DR5;
 196   __IO uint32_t DR6;
 197   __IO uint32_t DR7;
 198   __IO uint32_t DR8;
 199   __IO uint32_t DR9;
 200   __IO uint32_t DR10;
 201   __IO uint32_t RTCCR;
 202   __IO uint32_t CR;
 203   __IO uint32_t CSR;
 204 } BKP_TypeDef;
 205
 206
 207 /**
 208   * @brief Consumer Electronics Control (CEC)
 209   */
 210 typedef struct
 211 {
 212   __IO uint32_t CFGR;
 213   __IO uint32_t OAR;
 214   __IO uint32_t PRES;
 215   __IO uint32_t ESR;
 216   __IO uint32_t CSR;
 217   __IO uint32_t TXD;
 218   __IO uint32_t RXD;
 219 } CEC_TypeDef;
 220
 221 /**
 222   * @brief CRC calculation unit
 223   */
 224
 225 typedef struct
 226 {
 227   __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
 228   __IO uint32_t IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
 229   __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */
 230 } CRC_TypeDef;
 231
 232 /**
 233   * @brief Digital to Analog Converter
 234   */
 235
 236 typedef struct
 237 {
 238   __IO uint32_t CR;
 239   __IO uint32_t SWTRIGR;
 240   __IO uint32_t DHR12R1;
 241   __IO uint32_t DHR12L1;
 242   __IO uint32_t DHR8R1;
 243   __IO uint32_t DHR12R2;
 244   __IO uint32_t DHR12L2;
 245   __IO uint32_t DHR8R2;
 246   __IO uint32_t DHR12RD;
 247   __IO uint32_t DHR12LD;
 248   __IO uint32_t DHR8RD;
 249   __IO uint32_t DOR1;
 250   __IO uint32_t DOR2;
 251   __IO uint32_t SR;
 252 } DAC_TypeDef;
 253
 254 /**
 255   * @brief Debug MCU
 256   */
 257
 258 typedef struct
 259 {
 260   __IO uint32_t IDCODE;
 261   __IO uint32_t CR;
 262 }DBGMCU_TypeDef;
 263
 264 /**
 265   * @brief DMA Controller
 266   */
 267
 268 typedef struct
 269 {
 270   __IO uint32_t CCR;
 271   __IO uint32_t CNDTR;
 272   __IO uint32_t CPAR;
 273   __IO uint32_t CMAR;
 274 } DMA_Channel_TypeDef;
 275
 276 typedef struct
 277 {
 278   __IO uint32_t ISR;
 279   __IO uint32_t IFCR;
 280 } DMA_TypeDef;
 281
 282
 283
 284 /**
 285   * @brief External Interrupt/Event Controller
 286   */
 287
 288 typedef struct
 289 {
 290   __IO uint32_t IMR;
 291   __IO uint32_t EMR;
 292   __IO uint32_t RTSR;
 293   __IO uint32_t FTSR;
 294   __IO uint32_t SWIER;
 295   __IO uint32_t PR;
 296 } EXTI_TypeDef;
 297
 298 /**
 299   * @brief FLASH Registers
 300   */
 301
 302 typedef struct
 303 {
 304   __IO uint32_t ACR;
 305   __IO uint32_t KEYR;
 306   __IO uint32_t OPTKEYR;
 307   __IO uint32_t SR;
 308   __IO uint32_t CR;
 309   __IO uint32_t AR;
 310   __IO uint32_t RESERVED;
 311   __IO uint32_t OBR;
 312   __IO uint32_t WRPR;
 313 } FLASH_TypeDef;
 314
 315 /**
 316   * @brief Option Bytes Registers
 317   */
 318
 319 typedef struct
 320 {
 321   __IO uint16_t RDP;
 322   __IO uint16_t USER;
 323   __IO uint16_t Data0;
 324   __IO uint16_t Data1;
 325   __IO uint16_t WRP0;
 326   __IO uint16_t WRP1;
 327   __IO uint16_t WRP2;
 328   __IO uint16_t WRP3;
 329 } OB_TypeDef;
 330
 331 /**
 332   * @brief General Purpose I/O
 333   */
 334
 335 typedef struct
 336 {
 337   __IO uint32_t CRL;
 338   __IO uint32_t CRH;
 339   __IO uint32_t IDR;
 340   __IO uint32_t ODR;
 341   __IO uint32_t BSRR;
 342   __IO uint32_t BRR;
 343   __IO uint32_t LCKR;
 344 } GPIO_TypeDef;
 345
 346 /**
 347   * @brief Alternate Function I/O
 348   */
 349
 350 typedef struct
 351 {
 352   __IO uint32_t EVCR;
 353   __IO uint32_t MAPR;
 354   __IO uint32_t EXTICR[4];
 355   uint32_t RESERVED0;
 356   __IO uint32_t MAPR2;
 357 } AFIO_TypeDef;
 358 /**
 359   * @brief Inter Integrated Circuit Interface
 360   */
 361
 362 typedef struct
 363 {
 364   __IO uint32_t CR1;
 365   __IO uint32_t CR2;
 366   __IO uint32_t OAR1;
 367   __IO uint32_t OAR2;
 368   __IO uint32_t DR;
 369   __IO uint32_t SR1;
 370   __IO uint32_t SR2;
 371   __IO uint32_t CCR;
 372   __IO uint32_t TRISE;
 373 } I2C_TypeDef;
 374
 375 /**
 376   * @brief Independent WATCHDOG
 377   */
 378
 379 typedef struct
 380 {
 381   __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
 382   __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
 383   __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
 384   __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
 385 } IWDG_TypeDef;
 386
 387 /**
 388   * @brief Power Control
 389   */
 390
 391 typedef struct
 392 {
 393   __IO uint32_t CR;
 394   __IO uint32_t CSR;
 395 } PWR_TypeDef;
 396
 397 /**
 398   * @brief Reset and Clock Control
 399   */
 400
 401 typedef struct
 402 {
 403   __IO uint32_t CR;
 404   __IO uint32_t CFGR;
 405   __IO uint32_t CIR;
 406   __IO uint32_t APB2RSTR;
 407   __IO uint32_t APB1RSTR;
 408   __IO uint32_t AHBENR;
 409   __IO uint32_t APB2ENR;
 410   __IO uint32_t APB1ENR;
 411   __IO uint32_t BDCR;
 412   __IO uint32_t CSR;
 413
 414
 415   uint32_t RESERVED0;
 416   __IO uint32_t CFGR2;
 417 } RCC_TypeDef;
 418
 419 /**
 420   * @brief Real-Time Clock
 421   */
 422
 423 typedef struct
 424 {
 425   __IO uint32_t CRH;
 426   __IO uint32_t CRL;
 427   __IO uint32_t PRLH;
 428   __IO uint32_t PRLL;
 429   __IO uint32_t DIVH;
 430   __IO uint32_t DIVL;
 431   __IO uint32_t CNTH;
 432   __IO uint32_t CNTL;
 433   __IO uint32_t ALRH;
 434   __IO uint32_t ALRL;
 435 } RTC_TypeDef;
 436
 437 /**
 438   * @brief SD host Interface
 439   */
 440
 441 typedef struct
 442 {
 443   __IO uint32_t POWER;
 444   __IO uint32_t CLKCR;
 445   __IO uint32_t ARG;
 446   __IO uint32_t CMD;
 447   __I uint32_t RESPCMD;
 448   __I uint32_t RESP1;
 449   __I uint32_t RESP2;
 450   __I uint32_t RESP3;
 451   __I uint32_t RESP4;
 452   __IO uint32_t DTIMER;
 453   __IO uint32_t DLEN;
 454   __IO uint32_t DCTRL;
 455   __I uint32_t DCOUNT;
 456   __I uint32_t STA;
 457   __IO uint32_t ICR;
 458   __IO uint32_t MASK;
 459   uint32_t  RESERVED0[2];
 460   __I uint32_t FIFOCNT;
 461   uint32_t  RESERVED1[13];
 462   __IO uint32_t FIFO;
 463 } SDIO_TypeDef;
 464
 465 /**
 466   * @brief Serial Peripheral Interface
 467   */
 468
 469 typedef struct
 470 {
 471   __IO uint32_t CR1;
 472   __IO uint32_t CR2;
 473   __IO uint32_t SR;
 474   __IO uint32_t DR;
 475   __IO uint32_t CRCPR;
 476   __IO uint32_t RXCRCR;
 477   __IO uint32_t TXCRCR;
 478 } SPI_TypeDef;
 479
 480 /**
 481   * @brief TIM Timers
 482   */
 483 typedef struct
 484 {
 485   __IO uint32_t CR1;             /*!< TIM control register 1,                      Address offset: 0x00 */
 486   __IO uint32_t CR2;             /*!< TIM control register 2,                      Address offset: 0x04 */
 487   __IO uint32_t SMCR;            /*!< TIM slave Mode Control register,             Address offset: 0x08 */
 488   __IO uint32_t DIER;            /*!< TIM DMA/interrupt enable register,           Address offset: 0x0C */
 489   __IO uint32_t SR;              /*!< TIM status register,                         Address offset: 0x10 */
 490   __IO uint32_t EGR;             /*!< TIM event generation register,               Address offset: 0x14 */
 491   __IO uint32_t CCMR1;           /*!< TIM  capture/compare mode register 1,        Address offset: 0x18 */
 492   __IO uint32_t CCMR2;           /*!< TIM  capture/compare mode register 2,        Address offset: 0x1C */
 493   __IO uint32_t CCER;            /*!< TIM capture/compare enable register,         Address offset: 0x20 */
 494   __IO uint32_t CNT;             /*!< TIM counter register,                        Address offset: 0x24 */
 495   __IO uint32_t PSC;             /*!< TIM prescaler register,                      Address offset: 0x28 */
 496   __IO uint32_t ARR;             /*!< TIM auto-reload register,                    Address offset: 0x2C */
 497   __IO uint32_t RCR;             /*!< TIM  repetition counter register,            Address offset: 0x30 */
 498   __IO uint32_t CCR1;            /*!< TIM capture/compare register 1,              Address offset: 0x34 */
 499   __IO uint32_t CCR2;            /*!< TIM capture/compare register 2,              Address offset: 0x38 */
 500   __IO uint32_t CCR3;            /*!< TIM capture/compare register 3,              Address offset: 0x3C */
 501   __IO uint32_t CCR4;            /*!< TIM capture/compare register 4,              Address offset: 0x40 */
 502   __IO uint32_t BDTR;            /*!< TIM break and dead-time register,            Address offset: 0x44 */
 503   __IO uint32_t DCR;             /*!< TIM DMA control register,                    Address offset: 0x48 */
 504   __IO uint32_t DMAR;            /*!< TIM DMA address for full transfer register,  Address offset: 0x4C */
 505   __IO uint32_t OR;              /*!< TIM option register,                         Address offset: 0x50 */
 506 }TIM_TypeDef;
 507
 508
 509 /**
 510   * @brief Universal Synchronous Asynchronous Receiver Transmitter
 511   */
 512
 513 typedef struct
 514 {
 515   __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
 516   __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
 517   __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
 518   __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
 519   __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
 520   __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
 521   __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
 522 } USART_TypeDef;
 523
 524
 525
 526 /**
 527   * @brief Window WATCHDOG
 528   */
 529
 530 typedef struct
 531 {
 532   __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
 533   __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
 534   __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
 535 } WWDG_TypeDef;
 536
 537 /**
 538   * @}
 539   */
 540
 541 /** @addtogroup Peripheral_memory_map
 542   * @{
 543   */
 544
 545
 546 #define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
 547 #define FLASH_BANK1_END       ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */
 548 #define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
 549 #define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
 550
 551 #define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
 552 #define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
 553
 554
 555 /*!< Peripheral memory map */
 556 #define APB1PERIPH_BASE       PERIPH_BASE
 557 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)
 558 #define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)
 559
 560 #define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
 561 #define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
 562 #define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
 563 #define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
 564 #define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
 565 #define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
 566 #define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
 567 #define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
 568 #define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
 569 #define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
 570 #define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
 571 #define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
 572 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
 573 #define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)
 574 #define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
 575 #define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
 576 #define CEC_BASE              (APB1PERIPH_BASE + 0x7800)
 577 #define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)
 578 #define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)
 579 #define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)
 580 #define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)
 581 #define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)
 582 #define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)
 583 #define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)
 584 #define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)
 585 #define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00)
 586 #define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
 587 #define USART1_BASE           (APB2PERIPH_BASE + 0x3800)
 588 #define TIM15_BASE            (APB2PERIPH_BASE + 0x4000)
 589 #define TIM16_BASE            (APB2PERIPH_BASE + 0x4400)
 590 #define TIM17_BASE            (APB2PERIPH_BASE + 0x4800)
 591
 592 #define SDIO_BASE             (PERIPH_BASE + 0x18000)
 593
 594 #define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)
 595 #define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)
 596 #define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)
 597 #define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)
 598 #define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)
 599 #define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)
 600 #define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)
 601 #define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)
 602 #define RCC_BASE              (AHBPERIPH_BASE + 0x1000)
 603 #define CRC_BASE              (AHBPERIPH_BASE + 0x3000)
 604
 605 #define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */
 606 #define OB_BASE               ((uint32_t)0x1FFFF800)    /*!< Flash Option Bytes base address */
 607
 608
 609
 610 #define DBGMCU_BASE          ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
 611
 612
 613
 614 /**
 615   * @}
 616   */
 617
 618 /** @addtogroup Peripheral_declaration
 619   * @{
 620   */
 621
 622 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
 623 #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
 624 #define TIM4                ((TIM_TypeDef *) TIM4_BASE)
 625 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
 626 #define TIM7                ((TIM_TypeDef *) TIM7_BASE)
 627 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
 628 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
 629 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
 630 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
 631 #define USART2              ((USART_TypeDef *) USART2_BASE)
 632 #define USART3              ((USART_TypeDef *) USART3_BASE)
 633 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
 634 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
 635 #define BKP                 ((BKP_TypeDef *) BKP_BASE)
 636 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
 637 #define DAC                 ((DAC_TypeDef *) DAC_BASE)
 638 #define CEC                 ((CEC_TypeDef *) CEC_BASE)
 639 #define AFIO                ((AFIO_TypeDef *) AFIO_BASE)
 640 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
 641 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
 642 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
 643 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
 644 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
 645 #define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
 646 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
 647 #define TIM1                ((TIM_TypeDef *) TIM1_BASE)
 648 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
 649 #define USART1              ((USART_TypeDef *) USART1_BASE)
 650 #define TIM15               ((TIM_TypeDef *) TIM15_BASE)
 651 #define TIM16               ((TIM_TypeDef *) TIM16_BASE)
 652 #define TIM17               ((TIM_TypeDef *) TIM17_BASE)
 653 #define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
 654 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
 655 #define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
 656 #define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
 657 #define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
 658 #define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
 659 #define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
 660 #define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
 661 #define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
 662 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
 663 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
 664 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
 665 #define OB                  ((OB_TypeDef *) OB_BASE)
 666 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
 667
 668
 669 /**
 670   * @}
 671   */
 672
 673 /** @addtogroup Exported_constants
 674   * @{
 675   */
 676
 677   /** @addtogroup Peripheral_Registers_Bits_Definition
 678   * @{
 679   */
 680
 681 /******************************************************************************/
 682 /*                         Peripheral Registers_Bits_Definition               */
 683 /******************************************************************************/
 684
 685 /******************************************************************************/
 686 /*                                                                            */
 687 /*                       CRC calculation unit (CRC)                           */
 688 /*                                                                            */
 689 /******************************************************************************/
 690
 691 /*******************  Bit definition for CRC_DR register  *********************/
 692 #define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF)        /*!< Data register bits */
 693
 694 /*******************  Bit definition for CRC_IDR register  ********************/
 695 #define  CRC_IDR_IDR                         ((uint32_t)0x000000FF)        /*!< General-purpose 8-bit data register bits */
 696
 697 /********************  Bit definition for CRC_CR register  ********************/
 698 #define  CRC_CR_RESET                        ((uint32_t)0x00000001)        /*!< RESET bit */
 699
 700 /******************************************************************************/
 701 /*                                                                            */
 702 /*                             Power Control                                  */
 703 /*                                                                            */
 704 /******************************************************************************/
 705
 706 /********************  Bit definition for PWR_CR register  ********************/
 707 #define  PWR_CR_LPDS                         ((uint32_t)0x00000001)     /*!< Low-Power Deepsleep */
 708 #define  PWR_CR_PDDS                         ((uint32_t)0x00000002)     /*!< Power Down Deepsleep */
 709 #define  PWR_CR_CWUF                         ((uint32_t)0x00000004)     /*!< Clear Wakeup Flag */
 710 #define  PWR_CR_CSBF                         ((uint32_t)0x00000008)     /*!< Clear Standby Flag */
 711 #define  PWR_CR_PVDE                         ((uint32_t)0x00000010)     /*!< Power Voltage Detector Enable */
 712
 713 #define  PWR_CR_PLS                          ((uint32_t)0x000000E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
 714 #define  PWR_CR_PLS_0                        ((uint32_t)0x00000020)     /*!< Bit 0 */
 715 #define  PWR_CR_PLS_1                        ((uint32_t)0x00000040)     /*!< Bit 1 */
 716 #define  PWR_CR_PLS_2                        ((uint32_t)0x00000080)     /*!< Bit 2 */
 717
 718 /*!< PVD level configuration */
 719 #define  PWR_CR_PLS_2V2                      ((uint32_t)0x00000000)     /*!< PVD level 2.2V */
 720 #define  PWR_CR_PLS_2V3                      ((uint32_t)0x00000020)     /*!< PVD level 2.3V */
 721 #define  PWR_CR_PLS_2V4                      ((uint32_t)0x00000040)     /*!< PVD level 2.4V */
 722 #define  PWR_CR_PLS_2V5                      ((uint32_t)0x00000060)     /*!< PVD level 2.5V */
 723 #define  PWR_CR_PLS_2V6                      ((uint32_t)0x00000080)     /*!< PVD level 2.6V */
 724 #define  PWR_CR_PLS_2V7                      ((uint32_t)0x000000A0)     /*!< PVD level 2.7V */
 725 #define  PWR_CR_PLS_2V8                      ((uint32_t)0x000000C0)     /*!< PVD level 2.8V */
 726 #define  PWR_CR_PLS_2V9                      ((uint32_t)0x000000E0)     /*!< PVD level 2.9V */
 727
 728 #define  PWR_CR_DBP                          ((uint32_t)0x00000100)     /*!< Disable Backup Domain write protection */
 729
 730
 731 /*******************  Bit definition for PWR_CSR register  ********************/
 732 #define  PWR_CSR_WUF                         ((uint32_t)0x00000001)     /*!< Wakeup Flag */
 733 #define  PWR_CSR_SBF                         ((uint32_t)0x00000002)     /*!< Standby Flag */
 734 #define  PWR_CSR_PVDO                        ((uint32_t)0x00000004)     /*!< PVD Output */
 735 #define  PWR_CSR_EWUP                        ((uint32_t)0x00000100)     /*!< Enable WKUP pin */
 736
 737 /******************************************************************************/
 738 /*                                                                            */
 739 /*                            Backup registers                                */
 740 /*                                                                            */
 741 /******************************************************************************/
 742
 743 /*******************  Bit definition for BKP_DR1 register  ********************/
 744 #define  BKP_DR1_D                           ((uint32_t)0x0000FFFF)     /*!< Backup data */
 745
 746 /*******************  Bit definition for BKP_DR2 register  ********************/
 747 #define  BKP_DR2_D                           ((uint32_t)0x0000FFFF)     /*!< Backup data */
 748
 749 /*******************  Bit definition for BKP_DR3 register  ********************/
 750 #define  BKP_DR3_D                           ((uint32_t)0x0000FFFF)     /*!< Backup data */
 751
 752 /*******************  Bit definition for BKP_DR4 register  ********************/
 753 #define  BKP_DR4_D                           ((uint32_t)0x0000FFFF)     /*!< Backup data */
 754
 755 /*******************  Bit definition for BKP_DR5 register  ********************/
 756 #define  BKP_DR5_D                           ((uint32_t)0x0000FFFF)     /*!< Backup data */
 757
 758 /*******************  Bit definition for BKP_DR6 register  ********************/
 759 #define  BKP_DR6_D                           ((uint32_t)0x0000FFFF)     /*!< Backup data */
 760
 761 /*******************  Bit definition for BKP_DR7 register  ********************/
 762 #define  BKP_DR7_D                           ((uint32_t)0x0000FFFF)     /*!< Backup data */
 763
 764 /*******************  Bit definition for BKP_DR8 register  ********************/
 765 #define  BKP_DR8_D                           ((uint32_t)0x0000FFFF)     /*!< Backup data */
 766
 767 /*******************  Bit definition for BKP_DR9 register  ********************/
 768 #define  BKP_DR9_D                           ((uint32_t)0x0000FFFF)     /*!< Backup data */
 769
 770 /*******************  Bit definition for BKP_DR10 register  *******************/
 771 #define  BKP_DR10_D                          ((uint32_t)0x0000FFFF)     /*!< Backup data */
 772
 773 #define RTC_BKP_NUMBER 10
 774
 775 /******************  Bit definition for BKP_RTCCR register  *******************/
 776 #define  BKP_RTCCR_CAL                       ((uint32_t)0x0000007F)     /*!< Calibration value */
 777 #define  BKP_RTCCR_CCO                       ((uint32_t)0x00000080)     /*!< Calibration Clock Output */
 778 #define  BKP_RTCCR_ASOE                      ((uint32_t)0x00000100)     /*!< Alarm or Second Output Enable */
 779 #define  BKP_RTCCR_ASOS                      ((uint32_t)0x00000200)     /*!< Alarm or Second Output Selection */
 780
 781 /********************  Bit definition for BKP_CR register  ********************/
 782 #define  BKP_CR_TPE                          ((uint32_t)0x00000001)     /*!< TAMPER pin enable */
 783 #define  BKP_CR_TPAL                         ((uint32_t)0x00000002)     /*!< TAMPER pin active level */
 784
 785 /*******************  Bit definition for BKP_CSR register  ********************/
 786 #define  BKP_CSR_CTE                         ((uint32_t)0x00000001)     /*!< Clear Tamper event */
 787 #define  BKP_CSR_CTI                         ((uint32_t)0x00000002)     /*!< Clear Tamper Interrupt */
 788 #define  BKP_CSR_TPIE                        ((uint32_t)0x00000004)     /*!< TAMPER Pin interrupt enable */
 789 #define  BKP_CSR_TEF                         ((uint32_t)0x00000100)     /*!< Tamper Event Flag */
 790 #define  BKP_CSR_TIF                         ((uint32_t)0x00000200)     /*!< Tamper Interrupt Flag */
 791
 792 /******************************************************************************/
 793 /*                                                                            */
 794 /*                         Reset and Clock Control                            */
 795 /*                                                                            */
 796 /******************************************************************************/
 797
 798 /********************  Bit definition for RCC_CR register  ********************/
 799 #define  RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
 800 #define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */
 801 #define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)        /*!< Internal High Speed clock trimming */
 802 #define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)        /*!< Internal High Speed clock Calibration */
 803 #define  RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */
 804 #define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */
 805 #define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */
 806 #define  RCC_CR_CSSON                        ((uint32_t)0x00080000)        /*!< Clock Security System enable */
 807 #define  RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */
 808 #define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */
 809
 810
 811 /*******************  Bit definition for RCC_CFGR register  *******************/
 812 /*!< SW configuration */
 813 #define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
 814 #define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
 815 #define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
 816
 817 #define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
 818 #define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
 819 #define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
 820
 821 /*!< SWS configuration */
 822 #define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
 823 #define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
 824 #define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
 825
 826 #define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
 827 #define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
 828 #define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
 829
 830 /*!< HPRE configuration */
 831 #define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
 832 #define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
 833 #define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
 834 #define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
 835 #define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
 836
 837 #define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
 838 #define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
 839 #define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
 840 #define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
 841 #define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
 842 #define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
 843 #define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
 844 #define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
 845 #define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
 846
 847 /*!< PPRE1 configuration */
 848 #define  RCC_CFGR_PPRE1                      ((uint32_t)0x00000700)        /*!< PRE1[2:0] bits (APB1 prescaler) */
 849 #define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */
 850 #define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */
 851 #define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00000400)        /*!< Bit 2 */
 852
 853 #define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
 854 #define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
 855 #define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
 856 #define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
 857 #define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
 858
 859 /*!< PPRE2 configuration */
 860 #define  RCC_CFGR_PPRE2                      ((uint32_t)0x00003800)        /*!< PRE2[2:0] bits (APB2 prescaler) */
 861 #define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00000800)        /*!< Bit 0 */
 862 #define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00001000)        /*!< Bit 1 */
 863 #define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00002000)        /*!< Bit 2 */
 864
 865 #define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
 866 #define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00002000)        /*!< HCLK divided by 2 */
 867 #define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x00002800)        /*!< HCLK divided by 4 */
 868 #define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x00003000)        /*!< HCLK divided by 8 */
 869 #define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x00003800)        /*!< HCLK divided by 16 */
 870
 871 /*!< ADCPPRE configuration */
 872 #define  RCC_CFGR_ADCPRE                     ((uint32_t)0x0000C000)        /*!< ADCPRE[1:0] bits (ADC prescaler) */
 873 #define  RCC_CFGR_ADCPRE_0                   ((uint32_t)0x00004000)        /*!< Bit 0 */
 874 #define  RCC_CFGR_ADCPRE_1                   ((uint32_t)0x00008000)        /*!< Bit 1 */
 875
 876 #define  RCC_CFGR_ADCPRE_DIV2                ((uint32_t)0x00000000)        /*!< PCLK2 divided by 2 */
 877 #define  RCC_CFGR_ADCPRE_DIV4                ((uint32_t)0x00004000)        /*!< PCLK2 divided by 4 */
 878 #define  RCC_CFGR_ADCPRE_DIV6                ((uint32_t)0x00008000)        /*!< PCLK2 divided by 6 */
 879 #define  RCC_CFGR_ADCPRE_DIV8                ((uint32_t)0x0000C000)        /*!< PCLK2 divided by 8 */
 880
 881 #define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00010000)        /*!< PLL entry clock source */
 882
 883 #define  RCC_CFGR_PLLXTPRE                   ((uint32_t)0x00020000)        /*!< HSE divider for PLL entry */
 884
 885 /*!< PLLMUL configuration */
 886 #define  RCC_CFGR_PLLMULL                    ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
 887 #define  RCC_CFGR_PLLMULL_0                  ((uint32_t)0x00040000)        /*!< Bit 0 */
 888 #define  RCC_CFGR_PLLMULL_1                  ((uint32_t)0x00080000)        /*!< Bit 1 */
 889 #define  RCC_CFGR_PLLMULL_2                  ((uint32_t)0x00100000)        /*!< Bit 2 */
 890 #define  RCC_CFGR_PLLMULL_3                  ((uint32_t)0x00200000)        /*!< Bit 3 */
 891
 892  #define  RCC_CFGR_PLLXTPRE_PREDIV1          ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */
 893  #define  RCC_CFGR_PLLXTPRE_PREDIV1_DIV2     ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */
 894
 895  #define  RCC_CFGR_PLLMULL2                  ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
 896  #define  RCC_CFGR_PLLMULL3                  ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
 897  #define  RCC_CFGR_PLLMULL4                  ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
 898  #define  RCC_CFGR_PLLMULL5                  ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
 899  #define  RCC_CFGR_PLLMULL6                  ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
 900  #define  RCC_CFGR_PLLMULL7                  ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
 901  #define  RCC_CFGR_PLLMULL8                  ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
 902  #define  RCC_CFGR_PLLMULL9                  ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
 903  #define  RCC_CFGR_PLLMULL10                 ((uint32_t)0x00200000)        /*!< PLL input clock10 */
 904  #define  RCC_CFGR_PLLMULL11                 ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
 905  #define  RCC_CFGR_PLLMULL12                 ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
 906  #define  RCC_CFGR_PLLMULL13                 ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
 907  #define  RCC_CFGR_PLLMULL14                 ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
 908  #define  RCC_CFGR_PLLMULL15                 ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
 909  #define  RCC_CFGR_PLLMULL16                 ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
 910
 911 /*!< MCO configuration */
 912  #define  RCC_CFGR_MCO                       ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
 913  #define  RCC_CFGR_MCO_0                     ((uint32_t)0x01000000)        /*!< Bit 0 */
 914  #define  RCC_CFGR_MCO_1                     ((uint32_t)0x02000000)        /*!< Bit 1 */
 915  #define  RCC_CFGR_MCO_2                     ((uint32_t)0x04000000)        /*!< Bit 2 */
 916
 917  #define  RCC_CFGR_MCO_NOCLOCK               ((uint32_t)0x00000000)        /*!< No clock */
 918  #define  RCC_CFGR_MCO_SYSCLK                ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
 919  #define  RCC_CFGR_MCO_HSI                   ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
 920  #define  RCC_CFGR_MCO_HSE                   ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
 921  #define  RCC_CFGR_MCO_PLLCLK_DIV2           ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */
 922
 923 /*!<******************  Bit definition for RCC_CIR register  ********************/
 924 #define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
 925 #define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
 926 #define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
 927 #define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
 928 #define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
 929 #define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
 930 #define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
 931 #define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
 932 #define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
 933 #define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
 934 #define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
 935 #define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
 936 #define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
 937 #define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
 938 #define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
 939 #define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
 940 #define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
 941
 942
 943 /*****************  Bit definition for RCC_APB2RSTR register  *****************/
 944 #define  RCC_APB2RSTR_AFIORST                ((uint32_t)0x00000001)        /*!< Alternate Function I/O reset */
 945 #define  RCC_APB2RSTR_IOPARST                ((uint32_t)0x00000004)        /*!< I/O port A reset */
 946 #define  RCC_APB2RSTR_IOPBRST                ((uint32_t)0x00000008)        /*!< I/O port B reset */
 947 #define  RCC_APB2RSTR_IOPCRST                ((uint32_t)0x00000010)        /*!< I/O port C reset */
 948 #define  RCC_APB2RSTR_IOPDRST                ((uint32_t)0x00000020)        /*!< I/O port D reset */
 949 #define  RCC_APB2RSTR_ADC1RST                ((uint32_t)0x00000200)        /*!< ADC 1 interface reset */
 950
 951
 952 #define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000800)        /*!< TIM1 Timer reset */
 953 #define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI 1 reset */
 954 #define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 reset */
 955
 956 #define  RCC_APB2RSTR_TIM15RST               ((uint32_t)0x00010000)        /*!< TIM15 Timer reset */
 957 #define  RCC_APB2RSTR_TIM16RST               ((uint32_t)0x00020000)        /*!< TIM16 Timer reset */
 958 #define  RCC_APB2RSTR_TIM17RST               ((uint32_t)0x00040000)        /*!< TIM17 Timer reset */
 959
 960 #define  RCC_APB2RSTR_IOPERST               ((uint32_t)0x00000040)        /*!< I/O port E reset */
 961
 962
 963
 964
 965 /*****************  Bit definition for RCC_APB1RSTR register  *****************/
 966 #define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 reset */
 967 #define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 reset */
 968 #define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog reset */
 969 #define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 reset */
 970 #define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 reset */
 971
 972
 973 #define  RCC_APB1RSTR_BKPRST                 ((uint32_t)0x08000000)        /*!< Backup interface reset */
 974 #define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< Power interface reset */
 975
 976 #define  RCC_APB1RSTR_TIM4RST               ((uint32_t)0x00000004)        /*!< Timer 4 reset */
 977 #define  RCC_APB1RSTR_SPI2RST               ((uint32_t)0x00004000)        /*!< SPI 2 reset */
 978 #define  RCC_APB1RSTR_USART3RST             ((uint32_t)0x00040000)        /*!< USART 3 reset */
 979 #define  RCC_APB1RSTR_I2C2RST               ((uint32_t)0x00400000)        /*!< I2C 2 reset */
 980
 981
 982
 983 #define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 reset */
 984 #define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 reset */
 985 #define  RCC_APB1RSTR_CECRST                 ((uint32_t)0x40000000)        /*!< CEC interface reset */
 986
 987
 988
 989 #define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC interface reset */
 990
 991 /******************  Bit definition for RCC_AHBENR register  ******************/
 992 #define  RCC_AHBENR_DMA1EN                   ((uint32_t)0x00000001)            /*!< DMA1 clock enable */
 993 #define  RCC_AHBENR_SRAMEN                   ((uint32_t)0x00000004)            /*!< SRAM interface clock enable */
 994 #define  RCC_AHBENR_FLITFEN                  ((uint32_t)0x00000010)            /*!< FLITF clock enable */
 995 #define  RCC_AHBENR_CRCEN                    ((uint32_t)0x00000040)            /*!< CRC clock enable */
 996
 997
 998
 999
1000 /******************  Bit definition for RCC_APB2ENR register  *****************/
1001 #define  RCC_APB2ENR_AFIOEN                  ((uint32_t)0x00000001)         /*!< Alternate Function I/O clock enable */
1002 #define  RCC_APB2ENR_IOPAEN                  ((uint32_t)0x00000004)         /*!< I/O port A clock enable */
1003 #define  RCC_APB2ENR_IOPBEN                  ((uint32_t)0x00000008)         /*!< I/O port B clock enable */
1004 #define  RCC_APB2ENR_IOPCEN                  ((uint32_t)0x00000010)         /*!< I/O port C clock enable */
1005 #define  RCC_APB2ENR_IOPDEN                  ((uint32_t)0x00000020)         /*!< I/O port D clock enable */
1006 #define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000200)         /*!< ADC 1 interface clock enable */
1007
1008
1009 #define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000800)         /*!< TIM1 Timer clock enable */
1010 #define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)         /*!< SPI 1 clock enable */
1011 #define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)         /*!< USART1 clock enable */
1012
1013 #define  RCC_APB2ENR_TIM15EN                 ((uint32_t)0x00010000)         /*!< TIM15 Timer clock enable */
1014 #define  RCC_APB2ENR_TIM16EN                 ((uint32_t)0x00020000)         /*!< TIM16 Timer clock enable */
1015 #define  RCC_APB2ENR_TIM17EN                 ((uint32_t)0x00040000)         /*!< TIM17 Timer clock enable */
1016
1017 #define  RCC_APB2ENR_IOPEEN                 ((uint32_t)0x00000040)         /*!< I/O port E clock enable */
1018
1019
1020
1021
1022 /*****************  Bit definition for RCC_APB1ENR register  ******************/
1023 #define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enabled*/
1024 #define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
1025 #define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
1026 #define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART 2 clock enable */
1027 #define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C 1 clock enable */
1028
1029
1030 #define  RCC_APB1ENR_BKPEN                   ((uint32_t)0x08000000)        /*!< Backup interface clock enable */
1031 #define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< Power interface clock enable */
1032
1033 #define  RCC_APB1ENR_TIM4EN                 ((uint32_t)0x00000004)        /*!< Timer 4 clock enable */
1034 #define  RCC_APB1ENR_SPI2EN                 ((uint32_t)0x00004000)        /*!< SPI 2 clock enable */
1035 #define  RCC_APB1ENR_USART3EN               ((uint32_t)0x00040000)        /*!< USART 3 clock enable */
1036 #define  RCC_APB1ENR_I2C2EN                 ((uint32_t)0x00400000)        /*!< I2C 2 clock enable */
1037
1038
1039
1040 #define  RCC_APB1ENR_TIM6EN                 ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
1041 #define  RCC_APB1ENR_TIM7EN                 ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
1042 #define  RCC_APB1ENR_CECEN                  ((uint32_t)0x40000000)        /*!< CEC interface clock enable */
1043
1044
1045
1046 #define  RCC_APB1ENR_DACEN                  ((uint32_t)0x20000000)        /*!< DAC interface clock enable */
1047
1048 /*******************  Bit definition for RCC_BDCR register  *******************/
1049 #define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)        /*!< External Low Speed oscillator enable */
1050 #define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)        /*!< External Low Speed oscillator Ready */
1051 #define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)        /*!< External Low Speed oscillator Bypass */
1052
1053 #define  RCC_BDCR_RTCSEL                     ((uint32_t)0x00000300)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
1054 #define  RCC_BDCR_RTCSEL_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
1055 #define  RCC_BDCR_RTCSEL_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
1056
1057 /*!< RTC congiguration */
1058 #define  RCC_BDCR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
1059 #define  RCC_BDCR_RTCSEL_LSE                 ((uint32_t)0x00000100)        /*!< LSE oscillator clock used as RTC clock */
1060 #define  RCC_BDCR_RTCSEL_LSI                 ((uint32_t)0x00000200)        /*!< LSI oscillator clock used as RTC clock */
1061 #define  RCC_BDCR_RTCSEL_HSE                 ((uint32_t)0x00000300)        /*!< HSE oscillator clock divided by 128 used as RTC clock */
1062
1063 #define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)        /*!< RTC clock enable */
1064 #define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)        /*!< Backup domain software reset  */
1065
1066 /*******************  Bit definition for RCC_CSR register  ********************/
1067 #define  RCC_CSR_LSION                       ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
1068 #define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
1069 #define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)        /*!< Remove reset flag */
1070 #define  RCC_CSR_PINRSTF                     ((uint32_t)0x04000000)        /*!< PIN reset flag */
1071 #define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
1072 #define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)        /*!< Software Reset flag */
1073 #define  RCC_CSR_IWDGRSTF                    ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
1074 #define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
1075 #define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
1076
1077
1078 /*******************  Bit definition for RCC_CFGR2 register  ******************/
1079 /*!< PREDIV1 configuration */
1080  #define  RCC_CFGR2_PREDIV1                  ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */
1081  #define  RCC_CFGR2_PREDIV1_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
1082  #define  RCC_CFGR2_PREDIV1_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
1083  #define  RCC_CFGR2_PREDIV1_2                ((uint32_t)0x00000004)        /*!< Bit 2 */
1084  #define  RCC_CFGR2_PREDIV1_3                ((uint32_t)0x00000008)        /*!< Bit 3 */
1085
1086  #define  RCC_CFGR2_PREDIV1_DIV1             ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */
1087  #define  RCC_CFGR2_PREDIV1_DIV2             ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */
1088  #define  RCC_CFGR2_PREDIV1_DIV3             ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */
1089  #define  RCC_CFGR2_PREDIV1_DIV4             ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */
1090  #define  RCC_CFGR2_PREDIV1_DIV5             ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */
1091  #define  RCC_CFGR2_PREDIV1_DIV6             ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */
1092  #define  RCC_CFGR2_PREDIV1_DIV7             ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */
1093  #define  RCC_CFGR2_PREDIV1_DIV8             ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */
1094  #define  RCC_CFGR2_PREDIV1_DIV9             ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */
1095  #define  RCC_CFGR2_PREDIV1_DIV10            ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */
1096  #define  RCC_CFGR2_PREDIV1_DIV11            ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */
1097  #define  RCC_CFGR2_PREDIV1_DIV12            ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */
1098  #define  RCC_CFGR2_PREDIV1_DIV13            ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */
1099  #define  RCC_CFGR2_PREDIV1_DIV14            ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */
1100  #define  RCC_CFGR2_PREDIV1_DIV15            ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */
1101  #define  RCC_CFGR2_PREDIV1_DIV16            ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */
1102
1103 /******************************************************************************/
1104 /*                                                                            */
1105 /*                General Purpose and Alternate Function I/O                  */
1106 /*                                                                            */
1107 /******************************************************************************/
1108
1109 /*******************  Bit definition for GPIO_CRL register  *******************/
1110 #define  GPIO_CRL_MODE                       ((uint32_t)0x33333333)        /*!< Port x mode bits */
1111
1112 #define  GPIO_CRL_MODE0                      ((uint32_t)0x00000003)        /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
1113 #define  GPIO_CRL_MODE0_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
1114 #define  GPIO_CRL_MODE0_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
1115
1116 #define  GPIO_CRL_MODE1                      ((uint32_t)0x00000030)        /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
1117 #define  GPIO_CRL_MODE1_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
1118 #define  GPIO_CRL_MODE1_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
1119
1120 #define  GPIO_CRL_MODE2                      ((uint32_t)0x00000300)        /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
1121 #define  GPIO_CRL_MODE2_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */
1122 #define  GPIO_CRL_MODE2_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */
1123
1124 #define  GPIO_CRL_MODE3                      ((uint32_t)0x00003000)        /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
1125 #define  GPIO_CRL_MODE3_0                    ((uint32_t)0x00001000)        /*!< Bit 0 */
1126 #define  GPIO_CRL_MODE3_1                    ((uint32_t)0x00002000)        /*!< Bit 1 */
1127
1128 #define  GPIO_CRL_MODE4                      ((uint32_t)0x00030000)        /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
1129 #define  GPIO_CRL_MODE4_0                    ((uint32_t)0x00010000)        /*!< Bit 0 */
1130 #define  GPIO_CRL_MODE4_1                    ((uint32_t)0x00020000)        /*!< Bit 1 */
1131
1132 #define  GPIO_CRL_MODE5                      ((uint32_t)0x00300000)        /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
1133 #define  GPIO_CRL_MODE5_0                    ((uint32_t)0x00100000)        /*!< Bit 0 */
1134 #define  GPIO_CRL_MODE5_1                    ((uint32_t)0x00200000)        /*!< Bit 1 */
1135
1136 #define  GPIO_CRL_MODE6                      ((uint32_t)0x03000000)        /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
1137 #define  GPIO_CRL_MODE6_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
1138 #define  GPIO_CRL_MODE6_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
1139
1140 #define  GPIO_CRL_MODE7                      ((uint32_t)0x30000000)        /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
1141 #define  GPIO_CRL_MODE7_0                    ((uint32_t)0x10000000)        /*!< Bit 0 */
1142 #define  GPIO_CRL_MODE7_1                    ((uint32_t)0x20000000)        /*!< Bit 1 */
1143
1144 #define  GPIO_CRL_CNF                        ((uint32_t)0xCCCCCCCC)        /*!< Port x configuration bits */
1145
1146 #define  GPIO_CRL_CNF0                       ((uint32_t)0x0000000C)        /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
1147 #define  GPIO_CRL_CNF0_0                     ((uint32_t)0x00000004)        /*!< Bit 0 */
1148 #define  GPIO_CRL_CNF0_1                     ((uint32_t)0x00000008)        /*!< Bit 1 */
1149
1150 #define  GPIO_CRL_CNF1                       ((uint32_t)0x000000C0)        /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
1151 #define  GPIO_CRL_CNF1_0                     ((uint32_t)0x00000040)        /*!< Bit 0 */
1152 #define  GPIO_CRL_CNF1_1                     ((uint32_t)0x00000080)        /*!< Bit 1 */
1153
1154 #define  GPIO_CRL_CNF2                       ((uint32_t)0x00000C00)        /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
1155 #define  GPIO_CRL_CNF2_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
1156 #define  GPIO_CRL_CNF2_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
1157
1158 #define  GPIO_CRL_CNF3                       ((uint32_t)0x0000C000)        /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
1159 #define  GPIO_CRL_CNF3_0                     ((uint32_t)0x00004000)        /*!< Bit 0 */
1160 #define  GPIO_CRL_CNF3_1                     ((uint32_t)0x00008000)        /*!< Bit 1 */
1161
1162 #define  GPIO_CRL_CNF4                       ((uint32_t)0x000C0000)        /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
1163 #define  GPIO_CRL_CNF4_0                     ((uint32_t)0x00040000)        /*!< Bit 0 */
1164 #define  GPIO_CRL_CNF4_1                     ((uint32_t)0x00080000)        /*!< Bit 1 */
1165
1166 #define  GPIO_CRL_CNF5                       ((uint32_t)0x00C00000)        /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
1167 #define  GPIO_CRL_CNF5_0                     ((uint32_t)0x00400000)        /*!< Bit 0 */
1168 #define  GPIO_CRL_CNF5_1                     ((uint32_t)0x00800000)        /*!< Bit 1 */
1169
1170 #define  GPIO_CRL_CNF6                       ((uint32_t)0x0C000000)        /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
1171 #define  GPIO_CRL_CNF6_0                     ((uint32_t)0x04000000)        /*!< Bit 0 */
1172 #define  GPIO_CRL_CNF6_1                     ((uint32_t)0x08000000)        /*!< Bit 1 */
1173
1174 #define  GPIO_CRL_CNF7                       ((uint32_t)0xC0000000)        /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
1175 #define  GPIO_CRL_CNF7_0                     ((uint32_t)0x40000000)        /*!< Bit 0 */
1176 #define  GPIO_CRL_CNF7_1                     ((uint32_t)0x80000000)        /*!< Bit 1 */
1177
1178 /*******************  Bit definition for GPIO_CRH register  *******************/
1179 #define  GPIO_CRH_MODE                       ((uint32_t)0x33333333)        /*!< Port x mode bits */
1180
1181 #define  GPIO_CRH_MODE8                      ((uint32_t)0x00000003)        /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
1182 #define  GPIO_CRH_MODE8_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
1183 #define  GPIO_CRH_MODE8_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
1184
1185 #define  GPIO_CRH_MODE9                      ((uint32_t)0x00000030)        /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
1186 #define  GPIO_CRH_MODE9_0                    ((uint32_t)0x00000010)        /*!< Bit 0 */
1187 #define  GPIO_CRH_MODE9_1                    ((uint32_t)0x00000020)        /*!< Bit 1 */
1188
1189 #define  GPIO_CRH_MODE10                     ((uint32_t)0x00000300)        /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
1190 #define  GPIO_CRH_MODE10_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
1191 #define  GPIO_CRH_MODE10_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
1192
1193 #define  GPIO_CRH_MODE11                     ((uint32_t)0x00003000)        /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
1194 #define  GPIO_CRH_MODE11_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
1195 #define  GPIO_CRH_MODE11_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
1196
1197 #define  GPIO_CRH_MODE12                     ((uint32_t)0x00030000)        /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
1198 #define  GPIO_CRH_MODE12_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */
1199 #define  GPIO_CRH_MODE12_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */
1200
1201 #define  GPIO_CRH_MODE13                     ((uint32_t)0x00300000)        /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
1202 #define  GPIO_CRH_MODE13_0                   ((uint32_t)0x00100000)        /*!< Bit 0 */
1203 #define  GPIO_CRH_MODE13_1                   ((uint32_t)0x00200000)        /*!< Bit 1 */
1204
1205 #define  GPIO_CRH_MODE14                     ((uint32_t)0x03000000)        /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
1206 #define  GPIO_CRH_MODE14_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
1207 #define  GPIO_CRH_MODE14_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
1208
1209 #define  GPIO_CRH_MODE15                     ((uint32_t)0x30000000)        /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
1210 #define  GPIO_CRH_MODE15_0                   ((uint32_t)0x10000000)        /*!< Bit 0 */
1211 #define  GPIO_CRH_MODE15_1                   ((uint32_t)0x20000000)        /*!< Bit 1 */
1212
1213 #define  GPIO_CRH_CNF                        ((uint32_t)0xCCCCCCCC)        /*!< Port x configuration bits */
1214
1215 #define  GPIO_CRH_CNF8                       ((uint32_t)0x0000000C)        /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
1216 #define  GPIO_CRH_CNF8_0                     ((uint32_t)0x00000004)        /*!< Bit 0 */
1217 #define  GPIO_CRH_CNF8_1                     ((uint32_t)0x00000008)        /*!< Bit 1 */
1218
1219 #define  GPIO_CRH_CNF9                       ((uint32_t)0x000000C0)        /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
1220 #define  GPIO_CRH_CNF9_0                     ((uint32_t)0x00000040)        /*!< Bit 0 */
1221 #define  GPIO_CRH_CNF9_1                     ((uint32_t)0x00000080)        /*!< Bit 1 */
1222
1223 #define  GPIO_CRH_CNF10                      ((uint32_t)0x00000C00)        /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
1224 #define  GPIO_CRH_CNF10_0                    ((uint32_t)0x00000400)        /*!< Bit 0 */
1225 #define  GPIO_CRH_CNF10_1                    ((uint32_t)0x00000800)        /*!< Bit 1 */
1226
1227 #define  GPIO_CRH_CNF11                      ((uint32_t)0x0000C000)        /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
1228 #define  GPIO_CRH_CNF11_0                    ((uint32_t)0x00004000)        /*!< Bit 0 */
1229 #define  GPIO_CRH_CNF11_1                    ((uint32_t)0x00008000)        /*!< Bit 1 */
1230
1231 #define  GPIO_CRH_CNF12                      ((uint32_t)0x000C0000)        /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
1232 #define  GPIO_CRH_CNF12_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
1233 #define  GPIO_CRH_CNF12_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
1234
1235 #define  GPIO_CRH_CNF13                      ((uint32_t)0x00C00000)        /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
1236 #define  GPIO_CRH_CNF13_0                    ((uint32_t)0x00400000)        /*!< Bit 0 */
1237 #define  GPIO_CRH_CNF13_1                    ((uint32_t)0x00800000)        /*!< Bit 1 */
1238
1239 #define  GPIO_CRH_CNF14                      ((uint32_t)0x0C000000)        /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
1240 #define  GPIO_CRH_CNF14_0                    ((uint32_t)0x04000000)        /*!< Bit 0 */
1241 #define  GPIO_CRH_CNF14_1                    ((uint32_t)0x08000000)        /*!< Bit 1 */
1242
1243 #define  GPIO_CRH_CNF15                      ((uint32_t)0xC0000000)        /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
1244 #define  GPIO_CRH_CNF15_0                    ((uint32_t)0x40000000)        /*!< Bit 0 */
1245 #define  GPIO_CRH_CNF15_1                    ((uint32_t)0x80000000)        /*!< Bit 1 */
1246
1247 /*!<******************  Bit definition for GPIO_IDR register  *******************/
1248 #define GPIO_IDR_IDR0                        ((uint32_t)0x0001)            /*!< Port input data, bit 0 */
1249 #define GPIO_IDR_IDR1                        ((uint32_t)0x0002)            /*!< Port input data, bit 1 */
1250 #define GPIO_IDR_IDR2                        ((uint32_t)0x0004)            /*!< Port input data, bit 2 */
1251 #define GPIO_IDR_IDR3                        ((uint32_t)0x0008)            /*!< Port input data, bit 3 */
1252 #define GPIO_IDR_IDR4                        ((uint32_t)0x0010)            /*!< Port input data, bit 4 */
1253 #define GPIO_IDR_IDR5                        ((uint32_t)0x0020)            /*!< Port input data, bit 5 */
1254 #define GPIO_IDR_IDR6                        ((uint32_t)0x0040)            /*!< Port input data, bit 6 */
1255 #define GPIO_IDR_IDR7                        ((uint32_t)0x0080)            /*!< Port input data, bit 7 */
1256 #define GPIO_IDR_IDR8                        ((uint32_t)0x0100)            /*!< Port input data, bit 8 */
1257 #define GPIO_IDR_IDR9                        ((uint32_t)0x0200)            /*!< Port input data, bit 9 */
1258 #define GPIO_IDR_IDR10                       ((uint32_t)0x0400)            /*!< Port input data, bit 10 */
1259 #define GPIO_IDR_IDR11                       ((uint32_t)0x0800)            /*!< Port input data, bit 11 */
1260 #define GPIO_IDR_IDR12                       ((uint32_t)0x1000)            /*!< Port input data, bit 12 */
1261 #define GPIO_IDR_IDR13                       ((uint32_t)0x2000)            /*!< Port input data, bit 13 */
1262 #define GPIO_IDR_IDR14                       ((uint32_t)0x4000)            /*!< Port input data, bit 14 */
1263 #define GPIO_IDR_IDR15                       ((uint32_t)0x8000)            /*!< Port input data, bit 15 */
1264
1265 /*******************  Bit definition for GPIO_ODR register  *******************/
1266 #define GPIO_ODR_ODR0                        ((uint32_t)0x0001)            /*!< Port output data, bit 0 */
1267 #define GPIO_ODR_ODR1                        ((uint32_t)0x0002)            /*!< Port output data, bit 1 */
1268 #define GPIO_ODR_ODR2                        ((uint32_t)0x0004)            /*!< Port output data, bit 2 */
1269 #define GPIO_ODR_ODR3                        ((uint32_t)0x0008)            /*!< Port output data, bit 3 */
1270 #define GPIO_ODR_ODR4                        ((uint32_t)0x0010)            /*!< Port output data, bit 4 */
1271 #define GPIO_ODR_ODR5                        ((uint32_t)0x0020)            /*!< Port output data, bit 5 */
1272 #define GPIO_ODR_ODR6                        ((uint32_t)0x0040)            /*!< Port output data, bit 6 */
1273 #define GPIO_ODR_ODR7                        ((uint32_t)0x0080)            /*!< Port output data, bit 7 */
1274 #define GPIO_ODR_ODR8                        ((uint32_t)0x0100)            /*!< Port output data, bit 8 */
1275 #define GPIO_ODR_ODR9                        ((uint32_t)0x0200)            /*!< Port output data, bit 9 */
1276 #define GPIO_ODR_ODR10                       ((uint32_t)0x0400)            /*!< Port output data, bit 10 */
1277 #define GPIO_ODR_ODR11                       ((uint32_t)0x0800)            /*!< Port output data, bit 11 */
1278 #define GPIO_ODR_ODR12                       ((uint32_t)0x1000)            /*!< Port output data, bit 12 */
1279 #define GPIO_ODR_ODR13                       ((uint32_t)0x2000)            /*!< Port output data, bit 13 */
1280 #define GPIO_ODR_ODR14                       ((uint32_t)0x4000)            /*!< Port output data, bit 14 */
1281 #define GPIO_ODR_ODR15                       ((uint32_t)0x8000)            /*!< Port output data, bit 15 */
1282
1283 /******************  Bit definition for GPIO_BSRR register  *******************/
1284 #define GPIO_BSRR_BS0                        ((uint32_t)0x00000001)        /*!< Port x Set bit 0 */
1285 #define GPIO_BSRR_BS1                        ((uint32_t)0x00000002)        /*!< Port x Set bit 1 */
1286 #define GPIO_BSRR_BS2                        ((uint32_t)0x00000004)        /*!< Port x Set bit 2 */
1287 #define GPIO_BSRR_BS3                        ((uint32_t)0x00000008)        /*!< Port x Set bit 3 */
1288 #define GPIO_BSRR_BS4                        ((uint32_t)0x00000010)        /*!< Port x Set bit 4 */
1289 #define GPIO_BSRR_BS5                        ((uint32_t)0x00000020)        /*!< Port x Set bit 5 */
1290 #define GPIO_BSRR_BS6                        ((uint32_t)0x00000040)        /*!< Port x Set bit 6 */
1291 #define GPIO_BSRR_BS7                        ((uint32_t)0x00000080)        /*!< Port x Set bit 7 */
1292 #define GPIO_BSRR_BS8                        ((uint32_t)0x00000100)        /*!< Port x Set bit 8 */
1293 #define GPIO_BSRR_BS9                        ((uint32_t)0x00000200)        /*!< Port x Set bit 9 */
1294 #define GPIO_BSRR_BS10                       ((uint32_t)0x00000400)        /*!< Port x Set bit 10 */
1295 #define GPIO_BSRR_BS11                       ((uint32_t)0x00000800)        /*!< Port x Set bit 11 */
1296 #define GPIO_BSRR_BS12                       ((uint32_t)0x00001000)        /*!< Port x Set bit 12 */
1297 #define GPIO_BSRR_BS13                       ((uint32_t)0x00002000)        /*!< Port x Set bit 13 */
1298 #define GPIO_BSRR_BS14                       ((uint32_t)0x00004000)        /*!< Port x Set bit 14 */
1299 #define GPIO_BSRR_BS15                       ((uint32_t)0x00008000)        /*!< Port x Set bit 15 */
1300
1301 #define GPIO_BSRR_BR0                        ((uint32_t)0x00010000)        /*!< Port x Reset bit 0 */
1302 #define GPIO_BSRR_BR1                        ((uint32_t)0x00020000)        /*!< Port x Reset bit 1 */
1303 #define GPIO_BSRR_BR2                        ((uint32_t)0x00040000)        /*!< Port x Reset bit 2 */
1304 #define GPIO_BSRR_BR3                        ((uint32_t)0x00080000)        /*!< Port x Reset bit 3 */
1305 #define GPIO_BSRR_BR4                        ((uint32_t)0x00100000)        /*!< Port x Reset bit 4 */
1306 #define GPIO_BSRR_BR5                        ((uint32_t)0x00200000)        /*!< Port x Reset bit 5 */
1307 #define GPIO_BSRR_BR6                        ((uint32_t)0x00400000)        /*!< Port x Reset bit 6 */
1308 #define GPIO_BSRR_BR7                        ((uint32_t)0x00800000)        /*!< Port x Reset bit 7 */
1309 #define GPIO_BSRR_BR8                        ((uint32_t)0x01000000)        /*!< Port x Reset bit 8 */
1310 #define GPIO_BSRR_BR9                        ((uint32_t)0x02000000)        /*!< Port x Reset bit 9 */
1311 #define GPIO_BSRR_BR10                       ((uint32_t)0x04000000)        /*!< Port x Reset bit 10 */
1312 #define GPIO_BSRR_BR11                       ((uint32_t)0x08000000)        /*!< Port x Reset bit 11 */
1313 #define GPIO_BSRR_BR12                       ((uint32_t)0x10000000)        /*!< Port x Reset bit 12 */
1314 #define GPIO_BSRR_BR13                       ((uint32_t)0x20000000)        /*!< Port x Reset bit 13 */
1315 #define GPIO_BSRR_BR14                       ((uint32_t)0x40000000)        /*!< Port x Reset bit 14 */
1316 #define GPIO_BSRR_BR15                       ((uint32_t)0x80000000)        /*!< Port x Reset bit 15 */
1317
1318 /*******************  Bit definition for GPIO_BRR register  *******************/
1319 #define GPIO_BRR_BR0                         ((uint32_t)0x0001)            /*!< Port x Reset bit 0 */
1320 #define GPIO_BRR_BR1                         ((uint32_t)0x0002)            /*!< Port x Reset bit 1 */
1321 #define GPIO_BRR_BR2                         ((uint32_t)0x0004)            /*!< Port x Reset bit 2 */
1322 #define GPIO_BRR_BR3                         ((uint32_t)0x0008)            /*!< Port x Reset bit 3 */
1323 #define GPIO_BRR_BR4                         ((uint32_t)0x0010)            /*!< Port x Reset bit 4 */
1324 #define GPIO_BRR_BR5                         ((uint32_t)0x0020)            /*!< Port x Reset bit 5 */
1325 #define GPIO_BRR_BR6                         ((uint32_t)0x0040)            /*!< Port x Reset bit 6 */
1326 #define GPIO_BRR_BR7                         ((uint32_t)0x0080)            /*!< Port x Reset bit 7 */
1327 #define GPIO_BRR_BR8                         ((uint32_t)0x0100)            /*!< Port x Reset bit 8 */
1328 #define GPIO_BRR_BR9                         ((uint32_t)0x0200)            /*!< Port x Reset bit 9 */
1329 #define GPIO_BRR_BR10                        ((uint32_t)0x0400)            /*!< Port x Reset bit 10 */
1330 #define GPIO_BRR_BR11                        ((uint32_t)0x0800)            /*!< Port x Reset bit 11 */
1331 #define GPIO_BRR_BR12                        ((uint32_t)0x1000)            /*!< Port x Reset bit 12 */
1332 #define GPIO_BRR_BR13                        ((uint32_t)0x2000)            /*!< Port x Reset bit 13 */
1333 #define GPIO_BRR_BR14                        ((uint32_t)0x4000)            /*!< Port x Reset bit 14 */
1334 #define GPIO_BRR_BR15                        ((uint32_t)0x8000)            /*!< Port x Reset bit 15 */
1335
1336 /******************  Bit definition for GPIO_LCKR register  *******************/
1337 #define GPIO_LCKR_LCK0                       ((uint32_t)0x00000001)        /*!< Port x Lock bit 0 */
1338 #define GPIO_LCKR_LCK1                       ((uint32_t)0x00000002)        /*!< Port x Lock bit 1 */
1339 #define GPIO_LCKR_LCK2                       ((uint32_t)0x00000004)        /*!< Port x Lock bit 2 */
1340 #define GPIO_LCKR_LCK3                       ((uint32_t)0x00000008)        /*!< Port x Lock bit 3 */
1341 #define GPIO_LCKR_LCK4                       ((uint32_t)0x00000010)        /*!< Port x Lock bit 4 */
1342 #define GPIO_LCKR_LCK5                       ((uint32_t)0x00000020)        /*!< Port x Lock bit 5 */
1343 #define GPIO_LCKR_LCK6                       ((uint32_t)0x00000040)        /*!< Port x Lock bit 6 */
1344 #define GPIO_LCKR_LCK7                       ((uint32_t)0x00000080)        /*!< Port x Lock bit 7 */
1345 #define GPIO_LCKR_LCK8                       ((uint32_t)0x00000100)        /*!< Port x Lock bit 8 */
1346 #define GPIO_LCKR_LCK9                       ((uint32_t)0x00000200)        /*!< Port x Lock bit 9 */
1347 #define GPIO_LCKR_LCK10                      ((uint32_t)0x00000400)        /*!< Port x Lock bit 10 */
1348 #define GPIO_LCKR_LCK11                      ((uint32_t)0x00000800)        /*!< Port x Lock bit 11 */
1349 #define GPIO_LCKR_LCK12                      ((uint32_t)0x00001000)        /*!< Port x Lock bit 12 */
1350 #define GPIO_LCKR_LCK13                      ((uint32_t)0x00002000)        /*!< Port x Lock bit 13 */
1351 #define GPIO_LCKR_LCK14                      ((uint32_t)0x00004000)        /*!< Port x Lock bit 14 */
1352 #define GPIO_LCKR_LCK15                      ((uint32_t)0x00008000)        /*!< Port x Lock bit 15 */
1353 #define GPIO_LCKR_LCKK                       ((uint32_t)0x00010000)        /*!< Lock key */
1354
1355 /*----------------------------------------------------------------------------*/
1356
1357 /******************  Bit definition for AFIO_EVCR register  *******************/
1358 #define AFIO_EVCR_PIN                        ((uint32_t)0x0000000F)               /*!< PIN[3:0] bits (Pin selection) */
1359 #define AFIO_EVCR_PIN_0                      ((uint32_t)0x00000001)               /*!< Bit 0 */
1360 #define AFIO_EVCR_PIN_1                      ((uint32_t)0x00000002)               /*!< Bit 1 */
1361 #define AFIO_EVCR_PIN_2                      ((uint32_t)0x00000004)               /*!< Bit 2 */
1362 #define AFIO_EVCR_PIN_3                      ((uint32_t)0x00000008)               /*!< Bit 3 */
1363
1364 /*!< PIN configuration */
1365 #define AFIO_EVCR_PIN_PX0                    ((uint32_t)0x00000000)               /*!< Pin 0 selected */
1366 #define AFIO_EVCR_PIN_PX1                    ((uint32_t)0x00000001)               /*!< Pin 1 selected */
1367 #define AFIO_EVCR_PIN_PX2                    ((uint32_t)0x00000002)               /*!< Pin 2 selected */
1368 #define AFIO_EVCR_PIN_PX3                    ((uint32_t)0x00000003)               /*!< Pin 3 selected */
1369 #define AFIO_EVCR_PIN_PX4                    ((uint32_t)0x00000004)               /*!< Pin 4 selected */
1370 #define AFIO_EVCR_PIN_PX5                    ((uint32_t)0x00000005)               /*!< Pin 5 selected */
1371 #define AFIO_EVCR_PIN_PX6                    ((uint32_t)0x00000006)               /*!< Pin 6 selected */
1372 #define AFIO_EVCR_PIN_PX7                    ((uint32_t)0x00000007)               /*!< Pin 7 selected */
1373 #define AFIO_EVCR_PIN_PX8                    ((uint32_t)0x00000008)               /*!< Pin 8 selected */
1374 #define AFIO_EVCR_PIN_PX9                    ((uint32_t)0x00000009)               /*!< Pin 9 selected */
1375 #define AFIO_EVCR_PIN_PX10                   ((uint32_t)0x0000000A)               /*!< Pin 10 selected */
1376 #define AFIO_EVCR_PIN_PX11                   ((uint32_t)0x0000000B)               /*!< Pin 11 selected */
1377 #define AFIO_EVCR_PIN_PX12                   ((uint32_t)0x0000000C)               /*!< Pin 12 selected */
1378 #define AFIO_EVCR_PIN_PX13                   ((uint32_t)0x0000000D)               /*!< Pin 13 selected */
1379 #define AFIO_EVCR_PIN_PX14                   ((uint32_t)0x0000000E)               /*!< Pin 14 selected */
1380 #define AFIO_EVCR_PIN_PX15                   ((uint32_t)0x0000000F)               /*!< Pin 15 selected */
1381
1382 #define AFIO_EVCR_PORT                       ((uint32_t)0x00000070)               /*!< PORT[2:0] bits (Port selection) */
1383 #define AFIO_EVCR_PORT_0                     ((uint32_t)0x00000010)               /*!< Bit 0 */
1384 #define AFIO_EVCR_PORT_1                     ((uint32_t)0x00000020)               /*!< Bit 1 */
1385 #define AFIO_EVCR_PORT_2                     ((uint32_t)0x00000040)               /*!< Bit 2 */
1386
1387 /*!< PORT configuration */
1388 #define AFIO_EVCR_PORT_PA                    ((uint32_t)0x00000000)               /*!< Port A selected */
1389 #define AFIO_EVCR_PORT_PB                    ((uint32_t)0x00000010)               /*!< Port B selected */
1390 #define AFIO_EVCR_PORT_PC                    ((uint32_t)0x00000020)               /*!< Port C selected */
1391 #define AFIO_EVCR_PORT_PD                    ((uint32_t)0x00000030)               /*!< Port D selected */
1392 #define AFIO_EVCR_PORT_PE                    ((uint32_t)0x00000040)               /*!< Port E selected */
1393
1394 #define AFIO_EVCR_EVOE                       ((uint32_t)0x00000080)               /*!< Event Output Enable */
1395
1396 /******************  Bit definition for AFIO_MAPR register  *******************/
1397 #define AFIO_MAPR_SPI1_REMAP                 ((uint32_t)0x00000001)        /*!< SPI1 remapping */
1398 #define AFIO_MAPR_I2C1_REMAP                 ((uint32_t)0x00000002)        /*!< I2C1 remapping */
1399 #define AFIO_MAPR_USART1_REMAP               ((uint32_t)0x00000004)        /*!< USART1 remapping */
1400 #define AFIO_MAPR_USART2_REMAP               ((uint32_t)0x00000008)        /*!< USART2 remapping */
1401
1402 #define AFIO_MAPR_USART3_REMAP               ((uint32_t)0x00000030)        /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
1403 #define AFIO_MAPR_USART3_REMAP_0             ((uint32_t)0x00000010)        /*!< Bit 0 */
1404 #define AFIO_MAPR_USART3_REMAP_1             ((uint32_t)0x00000020)        /*!< Bit 1 */
1405
1406 /* USART3_REMAP configuration */
1407 #define AFIO_MAPR_USART3_REMAP_NOREMAP       ((uint32_t)0x00000000)        /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
1408 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP  ((uint32_t)0x00000010)        /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
1409 #define AFIO_MAPR_USART3_REMAP_FULLREMAP     ((uint32_t)0x00000030)        /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
1410
1411 #define AFIO_MAPR_TIM1_REMAP                 ((uint32_t)0x000000C0)        /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
1412 #define AFIO_MAPR_TIM1_REMAP_0               ((uint32_t)0x00000040)        /*!< Bit 0 */
1413 #define AFIO_MAPR_TIM1_REMAP_1               ((uint32_t)0x00000080)        /*!< Bit 1 */
1414
1415 /*!< TIM1_REMAP configuration */
1416 #define AFIO_MAPR_TIM1_REMAP_NOREMAP         ((uint32_t)0x00000000)        /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
1417 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP    ((uint32_t)0x00000040)        /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
1418 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP       ((uint32_t)0x000000C0)        /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
1419
1420 #define AFIO_MAPR_TIM2_REMAP                 ((uint32_t)0x00000300)        /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
1421 #define AFIO_MAPR_TIM2_REMAP_0               ((uint32_t)0x00000100)        /*!< Bit 0 */
1422 #define AFIO_MAPR_TIM2_REMAP_1               ((uint32_t)0x00000200)        /*!< Bit 1 */
1423
1424 /*!< TIM2_REMAP configuration */
1425 #define AFIO_MAPR_TIM2_REMAP_NOREMAP         ((uint32_t)0x00000000)        /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
1426 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   ((uint32_t)0x00000100)        /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
1427 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2   ((uint32_t)0x00000200)        /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
1428 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP       ((uint32_t)0x00000300)        /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
1429
1430 #define AFIO_MAPR_TIM3_REMAP                 ((uint32_t)0x00000C00)        /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
1431 #define AFIO_MAPR_TIM3_REMAP_0               ((uint32_t)0x00000400)        /*!< Bit 0 */
1432 #define AFIO_MAPR_TIM3_REMAP_1               ((uint32_t)0x00000800)        /*!< Bit 1 */
1433
1434 /*!< TIM3_REMAP configuration */
1435 #define AFIO_MAPR_TIM3_REMAP_NOREMAP         ((uint32_t)0x00000000)        /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
1436 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP    ((uint32_t)0x00000800)        /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
1437 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP       ((uint32_t)0x00000C00)        /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
1438
1439 #define AFIO_MAPR_TIM4_REMAP                 ((uint32_t)0x00001000)        /*!< TIM4_REMAP bit (TIM4 remapping) */
1440
1441
1442 #define AFIO_MAPR_PD01_REMAP                 ((uint32_t)0x00008000)        /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
1443
1444 /*!< SWJ_CFG configuration */
1445 #define AFIO_MAPR_SWJ_CFG                    ((uint32_t)0x07000000)        /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
1446 #define AFIO_MAPR_SWJ_CFG_0                  ((uint32_t)0x01000000)        /*!< Bit 0 */
1447 #define AFIO_MAPR_SWJ_CFG_1                  ((uint32_t)0x02000000)        /*!< Bit 1 */
1448 #define AFIO_MAPR_SWJ_CFG_2                  ((uint32_t)0x04000000)        /*!< Bit 2 */
1449
1450 #define AFIO_MAPR_SWJ_CFG_RESET              ((uint32_t)0x00000000)        /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
1451 #define AFIO_MAPR_SWJ_CFG_NOJNTRST           ((uint32_t)0x01000000)        /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
1452 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE        ((uint32_t)0x02000000)        /*!< JTAG-DP Disabled and SW-DP Enabled */
1453 #define AFIO_MAPR_SWJ_CFG_DISABLE            ((uint32_t)0x04000000)        /*!< JTAG-DP Disabled and SW-DP Disabled */
1454
1455
1456 /*****************  Bit definition for AFIO_EXTICR1 register  *****************/
1457 #define AFIO_EXTICR1_EXTI0                   ((uint32_t)0x0000000F)            /*!< EXTI 0 configuration */
1458 #define AFIO_EXTICR1_EXTI1                   ((uint32_t)0x000000F0)            /*!< EXTI 1 configuration */
1459 #define AFIO_EXTICR1_EXTI2                   ((uint32_t)0x00000F00)            /*!< EXTI 2 configuration */
1460 #define AFIO_EXTICR1_EXTI3                   ((uint32_t)0x0000F000)            /*!< EXTI 3 configuration */
1461
1462 /*!< EXTI0 configuration */
1463 #define AFIO_EXTICR1_EXTI0_PA                ((uint32_t)0x00000000)            /*!< PA[0] pin */
1464 #define AFIO_EXTICR1_EXTI0_PB                ((uint32_t)0x00000001)            /*!< PB[0] pin */
1465 #define AFIO_EXTICR1_EXTI0_PC                ((uint32_t)0x00000002)            /*!< PC[0] pin */
1466 #define AFIO_EXTICR1_EXTI0_PD                ((uint32_t)0x00000003)            /*!< PD[0] pin */
1467 #define AFIO_EXTICR1_EXTI0_PE                ((uint32_t)0x00000004)            /*!< PE[0] pin */
1468 #define AFIO_EXTICR1_EXTI0_PF                ((uint32_t)0x00000005)            /*!< PF[0] pin */
1469 #define AFIO_EXTICR1_EXTI0_PG                ((uint32_t)0x00000006)            /*!< PG[0] pin */
1470
1471 /*!< EXTI1 configuration */
1472 #define AFIO_EXTICR1_EXTI1_PA                ((uint32_t)0x00000000)            /*!< PA[1] pin */
1473 #define AFIO_EXTICR1_EXTI1_PB                ((uint32_t)0x00000010)            /*!< PB[1] pin */
1474 #define AFIO_EXTICR1_EXTI1_PC                ((uint32_t)0x00000020)            /*!< PC[1] pin */
1475 #define AFIO_EXTICR1_EXTI1_PD                ((uint32_t)0x00000030)            /*!< PD[1] pin */
1476 #define AFIO_EXTICR1_EXTI1_PE                ((uint32_t)0x00000040)            /*!< PE[1] pin */
1477 #define AFIO_EXTICR1_EXTI1_PF                ((uint32_t)0x00000050)            /*!< PF[1] pin */
1478 #define AFIO_EXTICR1_EXTI1_PG                ((uint32_t)0x00000060)            /*!< PG[1] pin */
1479
1480 /*!< EXTI2 configuration */
1481 #define AFIO_EXTICR1_EXTI2_PA                ((uint32_t)0x00000000)            /*!< PA[2] pin */
1482 #define AFIO_EXTICR1_EXTI2_PB                ((uint32_t)0x00000100)            /*!< PB[2] pin */
1483 #define AFIO_EXTICR1_EXTI2_PC                ((uint32_t)0x00000200)            /*!< PC[2] pin */
1484 #define AFIO_EXTICR1_EXTI2_PD                ((uint32_t)0x00000300)            /*!< PD[2] pin */
1485 #define AFIO_EXTICR1_EXTI2_PE                ((uint32_t)0x00000400)            /*!< PE[2] pin */
1486 #define AFIO_EXTICR1_EXTI2_PF                ((uint32_t)0x00000500)            /*!< PF[2] pin */
1487 #define AFIO_EXTICR1_EXTI2_PG                ((uint32_t)0x00000600)            /*!< PG[2] pin */
1488
1489 /*!< EXTI3 configuration */
1490 #define AFIO_EXTICR1_EXTI3_PA                ((uint32_t)0x00000000)            /*!< PA[3] pin */
1491 #define AFIO_EXTICR1_EXTI3_PB                ((uint32_t)0x00001000)            /*!< PB[3] pin */
1492 #define AFIO_EXTICR1_EXTI3_PC                ((uint32_t)0x00002000)            /*!< PC[3] pin */
1493 #define AFIO_EXTICR1_EXTI3_PD                ((uint32_t)0x00003000)            /*!< PD[3] pin */
1494 #define AFIO_EXTICR1_EXTI3_PE                ((uint32_t)0x00004000)            /*!< PE[3] pin */
1495 #define AFIO_EXTICR1_EXTI3_PF                ((uint32_t)0x00005000)            /*!< PF[3] pin */
1496 #define AFIO_EXTICR1_EXTI3_PG                ((uint32_t)0x00006000)            /*!< PG[3] pin */
1497
1498 /*****************  Bit definition for AFIO_EXTICR2 register  *****************/
1499 #define AFIO_EXTICR2_EXTI4                   ((uint32_t)0x0000000F)            /*!< EXTI 4 configuration */
1500 #define AFIO_EXTICR2_EXTI5                   ((uint32_t)0x000000F0)            /*!< EXTI 5 configuration */
1501 #define AFIO_EXTICR2_EXTI6                   ((uint32_t)0x00000F00)            /*!< EXTI 6 configuration */
1502 #define AFIO_EXTICR2_EXTI7                   ((uint32_t)0x0000F000)            /*!< EXTI 7 configuration */
1503
1504 /*!< EXTI4 configuration */
1505 #define AFIO_EXTICR2_EXTI4_PA                ((uint32_t)0x00000000)            /*!< PA[4] pin */
1506 #define AFIO_EXTICR2_EXTI4_PB                ((uint32_t)0x00000001)            /*!< PB[4] pin */
1507 #define AFIO_EXTICR2_EXTI4_PC                ((uint32_t)0x00000002)            /*!< PC[4] pin */
1508 #define AFIO_EXTICR2_EXTI4_PD                ((uint32_t)0x00000003)            /*!< PD[4] pin */
1509 #define AFIO_EXTICR2_EXTI4_PE                ((uint32_t)0x00000004)            /*!< PE[4] pin */
1510 #define AFIO_EXTICR2_EXTI4_PF                ((uint32_t)0x00000005)            /*!< PF[4] pin */
1511 #define AFIO_EXTICR2_EXTI4_PG                ((uint32_t)0x00000006)            /*!< PG[4] pin */
1512
1513 /* EXTI5 configuration */
1514 #define AFIO_EXTICR2_EXTI5_PA                ((uint32_t)0x00000000)            /*!< PA[5] pin */
1515 #define AFIO_EXTICR2_EXTI5_PB                ((uint32_t)0x00000010)            /*!< PB[5] pin */
1516 #define AFIO_EXTICR2_EXTI5_PC                ((uint32_t)0x00000020)            /*!< PC[5] pin */
1517 #define AFIO_EXTICR2_EXTI5_PD                ((uint32_t)0x00000030)            /*!< PD[5] pin */
1518 #define AFIO_EXTICR2_EXTI5_PE                ((uint32_t)0x00000040)            /*!< PE[5] pin */
1519 #define AFIO_EXTICR2_EXTI5_PF                ((uint32_t)0x00000050)            /*!< PF[5] pin */
1520 #define AFIO_EXTICR2_EXTI5_PG                ((uint32_t)0x00000060)            /*!< PG[5] pin */
1521
1522 /*!< EXTI6 configuration */
1523 #define AFIO_EXTICR2_EXTI6_PA                ((uint32_t)0x00000000)            /*!< PA[6] pin */
1524 #define AFIO_EXTICR2_EXTI6_PB                ((uint32_t)0x00000100)            /*!< PB[6] pin */
1525 #define AFIO_EXTICR2_EXTI6_PC                ((uint32_t)0x00000200)            /*!< PC[6] pin */
1526 #define AFIO_EXTICR2_EXTI6_PD                ((uint32_t)0x00000300)            /*!< PD[6] pin */
1527 #define AFIO_EXTICR2_EXTI6_PE                ((uint32_t)0x00000400)            /*!< PE[6] pin */
1528 #define AFIO_EXTICR2_EXTI6_PF                ((uint32_t)0x00000500)            /*!< PF[6] pin */
1529 #define AFIO_EXTICR2_EXTI6_PG                ((uint32_t)0x00000600)            /*!< PG[6] pin */
1530
1531 /*!< EXTI7 configuration */
1532 #define AFIO_EXTICR2_EXTI7_PA                ((uint32_t)0x00000000)            /*!< PA[7] pin */
1533 #define AFIO_EXTICR2_EXTI7_PB                ((uint32_t)0x00001000)            /*!< PB[7] pin */
1534 #define AFIO_EXTICR2_EXTI7_PC                ((uint32_t)0x00002000)            /*!< PC[7] pin */
1535 #define AFIO_EXTICR2_EXTI7_PD                ((uint32_t)0x00003000)            /*!< PD[7] pin */
1536 #define AFIO_EXTICR2_EXTI7_PE                ((uint32_t)0x00004000)            /*!< PE[7] pin */
1537 #define AFIO_EXTICR2_EXTI7_PF                ((uint32_t)0x00005000)            /*!< PF[7] pin */
1538 #define AFIO_EXTICR2_EXTI7_PG                ((uint32_t)0x00006000)            /*!< PG[7] pin */
1539
1540 /*****************  Bit definition for AFIO_EXTICR3 register  *****************/
1541 #define AFIO_EXTICR3_EXTI8                   ((uint32_t)0x0000000F)            /*!< EXTI 8 configuration */
1542 #define AFIO_EXTICR3_EXTI9                   ((uint32_t)0x000000F0)            /*!< EXTI 9 configuration */
1543 #define AFIO_EXTICR3_EXTI10                  ((uint32_t)0x00000F00)            /*!< EXTI 10 configuration */
1544 #define AFIO_EXTICR3_EXTI11                  ((uint32_t)0x0000F000)            /*!< EXTI 11 configuration */
1545
1546 /*!< EXTI8 configuration */
1547 #define AFIO_EXTICR3_EXTI8_PA                ((uint32_t)0x00000000)            /*!< PA[8] pin */
1548 #define AFIO_EXTICR3_EXTI8_PB                ((uint32_t)0x00000001)            /*!< PB[8] pin */
1549 #define AFIO_EXTICR3_EXTI8_PC                ((uint32_t)0x00000002)            /*!< PC[8] pin */
1550 #define AFIO_EXTICR3_EXTI8_PD                ((uint32_t)0x00000003)            /*!< PD[8] pin */
1551 #define AFIO_EXTICR3_EXTI8_PE                ((uint32_t)0x00000004)            /*!< PE[8] pin */
1552 #define AFIO_EXTICR3_EXTI8_PF                ((uint32_t)0x00000005)            /*!< PF[8] pin */
1553 #define AFIO_EXTICR3_EXTI8_PG                ((uint32_t)0x00000006)            /*!< PG[8] pin */
1554
1555 /*!< EXTI9 configuration */
1556 #define AFIO_EXTICR3_EXTI9_PA                ((uint32_t)0x00000000)            /*!< PA[9] pin */
1557 #define AFIO_EXTICR3_EXTI9_PB                ((uint32_t)0x00000010)            /*!< PB[9] pin */
1558 #define AFIO_EXTICR3_EXTI9_PC                ((uint32_t)0x00000020)            /*!< PC[9] pin */
1559 #define AFIO_EXTICR3_EXTI9_PD                ((uint32_t)0x00000030)            /*!< PD[9] pin */
1560 #define AFIO_EXTICR3_EXTI9_PE                ((uint32_t)0x00000040)            /*!< PE[9] pin */
1561 #define AFIO_EXTICR3_EXTI9_PF                ((uint32_t)0x00000050)            /*!< PF[9] pin */
1562 #define AFIO_EXTICR3_EXTI9_PG                ((uint32_t)0x00000060)            /*!< PG[9] pin */
1563
1564 /*!< EXTI10 configuration */
1565 #define AFIO_EXTICR3_EXTI10_PA               ((uint32_t)0x00000000)            /*!< PA[10] pin */
1566 #define AFIO_EXTICR3_EXTI10_PB               ((uint32_t)0x00000100)            /*!< PB[10] pin */
1567 #define AFIO_EXTICR3_EXTI10_PC               ((uint32_t)0x00000200)            /*!< PC[10] pin */
1568 #define AFIO_EXTICR3_EXTI10_PD               ((uint32_t)0x00000300)            /*!< PD[10] pin */
1569 #define AFIO_EXTICR3_EXTI10_PE               ((uint32_t)0x00000400)            /*!< PE[10] pin */
1570 #define AFIO_EXTICR3_EXTI10_PF               ((uint32_t)0x00000500)            /*!< PF[10] pin */
1571 #define AFIO_EXTICR3_EXTI10_PG               ((uint32_t)0x00000600)            /*!< PG[10] pin */
1572
1573 /*!< EXTI11 configuration */
1574 #define AFIO_EXTICR3_EXTI11_PA               ((uint32_t)0x00000000)            /*!< PA[11] pin */
1575 #define AFIO_EXTICR3_EXTI11_PB               ((uint32_t)0x00001000)            /*!< PB[11] pin */
1576 #define AFIO_EXTICR3_EXTI11_PC               ((uint32_t)0x00002000)            /*!< PC[11] pin */
1577 #define AFIO_EXTICR3_EXTI11_PD               ((uint32_t)0x00003000)            /*!< PD[11] pin */
1578 #define AFIO_EXTICR3_EXTI11_PE               ((uint32_t)0x00004000)            /*!< PE[11] pin */
1579 #define AFIO_EXTICR3_EXTI11_PF               ((uint32_t)0x00005000)            /*!< PF[11] pin */
1580 #define AFIO_EXTICR3_EXTI11_PG               ((uint32_t)0x00006000)            /*!< PG[11] pin */
1581
1582 /*****************  Bit definition for AFIO_EXTICR4 register  *****************/
1583 #define AFIO_EXTICR4_EXTI12                  ((uint32_t)0x0000000F)            /*!< EXTI 12 configuration */
1584 #define AFIO_EXTICR4_EXTI13                  ((uint32_t)0x000000F0)            /*!< EXTI 13 configuration */
1585 #define AFIO_EXTICR4_EXTI14                  ((uint32_t)0x00000F00)            /*!< EXTI 14 configuration */
1586 #define AFIO_EXTICR4_EXTI15                  ((uint32_t)0x0000F000)            /*!< EXTI 15 configuration */
1587
1588 /* EXTI12 configuration */
1589 #define AFIO_EXTICR4_EXTI12_PA               ((uint32_t)0x00000000)            /*!< PA[12] pin */
1590 #define AFIO_EXTICR4_EXTI12_PB               ((uint32_t)0x00000001)            /*!< PB[12] pin */
1591 #define AFIO_EXTICR4_EXTI12_PC               ((uint32_t)0x00000002)            /*!< PC[12] pin */
1592 #define AFIO_EXTICR4_EXTI12_PD               ((uint32_t)0x00000003)            /*!< PD[12] pin */
1593 #define AFIO_EXTICR4_EXTI12_PE               ((uint32_t)0x00000004)            /*!< PE[12] pin */
1594 #define AFIO_EXTICR4_EXTI12_PF               ((uint32_t)0x00000005)            /*!< PF[12] pin */
1595 #define AFIO_EXTICR4_EXTI12_PG               ((uint32_t)0x00000006)            /*!< PG[12] pin */
1596
1597 /* EXTI13 configuration */
1598 #define AFIO_EXTICR4_EXTI13_PA               ((uint32_t)0x00000000)            /*!< PA[13] pin */
1599 #define AFIO_EXTICR4_EXTI13_PB               ((uint32_t)0x00000010)            /*!< PB[13] pin */
1600 #define AFIO_EXTICR4_EXTI13_PC               ((uint32_t)0x00000020)            /*!< PC[13] pin */
1601 #define AFIO_EXTICR4_EXTI13_PD               ((uint32_t)0x00000030)            /*!< PD[13] pin */
1602 #define AFIO_EXTICR4_EXTI13_PE               ((uint32_t)0x00000040)            /*!< PE[13] pin */
1603 #define AFIO_EXTICR4_EXTI13_PF               ((uint32_t)0x00000050)            /*!< PF[13] pin */
1604 #define AFIO_EXTICR4_EXTI13_PG               ((uint32_t)0x00000060)            /*!< PG[13] pin */
1605
1606 /*!< EXTI14 configuration */
1607 #define AFIO_EXTICR4_EXTI14_PA               ((uint32_t)0x00000000)            /*!< PA[14] pin */
1608 #define AFIO_EXTICR4_EXTI14_PB               ((uint32_t)0x00000100)            /*!< PB[14] pin */
1609 #define AFIO_EXTICR4_EXTI14_PC               ((uint32_t)0x00000200)            /*!< PC[14] pin */
1610 #define AFIO_EXTICR4_EXTI14_PD               ((uint32_t)0x00000300)            /*!< PD[14] pin */
1611 #define AFIO_EXTICR4_EXTI14_PE               ((uint32_t)0x00000400)            /*!< PE[14] pin */
1612 #define AFIO_EXTICR4_EXTI14_PF               ((uint32_t)0x00000500)            /*!< PF[14] pin */
1613 #define AFIO_EXTICR4_EXTI14_PG               ((uint32_t)0x00000600)            /*!< PG[14] pin */
1614
1615 /*!< EXTI15 configuration */
1616 #define AFIO_EXTICR4_EXTI15_PA               ((uint32_t)0x00000000)            /*!< PA[15] pin */
1617 #define AFIO_EXTICR4_EXTI15_PB               ((uint32_t)0x00001000)            /*!< PB[15] pin */
1618 #define AFIO_EXTICR4_EXTI15_PC               ((uint32_t)0x00002000)            /*!< PC[15] pin */
1619 #define AFIO_EXTICR4_EXTI15_PD               ((uint32_t)0x00003000)            /*!< PD[15] pin */
1620 #define AFIO_EXTICR4_EXTI15_PE               ((uint32_t)0x00004000)            /*!< PE[15] pin */
1621 #define AFIO_EXTICR4_EXTI15_PF               ((uint32_t)0x00005000)            /*!< PF[15] pin */
1622 #define AFIO_EXTICR4_EXTI15_PG               ((uint32_t)0x00006000)            /*!< PG[15] pin */
1623
1624 /******************  Bit definition for AFIO_MAPR2 register  ******************/
1625 #define AFIO_MAPR2_TIM15_REMAP               ((uint32_t)0x00000001)        /*!< TIM15 remapping */
1626 #define AFIO_MAPR2_TIM16_REMAP               ((uint32_t)0x00000002)        /*!< TIM16 remapping */
1627 #define AFIO_MAPR2_TIM17_REMAP               ((uint32_t)0x00000004)        /*!< TIM17 remapping */
1628 #define AFIO_MAPR2_CEC_REMAP                 ((uint32_t)0x00000008)        /*!< CEC remapping */
1629 #define AFIO_MAPR2_TIM1_DMA_REMAP            ((uint32_t)0x00000010)        /*!< TIM1_DMA remapping */
1630
1631 #define AFIO_MAPR2_TIM67_DAC_DMA_REMAP       ((uint32_t)0x00000800)        /*!< TIM6/TIM7 and DAC DMA remapping */
1632
1633
1634 /******************************************************************************/
1635 /*                                                                            */
1636 /*                               SystemTick                                   */
1637 /*                                                                            */
1638 /******************************************************************************/
1639
1640 /*****************  Bit definition for SysTick_CTRL register  *****************/
1641 #define  SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)        /*!< Counter enable */
1642 #define  SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)        /*!< Counting down to 0 pends the SysTick handler */
1643 #define  SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)        /*!< Clock source */
1644 #define  SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)        /*!< Count Flag */
1645
1646 /*****************  Bit definition for SysTick_LOAD register  *****************/
1647 #define  SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)        /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
1648
1649 /*****************  Bit definition for SysTick_VAL register  ******************/
1650 #define  SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)        /*!< Current value at the time the register is accessed */
1651
1652 /*****************  Bit definition for SysTick_CALIB register  ****************/
1653 #define  SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)        /*!< Reload value to use for 10ms timing */
1654 #define  SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)        /*!< Calibration value is not exactly 10 ms */
1655 #define  SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)        /*!< The reference clock is not provided */
1656
1657 /******************************************************************************/
1658 /*                                                                            */
1659 /*                  Nested Vectored Interrupt Controller                      */
1660 /*                                                                            */
1661 /******************************************************************************/
1662
1663 /******************  Bit definition for NVIC_ISER register  *******************/
1664 #define  NVIC_ISER_SETENA                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set enable bits */
1665 #define  NVIC_ISER_SETENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
1666 #define  NVIC_ISER_SETENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
1667 #define  NVIC_ISER_SETENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
1668 #define  NVIC_ISER_SETENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
1669 #define  NVIC_ISER_SETENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
1670 #define  NVIC_ISER_SETENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
1671 #define  NVIC_ISER_SETENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
1672 #define  NVIC_ISER_SETENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
1673 #define  NVIC_ISER_SETENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
1674 #define  NVIC_ISER_SETENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
1675 #define  NVIC_ISER_SETENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
1676 #define  NVIC_ISER_SETENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
1677 #define  NVIC_ISER_SETENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
1678 #define  NVIC_ISER_SETENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
1679 #define  NVIC_ISER_SETENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
1680 #define  NVIC_ISER_SETENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
1681 #define  NVIC_ISER_SETENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
1682 #define  NVIC_ISER_SETENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
1683 #define  NVIC_ISER_SETENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
1684 #define  NVIC_ISER_SETENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
1685 #define  NVIC_ISER_SETENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
1686 #define  NVIC_ISER_SETENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
1687 #define  NVIC_ISER_SETENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
1688 #define  NVIC_ISER_SETENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
1689 #define  NVIC_ISER_SETENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
1690 #define  NVIC_ISER_SETENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
1691 #define  NVIC_ISER_SETENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
1692 #define  NVIC_ISER_SETENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
1693 #define  NVIC_ISER_SETENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
1694 #define  NVIC_ISER_SETENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
1695 #define  NVIC_ISER_SETENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
1696 #define  NVIC_ISER_SETENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
1697
1698 /******************  Bit definition for NVIC_ICER register  *******************/
1699 #define  NVIC_ICER_CLRENA                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-enable bits */
1700 #define  NVIC_ICER_CLRENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
1701 #define  NVIC_ICER_CLRENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
1702 #define  NVIC_ICER_CLRENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
1703 #define  NVIC_ICER_CLRENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
1704 #define  NVIC_ICER_CLRENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
1705 #define  NVIC_ICER_CLRENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
1706 #define  NVIC_ICER_CLRENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
1707 #define  NVIC_ICER_CLRENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
1708 #define  NVIC_ICER_CLRENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
1709 #define  NVIC_ICER_CLRENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
1710 #define  NVIC_ICER_CLRENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
1711 #define  NVIC_ICER_CLRENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
1712 #define  NVIC_ICER_CLRENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
1713 #define  NVIC_ICER_CLRENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
1714 #define  NVIC_ICER_CLRENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
1715 #define  NVIC_ICER_CLRENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
1716 #define  NVIC_ICER_CLRENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
1717 #define  NVIC_ICER_CLRENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
1718 #define  NVIC_ICER_CLRENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
1719 #define  NVIC_ICER_CLRENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
1720 #define  NVIC_ICER_CLRENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
1721 #define  NVIC_ICER_CLRENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
1722 #define  NVIC_ICER_CLRENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
1723 #define  NVIC_ICER_CLRENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
1724 #define  NVIC_ICER_CLRENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
1725 #define  NVIC_ICER_CLRENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
1726 #define  NVIC_ICER_CLRENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
1727 #define  NVIC_ICER_CLRENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
1728 #define  NVIC_ICER_CLRENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
1729 #define  NVIC_ICER_CLRENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
1730 #define  NVIC_ICER_CLRENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
1731 #define  NVIC_ICER_CLRENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
1732
1733 /******************  Bit definition for NVIC_ISPR register  *******************/
1734 #define  NVIC_ISPR_SETPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set-pending bits */
1735 #define  NVIC_ISPR_SETPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */
1736 #define  NVIC_ISPR_SETPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */
1737 #define  NVIC_ISPR_SETPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */
1738 #define  NVIC_ISPR_SETPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */
1739 #define  NVIC_ISPR_SETPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */
1740 #define  NVIC_ISPR_SETPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */
1741 #define  NVIC_ISPR_SETPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */
1742 #define  NVIC_ISPR_SETPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */
1743 #define  NVIC_ISPR_SETPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */
1744 #define  NVIC_ISPR_SETPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */
1745 #define  NVIC_ISPR_SETPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */
1746 #define  NVIC_ISPR_SETPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */
1747 #define  NVIC_ISPR_SETPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */
1748 #define  NVIC_ISPR_SETPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */
1749 #define  NVIC_ISPR_SETPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */
1750 #define  NVIC_ISPR_SETPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */
1751 #define  NVIC_ISPR_SETPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */
1752 #define  NVIC_ISPR_SETPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */
1753 #define  NVIC_ISPR_SETPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */
1754 #define  NVIC_ISPR_SETPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */
1755 #define  NVIC_ISPR_SETPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */
1756 #define  NVIC_ISPR_SETPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */
1757 #define  NVIC_ISPR_SETPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */
1758 #define  NVIC_ISPR_SETPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */
1759 #define  NVIC_ISPR_SETPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */
1760 #define  NVIC_ISPR_SETPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */
1761 #define  NVIC_ISPR_SETPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */
1762 #define  NVIC_ISPR_SETPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */
1763 #define  NVIC_ISPR_SETPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */
1764 #define  NVIC_ISPR_SETPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */
1765 #define  NVIC_ISPR_SETPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */
1766 #define  NVIC_ISPR_SETPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */
1767
1768 /******************  Bit definition for NVIC_ICPR register  *******************/
1769 #define  NVIC_ICPR_CLRPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-pending bits */
1770 #define  NVIC_ICPR_CLRPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */
1771 #define  NVIC_ICPR_CLRPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */
1772 #define  NVIC_ICPR_CLRPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */
1773 #define  NVIC_ICPR_CLRPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */
1774 #define  NVIC_ICPR_CLRPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */
1775 #define  NVIC_ICPR_CLRPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */
1776 #define  NVIC_ICPR_CLRPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */
1777 #define  NVIC_ICPR_CLRPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */
1778 #define  NVIC_ICPR_CLRPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */
1779 #define  NVIC_ICPR_CLRPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */
1780 #define  NVIC_ICPR_CLRPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */
1781 #define  NVIC_ICPR_CLRPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */
1782 #define  NVIC_ICPR_CLRPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */
1783 #define  NVIC_ICPR_CLRPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */
1784 #define  NVIC_ICPR_CLRPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */
1785 #define  NVIC_ICPR_CLRPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */
1786 #define  NVIC_ICPR_CLRPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */
1787 #define  NVIC_ICPR_CLRPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */
1788 #define  NVIC_ICPR_CLRPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */
1789 #define  NVIC_ICPR_CLRPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */
1790 #define  NVIC_ICPR_CLRPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */
1791 #define  NVIC_ICPR_CLRPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */
1792 #define  NVIC_ICPR_CLRPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */
1793 #define  NVIC_ICPR_CLRPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */
1794 #define  NVIC_ICPR_CLRPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */
1795 #define  NVIC_ICPR_CLRPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */
1796 #define  NVIC_ICPR_CLRPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */
1797 #define  NVIC_ICPR_CLRPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */
1798 #define  NVIC_ICPR_CLRPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */
1799 #define  NVIC_ICPR_CLRPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */
1800 #define  NVIC_ICPR_CLRPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */
1801 #define  NVIC_ICPR_CLRPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */
1802
1803 /******************  Bit definition for NVIC_IABR register  *******************/
1804 #define  NVIC_IABR_ACTIVE                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt active flags */
1805 #define  NVIC_IABR_ACTIVE_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
1806 #define  NVIC_IABR_ACTIVE_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
1807 #define  NVIC_IABR_ACTIVE_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
1808 #define  NVIC_IABR_ACTIVE_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
1809 #define  NVIC_IABR_ACTIVE_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
1810 #define  NVIC_IABR_ACTIVE_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
1811 #define  NVIC_IABR_ACTIVE_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
1812 #define  NVIC_IABR_ACTIVE_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
1813 #define  NVIC_IABR_ACTIVE_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
1814 #define  NVIC_IABR_ACTIVE_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
1815 #define  NVIC_IABR_ACTIVE_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
1816 #define  NVIC_IABR_ACTIVE_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
1817 #define  NVIC_IABR_ACTIVE_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
1818 #define  NVIC_IABR_ACTIVE_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
1819 #define  NVIC_IABR_ACTIVE_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
1820 #define  NVIC_IABR_ACTIVE_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
1821 #define  NVIC_IABR_ACTIVE_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
1822 #define  NVIC_IABR_ACTIVE_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
1823 #define  NVIC_IABR_ACTIVE_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
1824 #define  NVIC_IABR_ACTIVE_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
1825 #define  NVIC_IABR_ACTIVE_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
1826 #define  NVIC_IABR_ACTIVE_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
1827 #define  NVIC_IABR_ACTIVE_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
1828 #define  NVIC_IABR_ACTIVE_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
1829 #define  NVIC_IABR_ACTIVE_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
1830 #define  NVIC_IABR_ACTIVE_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
1831 #define  NVIC_IABR_ACTIVE_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
1832 #define  NVIC_IABR_ACTIVE_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
1833 #define  NVIC_IABR_ACTIVE_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
1834 #define  NVIC_IABR_ACTIVE_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
1835 #define  NVIC_IABR_ACTIVE_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
1836 #define  NVIC_IABR_ACTIVE_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
1837
1838 /******************  Bit definition for NVIC_PRI0 register  *******************/
1839 #define  NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 0 */
1840 #define  NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 1 */
1841 #define  NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 2 */
1842 #define  NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 3 */
1843
1844 /******************  Bit definition for NVIC_PRI1 register  *******************/
1845 #define  NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 4 */
1846 #define  NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 5 */
1847 #define  NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 6 */
1848 #define  NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 7 */
1849
1850 /******************  Bit definition for NVIC_PRI2 register  *******************/
1851 #define  NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 8 */
1852 #define  NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 9 */
1853 #define  NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 10 */
1854 #define  NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 11 */
1855
1856 /******************  Bit definition for NVIC_PRI3 register  *******************/
1857 #define  NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 12 */
1858 #define  NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 13 */
1859 #define  NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 14 */
1860 #define  NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 15 */
1861
1862 /******************  Bit definition for NVIC_PRI4 register  *******************/
1863 #define  NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 16 */
1864 #define  NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 17 */
1865 #define  NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 18 */
1866 #define  NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 19 */
1867
1868 /******************  Bit definition for NVIC_PRI5 register  *******************/
1869 #define  NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 20 */
1870 #define  NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 21 */
1871 #define  NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 22 */
1872 #define  NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 23 */
1873
1874 /******************  Bit definition for NVIC_PRI6 register  *******************/
1875 #define  NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 24 */
1876 #define  NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 25 */
1877 #define  NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 26 */
1878 #define  NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 27 */
1879
1880 /******************  Bit definition for NVIC_PRI7 register  *******************/
1881 #define  NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 28 */
1882 #define  NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 29 */
1883 #define  NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 30 */
1884 #define  NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 31 */
1885
1886 /******************  Bit definition for SCB_CPUID register  *******************/
1887 #define  SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)        /*!< Implementation defined revision number */
1888 #define  SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)        /*!< Number of processor within family */
1889 #define  SCB_CPUID_Constant                  ((uint32_t)0x000F0000)        /*!< Reads as 0x0F */
1890 #define  SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)        /*!< Implementation defined variant number */
1891 #define  SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)        /*!< Implementer code. ARM is 0x41 */
1892
1893 /*******************  Bit definition for SCB_ICSR register  *******************/
1894 #define  SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)        /*!< Active ISR number field */
1895 #define  SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)        /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
1896 #define  SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)        /*!< Pending ISR number field */
1897 #define  SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)        /*!< Interrupt pending flag */
1898 #define  SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)        /*!< It indicates that a pending interrupt becomes active in the next running cycle */
1899 #define  SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)        /*!< Clear pending SysTick bit */
1900 #define  SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)        /*!< Set pending SysTick bit */
1901 #define  SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)        /*!< Clear pending pendSV bit */
1902 #define  SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)        /*!< Set pending pendSV bit */
1903 #define  SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)        /*!< Set pending NMI bit */
1904
1905 /*******************  Bit definition for SCB_VTOR register  *******************/
1906 #define  SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)        /*!< Vector table base offset field */
1907 #define  SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)        /*!< Table base in code(0) or RAM(1) */
1908
1909 /*!<*****************  Bit definition for SCB_AIRCR register  *******************/
1910 #define  SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)        /*!< System Reset bit */
1911 #define  SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)        /*!< Clear active vector bit */
1912 #define  SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)        /*!< Requests chip control logic to generate a reset */
1913
1914 #define  SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)        /*!< PRIGROUP[2:0] bits (Priority group) */
1915 #define  SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)        /*!< Bit 0 */
1916 #define  SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)        /*!< Bit 1 */
1917 #define  SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)        /*!< Bit 2  */
1918
1919 /* prority group configuration */
1920 #define  SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)        /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
1921 #define  SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)        /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
1922 #define  SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)        /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
1923 #define  SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)        /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
1924 #define  SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)        /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
1925 #define  SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)        /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
1926 #define  SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)        /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
1927 #define  SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)        /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
1928
1929 #define  SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)        /*!< Data endianness bit */
1930 #define  SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)        /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
1931
1932 /*******************  Bit definition for SCB_SCR register  ********************/
1933 #define  SCB_SCR_SLEEPONEXIT                 ((uint32_t)0x00000002)        /*!< Sleep on exit bit */
1934 #define  SCB_SCR_SLEEPDEEP                   ((uint32_t)0x00000004)        /*!< Sleep deep bit */
1935 #define  SCB_SCR_SEVONPEND                   ((uint32_t)0x00000010)        /*!< Wake up from WFE */
1936
1937 /********************  Bit definition for SCB_CCR register  *******************/
1938 #define  SCB_CCR_NONBASETHRDENA              ((uint32_t)0x00000001)        /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
1939 #define  SCB_CCR_USERSETMPEND                ((uint32_t)0x00000002)        /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
1940 #define  SCB_CCR_UNALIGN_TRP                 ((uint32_t)0x00000008)        /*!< Trap for unaligned access */
1941 #define  SCB_CCR_DIV_0_TRP                   ((uint32_t)0x00000010)        /*!< Trap on Divide by 0 */
1942 #define  SCB_CCR_BFHFNMIGN                   ((uint32_t)0x00000100)        /*!< Handlers running at priority -1 and -2 */
1943 #define  SCB_CCR_STKALIGN                    ((uint32_t)0x00000200)        /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
1944
1945 /*******************  Bit definition for SCB_SHPR register ********************/
1946 #define  SCB_SHPR_PRI_N                      ((uint32_t)0x000000FF)        /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
1947 #define  SCB_SHPR_PRI_N1                     ((uint32_t)0x0000FF00)        /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
1948 #define  SCB_SHPR_PRI_N2                     ((uint32_t)0x00FF0000)        /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
1949 #define  SCB_SHPR_PRI_N3                     ((uint32_t)0xFF000000)        /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
1950
1951 /******************  Bit definition for SCB_SHCSR register  *******************/
1952 #define  SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)        /*!< MemManage is active */
1953 #define  SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)        /*!< BusFault is active */
1954 #define  SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)        /*!< UsageFault is active */
1955 #define  SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)        /*!< SVCall is active */
1956 #define  SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)        /*!< Monitor is active */
1957 #define  SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)        /*!< PendSV is active */
1958 #define  SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)        /*!< SysTick is active */
1959 #define  SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)        /*!< Usage Fault is pended */
1960 #define  SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)        /*!< MemManage is pended */
1961 #define  SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)        /*!< Bus Fault is pended */
1962 #define  SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)        /*!< SVCall is pended */
1963 #define  SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)        /*!< MemManage enable */
1964 #define  SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)        /*!< Bus Fault enable */
1965 #define  SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)        /*!< UsageFault enable */
1966
1967 /*******************  Bit definition for SCB_CFSR register  *******************/
1968 /*!< MFSR */
1969 #define  SCB_CFSR_IACCVIOL                   ((uint32_t)0x00000001)        /*!< Instruction access violation */
1970 #define  SCB_CFSR_DACCVIOL                   ((uint32_t)0x00000002)        /*!< Data access violation */
1971 #define  SCB_CFSR_MUNSTKERR                  ((uint32_t)0x00000008)        /*!< Unstacking error */
1972 #define  SCB_CFSR_MSTKERR                    ((uint32_t)0x00000010)        /*!< Stacking error */
1973 #define  SCB_CFSR_MMARVALID                  ((uint32_t)0x00000080)        /*!< Memory Manage Address Register address valid flag */
1974 /*!< BFSR */
1975 #define  SCB_CFSR_IBUSERR                    ((uint32_t)0x00000100)        /*!< Instruction bus error flag */
1976 #define  SCB_CFSR_PRECISERR                  ((uint32_t)0x00000200)        /*!< Precise data bus error */
1977 #define  SCB_CFSR_IMPRECISERR                ((uint32_t)0x00000400)        /*!< Imprecise data bus error */
1978 #define  SCB_CFSR_UNSTKERR                   ((uint32_t)0x00000800)        /*!< Unstacking error */
1979 #define  SCB_CFSR_STKERR                     ((uint32_t)0x00001000)        /*!< Stacking error */
1980 #define  SCB_CFSR_BFARVALID                  ((uint32_t)0x00008000)        /*!< Bus Fault Address Register address valid flag */
1981 /*!< UFSR */
1982 #define  SCB_CFSR_UNDEFINSTR                 ((uint32_t)0x00010000)        /*!< The processor attempt to execute an undefined instruction */
1983 #define  SCB_CFSR_INVSTATE                   ((uint32_t)0x00020000)        /*!< Invalid combination of EPSR and instruction */
1984 #define  SCB_CFSR_INVPC                      ((uint32_t)0x00040000)        /*!< Attempt to load EXC_RETURN into pc illegally */
1985 #define  SCB_CFSR_NOCP                       ((uint32_t)0x00080000)        /*!< Attempt to use a coprocessor instruction */
1986 #define  SCB_CFSR_UNALIGNED                  ((uint32_t)0x01000000)        /*!< Fault occurs when there is an attempt to make an unaligned memory access */
1987 #define  SCB_CFSR_DIVBYZERO                  ((uint32_t)0x02000000)        /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
1988
1989 /*******************  Bit definition for SCB_HFSR register  *******************/
1990 #define  SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)        /*!< Fault occurs because of vector table read on exception processing */
1991 #define  SCB_HFSR_FORCED                     ((uint32_t)0x40000000)        /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
1992 #define  SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)        /*!< Fault related to debug */
1993
1994 /*******************  Bit definition for SCB_DFSR register  *******************/
1995 #define  SCB_DFSR_HALTED                     ((uint32_t)0x00000001)        /*!< Halt request flag */
1996 #define  SCB_DFSR_BKPT                       ((uint32_t)0x00000002)        /*!< BKPT flag */
1997 #define  SCB_DFSR_DWTTRAP                    ((uint32_t)0x00000004)        /*!< Data Watchpoint and Trace (DWT) flag */
1998 #define  SCB_DFSR_VCATCH                     ((uint32_t)0x00000008)        /*!< Vector catch flag */
1999 #define  SCB_DFSR_EXTERNAL                   ((uint32_t)0x00000010)        /*!< External debug request flag */
2000
2001 /*******************  Bit definition for SCB_MMFAR register  ******************/
2002 #define  SCB_MMFAR_ADDRESS                   ((uint32_t)0xFFFFFFFF)        /*!< Mem Manage fault address field */
2003
2004 /*******************  Bit definition for SCB_BFAR register  *******************/
2005 #define  SCB_BFAR_ADDRESS                    ((uint32_t)0xFFFFFFFF)        /*!< Bus fault address field */
2006
2007 /*******************  Bit definition for SCB_afsr register  *******************/
2008 #define  SCB_AFSR_IMPDEF                     ((uint32_t)0xFFFFFFFF)        /*!< Implementation defined */
2009
2010 /******************************************************************************/
2011 /*                                                                            */
2012 /*                    External Interrupt/Event Controller                     */
2013 /*                                                                            */
2014 /******************************************************************************/
2015
2016 /*******************  Bit definition for EXTI_IMR register  *******************/
2017 #define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
2018 #define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
2019 #define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
2020 #define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
2021 #define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
2022 #define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
2023 #define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
2024 #define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
2025 #define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
2026 #define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
2027 #define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
2028 #define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
2029 #define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
2030 #define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
2031 #define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
2032 #define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
2033 #define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
2034 #define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
2035 #define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
2036 #define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
2037
2038 /*******************  Bit definition for EXTI_EMR register  *******************/
2039 #define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
2040 #define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
2041 #define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
2042 #define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
2043 #define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
2044 #define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
2045 #define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
2046 #define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
2047 #define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
2048 #define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
2049 #define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
2050 #define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
2051 #define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
2052 #define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
2053 #define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
2054 #define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
2055 #define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
2056 #define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
2057 #define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
2058 #define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
2059
2060 /******************  Bit definition for EXTI_RTSR register  *******************/
2061 #define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
2062 #define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
2063 #define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
2064 #define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
2065 #define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
2066 #define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
2067 #define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
2068 #define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
2069 #define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
2070 #define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
2071 #define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
2072 #define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
2073 #define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
2074 #define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
2075 #define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
2076 #define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
2077 #define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
2078 #define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
2079 #define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
2080 #define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
2081
2082 /******************  Bit definition for EXTI_FTSR register  *******************/
2083 #define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
2084 #define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
2085 #define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
2086 #define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
2087 #define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
2088 #define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
2089 #define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
2090 #define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
2091 #define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
2092 #define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
2093 #define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
2094 #define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
2095 #define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
2096 #define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
2097 #define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
2098 #define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
2099 #define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
2100 #define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
2101 #define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
2102 #define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
2103
2104 /******************  Bit definition for EXTI_SWIER register  ******************/
2105 #define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
2106 #define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
2107 #define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
2108 #define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
2109 #define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
2110 #define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
2111 #define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
2112 #define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
2113 #define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
2114 #define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
2115 #define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
2116 #define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
2117 #define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
2118 #define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
2119 #define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
2120 #define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
2121 #define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
2122 #define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
2123 #define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
2124 #define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
2125
2126 /*******************  Bit definition for EXTI_PR register  ********************/
2127 #define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit for line 0 */
2128 #define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit for line 1 */
2129 #define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit for line 2 */
2130 #define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit for line 3 */
2131 #define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit for line 4 */
2132 #define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit for line 5 */
2133 #define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit for line 6 */
2134 #define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit for line 7 */
2135 #define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit for line 8 */
2136 #define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit for line 9 */
2137 #define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit for line 10 */
2138 #define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit for line 11 */
2139 #define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit for line 12 */
2140 #define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit for line 13 */
2141 #define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit for line 14 */
2142 #define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit for line 15 */
2143 #define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit for line 16 */
2144 #define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit for line 17 */
2145 #define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit for line 18 */
2146 #define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit for line 19 */
2147
2148 /******************************************************************************/
2149 /*                                                                            */
2150 /*                             DMA Controller                                 */
2151 /*                                                                            */
2152 /******************************************************************************/
2153
2154 /*******************  Bit definition for DMA_ISR register  ********************/
2155 #define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag */
2156 #define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag */
2157 #define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag */
2158 #define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag */
2159 #define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag */
2160 #define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag */
2161 #define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag */
2162 #define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag */
2163 #define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag */
2164 #define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag */
2165 #define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag */
2166 #define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag */
2167 #define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag */
2168 #define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag */
2169 #define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag */
2170 #define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag */
2171 #define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag */
2172 #define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag */
2173 #define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag */
2174 #define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag */
2175 #define  DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag */
2176 #define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag */
2177 #define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag */
2178 #define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag */
2179 #define  DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag */
2180 #define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag */
2181 #define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag */
2182 #define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag */
2183
2184 /*******************  Bit definition for DMA_IFCR register  *******************/
2185 #define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear */
2186 #define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear */
2187 #define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear */
2188 #define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear */
2189 #define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear */
2190 #define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear */
2191 #define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear */
2192 #define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear */
2193 #define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear */
2194 #define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear */
2195 #define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear */
2196 #define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear */
2197 #define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear */
2198 #define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear */
2199 #define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear */
2200 #define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear */
2201 #define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear */
2202 #define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear */
2203 #define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear */
2204 #define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear */
2205 #define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear */
2206 #define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear */
2207 #define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear */
2208 #define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear */
2209 #define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear */
2210 #define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear */
2211 #define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear */
2212 #define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear */
2213
2214 /*******************  Bit definition for DMA_CCR register   *******************/
2215 #define  DMA_CCR_EN                          ((uint32_t)0x00000001)        /*!< Channel enable */
2216 #define  DMA_CCR_TCIE                        ((uint32_t)0x00000002)        /*!< Transfer complete interrupt enable */
2217 #define  DMA_CCR_HTIE                        ((uint32_t)0x00000004)        /*!< Half Transfer interrupt enable */
2218 #define  DMA_CCR_TEIE                        ((uint32_t)0x00000008)        /*!< Transfer error interrupt enable */
2219 #define  DMA_CCR_DIR                         ((uint32_t)0x00000010)        /*!< Data transfer direction */
2220 #define  DMA_CCR_CIRC                        ((uint32_t)0x00000020)        /*!< Circular mode */
2221 #define  DMA_CCR_PINC                        ((uint32_t)0x00000040)        /*!< Peripheral increment mode */
2222 #define  DMA_CCR_MINC                        ((uint32_t)0x00000080)        /*!< Memory increment mode */
2223
2224 #define  DMA_CCR_PSIZE                       ((uint32_t)0x00000300)        /*!< PSIZE[1:0] bits (Peripheral size) */
2225 #define  DMA_CCR_PSIZE_0                     ((uint32_t)0x00000100)        /*!< Bit 0 */
2226 #define  DMA_CCR_PSIZE_1                     ((uint32_t)0x00000200)        /*!< Bit 1 */
2227
2228 #define  DMA_CCR_MSIZE                       ((uint32_t)0x00000C00)        /*!< MSIZE[1:0] bits (Memory size) */
2229 #define  DMA_CCR_MSIZE_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
2230 #define  DMA_CCR_MSIZE_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
2231
2232 #define  DMA_CCR_PL                          ((uint32_t)0x00003000)        /*!< PL[1:0] bits(Channel Priority level) */
2233 #define  DMA_CCR_PL_0                        ((uint32_t)0x00001000)        /*!< Bit 0 */
2234 #define  DMA_CCR_PL_1                        ((uint32_t)0x00002000)        /*!< Bit 1 */
2235
2236 #define  DMA_CCR_MEM2MEM                     ((uint32_t)0x00004000)        /*!< Memory to memory mode */
2237
2238 /******************  Bit definition for DMA_CNDTR  register  ******************/
2239 #define  DMA_CNDTR_NDT                       ((uint32_t)0x0000FFFF)            /*!< Number of data to Transfer */
2240
2241 /******************  Bit definition for DMA_CPAR  register  *******************/
2242 #define  DMA_CPAR_PA                         ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
2243
2244 /******************  Bit definition for DMA_CMAR  register  *******************/
2245 #define  DMA_CMAR_MA                         ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
2246
2247 /******************************************************************************/
2248 /*                                                                            */
2249 /*                        Analog to Digital Converter                         */
2250 /*                                                                            */
2251 /******************************************************************************/
2252
2253 /********************  Bit definition for ADC_SR register  ********************/
2254 #define  ADC_SR_AWD                          ((uint32_t)0x00000001)        /*!< Analog watchdog flag */
2255 #define  ADC_SR_EOC                          ((uint32_t)0x00000002)        /*!< End of conversion */
2256 #define  ADC_SR_JEOC                         ((uint32_t)0x00000004)        /*!< Injected channel end of conversion */
2257 #define  ADC_SR_JSTRT                        ((uint32_t)0x00000008)        /*!< Injected channel Start flag */
2258 #define  ADC_SR_STRT                         ((uint32_t)0x00000010)        /*!< Regular channel Start flag */
2259
2260 /*******************  Bit definition for ADC_CR1 register  ********************/
2261 #define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)        /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
2262 #define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
2263 #define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
2264 #define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
2265 #define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
2266 #define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
2267
2268 #define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)        /*!< Interrupt enable for EOC */
2269 #define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)        /*!< Analog Watchdog interrupt enable */
2270 #define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)        /*!< Interrupt enable for injected channels */
2271 #define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)        /*!< Scan mode */
2272 #define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)        /*!< Enable the watchdog on a single channel in scan mode */
2273 #define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)        /*!< Automatic injected group conversion */
2274 #define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)        /*!< Discontinuous mode on regular channels */
2275 #define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)        /*!< Discontinuous mode on injected channels */
2276
2277 #define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)        /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
2278 #define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)        /*!< Bit 0 */
2279 #define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)        /*!< Bit 1 */
2280 #define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)        /*!< Bit 2 */
2281
2282 #define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)        /*!< Analog watchdog enable on injected channels */
2283 #define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)        /*!< Analog watchdog enable on regular channels */
2284
2285
2286 /*******************  Bit definition for ADC_CR2 register  ********************/
2287 #define  ADC_CR2_ADON                        ((uint32_t)0x00000001)        /*!< A/D Converter ON / OFF */
2288 #define  ADC_CR2_CONT                        ((uint32_t)0x00000002)        /*!< Continuous Conversion */
2289 #define  ADC_CR2_CAL                         ((uint32_t)0x00000004)        /*!< A/D Calibration */
2290 #define  ADC_CR2_RSTCAL                      ((uint32_t)0x00000008)        /*!< Reset Calibration */
2291 #define  ADC_CR2_DMA                         ((uint32_t)0x00000100)        /*!< Direct Memory access mode */
2292 #define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)        /*!< Data Alignment */
2293
2294 #define  ADC_CR2_JEXTSEL                     ((uint32_t)0x00007000)        /*!< JEXTSEL[2:0] bits (External event select for injected group) */
2295 #define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
2296 #define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
2297 #define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00004000)        /*!< Bit 2 */
2298
2299 #define  ADC_CR2_JEXTTRIG                    ((uint32_t)0x00008000)        /*!< External Trigger Conversion mode for injected channels */
2300
2301 #define  ADC_CR2_EXTSEL                      ((uint32_t)0x000E0000)        /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
2302 #define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x00020000)        /*!< Bit 0 */
2303 #define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x00040000)        /*!< Bit 1 */
2304 #define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x00080000)        /*!< Bit 2 */
2305
2306 #define  ADC_CR2_EXTTRIG                     ((uint32_t)0x00100000)        /*!< External Trigger Conversion mode for regular channels */
2307 #define  ADC_CR2_JSWSTART                    ((uint32_t)0x00200000)        /*!< Start Conversion of injected channels */
2308 #define  ADC_CR2_SWSTART                     ((uint32_t)0x00400000)        /*!< Start Conversion of regular channels */
2309 #define  ADC_CR2_TSVREFE                     ((uint32_t)0x00800000)        /*!< Temperature Sensor and VREFINT Enable */
2310
2311 /******************  Bit definition for ADC_SMPR1 register  *******************/
2312 #define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007)        /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
2313 #define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001)        /*!< Bit 0 */
2314 #define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002)        /*!< Bit 1 */
2315 #define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004)        /*!< Bit 2 */
2316
2317 #define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038)        /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
2318 #define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
2319 #define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
2320 #define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */
2321
2322 #define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0)        /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
2323 #define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040)        /*!< Bit 0 */
2324 #define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080)        /*!< Bit 1 */
2325 #define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100)        /*!< Bit 2 */
2326
2327 #define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00)        /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
2328 #define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200)        /*!< Bit 0 */
2329 #define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400)        /*!< Bit 1 */
2330 #define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800)        /*!< Bit 2 */
2331
2332 #define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000)        /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
2333 #define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
2334 #define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
2335 #define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000)        /*!< Bit 2 */
2336
2337 #define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000)        /*!< SMP15[2:0] bits (Channel 15 Sample time selection) */
2338 #define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000)        /*!< Bit 0 */
2339 #define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */
2340 #define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000)        /*!< Bit 2 */
2341
2342 #define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000)        /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
2343 #define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
2344 #define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
2345 #define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
2346
2347 #define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000)        /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
2348 #define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */
2349 #define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */
2350 #define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */
2351
2352 /******************  Bit definition for ADC_SMPR2 register  *******************/
2353 #define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007)        /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
2354 #define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
2355 #define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
2356 #define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
2357
2358 #define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038)        /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
2359 #define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008)        /*!< Bit 0 */
2360 #define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010)        /*!< Bit 1 */
2361 #define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020)        /*!< Bit 2 */
2362
2363 #define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0)        /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
2364 #define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040)        /*!< Bit 0 */
2365 #define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080)        /*!< Bit 1 */
2366 #define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100)        /*!< Bit 2 */
2367
2368 #define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00)        /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
2369 #define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
2370 #define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
2371 #define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
2372
2373 #define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000)        /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
2374 #define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000)        /*!< Bit 0 */
2375 #define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000)        /*!< Bit 1 */
2376 #define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000)        /*!< Bit 2 */
2377
2378 #define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000)        /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
2379 #define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000)        /*!< Bit 0 */
2380 #define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000)        /*!< Bit 1 */
2381 #define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000)        /*!< Bit 2 */
2382
2383 #define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000)        /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
2384 #define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
2385 #define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
2386 #define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000)        /*!< Bit 2 */
2387
2388 #define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000)        /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
2389 #define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000)        /*!< Bit 0 */
2390 #define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000)        /*!< Bit 1 */
2391 #define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000)        /*!< Bit 2 */
2392
2393 #define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000)        /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
2394 #define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
2395 #define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
2396 #define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000)        /*!< Bit 2 */
2397
2398 #define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000)        /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
2399 #define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000)        /*!< Bit 0 */
2400 #define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000)        /*!< Bit 1 */
2401 #define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000)        /*!< Bit 2 */
2402
2403 /******************  Bit definition for ADC_JOFR1 register  *******************/
2404 #define  ADC_JOFR1_JOFFSET1                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 1 */
2405
2406 /******************  Bit definition for ADC_JOFR2 register  *******************/
2407 #define  ADC_JOFR2_JOFFSET2                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 2 */
2408
2409 /******************  Bit definition for ADC_JOFR3 register  *******************/
2410 #define  ADC_JOFR3_JOFFSET3                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 3 */
2411
2412 /******************  Bit definition for ADC_JOFR4 register  *******************/
2413 #define  ADC_JOFR4_JOFFSET4                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 4 */
2414
2415 /*******************  Bit definition for ADC_HTR register  ********************/
2416 #define  ADC_HTR_HT                          ((uint32_t)0x00000FFF)        /*!< Analog watchdog high threshold */
2417
2418 /*******************  Bit definition for ADC_LTR register  ********************/
2419 #define  ADC_LTR_LT                          ((uint32_t)0x00000FFF)        /*!< Analog watchdog low threshold */
2420
2421 /*******************  Bit definition for ADC_SQR1 register  *******************/
2422 #define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001F)        /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
2423 #define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
2424 #define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
2425 #define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
2426 #define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
2427 #define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
2428
2429 #define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0)        /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
2430 #define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
2431 #define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
2432 #define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
2433 #define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
2434 #define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
2435
2436 #define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00)        /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
2437 #define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
2438 #define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
2439 #define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
2440 #define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
2441 #define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
2442
2443 #define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000)        /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
2444 #define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
2445 #define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
2446 #define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
2447 #define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
2448 #define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
2449
2450 #define  ADC_SQR1_L                          ((uint32_t)0x00F00000)        /*!< L[3:0] bits (Regular channel sequence length) */
2451 #define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!< Bit 0 */
2452 #define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!< Bit 1 */
2453 #define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!< Bit 2 */
2454 #define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!< Bit 3 */
2455
2456 /*******************  Bit definition for ADC_SQR2 register  *******************/
2457 #define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001F)        /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
2458 #define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
2459 #define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
2460 #define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
2461 #define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
2462 #define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
2463
2464 #define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0)        /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
2465 #define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
2466 #define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
2467 #define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
2468 #define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
2469 #define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
2470
2471 #define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00)        /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
2472 #define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
2473 #define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
2474 #define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
2475 #define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
2476 #define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
2477
2478 #define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000)        /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
2479 #define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
2480 #define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
2481 #define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
2482 #define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
2483 #define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
2484
2485 #define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000)        /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
2486 #define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000)        /*!< Bit 0 */
2487 #define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000)        /*!< Bit 1 */
2488 #define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000)        /*!< Bit 2 */
2489 #define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000)        /*!< Bit 3 */
2490 #define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000)        /*!< Bit 4 */
2491
2492 #define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000)        /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
2493 #define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000)        /*!< Bit 0 */
2494 #define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000)        /*!< Bit 1 */
2495 #define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000)        /*!< Bit 2 */
2496 #define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000)        /*!< Bit 3 */
2497 #define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000)        /*!< Bit 4 */
2498
2499 /*******************  Bit definition for ADC_SQR3 register  *******************/
2500 #define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001F)        /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
2501 #define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
2502 #define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
2503 #define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
2504 #define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
2505 #define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
2506
2507 #define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0)        /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
2508 #define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
2509 #define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
2510 #define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
2511 #define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
2512 #define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
2513
2514 #define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00)        /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
2515 #define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
2516 #define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
2517 #define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
2518 #define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
2519 #define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
2520
2521 #define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000)        /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
2522 #define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000)        /*!< Bit 0 */
2523 #define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000)        /*!< Bit 1 */
2524 #define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000)        /*!< Bit 2 */
2525 #define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000)        /*!< Bit 3 */
2526 #define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000)        /*!< Bit 4 */
2527
2528 #define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000)        /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
2529 #define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000)        /*!< Bit 0 */
2530 #define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000)        /*!< Bit 1 */
2531 #define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000)        /*!< Bit 2 */
2532 #define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000)        /*!< Bit 3 */
2533 #define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000)        /*!< Bit 4 */
2534
2535 #define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000)        /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
2536 #define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000)        /*!< Bit 0 */
2537 #define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000)        /*!< Bit 1 */
2538 #define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000)        /*!< Bit 2 */
2539 #define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000)        /*!< Bit 3 */
2540 #define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000)        /*!< Bit 4 */
2541
2542 /*******************  Bit definition for ADC_JSQR register  *******************/
2543 #define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */
2544 #define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
2545 #define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
2546 #define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
2547 #define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
2548 #define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
2549
2550 #define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
2551 #define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
2552 #define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
2553 #define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
2554 #define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
2555 #define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
2556
2557 #define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
2558 #define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
2559 #define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
2560 #define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
2561 #define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
2562 #define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
2563
2564 #define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
2565 #define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
2566 #define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
2567 #define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
2568 #define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
2569 #define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
2570
2571 #define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!< JL[1:0] bits (Injected Sequence length) */
2572 #define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!< Bit 0 */
2573 #define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!< Bit 1 */
2574
2575 /*******************  Bit definition for ADC_JDR1 register  *******************/
2576 #define  ADC_JDR1_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */
2577
2578 /*******************  Bit definition for ADC_JDR2 register  *******************/
2579 #define  ADC_JDR2_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */
2580
2581 /*******************  Bit definition for ADC_JDR3 register  *******************/
2582 #define  ADC_JDR3_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */
2583
2584 /*******************  Bit definition for ADC_JDR4 register  *******************/
2585 #define  ADC_JDR4_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */
2586
2587 /********************  Bit definition for ADC_DR register  ********************/
2588 #define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */
2589 /******************************************************************************/
2590 /*                                                                            */
2591 /*                      Digital to Analog Converter                           */
2592 /*                                                                            */
2593 /******************************************************************************/
2594
2595 /********************  Bit definition for DAC_CR register  ********************/
2596 #define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!< DAC channel1 enable */
2597 #define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!< DAC channel1 output buffer disable */
2598 #define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!< DAC channel1 Trigger enable */
2599
2600 #define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
2601 #define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!< Bit 0 */
2602 #define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!< Bit 1 */
2603 #define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!< Bit 2 */
2604
2605 #define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
2606 #define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!< Bit 0 */
2607 #define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!< Bit 1 */
2608
2609 #define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
2610 #define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!< Bit 0 */
2611 #define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!< Bit 1 */
2612 #define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!< Bit 2 */
2613 #define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!< Bit 3 */
2614
2615 #define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!< DAC channel1 DMA enable */
2616 #define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!< DAC channel2 enable */
2617 #define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!< DAC channel2 output buffer disable */
2618 #define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!< DAC channel2 Trigger enable */
2619
2620 #define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
2621 #define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!< Bit 0 */
2622 #define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!< Bit 1 */
2623 #define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!< Bit 2 */
2624
2625 #define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
2626 #define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!< Bit 0 */
2627 #define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!< Bit 1 */
2628
2629 #define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
2630 #define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
2631 #define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
2632 #define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
2633 #define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!< Bit 3 */
2634
2635 #define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!< DAC channel2 DMA enabled */
2636
2637  #define  DAC_CR_DMAUDRIE1                   ((uint32_t)0x00002000)        /*!< DAC channel1 DMA underrun interrupt enable */
2638  #define  DAC_CR_DMAUDRIE2                   ((uint32_t)0x20000000)        /*!< DAC channel2 DMA underrun interrupt enable */
2639
2640 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
2641 #define  DAC_SWTRIGR_SWTRIG1                 ((uint32_t)0x00000001)        /*!< DAC channel1 software trigger */
2642 #define  DAC_SWTRIGR_SWTRIG2                 ((uint32_t)0x00000002)        /*!< DAC channel2 software trigger */
2643
2644 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
2645 #define  DAC_DHR12R1_DACC1DHR                ((uint32_t)0x00000FFF)        /*!< DAC channel1 12-bit Right aligned data */
2646
2647 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
2648 #define  DAC_DHR12L1_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!< DAC channel1 12-bit Left aligned data */
2649
2650 /******************  Bit definition for DAC_DHR8R1 register  ******************/
2651 #define  DAC_DHR8R1_DACC1DHR                 ((uint32_t)0x000000FF)        /*!< DAC channel1 8-bit Right aligned data */
2652
2653 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
2654 #define  DAC_DHR12R2_DACC2DHR                ((uint32_t)0x00000FFF)        /*!< DAC channel2 12-bit Right aligned data */
2655
2656 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
2657 #define  DAC_DHR12L2_DACC2DHR                ((uint32_t)0x0000FFF0)        /*!< DAC channel2 12-bit Left aligned data */
2658
2659 /******************  Bit definition for DAC_DHR8R2 register  ******************/
2660 #define  DAC_DHR8R2_DACC2DHR                 ((uint32_t)0x000000FF)        /*!< DAC channel2 8-bit Right aligned data */
2661
2662 /*****************  Bit definition for DAC_DHR12RD register  ******************/
2663 #define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!< DAC channel1 12-bit Right aligned data */
2664 #define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!< DAC channel2 12-bit Right aligned data */
2665
2666 /*****************  Bit definition for DAC_DHR12LD register  ******************/
2667 #define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!< DAC channel1 12-bit Left aligned data */
2668 #define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!< DAC channel2 12-bit Left aligned data */
2669
2670 /******************  Bit definition for DAC_DHR8RD register  ******************/
2671 #define  DAC_DHR8RD_DACC1DHR                 ((uint32_t)0x000000FF)        /*!< DAC channel1 8-bit Right aligned data */
2672 #define  DAC_DHR8RD_DACC2DHR                 ((uint32_t)0x0000FF00)        /*!< DAC channel2 8-bit Right aligned data */
2673
2674 /*******************  Bit definition for DAC_DOR1 register  *******************/
2675 #define  DAC_DOR1_DACC1DOR                   ((uint32_t)0x00000FFF)        /*!< DAC channel1 data output */
2676
2677 /*******************  Bit definition for DAC_DOR2 register  *******************/
2678 #define  DAC_DOR2_DACC2DOR                   ((uint32_t)0x00000FFF)        /*!< DAC channel2 data output */
2679
2680 /********************  Bit definition for DAC_SR register  ********************/
2681 #define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!< DAC channel1 DMA underrun flag */
2682 #define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!< DAC channel2 DMA underrun flag */
2683
2684 /******************************************************************************/
2685 /*                                                                            */
2686 /*                                    CEC                                     */
2687 /*                                                                            */
2688 /******************************************************************************/
2689 /********************  Bit definition for CEC_CFGR register  ******************/
2690 #define  CEC_CFGR_PE              ((uint32_t)0x00000001)     /*!<  Peripheral Enable */
2691 #define  CEC_CFGR_IE              ((uint32_t)0x00000002)     /*!<  Interrupt Enable */
2692 #define  CEC_CFGR_BTEM            ((uint32_t)0x00000004)     /*!<  Bit Timing Error Mode */
2693 #define  CEC_CFGR_BPEM            ((uint32_t)0x00000008)     /*!<  Bit Period Error Mode */
2694
2695 /********************  Bit definition for CEC_OAR register  ******************/
2696 #define  CEC_OAR_OA               ((uint32_t)0x0000000F)     /*!<  OA[3:0]: Own Address */
2697 #define  CEC_OAR_OA_0             ((uint32_t)0x00000001)     /*!<  Bit 0 */
2698 #define  CEC_OAR_OA_1             ((uint32_t)0x00000002)     /*!<  Bit 1 */
2699 #define  CEC_OAR_OA_2             ((uint32_t)0x00000004)     /*!<  Bit 2 */
2700 #define  CEC_OAR_OA_3             ((uint32_t)0x00000008)     /*!<  Bit 3 */
2701
2702 /********************  Bit definition for CEC_PRES register  ******************/
2703 #define  CEC_PRES_PRES            ((uint32_t)0x00003FFF)     /*!<  Prescaler Counter Value */
2704
2705 /********************  Bit definition for CEC_ESR register  ******************/
2706 #define  CEC_ESR_BTE              ((uint32_t)0x00000001)     /*!<  Bit Timing Error */
2707 #define  CEC_ESR_BPE              ((uint32_t)0x00000002)     /*!<  Bit Period Error */
2708 #define  CEC_ESR_RBTFE            ((uint32_t)0x00000004)     /*!<  Rx Block Transfer Finished Error */
2709 #define  CEC_ESR_SBE              ((uint32_t)0x00000008)     /*!<  Start Bit Error */
2710 #define  CEC_ESR_ACKE             ((uint32_t)0x00000010)     /*!<  Block Acknowledge Error */
2711 #define  CEC_ESR_LINE             ((uint32_t)0x00000020)     /*!<  Line Error */
2712 #define  CEC_ESR_TBTFE            ((uint32_t)0x00000040)     /*!<  Tx Block Transfer Finished Error */
2713
2714 /********************  Bit definition for CEC_CSR register  ******************/
2715 #define  CEC_CSR_TSOM             ((uint32_t)0x00000001)     /*!<  Tx Start Of Message */
2716 #define  CEC_CSR_TEOM             ((uint32_t)0x00000002)     /*!<  Tx End Of Message */
2717 #define  CEC_CSR_TERR             ((uint32_t)0x00000004)     /*!<  Tx Error */
2718 #define  CEC_CSR_TBTRF            ((uint32_t)0x00000008)     /*!<  Tx Byte Transfer Request or Block Transfer Finished */
2719 #define  CEC_CSR_RSOM             ((uint32_t)0x00000010)     /*!<  Rx Start Of Message */
2720 #define  CEC_CSR_REOM             ((uint32_t)0x00000020)     /*!<  Rx End Of Message */
2721 #define  CEC_CSR_RERR             ((uint32_t)0x00000040)     /*!<  Rx Error */
2722 #define  CEC_CSR_RBTF             ((uint32_t)0x00000080)     /*!<  Rx Block Transfer Finished */
2723
2724 /********************  Bit definition for CEC_TXD register  ******************/
2725 #define  CEC_TXD_TXD              ((uint32_t)0x000000FF)     /*!<  Tx Data register */
2726
2727 /********************  Bit definition for CEC_RXD register  ******************/
2728 #define  CEC_RXD_RXD              ((uint32_t)0x000000FF)     /*!<  Rx Data register */
2729
2730 /*****************************************************************************/
2731 /*                                                                           */
2732 /*                               Timers (TIM)                                */
2733 /*                                                                           */
2734 /*****************************************************************************/
2735 /*******************  Bit definition for TIM_CR1 register  *******************/
2736 #define  TIM_CR1_CEN                         ((uint32_t)0x00000001)            /*!<Counter enable */
2737 #define  TIM_CR1_UDIS                        ((uint32_t)0x00000002)            /*!<Update disable */
2738 #define  TIM_CR1_URS                         ((uint32_t)0x00000004)            /*!<Update request source */
2739 #define  TIM_CR1_OPM                         ((uint32_t)0x00000008)            /*!<One pulse mode */
2740 #define  TIM_CR1_DIR                         ((uint32_t)0x00000010)            /*!<Direction */
2741
2742 #define  TIM_CR1_CMS                         ((uint32_t)0x00000060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
2743 #define  TIM_CR1_CMS_0                       ((uint32_t)0x00000020)            /*!<Bit 0 */
2744 #define  TIM_CR1_CMS_1                       ((uint32_t)0x00000040)            /*!<Bit 1 */
2745
2746 #define  TIM_CR1_ARPE                        ((uint32_t)0x00000080)            /*!<Auto-reload preload enable */
2747
2748 #define  TIM_CR1_CKD                         ((uint32_t)0x00000300)            /*!<CKD[1:0] bits (clock division) */
2749 #define  TIM_CR1_CKD_0                       ((uint32_t)0x00000100)            /*!<Bit 0 */
2750 #define  TIM_CR1_CKD_1                       ((uint32_t)0x00000200)            /*!<Bit 1 */
2751
2752 /*******************  Bit definition for TIM_CR2 register  *******************/
2753 #define  TIM_CR2_CCPC                        ((uint32_t)0x00000001)            /*!<Capture/Compare Preloaded Control */
2754 #define  TIM_CR2_CCUS                        ((uint32_t)0x00000004)            /*!<Capture/Compare Control Update Selection */
2755 #define  TIM_CR2_CCDS                        ((uint32_t)0x00000008)            /*!<Capture/Compare DMA Selection */
2756
2757 #define  TIM_CR2_MMS                         ((uint32_t)0x00000070)            /*!<MMS[2:0] bits (Master Mode Selection) */
2758 #define  TIM_CR2_MMS_0                       ((uint32_t)0x00000010)            /*!<Bit 0 */
2759 #define  TIM_CR2_MMS_1                       ((uint32_t)0x00000020)            /*!<Bit 1 */
2760 #define  TIM_CR2_MMS_2                       ((uint32_t)0x00000040)            /*!<Bit 2 */
2761
2762 #define  TIM_CR2_TI1S                        ((uint32_t)0x00000080)            /*!<TI1 Selection */
2763 #define  TIM_CR2_OIS1                        ((uint32_t)0x00000100)            /*!<Output Idle state 1 (OC1 output) */
2764 #define  TIM_CR2_OIS1N                       ((uint32_t)0x00000200)            /*!<Output Idle state 1 (OC1N output) */
2765 #define  TIM_CR2_OIS2                        ((uint32_t)0x00000400)            /*!<Output Idle state 2 (OC2 output) */
2766 #define  TIM_CR2_OIS2N                       ((uint32_t)0x00000800)            /*!<Output Idle state 2 (OC2N output) */
2767 #define  TIM_CR2_OIS3                        ((uint32_t)0x00001000)            /*!<Output Idle state 3 (OC3 output) */
2768 #define  TIM_CR2_OIS3N                       ((uint32_t)0x00002000)            /*!<Output Idle state 3 (OC3N output) */
2769 #define  TIM_CR2_OIS4                        ((uint32_t)0x00004000)            /*!<Output Idle state 4 (OC4 output) */
2770
2771 /*******************  Bit definition for TIM_SMCR register  ******************/
2772 #define  TIM_SMCR_SMS                        ((uint32_t)0x00000007)            /*!<SMS[2:0] bits (Slave mode selection) */
2773 #define  TIM_SMCR_SMS_0                      ((uint32_t)0x00000001)            /*!<Bit 0 */
2774 #define  TIM_SMCR_SMS_1                      ((uint32_t)0x00000002)            /*!<Bit 1 */
2775 #define  TIM_SMCR_SMS_2                      ((uint32_t)0x00000004)            /*!<Bit 2 */
2776
2777 #define  TIM_SMCR_OCCS                       ((uint32_t)0x00000008)            /*!< OCREF clear selection */
2778
2779 #define  TIM_SMCR_TS                         ((uint32_t)0x00000070)            /*!<TS[2:0] bits (Trigger selection) */
2780 #define  TIM_SMCR_TS_0                       ((uint32_t)0x00000010)            /*!<Bit 0 */
2781 #define  TIM_SMCR_TS_1                       ((uint32_t)0x00000020)            /*!<Bit 1 */
2782 #define  TIM_SMCR_TS_2                       ((uint32_t)0x00000040)            /*!<Bit 2 */
2783
2784 #define  TIM_SMCR_MSM                        ((uint32_t)0x00000080)            /*!<Master/slave mode */
2785
2786 #define  TIM_SMCR_ETF                        ((uint32_t)0x00000F00)            /*!<ETF[3:0] bits (External trigger filter) */
2787 #define  TIM_SMCR_ETF_0                      ((uint32_t)0x00000100)            /*!<Bit 0 */
2788 #define  TIM_SMCR_ETF_1                      ((uint32_t)0x00000200)            /*!<Bit 1 */
2789 #define  TIM_SMCR_ETF_2                      ((uint32_t)0x00000400)            /*!<Bit 2 */
2790 #define  TIM_SMCR_ETF_3                      ((uint32_t)0x00000800)            /*!<Bit 3 */
2791
2792 #define  TIM_SMCR_ETPS                       ((uint32_t)0x00003000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
2793 #define  TIM_SMCR_ETPS_0                     ((uint32_t)0x00001000)            /*!<Bit 0 */
2794 #define  TIM_SMCR_ETPS_1                     ((uint32_t)0x00002000)            /*!<Bit 1 */
2795
2796 #define  TIM_SMCR_ECE                        ((uint32_t)0x00004000)            /*!<External clock enable */
2797 #define  TIM_SMCR_ETP                        ((uint32_t)0x00008000)            /*!<External trigger polarity */
2798
2799 /*******************  Bit definition for TIM_DIER register  ******************/
2800 #define  TIM_DIER_UIE                        ((uint32_t)0x00000001)            /*!<Update interrupt enable */
2801 #define  TIM_DIER_CC1IE                      ((uint32_t)0x00000002)            /*!<Capture/Compare 1 interrupt enable */
2802 #define  TIM_DIER_CC2IE                      ((uint32_t)0x00000004)            /*!<Capture/Compare 2 interrupt enable */
2803 #define  TIM_DIER_CC3IE                      ((uint32_t)0x00000008)            /*!<Capture/Compare 3 interrupt enable */
2804 #define  TIM_DIER_CC4IE                      ((uint32_t)0x00000010)            /*!<Capture/Compare 4 interrupt enable */
2805 #define  TIM_DIER_COMIE                      ((uint32_t)0x00000020)            /*!<COM interrupt enable */
2806 #define  TIM_DIER_TIE                        ((uint32_t)0x00000040)            /*!<Trigger interrupt enable */
2807 #define  TIM_DIER_BIE                        ((uint32_t)0x00000080)            /*!<Break interrupt enable */
2808 #define  TIM_DIER_UDE                        ((uint32_t)0x00000100)            /*!<Update DMA request enable */
2809 #define  TIM_DIER_CC1DE                      ((uint32_t)0x00000200)            /*!<Capture/Compare 1 DMA request enable */
2810 #define  TIM_DIER_CC2DE                      ((uint32_t)0x00000400)            /*!<Capture/Compare 2 DMA request enable */
2811 #define  TIM_DIER_CC3DE                      ((uint32_t)0x00000800)            /*!<Capture/Compare 3 DMA request enable */
2812 #define  TIM_DIER_CC4DE                      ((uint32_t)0x00001000)            /*!<Capture/Compare 4 DMA request enable */
2813 #define  TIM_DIER_COMDE                      ((uint32_t)0x00002000)            /*!<COM DMA request enable */
2814 #define  TIM_DIER_TDE                        ((uint32_t)0x00004000)            /*!<Trigger DMA request enable */
2815
2816 /********************  Bit definition for TIM_SR register  *******************/
2817 #define  TIM_SR_UIF                          ((uint32_t)0x00000001)            /*!<Update interrupt Flag */
2818 #define  TIM_SR_CC1IF                        ((uint32_t)0x00000002)            /*!<Capture/Compare 1 interrupt Flag */
2819 #define  TIM_SR_CC2IF                        ((uint32_t)0x00000004)            /*!<Capture/Compare 2 interrupt Flag */
2820 #define  TIM_SR_CC3IF                        ((uint32_t)0x00000008)            /*!<Capture/Compare 3 interrupt Flag */
2821 #define  TIM_SR_CC4IF                        ((uint32_t)0x00000010)            /*!<Capture/Compare 4 interrupt Flag */
2822 #define  TIM_SR_COMIF                        ((uint32_t)0x00000020)            /*!<COM interrupt Flag */
2823 #define  TIM_SR_TIF                          ((uint32_t)0x00000040)            /*!<Trigger interrupt Flag */
2824 #define  TIM_SR_BIF                          ((uint32_t)0x00000080)            /*!<Break interrupt Flag */
2825 #define  TIM_SR_CC1OF                        ((uint32_t)0x00000200)            /*!<Capture/Compare 1 Overcapture Flag */
2826 #define  TIM_SR_CC2OF                        ((uint32_t)0x00000400)            /*!<Capture/Compare 2 Overcapture Flag */
2827 #define  TIM_SR_CC3OF                        ((uint32_t)0x00000800)            /*!<Capture/Compare 3 Overcapture Flag */
2828 #define  TIM_SR_CC4OF                        ((uint32_t)0x00001000)            /*!<Capture/Compare 4 Overcapture Flag */
2829
2830 /*******************  Bit definition for TIM_EGR register  *******************/
2831 #define  TIM_EGR_UG                          ((uint32_t)0x00000001)               /*!<Update Generation */
2832 #define  TIM_EGR_CC1G                        ((uint32_t)0x00000002)               /*!<Capture/Compare 1 Generation */
2833 #define  TIM_EGR_CC2G                        ((uint32_t)0x00000004)               /*!<Capture/Compare 2 Generation */
2834 #define  TIM_EGR_CC3G                        ((uint32_t)0x00000008)               /*!<Capture/Compare 3 Generation */
2835 #define  TIM_EGR_CC4G                        ((uint32_t)0x00000010)               /*!<Capture/Compare 4 Generation */
2836 #define  TIM_EGR_COMG                        ((uint32_t)0x00000020)               /*!<Capture/Compare Control Update Generation */
2837 #define  TIM_EGR_TG                          ((uint32_t)0x00000040)               /*!<Trigger Generation */
2838 #define  TIM_EGR_BG                          ((uint32_t)0x00000080)               /*!<Break Generation */
2839
2840 /******************  Bit definition for TIM_CCMR1 register  ******************/
2841 #define  TIM_CCMR1_CC1S                      ((uint32_t)0x00000003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
2842 #define  TIM_CCMR1_CC1S_0                    ((uint32_t)0x00000001)            /*!<Bit 0 */
2843 #define  TIM_CCMR1_CC1S_1                    ((uint32_t)0x00000002)            /*!<Bit 1 */
2844
2845 #define  TIM_CCMR1_OC1FE                     ((uint32_t)0x00000004)            /*!<Output Compare 1 Fast enable */
2846 #define  TIM_CCMR1_OC1PE                     ((uint32_t)0x00000008)            /*!<Output Compare 1 Preload enable */
2847
2848 #define  TIM_CCMR1_OC1M                      ((uint32_t)0x00000070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
2849 #define  TIM_CCMR1_OC1M_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
2850 #define  TIM_CCMR1_OC1M_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
2851 #define  TIM_CCMR1_OC1M_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
2852
2853 #define  TIM_CCMR1_OC1CE                     ((uint32_t)0x00000080)            /*!<Output Compare 1Clear Enable */
2854
2855 #define  TIM_CCMR1_CC2S                      ((uint32_t)0x00000300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
2856 #define  TIM_CCMR1_CC2S_0                    ((uint32_t)0x00000100)            /*!<Bit 0 */
2857 #define  TIM_CCMR1_CC2S_1                    ((uint32_t)0x00000200)            /*!<Bit 1 */
2858
2859 #define  TIM_CCMR1_OC2FE                     ((uint32_t)0x00000400)            /*!<Output Compare 2 Fast enable */
2860 #define  TIM_CCMR1_OC2PE                     ((uint32_t)0x00000800)            /*!<Output Compare 2 Preload enable */
2861
2862 #define  TIM_CCMR1_OC2M                      ((uint32_t)0x00007000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
2863 #define  TIM_CCMR1_OC2M_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
2864 #define  TIM_CCMR1_OC2M_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
2865 #define  TIM_CCMR1_OC2M_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
2866
2867 #define  TIM_CCMR1_OC2CE                     ((uint32_t)0x00008000)            /*!<Output Compare 2 Clear Enable */
2868
2869 /*---------------------------------------------------------------------------*/
2870
2871 #define  TIM_CCMR1_IC1PSC                    ((uint32_t)0x0000000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
2872 #define  TIM_CCMR1_IC1PSC_0                  ((uint32_t)0x00000004)            /*!<Bit 0 */
2873 #define  TIM_CCMR1_IC1PSC_1                  ((uint32_t)0x00000008)            /*!<Bit 1 */
2874
2875 #define  TIM_CCMR1_IC1F                      ((uint32_t)0x000000F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
2876 #define  TIM_CCMR1_IC1F_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
2877 #define  TIM_CCMR1_IC1F_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
2878 #define  TIM_CCMR1_IC1F_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
2879 #define  TIM_CCMR1_IC1F_3                    ((uint32_t)0x00000080)            /*!<Bit 3 */
2880
2881 #define  TIM_CCMR1_IC2PSC                    ((uint32_t)0x00000C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
2882 #define  TIM_CCMR1_IC2PSC_0                  ((uint32_t)0x00000400)            /*!<Bit 0 */
2883 #define  TIM_CCMR1_IC2PSC_1                  ((uint32_t)0x00000800)            /*!<Bit 1 */
2884
2885 #define  TIM_CCMR1_IC2F                      ((uint32_t)0x0000F000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
2886 #define  TIM_CCMR1_IC2F_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
2887 #define  TIM_CCMR1_IC2F_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
2888 #define  TIM_CCMR1_IC2F_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
2889 #define  TIM_CCMR1_IC2F_3                    ((uint32_t)0x00008000)            /*!<Bit 3 */
2890
2891 /******************  Bit definition for TIM_CCMR2 register  ******************/
2892 #define  TIM_CCMR2_CC3S                      ((uint32_t)0x00000003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
2893 #define  TIM_CCMR2_CC3S_0                    ((uint32_t)0x00000001)            /*!<Bit 0 */
2894 #define  TIM_CCMR2_CC3S_1                    ((uint32_t)0x00000002)            /*!<Bit 1 */
2895
2896 #define  TIM_CCMR2_OC3FE                     ((uint32_t)0x00000004)            /*!<Output Compare 3 Fast enable */
2897 #define  TIM_CCMR2_OC3PE                     ((uint32_t)0x00000008)            /*!<Output Compare 3 Preload enable */
2898
2899 #define  TIM_CCMR2_OC3M                      ((uint32_t)0x00000070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
2900 #define  TIM_CCMR2_OC3M_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
2901 #define  TIM_CCMR2_OC3M_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
2902 #define  TIM_CCMR2_OC3M_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
2903
2904 #define  TIM_CCMR2_OC3CE                     ((uint32_t)0x00000080)            /*!<Output Compare 3 Clear Enable */
2905
2906 #define  TIM_CCMR2_CC4S                      ((uint32_t)0x00000300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
2907 #define  TIM_CCMR2_CC4S_0                    ((uint32_t)0x00000100)            /*!<Bit 0 */
2908 #define  TIM_CCMR2_CC4S_1                    ((uint32_t)0x00000200)            /*!<Bit 1 */
2909
2910 #define  TIM_CCMR2_OC4FE                     ((uint32_t)0x00000400)            /*!<Output Compare 4 Fast enable */
2911 #define  TIM_CCMR2_OC4PE                     ((uint32_t)0x00000800)            /*!<Output Compare 4 Preload enable */
2912
2913 #define  TIM_CCMR2_OC4M                      ((uint32_t)0x00007000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
2914 #define  TIM_CCMR2_OC4M_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
2915 #define  TIM_CCMR2_OC4M_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
2916 #define  TIM_CCMR2_OC4M_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
2917
2918 #define  TIM_CCMR2_OC4CE                     ((uint32_t)0x00008000)            /*!<Output Compare 4 Clear Enable */
2919
2920 /*---------------------------------------------------------------------------*/
2921
2922 #define  TIM_CCMR2_IC3PSC                    ((uint32_t)0x0000000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
2923 #define  TIM_CCMR2_IC3PSC_0                  ((uint32_t)0x00000004)            /*!<Bit 0 */
2924 #define  TIM_CCMR2_IC3PSC_1                  ((uint32_t)0x00000008)            /*!<Bit 1 */
2925
2926 #define  TIM_CCMR2_IC3F                      ((uint32_t)0x000000F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
2927 #define  TIM_CCMR2_IC3F_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
2928 #define  TIM_CCMR2_IC3F_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
2929 #define  TIM_CCMR2_IC3F_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
2930 #define  TIM_CCMR2_IC3F_3                    ((uint32_t)0x00000080)            /*!<Bit 3 */
2931
2932 #define  TIM_CCMR2_IC4PSC                    ((uint32_t)0x00000C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
2933 #define  TIM_CCMR2_IC4PSC_0                  ((uint32_t)0x00000400)            /*!<Bit 0 */
2934 #define  TIM_CCMR2_IC4PSC_1                  ((uint32_t)0x00000800)            /*!<Bit 1 */
2935
2936 #define  TIM_CCMR2_IC4F                      ((uint32_t)0x0000F000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
2937 #define  TIM_CCMR2_IC4F_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
2938 #define  TIM_CCMR2_IC4F_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
2939 #define  TIM_CCMR2_IC4F_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
2940 #define  TIM_CCMR2_IC4F_3                    ((uint32_t)0x00008000)            /*!<Bit 3 */
2941
2942 /*******************  Bit definition for TIM_CCER register  ******************/
2943 #define  TIM_CCER_CC1E                       ((uint32_t)0x00000001)            /*!<Capture/Compare 1 output enable */
2944 #define  TIM_CCER_CC1P                       ((uint32_t)0x00000002)            /*!<Capture/Compare 1 output Polarity */
2945 #define  TIM_CCER_CC1NE                      ((uint32_t)0x00000004)            /*!<Capture/Compare 1 Complementary output enable */
2946 #define  TIM_CCER_CC1NP                      ((uint32_t)0x00000008)            /*!<Capture/Compare 1 Complementary output Polarity */
2947 #define  TIM_CCER_CC2E                       ((uint32_t)0x00000010)            /*!<Capture/Compare 2 output enable */
2948 #define  TIM_CCER_CC2P                       ((uint32_t)0x00000020)            /*!<Capture/Compare 2 output Polarity */
2949 #define  TIM_CCER_CC2NE                      ((uint32_t)0x00000040)            /*!<Capture/Compare 2 Complementary output enable */
2950 #define  TIM_CCER_CC2NP                      ((uint32_t)0x00000080)            /*!<Capture/Compare 2 Complementary output Polarity */
2951 #define  TIM_CCER_CC3E                       ((uint32_t)0x00000100)            /*!<Capture/Compare 3 output enable */
2952 #define  TIM_CCER_CC3P                       ((uint32_t)0x00000200)            /*!<Capture/Compare 3 output Polarity */
2953 #define  TIM_CCER_CC3NE                      ((uint32_t)0x00000400)            /*!<Capture/Compare 3 Complementary output enable */
2954 #define  TIM_CCER_CC3NP                      ((uint32_t)0x00000800)            /*!<Capture/Compare 3 Complementary output Polarity */
2955 #define  TIM_CCER_CC4E                       ((uint32_t)0x00001000)            /*!<Capture/Compare 4 output enable */
2956 #define  TIM_CCER_CC4P                       ((uint32_t)0x00002000)            /*!<Capture/Compare 4 output Polarity */
2957 #define  TIM_CCER_CC4NP                      ((uint32_t)0x00008000)            /*!<Capture/Compare 4 Complementary output Polarity */
2958
2959 /*******************  Bit definition for TIM_CNT register  *******************/
2960 #define  TIM_CNT_CNT                         ((uint32_t)0xFFFFFFFF)            /*!<Counter Value */
2961
2962 /*******************  Bit definition for TIM_PSC register  *******************/
2963 #define  TIM_PSC_PSC                         ((uint32_t)0x0000FFFF)            /*!<Prescaler Value */
2964
2965 /*******************  Bit definition for TIM_ARR register  *******************/
2966 #define  TIM_ARR_ARR                         ((uint32_t)0xFFFFFFFF)            /*!<actual auto-reload Value */
2967
2968 /*******************  Bit definition for TIM_RCR register  *******************/
2969 #define  TIM_RCR_REP                         ((uint32_t)0x000000FF)               /*!<Repetition Counter Value */
2970
2971 /*******************  Bit definition for TIM_CCR1 register  ******************/
2972 #define  TIM_CCR1_CCR1                       ((uint32_t)0x0000FFFF)            /*!<Capture/Compare 1 Value */
2973
2974 /*******************  Bit definition for TIM_CCR2 register  ******************/
2975 #define  TIM_CCR2_CCR2                       ((uint32_t)0x0000FFFF)            /*!<Capture/Compare 2 Value */
2976
2977 /*******************  Bit definition for TIM_CCR3 register  ******************/
2978 #define  TIM_CCR3_CCR3                       ((uint32_t)0x0000FFFF)            /*!<Capture/Compare 3 Value */
2979
2980 /*******************  Bit definition for TIM_CCR4 register  ******************/
2981 #define  TIM_CCR4_CCR4                       ((uint32_t)0x0000FFFF)            /*!<Capture/Compare 4 Value */
2982
2983 /*******************  Bit definition for TIM_BDTR register  ******************/
2984 #define  TIM_BDTR_DTG                        ((uint32_t)0x000000FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
2985 #define  TIM_BDTR_DTG_0                      ((uint32_t)0x00000001)            /*!<Bit 0 */
2986 #define  TIM_BDTR_DTG_1                      ((uint32_t)0x00000002)            /*!<Bit 1 */
2987 #define  TIM_BDTR_DTG_2                      ((uint32_t)0x00000004)            /*!<Bit 2 */
2988 #define  TIM_BDTR_DTG_3                      ((uint32_t)0x00000008)            /*!<Bit 3 */
2989 #define  TIM_BDTR_DTG_4                      ((uint32_t)0x00000010)            /*!<Bit 4 */
2990 #define  TIM_BDTR_DTG_5                      ((uint32_t)0x00000020)            /*!<Bit 5 */
2991 #define  TIM_BDTR_DTG_6                      ((uint32_t)0x00000040)            /*!<Bit 6 */
2992 #define  TIM_BDTR_DTG_7                      ((uint32_t)0x00000080)            /*!<Bit 7 */
2993
2994 #define  TIM_BDTR_LOCK                       ((uint32_t)0x00000300)            /*!<LOCK[1:0] bits (Lock Configuration) */
2995 #define  TIM_BDTR_LOCK_0                     ((uint32_t)0x00000100)            /*!<Bit 0 */
2996 #define  TIM_BDTR_LOCK_1                     ((uint32_t)0x00000200)            /*!<Bit 1 */
2997
2998 #define  TIM_BDTR_OSSI                       ((uint32_t)0x00000400)            /*!<Off-State Selection for Idle mode */
2999 #define  TIM_BDTR_OSSR                       ((uint32_t)0x00000800)            /*!<Off-State Selection for Run mode */
3000 #define  TIM_BDTR_BKE                        ((uint32_t)0x00001000)            /*!<Break enable */
3001 #define  TIM_BDTR_BKP                        ((uint32_t)0x00002000)            /*!<Break Polarity */
3002 #define  TIM_BDTR_AOE                        ((uint32_t)0x00004000)            /*!<Automatic Output enable */
3003 #define  TIM_BDTR_MOE                        ((uint32_t)0x00008000)            /*!<Main Output enable */
3004
3005 /*******************  Bit definition for TIM_DCR register  *******************/
3006 #define  TIM_DCR_DBA                         ((uint32_t)0x0000001F)            /*!<DBA[4:0] bits (DMA Base Address) */
3007 #define  TIM_DCR_DBA_0                       ((uint32_t)0x00000001)            /*!<Bit 0 */
3008 #define  TIM_DCR_DBA_1                       ((uint32_t)0x00000002)            /*!<Bit 1 */
3009 #define  TIM_DCR_DBA_2                       ((uint32_t)0x00000004)            /*!<Bit 2 */
3010 #define  TIM_DCR_DBA_3                       ((uint32_t)0x00000008)            /*!<Bit 3 */
3011 #define  TIM_DCR_DBA_4                       ((uint32_t)0x00000010)            /*!<Bit 4 */
3012
3013 #define  TIM_DCR_DBL                         ((uint32_t)0x00001F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
3014 #define  TIM_DCR_DBL_0                       ((uint32_t)0x00000100)            /*!<Bit 0 */
3015 #define  TIM_DCR_DBL_1                       ((uint32_t)0x00000200)            /*!<Bit 1 */
3016 #define  TIM_DCR_DBL_2                       ((uint32_t)0x00000400)            /*!<Bit 2 */
3017 #define  TIM_DCR_DBL_3                       ((uint32_t)0x00000800)            /*!<Bit 3 */
3018 #define  TIM_DCR_DBL_4                       ((uint32_t)0x00001000)            /*!<Bit 4 */
3019
3020 /*******************  Bit definition for TIM_DMAR register  ******************/
3021 #define  TIM_DMAR_DMAB                       ((uint32_t)0x0000FFFF)            /*!<DMA register for burst accesses */
3022
3023 /*******************  Bit definition for TIM_OR register  ********************/
3024
3025 /******************************************************************************/
3026 /*                                                                            */
3027 /*                             Real-Time Clock                                */
3028 /*                                                                            */
3029 /******************************************************************************/
3030
3031 /*******************  Bit definition for RTC_CRH register  ********************/
3032 #define  RTC_CRH_SECIE                       ((uint32_t)0x00000001)               /*!< Second Interrupt Enable */
3033 #define  RTC_CRH_ALRIE                       ((uint32_t)0x00000002)               /*!< Alarm Interrupt Enable */
3034 #define  RTC_CRH_OWIE                        ((uint32_t)0x00000004)               /*!< OverfloW Interrupt Enable */
3035
3036 /*******************  Bit definition for RTC_CRL register  ********************/
3037 #define  RTC_CRL_SECF                        ((uint32_t)0x00000001)               /*!< Second Flag */
3038 #define  RTC_CRL_ALRF                        ((uint32_t)0x00000002)               /*!< Alarm Flag */
3039 #define  RTC_CRL_OWF                         ((uint32_t)0x00000004)               /*!< OverfloW Flag */
3040 #define  RTC_CRL_RSF                         ((uint32_t)0x00000008)               /*!< Registers Synchronized Flag */
3041 #define  RTC_CRL_CNF                         ((uint32_t)0x00000010)               /*!< Configuration Flag */
3042 #define  RTC_CRL_RTOFF                       ((uint32_t)0x00000020)               /*!< RTC operation OFF */
3043
3044 /*******************  Bit definition for RTC_PRLH register  *******************/
3045 #define  RTC_PRLH_PRL                        ((uint32_t)0x0000000F)            /*!< RTC Prescaler Reload Value High */
3046
3047 /*******************  Bit definition for RTC_PRLL register  *******************/
3048 #define  RTC_PRLL_PRL                        ((uint32_t)0x0000FFFF)            /*!< RTC Prescaler Reload Value Low */
3049
3050 /*******************  Bit definition for RTC_DIVH register  *******************/
3051 #define  RTC_DIVH_RTC_DIV                    ((uint32_t)0x0000000F)            /*!< RTC Clock Divider High */
3052
3053 /*******************  Bit definition for RTC_DIVL register  *******************/
3054 #define  RTC_DIVL_RTC_DIV                    ((uint32_t)0x0000FFFF)            /*!< RTC Clock Divider Low */
3055
3056 /*******************  Bit definition for RTC_CNTH register  *******************/
3057 #define  RTC_CNTH_RTC_CNT                    ((uint32_t)0x0000FFFF)            /*!< RTC Counter High */
3058
3059 /*******************  Bit definition for RTC_CNTL register  *******************/
3060 #define  RTC_CNTL_RTC_CNT                    ((uint32_t)0x0000FFFF)            /*!< RTC Counter Low */
3061
3062 /*******************  Bit definition for RTC_ALRH register  *******************/
3063 #define  RTC_ALRH_RTC_ALR                    ((uint32_t)0x0000FFFF)            /*!< RTC Alarm High */
3064
3065 /*******************  Bit definition for RTC_ALRL register  *******************/
3066 #define  RTC_ALRL_RTC_ALR                    ((uint32_t)0x0000FFFF)            /*!< RTC Alarm Low */
3067
3068 /******************************************************************************/
3069 /*                                                                            */
3070 /*                        Independent WATCHDOG (IWDG)                         */
3071 /*                                                                            */
3072 /******************************************************************************/
3073
3074 /*******************  Bit definition for IWDG_KR register  ********************/
3075 #define  IWDG_KR_KEY                         ((uint32_t)0x0000FFFF)            /*!< Key value (write only, read 0000h) */
3076
3077 /*******************  Bit definition for IWDG_PR register  ********************/
3078 #define  IWDG_PR_PR                          ((uint32_t)0x00000007)               /*!< PR[2:0] (Prescaler divider) */
3079 #define  IWDG_PR_PR_0                        ((uint32_t)0x00000001)               /*!< Bit 0 */
3080 #define  IWDG_PR_PR_1                        ((uint32_t)0x00000002)               /*!< Bit 1 */
3081 #define  IWDG_PR_PR_2                        ((uint32_t)0x00000004)               /*!< Bit 2 */
3082
3083 /*******************  Bit definition for IWDG_RLR register  *******************/
3084 #define  IWDG_RLR_RL                         ((uint32_t)0x00000FFF)            /*!< Watchdog counter reload value */
3085
3086 /*******************  Bit definition for IWDG_SR register  ********************/
3087 #define  IWDG_SR_PVU                         ((uint32_t)0x00000001)               /*!< Watchdog prescaler value update */
3088 #define  IWDG_SR_RVU                         ((uint32_t)0x00000002)               /*!< Watchdog counter reload value update */
3089
3090 /******************************************************************************/
3091 /*                                                                            */
3092 /*                            Window WATCHDOG                                 */
3093 /*                                                                            */
3094 /******************************************************************************/
3095
3096 /*******************  Bit definition for WWDG_CR register  ********************/
3097 #define  WWDG_CR_T                           ((uint32_t)0x0000007F)               /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
3098 #define  WWDG_CR_T0                          ((uint32_t)0x00000001)               /*!< Bit 0 */
3099 #define  WWDG_CR_T1                          ((uint32_t)0x00000002)               /*!< Bit 1 */
3100 #define  WWDG_CR_T2                          ((uint32_t)0x00000004)               /*!< Bit 2 */
3101 #define  WWDG_CR_T3                          ((uint32_t)0x00000008)               /*!< Bit 3 */
3102 #define  WWDG_CR_T4                          ((uint32_t)0x00000010)               /*!< Bit 4 */
3103 #define  WWDG_CR_T5                          ((uint32_t)0x00000020)               /*!< Bit 5 */
3104 #define  WWDG_CR_T6                          ((uint32_t)0x00000040)               /*!< Bit 6 */
3105
3106 #define  WWDG_CR_WDGA                        ((uint32_t)0x00000080)               /*!< Activation bit */
3107
3108 /*******************  Bit definition for WWDG_CFR register  *******************/
3109 #define  WWDG_CFR_W                          ((uint32_t)0x0000007F)            /*!< W[6:0] bits (7-bit window value) */
3110 #define  WWDG_CFR_W0                         ((uint32_t)0x00000001)            /*!< Bit 0 */
3111 #define  WWDG_CFR_W1                         ((uint32_t)0x00000002)            /*!< Bit 1 */
3112 #define  WWDG_CFR_W2                         ((uint32_t)0x00000004)            /*!< Bit 2 */
3113 #define  WWDG_CFR_W3                         ((uint32_t)0x00000008)            /*!< Bit 3 */
3114 #define  WWDG_CFR_W4                         ((uint32_t)0x00000010)            /*!< Bit 4 */
3115 #define  WWDG_CFR_W5                         ((uint32_t)0x00000020)            /*!< Bit 5 */
3116 #define  WWDG_CFR_W6                         ((uint32_t)0x00000040)            /*!< Bit 6 */
3117
3118 #define  WWDG_CFR_WDGTB                      ((uint32_t)0x00000180)            /*!< WDGTB[1:0] bits (Timer Base) */
3119 #define  WWDG_CFR_WDGTB0                     ((uint32_t)0x00000080)            /*!< Bit 0 */
3120 #define  WWDG_CFR_WDGTB1                     ((uint32_t)0x00000100)            /*!< Bit 1 */
3121
3122 #define  WWDG_CFR_EWI                        ((uint32_t)0x00000200)            /*!< Early Wakeup Interrupt */
3123
3124 /*******************  Bit definition for WWDG_SR register  ********************/
3125 #define  WWDG_SR_EWIF                        ((uint32_t)0x00000001)               /*!< Early Wakeup Interrupt Flag */
3126
3127
3128 /******************************************************************************/
3129 /*                                                                            */
3130 /*                          SD host Interface                                 */
3131 /*                                                                            */
3132 /******************************************************************************/
3133
3134 /******************  Bit definition for SDIO_POWER register  ******************/
3135 #define  SDIO_POWER_PWRCTRL                  ((uint32_t)0x03)               /*!< PWRCTRL[1:0] bits (Power supply control bits) */
3136 #define  SDIO_POWER_PWRCTRL_0                ((uint32_t)0x01)               /*!< Bit 0 */
3137 #define  SDIO_POWER_PWRCTRL_1                ((uint32_t)0x02)               /*!< Bit 1 */
3138
3139 /******************  Bit definition for SDIO_CLKCR register  ******************/
3140 #define  SDIO_CLKCR_CLKDIV                   ((uint32_t)0x00FF)            /*!< Clock divide factor */
3141 #define  SDIO_CLKCR_CLKEN                    ((uint32_t)0x0100)            /*!< Clock enable bit */
3142 #define  SDIO_CLKCR_PWRSAV                   ((uint32_t)0x0200)            /*!< Power saving configuration bit */
3143 #define  SDIO_CLKCR_BYPASS                   ((uint32_t)0x0400)            /*!< Clock divider bypass enable bit */
3144
3145 #define  SDIO_CLKCR_WIDBUS                   ((uint32_t)0x1800)            /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
3146 #define  SDIO_CLKCR_WIDBUS_0                 ((uint32_t)0x0800)            /*!< Bit 0 */
3147 #define  SDIO_CLKCR_WIDBUS_1                 ((uint32_t)0x1000)            /*!< Bit 1 */
3148
3149 #define  SDIO_CLKCR_NEGEDGE                  ((uint32_t)0x2000)            /*!< SDIO_CK dephasing selection bit */
3150 #define  SDIO_CLKCR_HWFC_EN                  ((uint32_t)0x4000)            /*!< HW Flow Control enable */
3151
3152 /*******************  Bit definition for SDIO_ARG register  *******************/
3153 #define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFF)            /*!< Command argument */
3154
3155 /*******************  Bit definition for SDIO_CMD register  *******************/
3156 #define  SDIO_CMD_CMDINDEX                   ((uint32_t)0x003F)            /*!< Command Index */
3157
3158 #define  SDIO_CMD_WAITRESP                   ((uint32_t)0x00C0)            /*!< WAITRESP[1:0] bits (Wait for response bits) */
3159 #define  SDIO_CMD_WAITRESP_0                 ((uint32_t)0x0040)            /*!<  Bit 0 */
3160 #define  SDIO_CMD_WAITRESP_1                 ((uint32_t)0x0080)            /*!<  Bit 1 */
3161
3162 #define  SDIO_CMD_WAITINT                    ((uint32_t)0x0100)            /*!< CPSM Waits for Interrupt Request */
3163 #define  SDIO_CMD_WAITPEND                   ((uint32_t)0x0200)            /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
3164 #define  SDIO_CMD_CPSMEN                     ((uint32_t)0x0400)            /*!< Command path state machine (CPSM) Enable bit */
3165 #define  SDIO_CMD_SDIOSUSPEND                ((uint32_t)0x0800)            /*!< SD I/O suspend command */
3166 #define  SDIO_CMD_ENCMDCOMPL                 ((uint32_t)0x1000)            /*!< Enable CMD completion */
3167 #define  SDIO_CMD_NIEN                       ((uint32_t)0x2000)            /*!< Not Interrupt Enable */
3168 #define  SDIO_CMD_CEATACMD                   ((uint32_t)0x4000)            /*!< CE-ATA command */
3169
3170 /*****************  Bit definition for SDIO_RESPCMD register  *****************/
3171 #define  SDIO_RESPCMD_RESPCMD                ((uint32_t)0x3F)               /*!< Response command index */
3172
3173 /******************  Bit definition for SDIO_RESP0 register  ******************/
3174 #define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
3175
3176 /******************  Bit definition for SDIO_RESP1 register  ******************/
3177 #define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
3178
3179 /******************  Bit definition for SDIO_RESP2 register  ******************/
3180 #define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
3181
3182 /******************  Bit definition for SDIO_RESP3 register  ******************/
3183 #define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
3184
3185 /******************  Bit definition for SDIO_RESP4 register  ******************/
3186 #define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFF)        /*!< Card Status */
3187
3188 /******************  Bit definition for SDIO_DTIMER register  *****************/
3189 #define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFF)        /*!< Data timeout period. */
3190
3191 /******************  Bit definition for SDIO_DLEN register  *******************/
3192 #define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFF)        /*!< Data length value */
3193
3194 /******************  Bit definition for SDIO_DCTRL register  ******************/
3195 #define  SDIO_DCTRL_DTEN                     ((uint32_t)0x0001)            /*!< Data transfer enabled bit */
3196 #define  SDIO_DCTRL_DTDIR                    ((uint32_t)0x0002)            /*!< Data transfer direction selection */
3197 #define  SDIO_DCTRL_DTMODE                   ((uint32_t)0x0004)            /*!< Data transfer mode selection */
3198 #define  SDIO_DCTRL_DMAEN                    ((uint32_t)0x0008)            /*!< DMA enabled bit */
3199
3200 #define  SDIO_DCTRL_DBLOCKSIZE               ((uint32_t)0x00F0)            /*!< DBLOCKSIZE[3:0] bits (Data block size) */
3201 #define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint32_t)0x0010)            /*!< Bit 0 */
3202 #define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint32_t)0x0020)            /*!< Bit 1 */
3203 #define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint32_t)0x0040)            /*!< Bit 2 */
3204 #define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint32_t)0x0080)            /*!< Bit 3 */
3205
3206 #define  SDIO_DCTRL_RWSTART                  ((uint32_t)0x0100)            /*!< Read wait start */
3207 #define  SDIO_DCTRL_RWSTOP                   ((uint32_t)0x0200)            /*!< Read wait stop */
3208 #define  SDIO_DCTRL_RWMOD                    ((uint32_t)0x0400)            /*!< Read wait mode */
3209 #define  SDIO_DCTRL_SDIOEN                   ((uint32_t)0x0800)            /*!< SD I/O enable functions */
3210
3211 /******************  Bit definition for SDIO_DCOUNT register  *****************/
3212 #define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFF)        /*!< Data count value */
3213
3214 /******************  Bit definition for SDIO_STA register  ********************/
3215 #define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001)        /*!< Command response received (CRC check failed) */
3216 #define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002)        /*!< Data block sent/received (CRC check failed) */
3217 #define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004)        /*!< Command response timeout */
3218 #define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008)        /*!< Data timeout */
3219 #define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010)        /*!< Transmit FIFO underrun error */
3220 #define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020)        /*!< Received FIFO overrun error */
3221 #define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040)        /*!< Command response received (CRC check passed) */
3222 #define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080)        /*!< Command sent (no response required) */
3223 #define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100)        /*!< Data end (data counter, SDIDCOUNT, is zero) */
3224 #define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200)        /*!< Start bit not detected on all data signals in wide bus mode */
3225 #define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400)        /*!< Data block sent/received (CRC check passed) */
3226 #define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800)        /*!< Command transfer in progress */
3227 #define  SDIO_STA_TXACT                      ((uint32_t)0x00001000)        /*!< Data transmit in progress */
3228 #define  SDIO_STA_RXACT                      ((uint32_t)0x00002000)        /*!< Data receive in progress */
3229 #define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000)        /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
3230 #define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000)        /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
3231 #define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000)        /*!< Transmit FIFO full */
3232 #define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000)        /*!< Receive FIFO full */
3233 #define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000)        /*!< Transmit FIFO empty */
3234 #define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000)        /*!< Receive FIFO empty */
3235 #define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000)        /*!< Data available in transmit FIFO */
3236 #define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000)        /*!< Data available in receive FIFO */
3237 #define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000)        /*!< SDIO interrupt received */
3238 #define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000)        /*!< CE-ATA command completion signal received for CMD61 */
3239
3240 /*******************  Bit definition for SDIO_ICR register  *******************/
3241 #define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001)        /*!< CCRCFAIL flag clear bit */
3242 #define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002)        /*!< DCRCFAIL flag clear bit */
3243 #define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004)        /*!< CTIMEOUT flag clear bit */
3244 #define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008)        /*!< DTIMEOUT flag clear bit */
3245 #define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010)        /*!< TXUNDERR flag clear bit */
3246 #define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020)        /*!< RXOVERR flag clear bit */
3247 #define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040)        /*!< CMDREND flag clear bit */
3248 #define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080)        /*!< CMDSENT flag clear bit */
3249 #define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100)        /*!< DATAEND flag clear bit */
3250 #define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200)        /*!< STBITERR flag clear bit */
3251 #define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400)        /*!< DBCKEND flag clear bit */
3252 #define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000)        /*!< SDIOIT flag clear bit */
3253 #define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000)        /*!< CEATAEND flag clear bit */
3254
3255 /******************  Bit definition for SDIO_MASK register  *******************/
3256 #define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001)        /*!< Command CRC Fail Interrupt Enable */
3257 #define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002)        /*!< Data CRC Fail Interrupt Enable */
3258 #define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004)        /*!< Command TimeOut Interrupt Enable */
3259 #define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008)        /*!< Data TimeOut Interrupt Enable */
3260 #define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010)        /*!< Tx FIFO UnderRun Error Interrupt Enable */
3261 #define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020)        /*!< Rx FIFO OverRun Error Interrupt Enable */
3262 #define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040)        /*!< Command Response Received Interrupt Enable */
3263 #define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080)        /*!< Command Sent Interrupt Enable */
3264 #define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100)        /*!< Data End Interrupt Enable */
3265 #define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200)        /*!< Start Bit Error Interrupt Enable */
3266 #define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400)        /*!< Data Block End Interrupt Enable */
3267 #define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800)        /*!< Command Acting Interrupt Enable */
3268 #define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000)        /*!< Data Transmit Acting Interrupt Enable */
3269 #define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000)        /*!< Data receive acting interrupt enabled */
3270 #define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000)        /*!< Tx FIFO Half Empty interrupt Enable */
3271 #define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000)        /*!< Rx FIFO Half Full interrupt Enable */
3272 #define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000)        /*!< Tx FIFO Full interrupt Enable */
3273 #define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000)        /*!< Rx FIFO Full interrupt Enable */
3274 #define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000)        /*!< Tx FIFO Empty interrupt Enable */
3275 #define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000)        /*!< Rx FIFO Empty interrupt Enable */
3276 #define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000)        /*!< Data available in Tx FIFO interrupt Enable */
3277 #define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000)        /*!< Data available in Rx FIFO interrupt Enable */
3278 #define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000)        /*!< SDIO Mode Interrupt Received interrupt Enable */
3279 #define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000)        /*!< CE-ATA command completion signal received Interrupt Enable */
3280
3281 /*****************  Bit definition for SDIO_FIFOCNT register  *****************/
3282 #define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFF)        /*!< Remaining number of words to be written to or read from the FIFO */
3283
3284 /******************  Bit definition for SDIO_FIFO register  *******************/
3285 #define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFF)        /*!< Receive and transmit FIFO data */
3286
3287
3288
3289 /******************************************************************************/
3290 /*                                                                            */
3291 /*                        Serial Peripheral Interface                         */
3292 /*                                                                            */
3293 /******************************************************************************/
3294
3295 /*******************  Bit definition for SPI_CR1 register  ********************/
3296 #define  SPI_CR1_CPHA                        ((uint32_t)0x00000001)        /*!< Clock Phase */
3297 #define  SPI_CR1_CPOL                        ((uint32_t)0x00000002)        /*!< Clock Polarity */
3298 #define  SPI_CR1_MSTR                        ((uint32_t)0x00000004)        /*!< Master Selection */
3299
3300 #define  SPI_CR1_BR                          ((uint32_t)0x00000038)        /*!< BR[2:0] bits (Baud Rate Control) */
3301 #define  SPI_CR1_BR_0                        ((uint32_t)0x00000008)        /*!< Bit 0 */
3302 #define  SPI_CR1_BR_1                        ((uint32_t)0x00000010)        /*!< Bit 1 */
3303 #define  SPI_CR1_BR_2                        ((uint32_t)0x00000020)        /*!< Bit 2 */
3304
3305 #define  SPI_CR1_SPE                         ((uint32_t)0x00000040)        /*!< SPI Enable */
3306 #define  SPI_CR1_LSBFIRST                    ((uint32_t)0x00000080)        /*!< Frame Format */
3307 #define  SPI_CR1_SSI                         ((uint32_t)0x00000100)        /*!< Internal slave select */
3308 #define  SPI_CR1_SSM                         ((uint32_t)0x00000200)        /*!< Software slave management */
3309 #define  SPI_CR1_RXONLY                      ((uint32_t)0x00000400)        /*!< Receive only */
3310 #define  SPI_CR1_DFF                         ((uint32_t)0x00000800)        /*!< Data Frame Format */
3311 #define  SPI_CR1_CRCNEXT                     ((uint32_t)0x00001000)        /*!< Transmit CRC next */
3312 #define  SPI_CR1_CRCEN                       ((uint32_t)0x00002000)        /*!< Hardware CRC calculation enable */
3313 #define  SPI_CR1_BIDIOE                      ((uint32_t)0x00004000)        /*!< Output enable in bidirectional mode */
3314 #define  SPI_CR1_BIDIMODE                    ((uint32_t)0x00008000)        /*!< Bidirectional data mode enable */
3315
3316 /*******************  Bit definition for SPI_CR2 register  ********************/
3317 #define  SPI_CR2_RXDMAEN                     ((uint32_t)0x00000001)        /*!< Rx Buffer DMA Enable */
3318 #define  SPI_CR2_TXDMAEN                     ((uint32_t)0x00000002)        /*!< Tx Buffer DMA Enable */
3319 #define  SPI_CR2_SSOE                        ((uint32_t)0x00000004)        /*!< SS Output Enable */
3320 #define  SPI_CR2_ERRIE                       ((uint32_t)0x00000020)        /*!< Error Interrupt Enable */
3321 #define  SPI_CR2_RXNEIE                      ((uint32_t)0x00000040)        /*!< RX buffer Not Empty Interrupt Enable */
3322 #define  SPI_CR2_TXEIE                       ((uint32_t)0x00000080)        /*!< Tx buffer Empty Interrupt Enable */
3323
3324 /********************  Bit definition for SPI_SR register  ********************/
3325 #define  SPI_SR_RXNE                         ((uint32_t)0x00000001)        /*!< Receive buffer Not Empty */
3326 #define  SPI_SR_TXE                          ((uint32_t)0x00000002)        /*!< Transmit buffer Empty */
3327 #define  SPI_SR_CHSIDE                       ((uint32_t)0x00000004)        /*!< Channel side */
3328 #define  SPI_SR_UDR                          ((uint32_t)0x00000008)        /*!< Underrun flag */
3329 #define  SPI_SR_CRCERR                       ((uint32_t)0x00000010)        /*!< CRC Error flag */
3330 #define  SPI_SR_MODF                         ((uint32_t)0x00000020)        /*!< Mode fault */
3331 #define  SPI_SR_OVR                          ((uint32_t)0x00000040)        /*!< Overrun flag */
3332 #define  SPI_SR_BSY                          ((uint32_t)0x00000080)        /*!< Busy flag */
3333
3334 /********************  Bit definition for SPI_DR register  ********************/
3335 #define  SPI_DR_DR                           ((uint32_t)0x0000FFFF)        /*!< Data Register */
3336
3337 /*******************  Bit definition for SPI_CRCPR register  ******************/
3338 #define  SPI_CRCPR_CRCPOLY                   ((uint32_t)0x0000FFFF)        /*!< CRC polynomial register */
3339
3340 /******************  Bit definition for SPI_RXCRCR register  ******************/
3341 #define  SPI_RXCRCR_RXCRC                    ((uint32_t)0x0000FFFF)        /*!< Rx CRC Register */
3342
3343 /******************  Bit definition for SPI_TXCRCR register  ******************/
3344 #define  SPI_TXCRCR_TXCRC                    ((uint32_t)0x0000FFFF)        /*!< Tx CRC Register */
3345
3346
3347
3348 /******************************************************************************/
3349 /*                                                                            */
3350 /*                      Inter-integrated Circuit Interface                    */
3351 /*                                                                            */
3352 /******************************************************************************/
3353
3354 /*******************  Bit definition for I2C_CR1 register  ********************/
3355 #define  I2C_CR1_PE                          ((uint32_t)0x00000001)        /*!< Peripheral Enable */
3356 #define  I2C_CR1_SMBUS                       ((uint32_t)0x00000002)        /*!< SMBus Mode */
3357 #define  I2C_CR1_SMBTYPE                     ((uint32_t)0x00000008)        /*!< SMBus Type */
3358 #define  I2C_CR1_ENARP                       ((uint32_t)0x00000010)        /*!< ARP Enable */
3359 #define  I2C_CR1_ENPEC                       ((uint32_t)0x00000020)        /*!< PEC Enable */
3360 #define  I2C_CR1_ENGC                        ((uint32_t)0x00000040)        /*!< General Call Enable */
3361 #define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00000080)        /*!< Clock Stretching Disable (Slave mode) */
3362 #define  I2C_CR1_START                       ((uint32_t)0x00000100)        /*!< Start Generation */
3363 #define  I2C_CR1_STOP                        ((uint32_t)0x00000200)        /*!< Stop Generation */
3364 #define  I2C_CR1_ACK                         ((uint32_t)0x00000400)        /*!< Acknowledge Enable */
3365 #define  I2C_CR1_POS                         ((uint32_t)0x00000800)        /*!< Acknowledge/PEC Position (for data reception) */
3366 #define  I2C_CR1_PEC                         ((uint32_t)0x00001000)        /*!< Packet Error Checking */
3367 #define  I2C_CR1_ALERT                       ((uint32_t)0x00002000)        /*!< SMBus Alert */
3368 #define  I2C_CR1_SWRST                       ((uint32_t)0x00008000)        /*!< Software Reset */
3369
3370 /*******************  Bit definition for I2C_CR2 register  ********************/
3371 #define  I2C_CR2_FREQ                        ((uint32_t)0x0000003F)        /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
3372 #define  I2C_CR2_FREQ_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
3373 #define  I2C_CR2_FREQ_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
3374 #define  I2C_CR2_FREQ_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
3375 #define  I2C_CR2_FREQ_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
3376 #define  I2C_CR2_FREQ_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
3377 #define  I2C_CR2_FREQ_5                      ((uint32_t)0x00000020)        /*!< Bit 5 */
3378
3379 #define  I2C_CR2_ITERREN                     ((uint32_t)0x00000100)        /*!< Error Interrupt Enable */
3380 #define  I2C_CR2_ITEVTEN                     ((uint32_t)0x00000200)        /*!< Event Interrupt Enable */
3381 #define  I2C_CR2_ITBUFEN                     ((uint32_t)0x00000400)        /*!< Buffer Interrupt Enable */
3382 #define  I2C_CR2_DMAEN                       ((uint32_t)0x00000800)        /*!< DMA Requests Enable */
3383 #define  I2C_CR2_LAST                        ((uint32_t)0x00001000)        /*!< DMA Last Transfer */
3384
3385 /*******************  Bit definition for I2C_OAR1 register  *******************/
3386 #define  I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FE)        /*!< Interface Address */
3387 #define  I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300)        /*!< Interface Address */
3388
3389 #define  I2C_OAR1_ADD0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
3390 #define  I2C_OAR1_ADD1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
3391 #define  I2C_OAR1_ADD2                       ((uint32_t)0x00000004)        /*!< Bit 2 */
3392 #define  I2C_OAR1_ADD3                       ((uint32_t)0x00000008)        /*!< Bit 3 */
3393 #define  I2C_OAR1_ADD4                       ((uint32_t)0x00000010)        /*!< Bit 4 */
3394 #define  I2C_OAR1_ADD5                       ((uint32_t)0x00000020)        /*!< Bit 5 */
3395 #define  I2C_OAR1_ADD6                       ((uint32_t)0x00000040)        /*!< Bit 6 */
3396 #define  I2C_OAR1_ADD7                       ((uint32_t)0x00000080)        /*!< Bit 7 */
3397 #define  I2C_OAR1_ADD8                       ((uint32_t)0x00000100)        /*!< Bit 8 */
3398 #define  I2C_OAR1_ADD9                       ((uint32_t)0x00000200)        /*!< Bit 9 */
3399
3400 #define  I2C_OAR1_ADDMODE                    ((uint32_t)0x00008000)        /*!< Addressing Mode (Slave mode) */
3401
3402 /*******************  Bit definition for I2C_OAR2 register  *******************/
3403 #define  I2C_OAR2_ENDUAL                     ((uint32_t)0x00000001)        /*!< Dual addressing mode enable */
3404 #define  I2C_OAR2_ADD2                       ((uint32_t)0x000000FE)        /*!< Interface address */
3405
3406 /*******************  Bit definition for I2C_SR1 register  ********************/
3407 #define  I2C_SR1_SB                          ((uint32_t)0x00000001)        /*!< Start Bit (Master mode) */
3408 #define  I2C_SR1_ADDR                        ((uint32_t)0x00000002)        /*!< Address sent (master mode)/matched (slave mode) */
3409 #define  I2C_SR1_BTF                         ((uint32_t)0x00000004)        /*!< Byte Transfer Finished */
3410 #define  I2C_SR1_ADD10                       ((uint32_t)0x00000008)        /*!< 10-bit header sent (Master mode) */
3411 #define  I2C_SR1_STOPF                       ((uint32_t)0x00000010)        /*!< Stop detection (Slave mode) */
3412 #define  I2C_SR1_RXNE                        ((uint32_t)0x00000040)        /*!< Data Register not Empty (receivers) */
3413 #define  I2C_SR1_TXE                         ((uint32_t)0x00000080)        /*!< Data Register Empty (transmitters) */
3414 #define  I2C_SR1_BERR                        ((uint32_t)0x00000100)        /*!< Bus Error */
3415 #define  I2C_SR1_ARLO                        ((uint32_t)0x00000200)        /*!< Arbitration Lost (master mode) */
3416 #define  I2C_SR1_AF                          ((uint32_t)0x00000400)        /*!< Acknowledge Failure */
3417 #define  I2C_SR1_OVR                         ((uint32_t)0x00000800)        /*!< Overrun/Underrun */
3418 #define  I2C_SR1_PECERR                      ((uint32_t)0x00001000)        /*!< PEC Error in reception */
3419 #define  I2C_SR1_TIMEOUT                     ((uint32_t)0x00004000)        /*!< Timeout or Tlow Error */
3420 #define  I2C_SR1_SMBALERT                    ((uint32_t)0x00008000)        /*!< SMBus Alert */
3421
3422 /*******************  Bit definition for I2C_SR2 register  ********************/
3423 #define  I2C_SR2_MSL                         ((uint32_t)0x00000001)        /*!< Master/Slave */
3424 #define  I2C_SR2_BUSY                        ((uint32_t)0x00000002)        /*!< Bus Busy */
3425 #define  I2C_SR2_TRA                         ((uint32_t)0x00000004)        /*!< Transmitter/Receiver */
3426 #define  I2C_SR2_GENCALL                     ((uint32_t)0x00000010)        /*!< General Call Address (Slave mode) */
3427 #define  I2C_SR2_SMBDEFAULT                  ((uint32_t)0x00000020)        /*!< SMBus Device Default Address (Slave mode) */
3428 #define  I2C_SR2_SMBHOST                     ((uint32_t)0x00000040)        /*!< SMBus Host Header (Slave mode) */
3429 #define  I2C_SR2_DUALF                       ((uint32_t)0x00000080)        /*!< Dual Flag (Slave mode) */
3430 #define  I2C_SR2_PEC                         ((uint32_t)0x0000FF00)        /*!< Packet Error Checking Register */
3431
3432 /*******************  Bit definition for I2C_CCR register  ********************/
3433 #define  I2C_CCR_CCR                         ((uint32_t)0x00000FFF)        /*!< Clock Control Register in Fast/Standard mode (Master mode) */
3434 #define  I2C_CCR_DUTY                        ((uint32_t)0x00004000)        /*!< Fast Mode Duty Cycle */
3435 #define  I2C_CCR_FS                          ((uint32_t)0x00008000)        /*!< I2C Master Mode Selection */
3436
3437 /******************  Bit definition for I2C_TRISE register  *******************/
3438 #define  I2C_TRISE_TRISE                     ((uint32_t)0x0000003F)        /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
3439
3440 /******************************************************************************/
3441 /*                                                                            */
3442 /*         Universal Synchronous Asynchronous Receiver Transmitter            */
3443 /*                                                                            */
3444 /******************************************************************************/
3445
3446 /*******************  Bit definition for USART_SR register  *******************/
3447 #define  USART_SR_PE                         ((uint32_t)0x00000001)            /*!< Parity Error */
3448 #define  USART_SR_FE                         ((uint32_t)0x00000002)            /*!< Framing Error */
3449 #define  USART_SR_NE                         ((uint32_t)0x00000004)            /*!< Noise Error Flag */
3450 #define  USART_SR_ORE                        ((uint32_t)0x00000008)            /*!< OverRun Error */
3451 #define  USART_SR_IDLE                       ((uint32_t)0x00000010)            /*!< IDLE line detected */
3452 #define  USART_SR_RXNE                       ((uint32_t)0x00000020)            /*!< Read Data Register Not Empty */
3453 #define  USART_SR_TC                         ((uint32_t)0x00000040)            /*!< Transmission Complete */
3454 #define  USART_SR_TXE                        ((uint32_t)0x00000080)            /*!< Transmit Data Register Empty */
3455 #define  USART_SR_LBD                        ((uint32_t)0x00000100)            /*!< LIN Break Detection Flag */
3456 #define  USART_SR_CTS                        ((uint32_t)0x00000200)            /*!< CTS Flag */
3457
3458 /*******************  Bit definition for USART_DR register  *******************/
3459 #define  USART_DR_DR                         ((uint32_t)0x000001FF)            /*!< Data value */
3460
3461 /******************  Bit definition for USART_BRR register  *******************/
3462 #define  USART_BRR_DIV_Fraction              ((uint32_t)0x0000000F)            /*!< Fraction of USARTDIV */
3463 #define  USART_BRR_DIV_Mantissa              ((uint32_t)0x0000FFF0)            /*!< Mantissa of USARTDIV */
3464
3465 /******************  Bit definition for USART_CR1 register  *******************/
3466 #define  USART_CR1_SBK                       ((uint32_t)0x00000001)            /*!< Send Break */
3467 #define  USART_CR1_RWU                       ((uint32_t)0x00000002)            /*!< Receiver wakeup */
3468 #define  USART_CR1_RE                        ((uint32_t)0x00000004)            /*!< Receiver Enable */
3469 #define  USART_CR1_TE                        ((uint32_t)0x00000008)            /*!< Transmitter Enable */
3470 #define  USART_CR1_IDLEIE                    ((uint32_t)0x00000010)            /*!< IDLE Interrupt Enable */
3471 #define  USART_CR1_RXNEIE                    ((uint32_t)0x00000020)            /*!< RXNE Interrupt Enable */
3472 #define  USART_CR1_TCIE                      ((uint32_t)0x00000040)            /*!< Transmission Complete Interrupt Enable */
3473 #define  USART_CR1_TXEIE                     ((uint32_t)0x00000080)            /*!< PE Interrupt Enable */
3474 #define  USART_CR1_PEIE                      ((uint32_t)0x00000100)            /*!< PE Interrupt Enable */
3475 #define  USART_CR1_PS                        ((uint32_t)0x00000200)            /*!< Parity Selection */
3476 #define  USART_CR1_PCE                       ((uint32_t)0x00000400)            /*!< Parity Control Enable */
3477 #define  USART_CR1_WAKE                      ((uint32_t)0x00000800)            /*!< Wakeup method */
3478 #define  USART_CR1_M                         ((uint32_t)0x00001000)            /*!< Word length */
3479 #define  USART_CR1_UE                        ((uint32_t)0x00002000)            /*!< USART Enable */
3480
3481 /******************  Bit definition for USART_CR2 register  *******************/
3482 #define  USART_CR2_ADD                       ((uint32_t)0x0000000F)            /*!< Address of the USART node */
3483 #define  USART_CR2_LBDL                      ((uint32_t)0x00000020)            /*!< LIN Break Detection Length */
3484 #define  USART_CR2_LBDIE                     ((uint32_t)0x00000040)            /*!< LIN Break Detection Interrupt Enable */
3485 #define  USART_CR2_LBCL                      ((uint32_t)0x00000100)            /*!< Last Bit Clock pulse */
3486 #define  USART_CR2_CPHA                      ((uint32_t)0x00000200)            /*!< Clock Phase */
3487 #define  USART_CR2_CPOL                      ((uint32_t)0x00000400)            /*!< Clock Polarity */
3488 #define  USART_CR2_CLKEN                     ((uint32_t)0x00000800)            /*!< Clock Enable */
3489
3490 #define  USART_CR2_STOP                      ((uint32_t)0x00003000)            /*!< STOP[1:0] bits (STOP bits) */
3491 #define  USART_CR2_STOP_0                    ((uint32_t)0x00001000)            /*!< Bit 0 */
3492 #define  USART_CR2_STOP_1                    ((uint32_t)0x00002000)            /*!< Bit 1 */
3493
3494 #define  USART_CR2_LINEN                     ((uint32_t)0x00004000)            /*!< LIN mode enable */
3495
3496 /******************  Bit definition for USART_CR3 register  *******************/
3497 #define  USART_CR3_EIE                       ((uint32_t)0x00000001)            /*!< Error Interrupt Enable */
3498 #define  USART_CR3_IREN                      ((uint32_t)0x00000002)            /*!< IrDA mode Enable */
3499 #define  USART_CR3_IRLP                      ((uint32_t)0x00000004)            /*!< IrDA Low-Power */
3500 #define  USART_CR3_HDSEL                     ((uint32_t)0x00000008)            /*!< Half-Duplex Selection */
3501 #define  USART_CR3_NACK                      ((uint32_t)0x00000010)            /*!< Smartcard NACK enable */
3502 #define  USART_CR3_SCEN                      ((uint32_t)0x00000020)            /*!< Smartcard mode enable */
3503 #define  USART_CR3_DMAR                      ((uint32_t)0x00000040)            /*!< DMA Enable Receiver */
3504 #define  USART_CR3_DMAT                      ((uint32_t)0x00000080)            /*!< DMA Enable Transmitter */
3505 #define  USART_CR3_RTSE                      ((uint32_t)0x00000100)            /*!< RTS Enable */
3506 #define  USART_CR3_CTSE                      ((uint32_t)0x00000200)            /*!< CTS Enable */
3507 #define  USART_CR3_CTSIE                     ((uint32_t)0x00000400)            /*!< CTS Interrupt Enable */
3508
3509 /******************  Bit definition for USART_GTPR register  ******************/
3510 #define  USART_GTPR_PSC                      ((uint32_t)0x000000FF)            /*!< PSC[7:0] bits (Prescaler value) */
3511 #define  USART_GTPR_PSC_0                    ((uint32_t)0x00000001)            /*!< Bit 0 */
3512 #define  USART_GTPR_PSC_1                    ((uint32_t)0x00000002)            /*!< Bit 1 */
3513 #define  USART_GTPR_PSC_2                    ((uint32_t)0x00000004)            /*!< Bit 2 */
3514 #define  USART_GTPR_PSC_3                    ((uint32_t)0x00000008)            /*!< Bit 3 */
3515 #define  USART_GTPR_PSC_4                    ((uint32_t)0x00000010)            /*!< Bit 4 */
3516 #define  USART_GTPR_PSC_5                    ((uint32_t)0x00000020)            /*!< Bit 5 */
3517 #define  USART_GTPR_PSC_6                    ((uint32_t)0x00000040)            /*!< Bit 6 */
3518 #define  USART_GTPR_PSC_7                    ((uint32_t)0x00000080)            /*!< Bit 7 */
3519
3520 #define  USART_GTPR_GT                       ((uint32_t)0x0000FF00)            /*!< Guard time value */
3521
3522 /******************************************************************************/
3523 /*                                                                            */
3524 /*                                 Debug MCU                                  */
3525 /*                                                                            */
3526 /******************************************************************************/
3527
3528 /****************  Bit definition for DBGMCU_IDCODE register  *****************/
3529 #define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */
3530
3531 #define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */
3532 #define  DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */
3533 #define  DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */
3534 #define  DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */
3535 #define  DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */
3536 #define  DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */
3537 #define  DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */
3538 #define  DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */
3539 #define  DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */
3540 #define  DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */
3541 #define  DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */
3542 #define  DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */
3543 #define  DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */
3544 #define  DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */
3545 #define  DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */
3546 #define  DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */
3547 #define  DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */
3548
3549 /******************  Bit definition for DBGMCU_CR register  *******************/
3550 #define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)        /*!< Debug Sleep Mode */
3551 #define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */
3552 #define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */
3553 #define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)        /*!< Trace Pin Assignment Control */
3554
3555 #define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)        /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
3556 #define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040)        /*!< Bit 0 */
3557 #define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080)        /*!< Bit 1 */
3558
3559 #define  DBGMCU_CR_DBG_IWDG_STOP             ((uint32_t)0x00000100)        /*!< Debug Independent Watchdog stopped when Core is halted */
3560 #define  DBGMCU_CR_DBG_WWDG_STOP             ((uint32_t)0x00000200)        /*!< Debug Window Watchdog stopped when Core is halted */
3561 #define  DBGMCU_CR_DBG_TIM1_STOP             ((uint32_t)0x00000400)        /*!< TIM1 counter stopped when core is halted */
3562 #define  DBGMCU_CR_DBG_TIM2_STOP             ((uint32_t)0x00000800)        /*!< TIM2 counter stopped when core is halted */
3563 #define  DBGMCU_CR_DBG_TIM3_STOP             ((uint32_t)0x00001000)        /*!< TIM3 counter stopped when core is halted */
3564 #define  DBGMCU_CR_DBG_TIM4_STOP             ((uint32_t)0x00002000)        /*!< TIM4 counter stopped when core is halted */
3565 #define  DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00008000)        /*!< SMBUS timeout mode stopped when Core is halted */
3566 #define  DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00010000)        /*!< SMBUS timeout mode stopped when Core is halted */
3567 #define  DBGMCU_CR_DBG_TIM15_STOP            ((uint32_t)0x00400000)        /*!< Debug TIM15 stopped when Core is halted */
3568 #define  DBGMCU_CR_DBG_TIM16_STOP            ((uint32_t)0x00800000)        /*!< Debug TIM16 stopped when Core is halted */
3569 #define  DBGMCU_CR_DBG_TIM17_STOP            ((uint32_t)0x01000000)        /*!< Debug TIM17 stopped when Core is halted */
3570
3571 /******************************************************************************/
3572 /*                                                                            */
3573 /*                      FLASH and Option Bytes Registers                      */
3574 /*                                                                            */
3575 /******************************************************************************/
3576 /*******************  Bit definition for FLASH_ACR register  ******************/
3577 #define  FLASH_ACR_HLFCYA                    ((uint32_t)0x00000008)        /*!< Flash Half Cycle Access Enable */
3578
3579 /******************  Bit definition for FLASH_KEYR register  ******************/
3580 #define  FLASH_KEYR_FKEYR                    ((uint32_t)0xFFFFFFFF)        /*!< FPEC Key */
3581
3582 #define  RDP_KEY                             ((uint32_t)0x000000A5)        /*!< RDP Key */
3583 #define  FLASH_KEY1                          ((uint32_t)0x45670123)        /*!< FPEC Key1 */
3584 #define  FLASH_KEY2                          ((uint32_t)0xCDEF89AB)        /*!< FPEC Key2 */
3585
3586 /*****************  Bit definition for FLASH_OPTKEYR register  ****************/
3587 #define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option Byte Key */
3588
3589 #define  FLASH_OPTKEY1                       FLASH_KEY1                    /*!< Option Byte Key1 */
3590 #define  FLASH_OPTKEY2                       FLASH_KEY2                    /*!< Option Byte Key2 */
3591
3592 /******************  Bit definition for FLASH_SR register  ********************/
3593 #define  FLASH_SR_BSY                        ((uint32_t)0x00000001)        /*!< Busy */
3594 #define  FLASH_SR_PGERR                      ((uint32_t)0x00000004)        /*!< Programming Error */
3595 #define  FLASH_SR_WRPRTERR                   ((uint32_t)0x00000010)        /*!< Write Protection Error */
3596 #define  FLASH_SR_EOP                        ((uint32_t)0x00000020)        /*!< End of operation */
3597
3598 /*******************  Bit definition for FLASH_CR register  *******************/
3599 #define  FLASH_CR_PG                         ((uint32_t)0x00000001)        /*!< Programming */
3600 #define  FLASH_CR_PER                        ((uint32_t)0x00000002)        /*!< Page Erase */
3601 #define  FLASH_CR_MER                        ((uint32_t)0x00000004)        /*!< Mass Erase */
3602 #define  FLASH_CR_OPTPG                      ((uint32_t)0x00000010)        /*!< Option Byte Programming */
3603 #define  FLASH_CR_OPTER                      ((uint32_t)0x00000020)        /*!< Option Byte Erase */
3604 #define  FLASH_CR_STRT                       ((uint32_t)0x00000040)        /*!< Start */
3605 #define  FLASH_CR_LOCK                       ((uint32_t)0x00000080)        /*!< Lock */
3606 #define  FLASH_CR_OPTWRE                     ((uint32_t)0x00000200)        /*!< Option Bytes Write Enable */
3607 #define  FLASH_CR_ERRIE                      ((uint32_t)0x00000400)        /*!< Error Interrupt Enable */
3608 #define  FLASH_CR_EOPIE                      ((uint32_t)0x00001000)        /*!< End of operation interrupt enable */
3609
3610 /*******************  Bit definition for FLASH_AR register  *******************/
3611 #define  FLASH_AR_FAR                        ((uint32_t)0xFFFFFFFF)        /*!< Flash Address */
3612
3613 /******************  Bit definition for FLASH_OBR register  *******************/
3614 #define  FLASH_OBR_OPTERR                    ((uint32_t)0x00000001)        /*!< Option Byte Error */
3615 #define  FLASH_OBR_RDPRT                     ((uint32_t)0x00000002)        /*!< Read protection */
3616
3617 #define  FLASH_OBR_IWDG_SW                   ((uint32_t)0x00000004)        /*!< IWDG SW */
3618 #define  FLASH_OBR_nRST_STOP                 ((uint32_t)0x00000008)        /*!< nRST_STOP */
3619 #define  FLASH_OBR_nRST_STDBY                ((uint32_t)0x00000010)        /*!< nRST_STDBY */
3620 #define  FLASH_OBR_USER                      ((uint32_t)0x0000001C)        /*!< User Option Bytes */
3621
3622 /******************  Bit definition for FLASH_WRPR register  ******************/
3623 #define  FLASH_WRPR_WRP                      ((uint32_t)0xFFFFFFFF)      /*!< Write Protect */
3624
3625 /*----------------------------------------------------------------------------*/
3626
3627 /******************  Bit definition for FLASH_RDP register  *******************/
3628 #define  FLASH_RDP_RDP                       ((uint32_t)0x000000FF)        /*!< Read protection option byte */
3629 #define  FLASH_RDP_nRDP                      ((uint32_t)0x0000FF00)        /*!< Read protection complemented option byte */
3630
3631 /******************  Bit definition for FLASH_USER register  ******************/
3632 #define  FLASH_USER_USER                     ((uint32_t)0x00FF0000)        /*!< User option byte */
3633 #define  FLASH_USER_nUSER                    ((uint32_t)0xFF000000)        /*!< User complemented option byte */
3634
3635 /******************  Bit definition for FLASH_Data0 register  *****************/
3636 #define  FLASH_DATA0_DATA0                   ((uint32_t)0x000000FF)        /*!< User data storage option byte */
3637 #define  FLASH_DATA0_nDATA0                  ((uint32_t)0x0000FF00)        /*!< User data storage complemented option byte */
3638
3639 /******************  Bit definition for FLASH_Data1 register  *****************/
3640 #define  FLASH_DATA1_DATA1                   ((uint32_t)0x00FF0000)        /*!< User data storage option byte */
3641 #define  FLASH_DATA1_nDATA1                  ((uint32_t)0xFF000000)        /*!< User data storage complemented option byte */
3642
3643 /******************  Bit definition for FLASH_WRP0 register  ******************/
3644 #define  FLASH_WRP0_WRP0                     ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
3645 #define  FLASH_WRP0_nWRP0                    ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
3646
3647 /******************  Bit definition for FLASH_WRP1 register  ******************/
3648 #define  FLASH_WRP1_WRP1                     ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
3649 #define  FLASH_WRP1_nWRP1                    ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
3650
3651 /******************  Bit definition for FLASH_WRP2 register  ******************/
3652 #define  FLASH_WRP2_WRP2                     ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
3653 #define  FLASH_WRP2_nWRP2                    ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
3654
3655 /******************  Bit definition for FLASH_WRP3 register  ******************/
3656 #define  FLASH_WRP3_WRP3                     ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
3657 #define  FLASH_WRP3_nWRP3                    ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
3658
3659
3660
3661 /**
3662   * @}
3663 */
3664
3665 /**
3666   * @}
3667 */
3668
3669 /** @addtogroup Exported_macro
3670   * @{
3671   */
3672
3673 /****************************** ADC Instances *********************************/
3674 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1))
3675
3676 #define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
3677
3678 /****************************** CEC Instances *********************************/
3679 #define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
3680
3681 /****************************** CRC Instances *********************************/
3682 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
3683
3684 /****************************** DAC Instances *********************************/
3685 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
3686
3687 /****************************** DMA Instances *********************************/
3688 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
3689                                        ((INSTANCE) == DMA1_Channel2) || \
3690                                        ((INSTANCE) == DMA1_Channel3) || \
3691                                        ((INSTANCE) == DMA1_Channel4) || \
3692                                        ((INSTANCE) == DMA1_Channel5) || \
3693                                        ((INSTANCE) == DMA1_Channel6) || \
3694                                        ((INSTANCE) == DMA1_Channel7))
3695
3696 /******************************* GPIO Instances *******************************/
3697 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
3698                                         ((INSTANCE) == GPIOB) || \
3699                                         ((INSTANCE) == GPIOC) || \
3700                                         ((INSTANCE) == GPIOD) || \
3701                                         ((INSTANCE) == GPIOE))
3702
3703 /**************************** GPIO Alternate Function Instances ***************/
3704 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
3705
3706 /**************************** GPIO Lock Instances *****************************/
3707 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
3708
3709 /******************************** I2C Instances *******************************/
3710 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
3711                                        ((INSTANCE) == I2C2))
3712
3713 /****************************** IWDG Instances ********************************/
3714 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
3715
3716 /******************************** SPI Instances *******************************/
3717 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
3718                                        ((INSTANCE) == SPI2))
3719
3720 /****************************** START TIM Instances ***************************/
3721 /****************************** TIM Instances *********************************/
3722 #define IS_TIM_INSTANCE(INSTANCE)\
3723   (((INSTANCE) == TIM1)    || \
3724    ((INSTANCE) == TIM2)    || \
3725    ((INSTANCE) == TIM3)    || \
3726    ((INSTANCE) == TIM4)    || \
3727    ((INSTANCE) == TIM6)    || \
3728    ((INSTANCE) == TIM7)    || \
3729    ((INSTANCE) == TIM15)   || \
3730    ((INSTANCE) == TIM16)   || \
3731    ((INSTANCE) == TIM17))
3732
3733 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
3734   (((INSTANCE) == TIM1)    || \
3735    ((INSTANCE) == TIM2)    || \
3736    ((INSTANCE) == TIM3)    || \
3737    ((INSTANCE) == TIM4)    || \
3738    ((INSTANCE) == TIM15)   || \
3739    ((INSTANCE) == TIM16)   || \
3740    ((INSTANCE) == TIM17))
3741
3742 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
3743   (((INSTANCE) == TIM1)    || \
3744    ((INSTANCE) == TIM2)    || \
3745    ((INSTANCE) == TIM3)    || \
3746    ((INSTANCE) == TIM4)    || \
3747    ((INSTANCE) == TIM15))
3748
3749 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
3750   (((INSTANCE) == TIM1)    || \
3751    ((INSTANCE) == TIM2)    || \
3752    ((INSTANCE) == TIM3)    || \
3753    ((INSTANCE) == TIM4))
3754
3755 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
3756   (((INSTANCE) == TIM1)    || \
3757    ((INSTANCE) == TIM2)    || \
3758    ((INSTANCE) == TIM3)    || \
3759    ((INSTANCE) == TIM4))
3760
3761 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
3762   (((INSTANCE) == TIM1)    || \
3763    ((INSTANCE) == TIM2)    || \
3764    ((INSTANCE) == TIM3)    || \
3765    ((INSTANCE) == TIM4))
3766
3767 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
3768   (((INSTANCE) == TIM1)    || \
3769    ((INSTANCE) == TIM2)    || \
3770    ((INSTANCE) == TIM3)    || \
3771    ((INSTANCE) == TIM4))
3772
3773 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
3774   (((INSTANCE) == TIM1)    || \
3775    ((INSTANCE) == TIM2)    || \
3776    ((INSTANCE) == TIM3)    || \
3777    ((INSTANCE) == TIM4)    || \
3778    ((INSTANCE) == TIM15))
3779
3780 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
3781   (((INSTANCE) == TIM1)    || \
3782    ((INSTANCE) == TIM2)    || \
3783    ((INSTANCE) == TIM3)    || \
3784    ((INSTANCE) == TIM4)    || \
3785    ((INSTANCE) == TIM15))
3786
3787 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
3788   (((INSTANCE) == TIM1)    || \
3789    ((INSTANCE) == TIM2)    || \
3790    ((INSTANCE) == TIM3)    || \
3791    ((INSTANCE) == TIM4))
3792
3793 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
3794   (((INSTANCE) == TIM1)    || \
3795    ((INSTANCE) == TIM2)    || \
3796    ((INSTANCE) == TIM3)    || \
3797    ((INSTANCE) == TIM4))
3798
3799 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
3800   (((INSTANCE) == TIM1)    || \
3801    ((INSTANCE) == TIM2)    || \
3802    ((INSTANCE) == TIM3)    || \
3803    ((INSTANCE) == TIM4))
3804
3805 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
3806   (((INSTANCE) == TIM1)    || \
3807    ((INSTANCE) == TIM2)    || \
3808    ((INSTANCE) == TIM3)    || \
3809    ((INSTANCE) == TIM4)    || \
3810    ((INSTANCE) == TIM6)    || \
3811    ((INSTANCE) == TIM7)    || \
3812    ((INSTANCE) == TIM15))
3813
3814 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
3815   (((INSTANCE) == TIM1)    || \
3816    ((INSTANCE) == TIM2)    || \
3817    ((INSTANCE) == TIM3)    || \
3818    ((INSTANCE) == TIM4)    || \
3819    ((INSTANCE) == TIM15))
3820
3821 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
3822   (((INSTANCE) == TIM1)    || \
3823    ((INSTANCE) == TIM2)    || \
3824    ((INSTANCE) == TIM3)    || \
3825    ((INSTANCE) == TIM4)    || \
3826    ((INSTANCE) == TIM15)   || \
3827    ((INSTANCE) == TIM16)   || \
3828    ((INSTANCE) == TIM17))
3829
3830 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
3831   (((INSTANCE) == TIM1)    || \
3832    ((INSTANCE) == TIM15)   || \
3833    ((INSTANCE) == TIM16)   || \
3834    ((INSTANCE) == TIM17))
3835
3836 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
3837    ((((INSTANCE) == TIM1) &&                  \
3838      (((CHANNEL) == TIM_CHANNEL_1) ||          \
3839       ((CHANNEL) == TIM_CHANNEL_2) ||          \
3840       ((CHANNEL) == TIM_CHANNEL_3) ||          \
3841       ((CHANNEL) == TIM_CHANNEL_4)))           \
3842     ||                                         \
3843     (((INSTANCE) == TIM2) &&                   \
3844      (((CHANNEL) == TIM_CHANNEL_1) ||          \
3845       ((CHANNEL) == TIM_CHANNEL_2) ||          \
3846       ((CHANNEL) == TIM_CHANNEL_3) ||          \
3847       ((CHANNEL) == TIM_CHANNEL_4)))           \
3848     ||                                         \
3849     (((INSTANCE) == TIM3) &&                   \
3850      (((CHANNEL) == TIM_CHANNEL_1) ||          \
3851       ((CHANNEL) == TIM_CHANNEL_2) ||          \
3852       ((CHANNEL) == TIM_CHANNEL_3) ||          \
3853       ((CHANNEL) == TIM_CHANNEL_4)))           \
3854     ||                                         \
3855     (((INSTANCE) == TIM4) &&                   \
3856      (((CHANNEL) == TIM_CHANNEL_1) ||          \
3857       ((CHANNEL) == TIM_CHANNEL_2) ||          \
3858       ((CHANNEL) == TIM_CHANNEL_3) ||          \
3859       ((CHANNEL) == TIM_CHANNEL_4)))           \
3860     ||                                         \
3861     (((INSTANCE) == TIM15) &&                  \
3862      (((CHANNEL) == TIM_CHANNEL_1) ||          \
3863       ((CHANNEL) == TIM_CHANNEL_2)))           \
3864     ||                                         \
3865     (((INSTANCE) == TIM16) &&                  \
3866      (((CHANNEL) == TIM_CHANNEL_1)))           \
3867     ||                                         \
3868     (((INSTANCE) == TIM17) &&                  \
3869      (((CHANNEL) == TIM_CHANNEL_1))))
3870
3871 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
3872    ((((INSTANCE) == TIM1) &&                    \
3873      (((CHANNEL) == TIM_CHANNEL_1) ||           \
3874       ((CHANNEL) == TIM_CHANNEL_2) ||           \
3875       ((CHANNEL) == TIM_CHANNEL_3)))            \
3876     ||                                          \
3877     (((INSTANCE) == TIM15) &&                   \
3878       ((CHANNEL) == TIM_CHANNEL_1))             \
3879     ||                                          \
3880     (((INSTANCE) == TIM16) &&                   \
3881      ((CHANNEL) == TIM_CHANNEL_1))              \
3882     ||                                          \
3883     (((INSTANCE) == TIM17) &&                   \
3884      ((CHANNEL) == TIM_CHANNEL_1)))
3885
3886 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
3887   (((INSTANCE) == TIM1)    || \
3888    ((INSTANCE) == TIM2)    || \
3889    ((INSTANCE) == TIM3)    || \
3890    ((INSTANCE) == TIM4))
3891
3892 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
3893   (((INSTANCE) == TIM1)    || \
3894    ((INSTANCE) == TIM15)   || \
3895    ((INSTANCE) == TIM16)   || \
3896    ((INSTANCE) == TIM17))
3897
3898 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
3899   (((INSTANCE) == TIM1)    || \
3900    ((INSTANCE) == TIM2)    || \
3901    ((INSTANCE) == TIM3)    || \
3902    ((INSTANCE) == TIM4)    || \
3903    ((INSTANCE) == TIM15)   || \
3904    ((INSTANCE) == TIM16)   || \
3905    ((INSTANCE) == TIM17))
3906
3907 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
3908   (((INSTANCE) == TIM1)    || \
3909    ((INSTANCE) == TIM2)    || \
3910    ((INSTANCE) == TIM3)    || \
3911    ((INSTANCE) == TIM4)    || \
3912    ((INSTANCE) == TIM6)    || \
3913    ((INSTANCE) == TIM7)    || \
3914    ((INSTANCE) == TIM15)   || \
3915    ((INSTANCE) == TIM16)   || \
3916    ((INSTANCE) == TIM17))
3917
3918 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
3919   (((INSTANCE) == TIM1)    || \
3920    ((INSTANCE) == TIM2)    || \
3921    ((INSTANCE) == TIM3)    || \
3922    ((INSTANCE) == TIM4)    || \
3923    ((INSTANCE) == TIM15)   || \
3924    ((INSTANCE) == TIM16)   || \
3925    ((INSTANCE) == TIM17))
3926
3927 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
3928   (((INSTANCE) == TIM1)    || \
3929    ((INSTANCE) == TIM15)   || \
3930    ((INSTANCE) == TIM16)   || \
3931    ((INSTANCE) == TIM17))
3932
3933 /****************************** END TIM Instances *****************************/
3934
3935
3936 /******************** USART Instances : Synchronous mode **********************/
3937 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
3938                                      ((INSTANCE) == USART2) || \
3939                                      ((INSTANCE) == USART3))
3940
3941 /******************** UART Instances : Asynchronous mode **********************/
3942 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
3943                                     ((INSTANCE) == USART2) || \
3944                                     ((INSTANCE) == USART3))
3945
3946 /******************** UART Instances : Half-Duplex mode **********************/
3947 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
3948                                                ((INSTANCE) == USART2) || \
3949                                                ((INSTANCE) == USART3))
3950
3951 /******************** UART Instances : LIN mode **********************/
3952 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
3953                                         ((INSTANCE) == USART2) || \
3954                                         ((INSTANCE) == USART3))
3955
3956 /****************** UART Instances : Hardware Flow control ********************/
3957 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
3958                                            ((INSTANCE) == USART2) || \
3959                                            ((INSTANCE) == USART3))
3960
3961 /********************* UART Instances : Smard card mode ***********************/
3962 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
3963                                          ((INSTANCE) == USART2) || \
3964                                          ((INSTANCE) == USART3))
3965
3966 /*********************** UART Instances : IRDA mode ***************************/
3967 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
3968                                     ((INSTANCE) == USART2) || \
3969                                     ((INSTANCE) == USART3))
3970
3971 /***************** UART Instances : Multi-Processor mode **********************/
3972 #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
3973                                                    ((INSTANCE) == USART2) || \
3974                                                    ((INSTANCE) == USART3))
3975
3976 /***************** UART Instances : DMA mode available **********************/
3977 #define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
3978                                         ((INSTANCE) == USART2) || \
3979                                         ((INSTANCE) == USART3))
3980
3981 /****************************** RTC Instances *********************************/
3982 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
3983
3984 /**************************** WWDG Instances *****************************/
3985 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
3986
3987
3988
3989
3990
3991 /**
3992   * @}
3993 */
3994 /******************************************************************************/
3995 /*  For a painless codes migration between the STM32F1xx device product       */
3996 /*  lines, the aliases defined below are put in place to overcome the         */
3997 /*  differences in the interrupt handlers and IRQn definitions.               */
3998 /*  No need to update developed interrupt code when moving across             */
3999 /*  product lines within the same STM32F1 Family                              */
4000 /******************************************************************************/
4001
4002 /* Aliases for __IRQn */
4003 #define ADC1_2_IRQn               ADC1_IRQn
4004
4005
4006
4007 #define TIM1_BRK_TIM9_IRQn        TIM1_BRK_TIM15_IRQn
4008 #define TIM9_IRQn                 TIM1_BRK_TIM15_IRQn
4009 #define TIM1_BRK_IRQn             TIM1_BRK_TIM15_IRQn
4010
4011 #define TIM1_UP_TIM10_IRQn        TIM1_UP_TIM16_IRQn
4012 #define TIM10_IRQn                TIM1_UP_TIM16_IRQn
4013 #define TIM1_UP_IRQn              TIM1_UP_TIM16_IRQn
4014
4015 #define TIM1_TRG_COM_TIM11_IRQn   TIM1_TRG_COM_TIM17_IRQn
4016 #define TIM11_IRQn                TIM1_TRG_COM_TIM17_IRQn
4017 #define TIM1_TRG_COM_IRQn         TIM1_TRG_COM_TIM17_IRQn
4018
4019
4020
4021 #define OTG_FS_WKUP_IRQn          CEC_IRQn
4022 #define USBWakeUp_IRQn            CEC_IRQn
4023
4024
4025
4026 #define TIM6_IRQn                 TIM6_DAC_IRQn
4027
4028
4029 /* Aliases for __IRQHandler */
4030 #define ADC1_2_IRQHandler               ADC1_IRQHandler
4031
4032
4033
4034 #define TIM1_BRK_TIM9_IRQHandler        TIM1_BRK_TIM15_IRQHandler
4035 #define TIM9_IRQHandler                 TIM1_BRK_TIM15_IRQHandler
4036 #define TIM1_BRK_IRQHandler             TIM1_BRK_TIM15_IRQHandler
4037
4038 #define TIM1_UP_TIM10_IRQHandler        TIM1_UP_TIM16_IRQHandler
4039 #define TIM10_IRQHandler                TIM1_UP_TIM16_IRQHandler
4040 #define TIM1_UP_IRQHandler              TIM1_UP_TIM16_IRQHandler
4041
4042 #define TIM1_TRG_COM_TIM11_IRQHandler   TIM1_TRG_COM_TIM17_IRQHandler
4043 #define TIM11_IRQHandler                TIM1_TRG_COM_TIM17_IRQHandler
4044 #define TIM1_TRG_COM_IRQHandler         TIM1_TRG_COM_TIM17_IRQHandler
4045
4046
4047
4048 #define OTG_FS_WKUP_IRQHandler          CEC_IRQHandler
4049 #define USBWakeUp_IRQHandler            CEC_IRQHandler
4050
4051
4052
4053 #define TIM6_IRQHandler                 TIM6_DAC_IRQHandler
4054
4055
4056 /**
4057   * @}
4058   */
4059
4060 /**
4061   * @}
4062   */
4063
4064
4065 #ifdef __cplusplus
4066   }
4067 #endif /* __cplusplus */
4068
4069 #endif /* __STM32F100xB_H */
4070
4071
4072
4073   /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/