tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/system_stm32f1xx.c

   1 /**
   2   ******************************************************************************
   3   * @file    system_stm32f1xx.c
   4   * @author  MCD Application Team
   5   * @version V4.0.0
   6   * @date    16-December-2014
   7   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
   8   *
   9   * 1.  This file provides two functions and one global variable to be called from
  10   *     user application:
  11   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
  12   *                      factors, AHB/APBx prescalers and Flash settings).
  13   *                      This function is called at startup just after reset and
  14   *                      before branch to main program. This call is made inside
  15   *                      the "startup_stm32f1xx_xx.s" file.
  16   *
  17   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
  18   *                                  by the user application to setup the SysTick
  19   *                                  timer or configure other parameters.
  20   *
  21   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
  22   *                                 be called whenever the core clock is changed
  23   *                                 during program execution.
  24   *
  25   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
  26   *    Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to
  27   *    configure the system clock before to branch to main program.
  28   *
  29   * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
  30   *    the product used), refer to "HSE_VALUE".
  31   *    When HSE is used as system clock source, directly or through PLL, and you
  32   *    are using different crystal you have to adapt the HSE value to your own
  33   *    configuration.
  34   *
  35   * This file configures the system clock as follows:
  36   *-----------------------------------------------------------------------------
  37   * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
  38   *                                    | (external 8 MHz clock) | (internal 8 MHz)
  39   *                                    | 2- PLL_HSE_XTAL        |
  40   *                                    | (external 8 MHz xtal)  |
  41   *-----------------------------------------------------------------------------
  42   * SYSCLK(MHz)                        | 24                     | 24
  43   *-----------------------------------------------------------------------------
  44   * AHBCLK (MHz)                       | 24                     | 24
  45   *-----------------------------------------------------------------------------
  46   * APB1CLK (MHz)                      | 24                     | 24
  47   *-----------------------------------------------------------------------------
  48   * APB2CLK (MHz)                      | 24                     | 24
  49   *-----------------------------------------------------------------------------
  50   ******************************************************************************
  51   * @attention
  52   *
  53   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  54   *
  55   * Redistribution and use in source and binary forms, with or without modification,
  56   * are permitted provided that the following conditions are met:
  57   *   1. Redistributions of source code must retain the above copyright notice,
  58   *      this list of conditions and the following disclaimer.
  59   *   2. Redistributions in binary form must reproduce the above copyright notice,
  60   *      this list of conditions and the following disclaimer in the documentation
  61   *      and/or other materials provided with the distribution.
  62   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  63   *      may be used to endorse or promote products derived from this software
  64   *      without specific prior written permission.
  65   *
  66   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  67   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  68   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  69   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  70   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  71   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  72   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  73   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  74   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  75   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  76   *
  77   ******************************************************************************
  78   */
  79
  80 /** @addtogroup CMSIS
  81   * @{
  82   */
  83
  84 /** @addtogroup stm32f1xx_system
  85   * @{
  86   */
  87
  88 /** @addtogroup STM32F1xx_System_Private_Includes
  89   * @{
  90   */
  91
  92 #include "stm32f1xx.h"
  93 #include "hal_tick.h"
  94
  95 /**
  96   * @}
  97   */
  98
  99 /** @addtogroup STM32F1xx_System_Private_TypesDefinitions
 100   * @{
 101   */
 102
 103 /**
 104   * @}
 105   */
 106
 107 /** @addtogroup STM32F1xx_System_Private_Defines
 108   * @{
 109   */
 110
 111 #if !defined  (HSE_VALUE)
 112   #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
 113                                                 This value can be provided and adapted by the user application. */
 114 #endif /* HSE_VALUE */
 115
 116 #if !defined  (HSI_VALUE)
 117   #define HSI_VALUE    ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
 118                                                 This value can be provided and adapted by the user application. */
 119 #endif /* HSI_VALUE */
 120
 121 /*!< Uncomment the following line if you need to use external SRAM  */
 122 #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
 123 /* #define DATA_IN_ExtSRAM */
 124 #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
 125
 126 /*!< Uncomment the following line if you need to relocate your vector Table in
 127      Internal SRAM. */
 128 /* #define VECT_TAB_SRAM */
 129 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
 130                                   This value must be a multiple of 0x200. */
 131
 132
 133 /**
 134   * @}
 135   */
 136
 137 /** @addtogroup STM32F1xx_System_Private_Macros
 138   * @{
 139   */
 140
 141 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
 142 #define USE_PLL_HSE_EXTC (0) /* Use external clock */
 143 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
 144
 145 /**
 146   * @}
 147   */
 148
 149 /** @addtogroup STM32F1xx_System_Private_Variables
 150   * @{
 151   */
 152
 153 /*******************************************************************************
 154 *  Clock Definitions
 155 *******************************************************************************/
 156 #if defined(STM32F100xB) ||defined(STM32F100xE)
 157   uint32_t SystemCoreClock         = 24000000;        /*!< System Clock Frequency (Core Clock) */
 158 #else /*!< HSI Selected as System Clock source */
 159   uint32_t SystemCoreClock         = 72000000;        /*!< System Clock Frequency (Core Clock) */
 160 #endif
 161
 162 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 163 /**
 164   * @}
 165   */
 166
 167 /** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
 168   * @{
 169   */
 170
 171 #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
 172 #ifdef DATA_IN_ExtSRAM
 173   static void SystemInit_ExtMemCtl(void);
 174 #endif /* DATA_IN_ExtSRAM */
 175 #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
 176
 177 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
 178 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
 179 #endif
 180
 181 uint8_t SetSysClock_PLL_HSI(void);
 182
 183 /**
 184   * @}
 185   */
 186
 187 /** @addtogroup STM32F1xx_System_Private_Functions
 188   * @{
 189   */
 190
 191 /**
 192   * @brief  Setup the microcontroller system
 193   *         Initialize the Embedded Flash Interface, the PLL and update the
 194   *         SystemCoreClock variable.
 195   * @note   This function should be used only after reset.
 196   * @param  None
 197   * @retval None
 198   */
 199 void SystemInit (void)
 200 {
 201   /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
 202   /* Set HSION bit */
 203   RCC->CR |= (uint32_t)0x00000001;
 204
 205   /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
 206 #if !defined(STM32F105xC) && !defined(STM32F107xC)
 207   RCC->CFGR &= (uint32_t)0xF8FF0000;
 208 #else
 209   RCC->CFGR &= (uint32_t)0xF0FF0000;
 210 #endif /* STM32F105xC */
 211
 212   /* Reset HSEON, CSSON and PLLON bits */
 213   RCC->CR &= (uint32_t)0xFEF6FFFF;
 214
 215   /* Reset HSEBYP bit */
 216   RCC->CR &= (uint32_t)0xFFFBFFFF;
 217
 218   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
 219   RCC->CFGR &= (uint32_t)0xFF80FFFF;
 220
 221 #if defined(STM32F105xC) || defined(STM32F107xC)
 222   /* Reset PLL2ON and PLL3ON bits */
 223   RCC->CR &= (uint32_t)0xEBFFFFFF;
 224
 225   /* Disable all interrupts and clear pending bits  */
 226   RCC->CIR = 0x00FF0000;
 227
 228   /* Reset CFGR2 register */
 229   RCC->CFGR2 = 0x00000000;
 230 #elif defined(STM32F100xB) || defined(STM32F100xE)
 231   /* Disable all interrupts and clear pending bits  */
 232   RCC->CIR = 0x009F0000;
 233
 234   /* Reset CFGR2 register */
 235   RCC->CFGR2 = 0x00000000;
 236 #else
 237   /* Disable all interrupts and clear pending bits  */
 238   RCC->CIR = 0x009F0000;
 239 #endif /* STM32F105xC */
 240
 241 #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
 242   #ifdef DATA_IN_ExtSRAM
 243     SystemInit_ExtMemCtl();
 244   #endif /* DATA_IN_ExtSRAM */
 245 #endif
 246
 247 #ifdef VECT_TAB_SRAM
 248   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
 249 #else
 250   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
 251 #endif
 252
 253   /* Configure the Cube driver */
 254   SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
 255   HAL_Init();
 256
 257   /* Configure the System clock source, PLL Multiplier and Divider factors,
 258      AHB/APBx prescalers and Flash settings */
 259   SetSysClock();
 260
 261   /* Reset the timer to avoid issues after the RAM initialization */
 262   TIM_MST_RESET_ON;
 263   TIM_MST_RESET_OFF;
 264 }
 265
 266 /**
 267   * @brief  Update SystemCoreClock variable according to Clock Register Values.
 268   *         The SystemCoreClock variable contains the core clock (HCLK), it can
 269   *         be used by the user application to setup the SysTick timer or configure
 270   *         other parameters.
 271   *
 272   * @note   Each time the core clock (HCLK) changes, this function must be called
 273   *         to update SystemCoreClock variable value. Otherwise, any configuration
 274   *         based on this variable will be incorrect.
 275   *
 276   * @note   - The system frequency computed by this function is not the real
 277   *           frequency in the chip. It is calculated based on the predefined
 278   *           constant and the selected clock source:
 279   *
 280   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
 281   *
 282   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
 283   *
 284   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
 285   *             or HSI_VALUE(*) multiplied by the PLL factors.
 286   *
 287   *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
 288   *             8 MHz) but the real value may vary depending on the variations
 289   *             in voltage and temperature.
 290   *
 291   *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
 292   *              8 MHz or 25 MHz, depending on the product used), user has to ensure
 293   *              that HSE_VALUE is same as the real frequency of the crystal used.
 294   *              Otherwise, this function may have wrong result.
 295   *
 296   *         - The result of this function could be not correct when using fractional
 297   *           value for HSE crystal.
 298   * @param  None
 299   * @retval None
 300   */
 301 void SystemCoreClockUpdate (void)
 302 {
 303   uint32_t tmp = 0, pllmull = 0, pllsource = 0;
 304
 305 #if defined(STM32F105xC) || defined(STM32F107xC)
 306   uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
 307 #endif /* STM32F105xC */
 308
 309 #if defined(STM32F100xB) || defined(STM32F100xE)
 310   uint32_t prediv1factor = 0;
 311 #endif /* STM32F100xB or STM32F100xE */
 312
 313   /* Get SYSCLK source -------------------------------------------------------*/
 314   tmp = RCC->CFGR & RCC_CFGR_SWS;
 315
 316   switch (tmp)
 317   {
 318     case 0x00:  /* HSI used as system clock */
 319       SystemCoreClock = HSI_VALUE;
 320       break;
 321     case 0x04:  /* HSE used as system clock */
 322       SystemCoreClock = HSE_VALUE;
 323       break;
 324     case 0x08:  /* PLL used as system clock */
 325
 326       /* Get PLL clock source and multiplication factor ----------------------*/
 327       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
 328       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
 329
 330 #if !defined(STM32F105xC) && !defined(STM32F107xC)
 331       pllmull = ( pllmull >> 18) + 2;
 332
 333       if (pllsource == 0x00)
 334       {
 335         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
 336         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
 337       }
 338       else
 339       {
 340  #if defined(STM32F100xB) || defined(STM32F100xE)
 341        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
 342        /* HSE oscillator clock selected as PREDIV1 clock entry */
 343        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
 344  #else
 345         /* HSE selected as PLL clock entry */
 346         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
 347         {/* HSE oscillator clock divided by 2 */
 348           SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
 349         }
 350         else
 351         {
 352           SystemCoreClock = HSE_VALUE * pllmull;
 353         }
 354  #endif
 355       }
 356 #else
 357       pllmull = pllmull >> 18;
 358
 359       if (pllmull != 0x0D)
 360       {
 361          pllmull += 2;
 362       }
 363       else
 364       { /* PLL multiplication factor = PLL input clock * 6.5 */
 365         pllmull = 13 / 2;
 366       }
 367
 368       if (pllsource == 0x00)
 369       {
 370         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
 371         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
 372       }
 373       else
 374       {/* PREDIV1 selected as PLL clock entry */
 375
 376         /* Get PREDIV1 clock source and division factor */
 377         prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
 378         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
 379
 380         if (prediv1source == 0)
 381         {
 382           /* HSE oscillator clock selected as PREDIV1 clock entry */
 383           SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
 384         }
 385         else
 386         {/* PLL2 clock selected as PREDIV1 clock entry */
 387
 388           /* Get PREDIV2 division factor and PLL2 multiplication factor */
 389           prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
 390           pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
 391           SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
 392         }
 393       }
 394 #endif /* STM32F105xC */
 395       break;
 396
 397     default:
 398       SystemCoreClock = HSI_VALUE;
 399       break;
 400   }
 401
 402   /* Compute HCLK clock frequency ----------------*/
 403   /* Get HCLK prescaler */
 404   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
 405   /* HCLK clock frequency */
 406   SystemCoreClock >>= tmp;
 407 }
 408
 409 #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
 410 /**
 411   * @brief  Setup the external memory controller. Called in startup_stm32f1xx.s
 412   *          before jump to __main
 413   * @param  None
 414   * @retval None
 415   */
 416 #ifdef DATA_IN_ExtSRAM
 417 /**
 418   * @brief  Setup the external memory controller.
 419   *         Called in startup_stm32f1xx_xx.s/.c before jump to main.
 420   *         This function configures the external SRAM mounted on STM3210E-EVAL
 421   *         board (STM32 High density devices). This SRAM will be used as program
 422   *         data memory (including heap and stack).
 423   * @param  None
 424   * @retval None
 425   */
 426 void SystemInit_ExtMemCtl(void)
 427 {
 428   __IO uint32_t tmpreg;
 429   /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
 430     required, then adjust the Register Addresses */
 431
 432   /* Enable FSMC clock */
 433   RCC->AHBENR = 0x00000114;
 434
 435   /* Delay after an RCC peripheral clock enabling */
 436   tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
 437
 438   /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
 439   RCC->APB2ENR = 0x000001E0;
 440
 441   /* Delay after an RCC peripheral clock enabling */
 442   tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
 443
 444   (void)(tmpreg);
 445
 446 /* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
 447 /*----------------  SRAM Address lines configuration -------------------------*/
 448 /*----------------  NOE and NWE configuration --------------------------------*/
 449 /*----------------  NE3 configuration ----------------------------------------*/
 450 /*----------------  NBL0, NBL1 configuration ---------------------------------*/
 451
 452   GPIOD->CRL = 0x44BB44BB;
 453   GPIOD->CRH = 0xBBBBBBBB;
 454
 455   GPIOE->CRL = 0xB44444BB;
 456   GPIOE->CRH = 0xBBBBBBBB;
 457
 458   GPIOF->CRL = 0x44BBBBBB;
 459   GPIOF->CRH = 0xBBBB4444;
 460
 461   GPIOG->CRL = 0x44BBBBBB;
 462   GPIOG->CRH = 0x444B4B44;
 463
 464 /*----------------  FSMC Configuration ---------------------------------------*/
 465 /*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
 466
 467   FSMC_Bank1->BTCR[4] = 0x00001091;
 468   FSMC_Bank1->BTCR[5] = 0x00110212;
 469 }
 470 #endif /* DATA_IN_ExtSRAM */
 471 #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
 472
 473 /**
 474   * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
 475   *               AHB/APBx prescalers and Flash settings
 476   * @note   This function should be called only once the RCC clock configuration
 477   *         is reset to the default reset state (done in SystemInit() function).
 478   * @param  None
 479   * @retval None
 480   */
 481 void SetSysClock(void)
 482 {
 483   /* 1- Try to start with HSE and external clock */
 484 #if USE_PLL_HSE_EXTC != 0
 485   if (SetSysClock_PLL_HSE(1) == 0)
 486 #endif
 487   {
 488     /* 2- If fail try to start with HSE and external xtal */
 489     #if USE_PLL_HSE_XTAL != 0
 490     if (SetSysClock_PLL_HSE(0) == 0)
 491     #endif
 492     {
 493       /* 3- If fail start with HSI clock */
 494       if (SetSysClock_PLL_HSI() == 0)
 495       {
 496         while(1)
 497         {
 498           // [TODO] Put something here to tell the user that a problem occured...
 499         }
 500       }
 501     }
 502   }
 503
 504   /* Output clock on MCO1 pin(PA8) for debugging purpose */
 505   //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); // 24 MHz
 506 }
 507
 508 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
 509 /******************************************************************************/
 510 /*            PLL (clocked by HSE) used as System clock source                */
 511 /******************************************************************************/
 512 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
 513 {
 514   RCC_ClkInitTypeDef RCC_ClkInitStruct;
 515   RCC_OscInitTypeDef RCC_OscInitStruct;
 516
 517   /* Enable HSE oscillator and activate PLL with HSE as source */
 518   RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
 519   if (bypass == 0)
 520   {
 521     RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
 522   }
 523   else
 524   {
 525     RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
 526   }
 527   RCC_OscInitStruct.HSEPredivValue      = RCC_HSE_PREDIV_DIV2;
 528   RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
 529   RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
 530   RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL6; // 24 MHz (4 MHz * 6)
 531   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 532   {
 533     return 0; // FAIL
 534   }
 535
 536   /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
 537   RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
 538   RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 24 MHz
 539   RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 24 MHz
 540   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 24 MHz
 541   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 24 MHz
 542   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
 543   {
 544     return 0; // FAIL
 545   }
 546
 547   /* Output clock on MCO1 pin(PA8) for debugging purpose */
 548   //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
 549
 550   return 1; // OK
 551 }
 552 #endif
 553
 554 /******************************************************************************/
 555 /*            PLL (clocked by HSI) used as System clock source                */
 556 /******************************************************************************/
 557 uint8_t SetSysClock_PLL_HSI(void)
 558 {
 559   RCC_ClkInitTypeDef RCC_ClkInitStruct;
 560   RCC_OscInitTypeDef RCC_OscInitStruct;
 561
 562   /* Enable HSI oscillator and activate PLL with HSI as source */
 563   RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
 564   RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
 565   RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
 566   RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
 567   RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
 568   RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI_DIV2;
 569   RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL6; // 24 MHz (8 MHz/2 * 6)
 570   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 571   {
 572     return 0; // FAIL
 573   }
 574
 575   /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
 576   RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
 577   RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 24 MHz
 578   RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 24 MHz
 579   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 24 MHz
 580   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 24 MHz
 581   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
 582   {
 583     return 0; // FAIL
 584   }
 585
 586   /* Output clock on MCO1 pin(PA8) for debugging purpose */
 587   //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 8 MHz
 588
 589   return 1; // OK
 590 }
 591
 592 /**
 593   * @}
 594   */
 595
 596 /**
 597   * @}
 598   */
 599
 600 /**
 601   * @}
 602   */
 603 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/