tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32_hal_legacy.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32_hal_legacy.h
   4   * @author  MCD Application Team
   5   * @version V1.0.0
   6   * @date    15-December-2014
   7   * @brief   This file contains aliases definition for the STM32Cube HAL constants
   8   *          macros and functions maintained for legacy purpose.
   9   ******************************************************************************
  10   * @attention
  11   *
  12   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  13   *
  14   * Redistribution and use in source and binary forms, with or without modification,
  15   * are permitted provided that the following conditions are met:
  16   *   1. Redistributions of source code must retain the above copyright notice,
  17   *      this list of conditions and the following disclaimer.
  18   *   2. Redistributions in binary form must reproduce the above copyright notice,
  19   *      this list of conditions and the following disclaimer in the documentation
  20   *      and/or other materials provided with the distribution.
  21   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  22   *      may be used to endorse or promote products derived from this software
  23   *      without specific prior written permission.
  24   *
  25   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  26   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  27   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  28   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  29   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  30   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  31   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  32   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  33  UART * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  34   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35   *
  36   ******************************************************************************
  37   */
  38
  39 /* Define to prevent recursive inclusion -------------------------------------*/
  40 #ifndef __STM32_HAL_LEGACY
  41 #define __STM32_HAL_LEGACY
  42
  43 #ifdef __cplusplus
  44  extern "C" {
  45 #endif
  46
  47 /* Includes ------------------------------------------------------------------*/
  48 /* Exported types ------------------------------------------------------------*/
  49 /* Exported constants --------------------------------------------------------*/
  50
  51 /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
  52   * @{
  53   */
  54 #define AES_FLAG_RDERR                 CRYP_FLAG_RDERR
  55 #define AES_FLAG_WRERR                 CRYP_FLAG_WRERR
  56 #define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF
  57 #define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR
  58 #define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR
  59
  60 /**
  61   * @}
  62   */
  63
  64 /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
  65   * @{
  66   */
  67 #define ADC_RESOLUTION12b               ADC_RESOLUTION_12B
  68 #define ADC_RESOLUTION10b               ADC_RESOLUTION_10B
  69 #define ADC_RESOLUTION8b                ADC_RESOLUTION_8B
  70 #define ADC_RESOLUTION6b                ADC_RESOLUTION_6B
  71 #define OVR_DATA_OVERWRITTEN            ADC_OVR_DATA_OVERWRITTEN
  72 #define OVR_DATA_PRESERVED              ADC_OVR_DATA_PRESERVED
  73 #define EOC_SINGLE_CONV                 ADC_EOC_SINGLE_CONV
  74 #define EOC_SEQ_CONV                    ADC_EOC_SEQ_CONV
  75 #define EOC_SINGLE_SEQ_CONV             ADC_EOC_SINGLE_SEQ_CONV
  76 #define REGULAR_GROUP                   ADC_REGULAR_GROUP
  77 #define INJECTED_GROUP                  ADC_INJECTED_GROUP
  78 #define REGULAR_INJECTED_GROUP          ADC_REGULAR_INJECTED_GROUP
  79 #define AWD_EVENT                       ADC_AWD_EVENT
  80 #define AWD1_EVENT                      ADC_AWD1_EVENT
  81 #define AWD2_EVENT                      ADC_AWD2_EVENT
  82 #define AWD3_EVENT                      ADC_AWD3_EVENT
  83 #define OVR_EVENT                       ADC_OVR_EVENT
  84 #define JQOVF_EVENT                     ADC_JQOVF_EVENT
  85 #define ALL_CHANNELS                    ADC_ALL_CHANNELS
  86 #define REGULAR_CHANNELS                ADC_REGULAR_CHANNELS
  87 #define INJECTED_CHANNELS               ADC_INJECTED_CHANNELS
  88 #define SYSCFG_FLAG_SENSOR_ADC          ADC_FLAG_SENSOR
  89 #define SYSCFG_FLAG_VREF_ADC            ADC_FLAG_VREFINT
  90 #define ADC_CLOCKPRESCALER_PCLK_DIV1    ADC_CLOCK_SYNC_PCLK_DIV1
  91 #define ADC_CLOCKPRESCALER_PCLK_DIV2    ADC_CLOCK_SYNC_PCLK_DIV2
  92 #define ADC_CLOCKPRESCALER_PCLK_DIV4    ADC_CLOCK_SYNC_PCLK_DIV4
  93 #define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO
  94 #define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2
  95 #define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO
  96 #define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4
  97 #define ADC_EXTERNALTRIG4_T22_TRGO      ADC_EXTERNALTRIGCONV_T22_TRGO
  98 #define ADC_EXTERNALTRIG7_EXT_IT11      ADC_EXTERNALTRIGCONV_EXT_IT11
  99 #define ADC_CLOCK_ASYNC                 ADC_CLOCK_ASYNC_DIV1
 100
 101
 102 /**
 103   * @}
 104   */
 105
 106 /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
 107   * @{
 108   */
 109
 110 #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
 111
 112 /**
 113   * @}
 114   */
 115
 116 /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
 117   * @{
 118   */
 119
 120 #define COMP_WINDOWMODE_DISABLED    COMP_WINDOWMODE_DISABLE
 121 #define COMP_WINDOWMODE_ENABLED     COMP_WINDOWMODE_ENABLE
 122 #define COMP_EXTI_LINE_COMP1_EVENT  COMP_EXTI_LINE_COMP1
 123 #define COMP_EXTI_LINE_COMP2_EVENT  COMP_EXTI_LINE_COMP2
 124
 125 /**
 126   * @}
 127   */
 128
 129 /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
 130   * @{
 131   */
 132
 133 #define CRC_OUTPUTDATA_INVERSION_DISABLED    CRC_OUTPUTDATA_INVERSION_DISABLE
 134 #define CRC_OUTPUTDATA_INVERSION_ENABLED     CRC_OUTPUTDATA_INVERSION_ENABLE
 135
 136 /**
 137   * @}
 138   */
 139
 140 /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
 141   * @{
 142   */
 143
 144 #define DAC1_CHANNEL_1                                  DAC_CHANNEL_1
 145 #define DAC1_CHANNEL_2                                  DAC_CHANNEL_2
 146 #define DAC2_CHANNEL_1                                  DAC_CHANNEL_1
 147
 148 /**
 149   * @}
 150   */
 151
 152
 153 /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
 154   * @{
 155   */
 156
 157 #define TYPEPROGRAM_BYTE              FLASH_TYPEPROGRAM_BYTE
 158 #define TYPEPROGRAM_HALFWORD          FLASH_TYPEPROGRAM_HALFWORD
 159 #define TYPEPROGRAM_WORD              FLASH_TYPEPROGRAM_WORD
 160 #define TYPEPROGRAM_DOUBLEWORD        FLASH_TYPEPROGRAM_DOUBLEWORD
 161 #define TYPEERASE_SECTORS             FLASH_TYPEERASE_SECTORS
 162 #define TYPEERASE_PAGES               FLASH_TYPEERASE_PAGES
 163 #define TYPEERASE_PAGEERASE           FLASH_TYPEERASE_PAGES
 164 #define TYPEERASE_MASSERASE           FLASH_TYPEERASE_MASSERASE
 165 #define WRPSTATE_DISABLE              OB_WRPSTATE_DISABLE
 166 #define WRPSTATE_ENABLE               OB_WRPSTATE_ENABLE
 167 #define HAL_FLASH_TIMEOUT_VALUE       FLASH_TIMEOUT_VALUE
 168 #define OBEX_PCROP                    OPTIONBYTE_PCROP
 169 #define OBEX_BOOTCONFIG               OPTIONBYTE_BOOTCONFIG
 170 #define PCROPSTATE_DISABLE            OB_PCROP_STATE_DISABLE
 171 #define PCROPSTATE_ENABLE             OB_PCROP_STATE_ENABLE
 172 #define TYPEERASEDATA_BYTE            FLASH_TYPEERASEDATA_BYTE
 173 #define TYPEERASEDATA_HALFWORD        FLASH_TYPEERASEDATA_HALFWORD
 174 #define TYPEERASEDATA_WORD            FLASH_TYPEERASEDATA_WORD
 175 #define TYPEPROGRAMDATA_BYTE          FLASH_TYPEPROGRAMDATA_BYTE
 176 #define TYPEPROGRAMDATA_HALFWORD      FLASH_TYPEPROGRAMDATA_HALFWORD
 177 #define TYPEPROGRAMDATA_WORD          FLASH_TYPEPROGRAMDATA_WORD
 178 #define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE
 179 #define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD
 180 #define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD
 181 #define PAGESIZE                      FLASH_PAGE_SIZE
 182 #define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE
 183 #define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD
 184 #define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD
 185 #define VOLTAGE_RANGE_1               FLASH_VOLTAGE_RANGE_1
 186 #define VOLTAGE_RANGE_2               FLASH_VOLTAGE_RANGE_2
 187 #define VOLTAGE_RANGE_3               FLASH_VOLTAGE_RANGE_3
 188 #define VOLTAGE_RANGE_4               FLASH_VOLTAGE_RANGE_4
 189 #define TYPEPROGRAM_FAST              FLASH_TYPEPROGRAM_FAST
 190 #define TYPEPROGRAM_FAST_AND_LAST     FLASH_TYPEPROGRAM_FAST_AND_LAST
 191 #define WRPAREA_BANK1_AREAA           OB_WRPAREA_BANK1_AREAA
 192 #define WRPAREA_BANK1_AREAB           OB_WRPAREA_BANK1_AREAB
 193 #define WRPAREA_BANK2_AREAA           OB_WRPAREA_BANK2_AREAA
 194 #define WRPAREA_BANK2_AREAB           OB_WRPAREA_BANK2_AREAB
 195 #define IWDG_STDBY_FREEZE             OB_IWDG_STDBY_FREEZE
 196 #define IWDG_STDBY_ACTIVE             OB_IWDG_STDBY_RUN
 197 #define IWDG_STOP_FREEZE              OB_IWDG_STOP_FREEZE
 198 #define IWDG_STOP_ACTIVE              OB_IWDG_STOP_RUN
 199 #define IS_NBSECTORS                  IS_FLASH_NBSECTORS
 200 #define FLASH_ERROR_NONE              HAL_FLASH_ERROR_NONE
 201 #define FLASH_ERROR_RD                HAL_FLASH_ERROR_RD
 202 #define FLASH_ERROR_PG                HAL_FLASH_ERROR_PROG
 203 #define FLASH_ERROR_PGP               HAL_FLASH_ERROR_PGS
 204 #define FLASH_ERROR_WRP               HAL_FLASH_ERROR_WRP
 205 #define FLASH_ERROR_OPTV              HAL_FLASH_ERROR_OPTV
 206 #define FLASH_ERROR_OPTVUSR           HAL_FLASH_ERROR_OPTVUSR
 207 #define FLASH_ERROR_PROG              HAL_FLASH_ERROR_PROG
 208 #define FLASH_ERROR_OP                HAL_FLASH_ERROR_OPERATION
 209 #define FLASH_ERROR_PGA               HAL_FLASH_ERROR_PGA
 210 #define FLASH_ERROR_SIZE              HAL_FLASH_ERROR_SIZE
 211 #define FLASH_ERROR_SIZ               HAL_FLASH_ERROR_SIZE
 212 #define FLASH_ERROR_PGS               HAL_FLASH_ERROR_PGS
 213 #define FLASH_ERROR_MIS               HAL_FLASH_ERROR_MIS
 214 #define FLASH_ERROR_FAST              HAL_FLASH_ERROR_FAST
 215 #define FLASH_ERROR_FWWERR            HAL_FLASH_ERROR_FWWERR
 216 #define FLASH_ERROR_NOTZERO           HAL_FLASH_ERROR_NOTZERO
 217 #define FLASH_ERROR_OPERATION         HAL_FLASH_ERROR_OPERATION
 218 #define FLASH_ERROR_ERS               HAL_FLASH_ERROR_ERS
 219
 220 /**
 221   * @}
 222   */
 223
 224 /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
 225   * @{
 226   */
 227
 228 #define SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6
 229 #define SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7
 230 #define SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8
 231 #define SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9
 232 #define SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1
 233 #define SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2
 234 #define SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3
 235
 236 /**
 237   * @}
 238   */
 239
 240
 241 /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
 242   * @{
 243   */
 244
 245 #define FSMC_NORSRAM_TYPEDEF                      FSMC_NORSRAM_TypeDef
 246 #define FSMC_NORSRAM_EXTENDED_TYPEDEF             FSMC_NORSRAM_EXTENDED_TypeDef
 247 /**
 248   * @}
 249   */
 250
 251 /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
 252   * @{
 253   */
 254 #define GET_GPIO_SOURCE                           GPIO_GET_INDEX
 255 #define GET_GPIO_INDEX                            GPIO_GET_INDEX
 256 /**
 257   * @}
 258   */
 259
 260
 261 /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
 262   * @{
 263   */
 264 #define I2C_DUALADDRESS_DISABLED                I2C_DUALADDRESS_DISABLE
 265 #define I2C_DUALADDRESS_ENABLED                 I2C_DUALADDRESS_ENABLE
 266 #define I2C_GENERALCALL_DISABLED                I2C_GENERALCALL_DISABLE
 267 #define I2C_GENERALCALL_ENABLED                 I2C_GENERALCALL_ENABLE
 268 #define I2C_NOSTRETCH_DISABLED                  I2C_NOSTRETCH_DISABLE
 269 #define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE
 270 #define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE
 271 #define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE
 272 /**
 273   * @}
 274   */
 275
 276 /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
 277   * @{
 278   */
 279 #define IRDA_ONE_BIT_SAMPLE_DISABLED            IRDA_ONE_BIT_SAMPLE_DISABLE
 280 #define IRDA_ONE_BIT_SAMPLE_ENABLED             IRDA_ONE_BIT_SAMPLE_ENABLE
 281
 282 /**
 283   * @}
 284   */
 285
 286 /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
 287   * @{
 288   */
 289 #define KR_KEY_RELOAD                   IWDG_KEY_RELOAD
 290 #define KR_KEY_ENABLE                   IWDG_KEY_ENABLE
 291 #define KR_KEY_EWA                      IWDG_KEY_WRITE_ACCESS_ENABLE
 292 #define KR_KEY_DWA                      IWDG_KEY_WRITE_ACCESS_DISABLE
 293 /**
 294   * @}
 295   */
 296
 297 /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
 298   * @{
 299   */
 300 #define NAND_AddressTypedef             NAND_AddressTypeDef
 301
 302 /**
 303   * @}
 304   */
 305
 306 /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
 307   * @{
 308   */
 309 #define NOR_StatusTypedef              HAL_NOR_StatusTypeDef
 310 #define NOR_SUCCESS                    HAL_NOR_STATUS_SUCCESS
 311 #define NOR_ONGOING                    HAL_NOR_STATUS_ONGOING
 312 #define NOR_ERROR                      HAL_NOR_STATUS_ERROR
 313 #define NOR_TIMEOUT                    HAL_NOR_STATUS_TIMEOUT
 314
 315 /**
 316   * @}
 317   */
 318
 319 /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
 320   * @{
 321   */
 322
 323 #define OPAMP_NONINVERTINGINPUT_VP0           OPAMP_NONINVERTINGINPUT_IO0
 324 #define OPAMP_NONINVERTINGINPUT_VP1           OPAMP_NONINVERTINGINPUT_IO1
 325 #define OPAMP_NONINVERTINGINPUT_VP2           OPAMP_NONINVERTINGINPUT_IO2
 326 #define OPAMP_NONINVERTINGINPUT_VP3           OPAMP_NONINVERTINGINPUT_IO3
 327
 328 #define OPAMP_SEC_NONINVERTINGINPUT_VP0       OPAMP_SEC_NONINVERTINGINPUT_IO0
 329 #define OPAMP_SEC_NONINVERTINGINPUT_VP1       OPAMP_SEC_NONINVERTINGINPUT_IO1
 330 #define OPAMP_SEC_NONINVERTINGINPUT_VP2       OPAMP_SEC_NONINVERTINGINPUT_IO2
 331 #define OPAMP_SEC_NONINVERTINGINPUT_VP3       OPAMP_SEC_NONINVERTINGINPUT_IO3
 332
 333 #define OPAMP_INVERTINGINPUT_VM0              OPAMP_INVERTINGINPUT_IO0
 334 #define OPAMP_INVERTINGINPUT_VM1              OPAMP_INVERTINGINPUT_IO1
 335
 336 #define IOPAMP_INVERTINGINPUT_VM0             OPAMP_INVERTINGINPUT_IO0
 337 #define IOPAMP_INVERTINGINPUT_VM1             OPAMP_INVERTINGINPUT_IO1
 338
 339 #define OPAMP_SEC_INVERTINGINPUT_VM0          OPAMP_SEC_INVERTINGINPUT_IO0
 340 #define OPAMP_SEC_INVERTINGINPUT_VM1          OPAMP_SEC_INVERTINGINPUT_IO1
 341
 342 #define OPAMP_INVERTINGINPUT_VINM             OPAMP_SEC_INVERTINGINPUT_IO1
 343
 344 #define OPAMP_PGACONNECT_NO                   OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
 345 #define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
 346 #define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
 347
 348 /**
 349   * @}
 350   */
 351
 352 /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
 353   * @{
 354   */
 355 #define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS
 356 /**
 357   * @}
 358   */
 359
 360 /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
 361   * @{
 362   */
 363
 364 /* Compact Flash-ATA registers description */
 365 #define CF_DATA                       ATA_DATA
 366 #define CF_SECTOR_COUNT               ATA_SECTOR_COUNT
 367 #define CF_SECTOR_NUMBER              ATA_SECTOR_NUMBER
 368 #define CF_CYLINDER_LOW               ATA_CYLINDER_LOW
 369 #define CF_CYLINDER_HIGH              ATA_CYLINDER_HIGH
 370 #define CF_CARD_HEAD                  ATA_CARD_HEAD
 371 #define CF_STATUS_CMD                 ATA_STATUS_CMD
 372 #define CF_STATUS_CMD_ALTERNATE       ATA_STATUS_CMD_ALTERNATE
 373 #define CF_COMMON_DATA_AREA           ATA_COMMON_DATA_AREA
 374
 375 /* Compact Flash-ATA commands */
 376 #define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD
 377 #define CF_WRITE_SECTOR_CMD           ATA_WRITE_SECTOR_CMD
 378 #define CF_ERASE_SECTOR_CMD           ATA_ERASE_SECTOR_CMD
 379 #define CF_IDENTIFY_CMD               ATA_IDENTIFY_CMD
 380
 381 #define PCCARD_StatusTypedef          HAL_PCCARD_StatusTypeDef
 382 #define PCCARD_SUCCESS                HAL_PCCARD_STATUS_SUCCESS
 383 #define PCCARD_ONGOING                HAL_PCCARD_STATUS_ONGOING
 384 #define PCCARD_ERROR                  HAL_PCCARD_STATUS_ERROR
 385 #define PCCARD_TIMEOUT                HAL_PCCARD_STATUS_TIMEOUT
 386 /**
 387   * @}
 388   */
 389
 390 /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
 391   * @{
 392   */
 393
 394 #define FORMAT_BIN                  RTC_FORMAT_BIN
 395 #define FORMAT_BCD                  RTC_FORMAT_BCD
 396
 397 #define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE
 398 #define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
 399 #define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE
 400 #define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE
 401 #define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE
 402
 403 #define RTC_MASKTAMPERFLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE
 404 #define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE
 405 #define RTC_TAMPERERASEBACKUP_ENABLED  RTC_TAMPER_ERASE_BACKUP_ENABLE
 406 #define RTC_TAMPERERASEBACKUP_DISABLED   RTC_TAMPER_ERASE_BACKUP_DISABLE
 407 #define RTC_MASKTAMPERFLAG_DISABLED   RTC_TAMPERMASK_FLAG_DISABLE
 408 #define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE
 409 #define RTC_TAMPER1_2_INTERRUPT          RTC_ALL_TAMPER_INTERRUPT
 410 #define RTC_TAMPER1_2_3_INTERRUPT     RTC_ALL_TAMPER_INTERRUPT
 411
 412 /**
 413   * @}
 414   */
 415
 416
 417 /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
 418   * @{
 419   */
 420 #define SMARTCARD_NACK_ENABLED                  SMARTCARD_NACK_ENABLE
 421 #define SMARTCARD_NACK_DISABLED                 SMARTCARD_NACK_DISABLE
 422
 423 #define SMARTCARD_ONEBIT_SAMPLING_DISABLED      SMARTCARD_ONE_BIT_SAMPLE_DISABLE
 424 #define SMARTCARD_ONEBIT_SAMPLING_ENABLED       SMARTCARD_ONE_BIT_SAMPLE_ENABLE
 425 #define SMARTCARD_ONEBIT_SAMPLING_DISABLE       SMARTCARD_ONE_BIT_SAMPLE_DISABLE
 426 #define SMARTCARD_ONEBIT_SAMPLING_ENABLE        SMARTCARD_ONE_BIT_SAMPLE_ENABLE
 427
 428 #define SMARTCARD_TIMEOUT_DISABLED              SMARTCARD_TIMEOUT_DISABLE
 429 #define SMARTCARD_TIMEOUT_ENABLED               SMARTCARD_TIMEOUT_ENABLE
 430
 431 #define SMARTCARD_LASTBIT_DISABLED              SMARTCARD_LASTBIT_DISABLE
 432 #define SMARTCARD_LASTBIT_ENABLED               SMARTCARD_LASTBIT_ENABLE
 433 /**
 434   * @}
 435   */
 436
 437
 438   /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
 439   * @{
 440   */
 441 #define SMBUS_DUALADDRESS_DISABLED      SMBUS_DUALADDRESS_DISABLE
 442 #define SMBUS_DUALADDRESS_ENABLED       SMBUS_DUALADDRESS_ENABLE
 443 #define SMBUS_GENERALCALL_DISABLED      SMBUS_GENERALCALL_DISABLE
 444 #define SMBUS_GENERALCALL_ENABLED       SMBUS_GENERALCALL_ENABLE
 445 #define SMBUS_NOSTRETCH_DISABLED        SMBUS_NOSTRETCH_DISABLE
 446 #define SMBUS_NOSTRETCH_ENABLED         SMBUS_NOSTRETCH_ENABLE
 447 #define SMBUS_ANALOGFILTER_ENABLED      SMBUS_ANALOGFILTER_ENABLE
 448 #define SMBUS_ANALOGFILTER_DISABLED     SMBUS_ANALOGFILTER_DISABLE
 449 #define HAL_SMBUS_STATE_SLAVE_LISTEN    HAL_SMBUS_STATE_LISTEN
 450 /**
 451   * @}
 452   */
 453
 454   /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
 455   * @{
 456   */
 457 #define SPI_TIMODE_DISABLED             SPI_TIMODE_DISABLE
 458 #define SPI_TIMODE_ENABLED              SPI_TIMODE_ENABLE
 459
 460 #define SPI_CRCCALCULATION_DISABLED     SPI_CRCCALCULATION_DISABLE
 461 #define SPI_CRCCALCULATION_ENABLED      SPI_CRCCALCULATION_ENABLE
 462
 463 #define SPI_NSS_PULSE_DISABLED          SPI_NSS_PULSE_DISABLE
 464 #define SPI_NSS_PULSE_ENABLED           SPI_NSS_PULSE_ENABLE
 465
 466 /**
 467   * @}
 468   */
 469
 470 /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
 471   * @{
 472   */
 473 #define CCER_CCxE_MASK                   TIM_CCER_CCxE_MASK
 474 #define CCER_CCxNE_MASK                  TIM_CCER_CCxNE_MASK
 475
 476 #define TIM_DMABase_CR1                  TIM_DMABASE_CR1
 477 #define TIM_DMABase_CR2                  TIM_DMABASE_CR2
 478 #define TIM_DMABase_SMCR                 TIM_DMABASE_SMCR
 479 #define TIM_DMABase_DIER                 TIM_DMABASE_DIER
 480 #define TIM_DMABase_SR                   TIM_DMABASE_SR
 481 #define TIM_DMABase_EGR                  TIM_DMABASE_EGR
 482 #define TIM_DMABase_CCMR1                TIM_DMABASE_CCMR1
 483 #define TIM_DMABase_CCMR2                TIM_DMABASE_CCMR2
 484 #define TIM_DMABase_CCER                 TIM_DMABASE_CCER
 485 #define TIM_DMABase_CNT                  TIM_DMABASE_CNT
 486 #define TIM_DMABase_PSC                  TIM_DMABASE_PSC
 487 #define TIM_DMABase_ARR                  TIM_DMABASE_ARR
 488 #define TIM_DMABase_RCR                  TIM_DMABASE_RCR
 489 #define TIM_DMABase_CCR1                 TIM_DMABASE_CCR1
 490 #define TIM_DMABase_CCR2                 TIM_DMABASE_CCR2
 491 #define TIM_DMABase_CCR3                 TIM_DMABASE_CCR3
 492 #define TIM_DMABase_CCR4                 TIM_DMABASE_CCR4
 493 #define TIM_DMABase_BDTR                 TIM_DMABASE_BDTR
 494 #define TIM_DMABase_DCR                  TIM_DMABASE_DCR
 495 #define TIM_DMABase_DMAR                 TIM_DMABASE_DMAR
 496 #define TIM_DMABase_OR1                  TIM_DMABASE_OR1
 497 #define TIM_DMABase_CCMR3                TIM_DMABASE_CCMR3
 498 #define TIM_DMABase_CCR5                 TIM_DMABASE_CCR5
 499 #define TIM_DMABase_CCR6                 TIM_DMABASE_CCR6
 500 #define TIM_DMABase_OR2                  TIM_DMABASE_OR2
 501 #define TIM_DMABase_OR3                  TIM_DMABASE_OR3
 502
 503 #define TIM_EventSource_Update           TIM_EVENTSOURCE_UPDATE
 504 #define TIM_EventSource_CC1              TIM_EVENTSOURCE_CC1
 505 #define TIM_EventSource_CC2              TIM_EVENTSOURCE_CC2
 506 #define TIM_EventSource_CC3              TIM_EVENTSOURCE_CC3
 507 #define TIM_EventSource_CC4              TIM_EVENTSOURCE_CC4
 508 #define TIM_EventSource_COM              TIM_EVENTSOURCE_COM
 509 #define TIM_EventSource_Trigger          TIM_EVENTSOURCE_TRIGGER
 510 #define TIM_EventSource_Break            TIM_EVENTSOURCE_BREAK
 511 #define TIM_EventSource_Break2           TIM_EVENTSOURCE_BREAK2
 512
 513 #define TIM_DMABurstLength_1Transfer     TIM_DMABURSTLENGTH_1TRANSFER
 514 #define TIM_DMABurstLength_2Transfers    TIM_DMABURSTLENGTH_2TRANSFERS
 515 #define TIM_DMABurstLength_3Transfers    TIM_DMABURSTLENGTH_3TRANSFERS
 516 #define TIM_DMABurstLength_4Transfers    TIM_DMABURSTLENGTH_4TRANSFERS
 517 #define TIM_DMABurstLength_5Transfers    TIM_DMABURSTLENGTH_5TRANSFERS
 518 #define TIM_DMABurstLength_6Transfers    TIM_DMABURSTLENGTH_6TRANSFERS
 519 #define TIM_DMABurstLength_7Transfers    TIM_DMABURSTLENGTH_7TRANSFERS
 520 #define TIM_DMABurstLength_8Transfers    TIM_DMABURSTLENGTH_8TRANSFERS
 521 #define TIM_DMABurstLength_9Transfers    TIM_DMABURSTLENGTH_9TRANSFERS
 522 #define TIM_DMABurstLength_10Transfers   TIM_DMABURSTLENGTH_10TRANSFERS
 523 #define TIM_DMABurstLength_11Transfers   TIM_DMABURSTLENGTH_11TRANSFERS
 524 #define TIM_DMABurstLength_12Transfers   TIM_DMABURSTLENGTH_12TRANSFERS
 525 #define TIM_DMABurstLength_13Transfers   TIM_DMABURSTLENGTH_13TRANSFERS
 526 #define TIM_DMABurstLength_14Transfers   TIM_DMABURSTLENGTH_14TRANSFERS
 527 #define TIM_DMABurstLength_15Transfers   TIM_DMABURSTLENGTH_15TRANSFERS
 528 #define TIM_DMABurstLength_16Transfers   TIM_DMABURSTLENGTH_16TRANSFERS
 529 #define TIM_DMABurstLength_17Transfers   TIM_DMABURSTLENGTH_17TRANSFERS
 530 #define TIM_DMABurstLength_18Transfers   TIM_DMABURSTLENGTH_18TRANSFERS
 531
 532 /**
 533   * @}
 534   */
 535
 536 /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
 537   * @{
 538   */
 539 #define UART_ONEBIT_SAMPLING_DISABLED   UART_ONE_BIT_SAMPLE_DISABLE
 540 #define UART_ONEBIT_SAMPLING_ENABLED    UART_ONE_BIT_SAMPLE_ENABLE
 541 #define UART_ONE_BIT_SAMPLE_DISABLED    UART_ONE_BIT_SAMPLE_DISABLE
 542 #define UART_ONE_BIT_SAMPLE_ENABLED     UART_ONE_BIT_SAMPLE_ENABLE
 543
 544 #define __HAL_UART_ONEBIT_ENABLE        __HAL_UART_ONE_BIT_SAMPLE_ENABLE
 545 #define __HAL_UART_ONEBIT_DISABLE       __HAL_UART_ONE_BIT_SAMPLE_DISABLE
 546
 547 #define __DIV_SAMPLING16                UART_DIV_SAMPLING16
 548 #define __DIVMANT_SAMPLING16            UART_DIVMANT_SAMPLING16
 549 #define __DIVFRAQ_SAMPLING16            UART_DIVFRAQ_SAMPLING16
 550 #define __UART_BRR_SAMPLING16           UART_BRR_SAMPLING16
 551
 552 #define __DIV_SAMPLING8                 UART_DIV_SAMPLING8
 553 #define __DIVMANT_SAMPLING8             UART_DIVMANT_SAMPLING8
 554 #define __DIVFRAQ_SAMPLING8             UART_DIVFRAQ_SAMPLING8
 555 #define __UART_BRR_SAMPLING8            UART_BRR_SAMPLING8
 556
 557 #define UART_WAKEUPMETHODE_IDLELINE     UART_WAKEUPMETHOD_IDLELINE
 558 #define UART_WAKEUPMETHODE_ADDRESSMARK  UART_WAKEUPMETHOD_ADDRESSMARK
 559
 560 /**
 561   * @}
 562   */
 563
 564
 565 /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
 566   * @{
 567   */
 568
 569 #define USART_CLOCK_DISABLED            USART_CLOCK_DISABLE
 570 #define USART_CLOCK_ENABLED             USART_CLOCK_ENABLE
 571
 572 #define USARTNACK_ENABLED               USART_NACK_ENABLE
 573 #define USARTNACK_DISABLED              USART_NACK_DISABLE
 574 /**
 575   * @}
 576   */
 577
 578 /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
 579   * @{
 580   */
 581 #define CFR_BASE                    WWDG_CFR_BASE
 582
 583 /**
 584   * @}
 585   */
 586
 587 /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
 588   * @{
 589   */
 590 #define CAN_FilterFIFO0             CAN_FILTER_FIFO0
 591 #define CAN_FilterFIFO1             CAN_FILTER_FIFO1
 592 #define CAN_IT_RQCP0                CAN_IT_TME
 593 #define CAN_IT_RQCP1                CAN_IT_TME
 594 #define CAN_IT_RQCP2                CAN_IT_TME
 595 #define INAK_TIMEOUT                CAN_TIMEOUT_VALUE
 596 #define SLAK_TIMEOUT                CAN_TIMEOUT_VALUE
 597 #define CAN_TXSTATUS_FAILED         ((uint8_t)0x00)
 598 #define CAN_TXSTATUS_OK             ((uint8_t)0x01)
 599 #define CAN_TXSTATUS_PENDING        ((uint8_t)0x02)
 600
 601 /**
 602   * @}
 603   */
 604
 605 /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
 606   * @{
 607   */
 608
 609 #define VLAN_TAG                ETH_VLAN_TAG
 610 #define MIN_ETH_PAYLOAD         ETH_MIN_ETH_PAYLOAD
 611 #define MAX_ETH_PAYLOAD         ETH_MAX_ETH_PAYLOAD
 612 #define JUMBO_FRAME_PAYLOAD     ETH_JUMBO_FRAME_PAYLOAD
 613 #define MACMIIAR_CR_MASK        ETH_MACMIIAR_CR_MASK
 614 #define MACCR_CLEAR_MASK        ETH_MACCR_CLEAR_MASK
 615 #define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK
 616 #define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK
 617
 618 #define ETH_MMCCR              ((uint32_t)0x00000100)
 619 #define ETH_MMCRIR             ((uint32_t)0x00000104)
 620 #define ETH_MMCTIR             ((uint32_t)0x00000108)
 621 #define ETH_MMCRIMR            ((uint32_t)0x0000010C)
 622 #define ETH_MMCTIMR            ((uint32_t)0x00000110)
 623 #define ETH_MMCTGFSCCR         ((uint32_t)0x0000014C)
 624 #define ETH_MMCTGFMSCCR        ((uint32_t)0x00000150)
 625 #define ETH_MMCTGFCR           ((uint32_t)0x00000168)
 626 #define ETH_MMCRFCECR          ((uint32_t)0x00000194)
 627 #define ETH_MMCRFAECR          ((uint32_t)0x00000198)
 628 #define ETH_MMCRGUFCR          ((uint32_t)0x000001C4)
 629
 630 /**
 631   * @}
 632   */
 633
 634 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
 635   * @{
 636   */
 637
 638 /**
 639   * @}
 640   */
 641
 642 /* Exported functions --------------------------------------------------------*/
 643
 644 /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
 645   * @{
 646   */
 647 #define HAL_CRYP_ComputationCpltCallback     HAL_CRYPEx_ComputationCpltCallback
 648 /**
 649   * @}
 650   */
 651
 652 /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
 653   * @{
 654   */
 655
 656 #define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish
 657 #define HAL_HMAC_SHA1_Finish         HAL_HASH_SHA1_Finish
 658 #define HAL_HMAC_SHA224_Finish       HAL_HASH_SHA224_Finish
 659 #define HAL_HMAC_SHA256_Finish       HAL_HASH_SHA256_Finish
 660
 661 /*HASH Algorithm Selection*/
 662
 663 #define HASH_AlgoSelection_SHA1      HASH_ALGOSELECTION_SHA1
 664 #define HASH_AlgoSelection_SHA224    HASH_ALGOSELECTION_SHA224
 665 #define HASH_AlgoSelection_SHA256    HASH_ALGOSELECTION_SHA256
 666 #define HASH_AlgoSelection_MD5       HASH_ALGOSELECTION_MD5
 667
 668 #define HASH_AlgoMode_HASH         HASH_ALGOMODE_HASH
 669 #define HASH_AlgoMode_HMAC         HASH_ALGOMODE_HMAC
 670
 671 #define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY
 672 #define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY
 673 /**
 674   * @}
 675   */
 676
 677 /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
 678   * @{
 679   */
 680 #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
 681 #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
 682 #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
 683 #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
 684 #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
 685 #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
 686 #define HAL_DBG_LowPowerConfig(Periph, cmd) ((cmd==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
 687 #define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect
 688 #define HAL_Lock_Cmd(cmd) ((cmd==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
 689 #define HAL_VREFINT_Cmd(cmd) ((cmd==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
 690 #define HAL_ADC_EnableBuffer_Cmd(cmd)  ((cmd==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
 691 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) ((cmd==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
 692 /**
 693   * @}
 694   */
 695
 696 /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
 697   * @{
 698   */
 699 #define FLASH_HalfPageProgram      HAL_FLASHEx_HalfPageProgram
 700 #define FLASH_EnableRunPowerDown   HAL_FLASHEx_EnableRunPowerDown
 701 #define FLASH_DisableRunPowerDown  HAL_FLASHEx_DisableRunPowerDown
 702 #define HAL_DATA_EEPROMEx_Unlock   HAL_FLASHEx_DATAEEPROM_Unlock
 703 #define HAL_DATA_EEPROMEx_Lock     HAL_FLASHEx_DATAEEPROM_Lock
 704 #define HAL_DATA_EEPROMEx_Erase    HAL_FLASHEx_DATAEEPROM_Erase
 705 #define HAL_DATA_EEPROMEx_Program  HAL_FLASHEx_DATAEEPROM_Program
 706
 707  /**
 708   * @}
 709   */
 710
 711 /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
 712   * @{
 713   */
 714 #define HAL_I2CEx_AnalogFilter_Config      HAL_I2CEx_ConfigAnalogFilter
 715 #define HAL_I2CEx_DigitalFilter_Config     HAL_I2CEx_ConfigDigitalFilter
 716
 717 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
 718  /**
 719   * @}
 720   */
 721
 722 /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
 723   * @{
 724   */
 725 #define HAL_PWR_PVDConfig                             HAL_PWR_ConfigPVD
 726 #define HAL_PWR_DisableBkUpReg                        HAL_PWREx_DisableBkUpReg
 727 #define HAL_PWR_DisableFlashPowerDown                 HAL_PWREx_DisableFlashPowerDown
 728 #define HAL_PWR_DisableVddio2Monitor                  HAL_PWREx_DisableVddio2Monitor
 729 #define HAL_PWR_EnableBkUpReg                         HAL_PWREx_EnableBkUpReg
 730 #define HAL_PWR_EnableFlashPowerDown                  HAL_PWREx_EnableFlashPowerDown
 731 #define HAL_PWR_EnableVddio2Monitor                   HAL_PWREx_EnableVddio2Monitor
 732 #define HAL_PWR_PVD_PVM_IRQHandler                    HAL_PWREx_PVD_PVM_IRQHandler
 733 #define HAL_PWR_PVDLevelConfig                        HAL_PWR_ConfigPVD
 734 #define HAL_PWR_Vddio2Monitor_IRQHandler              HAL_PWREx_Vddio2Monitor_IRQHandler
 735 #define HAL_PWR_Vddio2MonitorCallback                 HAL_PWREx_Vddio2MonitorCallback
 736 #define HAL_PWREx_ActivateOverDrive                   HAL_PWREx_EnableOverDrive
 737 #define HAL_PWREx_DeactivateOverDrive                 HAL_PWREx_DisableOverDrive
 738 #define HAL_PWREx_DisableSDADCAnalog                  HAL_PWREx_DisableSDADC
 739 #define HAL_PWREx_EnableSDADCAnalog                   HAL_PWREx_EnableSDADC
 740 #define HAL_PWREx_PVMConfig                           HAL_PWREx_ConfigPVM
 741
 742 #define PWR_MODE_NORMAL                               PWR_PVD_MODE_NORMAL
 743 #define PWR_MODE_IT_RISING                            PWR_PVD_MODE_IT_RISING
 744 #define PWR_MODE_IT_FALLING                           PWR_PVD_MODE_IT_FALLING
 745 #define PWR_MODE_IT_RISING_FALLING                    PWR_PVD_MODE_IT_RISING_FALLING
 746 #define PWR_MODE_EVENT_RISING                         PWR_PVD_MODE_EVENT_RISING
 747 #define PWR_MODE_EVENT_FALLING                        PWR_PVD_MODE_EVENT_FALLING
 748 #define PWR_MODE_EVENT_RISING_FALLING                 PWR_PVD_MODE_EVENT_RISING_FALLING
 749
 750 #define CR_OFFSET_BB                                  PWR_CR_OFFSET_BB
 751 #define CSR_OFFSET_BB                                 PWR_CSR_OFFSET_BB
 752
 753 #define DBP_BitNumber                                 DBP_BIT_NUMBER
 754 #define PVDE_BitNumber                                PVDE_BIT_NUMBER
 755 #define PMODE_BitNumber                               PMODE_BIT_NUMBER
 756 #define EWUP_BitNumber                                EWUP_BIT_NUMBER
 757 #define FPDS_BitNumber                                FPDS_BIT_NUMBER
 758 #define ODEN_BitNumber                                ODEN_BIT_NUMBER
 759 #define ODSWEN_BitNumber                              ODSWEN_BIT_NUMBER
 760 #define MRLVDS_BitNumber                              MRLVDS_BIT_NUMBER
 761 #define LPLVDS_BitNumber                              LPLVDS_BIT_NUMBER
 762 #define BRE_BitNumber                                 BRE_BIT_NUMBER
 763
 764 #define PWR_MODE_EVT                                  PWR_PVD_MODE_NORMAL
 765
 766  /**
 767   * @}
 768   */
 769
 770 /** @defgroup HAL_RCC_Aliased_Functions HAL RCC Aliased Functions maintained for legacy purpose
 771   * @{
 772   */
 773 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
 774 #define HAL_RC48_EnableBuffer_Cmd(cmd) ((cmd==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
 775
 776  /**
 777   * @}
 778   */
 779
 780 /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
 781   * @{
 782   */
 783 #define HAL_SMBUS_Slave_Listen_IT          HAL_SMBUS_EnableListen_IT
 784 #define HAL_SMBUS_SlaveAddrCallback        HAL_SMBUS_AddrCallback
 785 #define HAL_SMBUS_SlaveListenCpltCallback  HAL_SMBUS_ListenCpltCallback
 786 /**
 787   * @}
 788   */
 789
 790 /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
 791   * @{
 792   */
 793 #define HAL_SPI_FlushRxFifo                HAL_SPIEx_FlushRxFifo
 794 /**
 795   * @}
 796   */
 797
 798 /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
 799   * @{
 800   */
 801 #define HAL_TIM_DMADelayPulseCplt                       TIM_DMADelayPulseCplt
 802 #define HAL_TIM_DMAError                                TIM_DMAError
 803 #define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt
 804 #define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt
 805 /**
 806   * @}
 807   */
 808
 809 /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
 810   * @{
 811   */
 812 #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
 813 /**
 814   * @}
 815   */
 816
 817
 818    /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
 819   * @{
 820   */
 821
 822 /**
 823   * @}
 824   */
 825
 826 /* Exported macros ------------------------------------------------------------*/
 827
 828 /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
 829   * @{
 830   */
 831 #define AES_IT_CC                      CRYP_IT_CC
 832 #define AES_IT_ERR                     CRYP_IT_ERR
 833 #define AES_FLAG_CCF                   CRYP_FLAG_CCF
 834 /**
 835   * @}
 836   */
 837
 838 /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
 839   * @{
 840   */
 841 #define __HAL_GET_BOOT_MODE                   __HAL_SYSCFG_GET_BOOT_MODE
 842 #define __HAL_REMAPMEMORY_FLASH               __HAL_SYSCFG_REMAPMEMORY_FLASH
 843 #define __HAL_REMAPMEMORY_SYSTEMFLASH         __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
 844 #define __HAL_REMAPMEMORY_SRAM                __HAL_SYSCFG_REMAPMEMORY_SRAM
 845 #define __HAL_REMAPMEMORY_FMC                 __HAL_SYSCFG_REMAPMEMORY_FMC
 846 #define __HAL_REMAPMEMORY_FMC_SDRAM           __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
 847 #define __HAL_FMC_BANK                        __HAL_SYSCFG_FMC_BANK
 848 #define __HAL_GET_FLAG                        __HAL_SYSCFG_GET_FLAG
 849 #define __HAL_CLEAR_FLAG                      __HAL_SYSCFG_CLEAR_FLAG
 850 #define SYSCFG_FLAG_VREF_READY                SYSCFG_FLAG_VREFINT_READY
 851 #define SYSCFG_FLAG_RC48                      RCC_FLAG_HSI48
 852 #define IS_SYSCFG_FASTMODEPLUS_CONFIG         IS_I2C_FASTMODEPLUS
 853 #define UFB_MODE_BitNumber                    UFB_MODE_BIT_NUMBER
 854 #define CMP_PD_BitNumber                      CMP_PD_BIT_NUMBER
 855
 856 /**
 857   * @}
 858   */
 859
 860
 861 /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
 862   * @{
 863   */
 864 #define __ADC_ENABLE                                     __HAL_ADC_ENABLE
 865 #define __ADC_DISABLE                                    __HAL_ADC_DISABLE
 866 #define __HAL_ADC_ENABLING_CONDITIONS                    ADC_ENABLING_CONDITIONS
 867 #define __HAL_ADC_DISABLING_CONDITIONS                   ADC_DISABLING_CONDITIONS
 868 #define __HAL_ADC_IS_ENABLED                             ADC_IS_ENABLE
 869 #define __ADC_IS_ENABLED                                 ADC_IS_ENABLE
 870 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR              ADC_IS_SOFTWARE_START_REGULAR
 871 #define __HAL_ADC_IS_SOFTWARE_START_INJECTED             ADC_IS_SOFTWARE_START_INJECTED
 872 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
 873 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR          ADC_IS_CONVERSION_ONGOING_REGULAR
 874 #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED         ADC_IS_CONVERSION_ONGOING_INJECTED
 875 #define __HAL_ADC_IS_CONVERSION_ONGOING                  ADC_IS_CONVERSION_ONGOING
 876 #define __HAL_ADC_CLEAR_ERRORCODE                        ADC_CLEAR_ERRORCODE
 877
 878 #define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
 879 #define __HAL_ADC_JSQR_RK                                ADC_JSQR_RK
 880 #define __HAL_ADC_CFGR_AWD1CH                            ADC_CFGR_AWD1CH_SHIFT
 881 #define __HAL_ADC_CFGR_AWD23CR                           ADC_CFGR_AWD23CR
 882 #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION            ADC_CFGR_INJECT_AUTO_CONVERSION
 883 #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE              ADC_CFGR_INJECT_CONTEXT_QUEUE
 884 #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS             ADC_CFGR_INJECT_DISCCONTINUOUS
 885 #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS                ADC_CFGR_REG_DISCCONTINUOUS
 886 #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM                 ADC_CFGR_DISCONTINUOUS_NUM
 887 #define __HAL_ADC_CFGR_AUTOWAIT                          ADC_CFGR_AUTOWAIT
 888 #define __HAL_ADC_CFGR_CONTINUOUS                        ADC_CFGR_CONTINUOUS
 889 #define __HAL_ADC_CFGR_OVERRUN                           ADC_CFGR_OVERRUN
 890 #define __HAL_ADC_CFGR_DMACONTREQ                        ADC_CFGR_DMACONTREQ
 891 #define __HAL_ADC_CFGR_EXTSEL                            ADC_CFGR_EXTSEL_SET
 892 #define __HAL_ADC_JSQR_JEXTSEL                           ADC_JSQR_JEXTSEL_SET
 893 #define __HAL_ADC_OFR_CHANNEL                            ADC_OFR_CHANNEL
 894 #define __HAL_ADC_DIFSEL_CHANNEL                         ADC_DIFSEL_CHANNEL
 895 #define __HAL_ADC_CALFACT_DIFF_SET                       ADC_CALFACT_DIFF_SET
 896 #define __HAL_ADC_CALFACT_DIFF_GET                       ADC_CALFACT_DIFF_GET
 897 #define __HAL_ADC_TRX_HIGHTHRESHOLD                      ADC_TRX_HIGHTHRESHOLD
 898
 899 #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION                ADC_OFFSET_SHIFT_RESOLUTION
 900 #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION         ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
 901 #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION        ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
 902 #define __HAL_ADC_COMMON_REGISTER                        ADC_COMMON_REGISTER
 903 #define __HAL_ADC_COMMON_CCR_MULTI                       ADC_COMMON_CCR_MULTI
 904 #define __HAL_ADC_MULTIMODE_IS_ENABLED                   ADC_MULTIMODE_IS_ENABLE
 905 #define __ADC_MULTIMODE_IS_ENABLED                       ADC_MULTIMODE_IS_ENABLE
 906 #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER        ADC_NONMULTIMODE_OR_MULTIMODEMASTER
 907 #define __HAL_ADC_COMMON_ADC_OTHER                       ADC_COMMON_ADC_OTHER
 908 #define __HAL_ADC_MULTI_SLAVE                            ADC_MULTI_SLAVE
 909
 910 #define __HAL_ADC_SQR1_L                                 ADC_SQR1_L_SHIFT
 911 #define __HAL_ADC_JSQR_JL                                ADC_JSQR_JL_SHIFT
 912 #define __HAL_ADC_JSQR_RK_JL                             ADC_JSQR_RK_JL
 913 #define __HAL_ADC_CR1_DISCONTINUOUS_NUM                  ADC_CR1_DISCONTINUOUS_NUM
 914 #define __HAL_ADC_CR1_SCAN                               ADC_CR1_SCAN_SET
 915 #define __HAL_ADC_CONVCYCLES_MAX_RANGE                   ADC_CONVCYCLES_MAX_RANGE
 916 #define __HAL_ADC_CLOCK_PRESCALER_RANGE                  ADC_CLOCK_PRESCALER_RANGE
 917 #define __HAL_ADC_GET_CLOCK_PRESCALER                    ADC_GET_CLOCK_PRESCALER
 918
 919 #define __HAL_ADC_SQR1                                   ADC_SQR1
 920 #define __HAL_ADC_SMPR1                                  ADC_SMPR1
 921 #define __HAL_ADC_SMPR2                                  ADC_SMPR2
 922 #define __HAL_ADC_SQR3_RK                                ADC_SQR3_RK
 923 #define __HAL_ADC_SQR2_RK                                ADC_SQR2_RK
 924 #define __HAL_ADC_SQR1_RK                                ADC_SQR1_RK
 925 #define __HAL_ADC_CR2_CONTINUOUS                         ADC_CR2_CONTINUOUS
 926 #define __HAL_ADC_CR1_DISCONTINUOUS                      ADC_CR1_DISCONTINUOUS
 927 #define __HAL_ADC_CR1_SCANCONV                           ADC_CR1_SCANCONV
 928 #define __HAL_ADC_CR2_EOCSelection                       ADC_CR2_EOCSelection
 929 #define __HAL_ADC_CR2_DMAContReq                         ADC_CR2_DMAContReq
 930 #define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
 931 #define __HAL_ADC_JSQR                                   ADC_JSQR
 932
 933 #define __HAL_ADC_CHSELR_CHANNEL                         ADC_CHSELR_CHANNEL
 934 #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS               ADC_CFGR1_REG_DISCCONTINUOUS
 935 #define __HAL_ADC_CFGR1_AUTOOFF                          ADC_CFGR1_AUTOOFF
 936 #define __HAL_ADC_CFGR1_AUTOWAIT                         ADC_CFGR1_AUTOWAIT
 937 #define __HAL_ADC_CFGR1_CONTINUOUS                       ADC_CFGR1_CONTINUOUS
 938 #define __HAL_ADC_CFGR1_OVERRUN                          ADC_CFGR1_OVERRUN
 939 #define __HAL_ADC_CFGR1_SCANDIR                          ADC_CFGR1_SCANDIR
 940 #define __HAL_ADC_CFGR1_DMACONTREQ                       ADC_CFGR1_DMACONTREQ
 941
 942 /**
 943   * @}
 944   */
 945
 946 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
 947   * @{
 948   */
 949 #define __HAL_DHR12R1_ALIGNEMENT                        DAC_DHR12R1_ALIGNMENT
 950 #define __HAL_DHR12R2_ALIGNEMENT                        DAC_DHR12R2_ALIGNMENT
 951 #define __HAL_DHR12RD_ALIGNEMENT                        DAC_DHR12RD_ALIGNMENT
 952
 953 /**
 954   * @}
 955   */
 956
 957 /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
 958   * @{
 959   */
 960 #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
 961 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
 962 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
 963 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
 964 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
 965 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
 966 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
 967 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
 968 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
 969 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
 970 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
 971 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
 972 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
 973 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
 974 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
 975 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
 976
 977 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
 978 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
 979 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
 980 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
 981 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
 982 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
 983 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
 984 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
 985 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
 986 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
 987 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
 988 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
 989 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
 990 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
 991
 992
 993 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
 994 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
 995 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
 996 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
 997 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
 998 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
 999 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
1000 #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
1001 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
1002 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
1003 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
1004 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
1005 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
1006 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
1007 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
1008 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
1009 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
1010 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
1011 #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
1012 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
1013 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
1014 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
1015 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
1016 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
1017
1018 /**
1019   * @}
1020   */
1021
1022 /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
1023   * @{
1024   */
1025
1026 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
1027                                                           __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
1028 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
1029                                                           __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
1030 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
1031                                                           __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
1032 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
1033                                                           __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
1034 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
1035                                                           __HAL_COMP_COMP2_EXTI_ENABLE_IT())
1036 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
1037                                                           __HAL_COMP_COMP2_EXTI_DISABLE_IT())
1038 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)   (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
1039                                                           __HAL_COMP_COMP2_EXTI_GET_FLAG())
1040 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)   (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
1041                                                           __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
1042 #define __HAL_COMP_GET_EXTI_LINE  COMP_GET_EXTI_LINE
1043
1044 /**
1045   * @}
1046   */
1047
1048 /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
1049   * @{
1050   */
1051
1052 #define IS_WRPAREA          IS_OB_WRPAREA
1053 #define IS_TYPEPROGRAM      IS_FLASH_TYPEPROGRAM
1054 #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
1055 #define IS_TYPEERASE        IS_FLASH_TYPEERASE
1056
1057 /**
1058   * @}
1059   */
1060
1061 /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
1062   * @{
1063   */
1064
1065 #define __HAL_I2C_RESET_CR2             I2C_RESET_CR2
1066 #define __HAL_I2C_GENERATE_START        I2C_GENERATE_START
1067 #define __HAL_I2C_FREQ_RANGE            I2C_FREQ_RANGE
1068 #define __HAL_I2C_RISE_TIME             I2C_RISE_TIME
1069 #define __HAL_I2C_SPEED_STANDARD        I2C_SPEED_STANDARD
1070 #define __HAL_I2C_SPEED_FAST            I2C_SPEED_FAST
1071 #define __HAL_I2C_SPEED                 I2C_SPEED
1072 #define __HAL_I2C_7BIT_ADD_WRITE        I2C_7BIT_ADD_WRITE
1073 #define __HAL_I2C_7BIT_ADD_READ         I2C_7BIT_ADD_READ
1074 #define __HAL_I2C_10BIT_ADDRESS         I2C_10BIT_ADDRESS
1075 #define __HAL_I2C_10BIT_HEADER_WRITE    I2C_10BIT_HEADER_WRITE
1076 #define __HAL_I2C_10BIT_HEADER_READ     I2C_10BIT_HEADER_READ
1077 #define __HAL_I2C_MEM_ADD_MSB           I2C_MEM_ADD_MSB
1078 #define __HAL_I2C_MEM_ADD_LSB           I2C_MEM_ADD_LSB
1079 #define __HAL_I2C_FREQRANGE             I2C_FREQRANGE
1080 /**
1081   * @}
1082   */
1083
1084 /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
1085   * @{
1086   */
1087
1088 #define IS_I2S_INSTANCE                 IS_I2S_ALL_INSTANCE
1089 #define IS_I2S_INSTANCE_EXT             IS_I2S_ALL_INSTANCE_EXT
1090
1091 /**
1092   * @}
1093   */
1094
1095 /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
1096   * @{
1097   */
1098
1099 #define __IRDA_DISABLE                  __HAL_IRDA_DISABLE
1100 #define __IRDA_ENABLE                   __HAL_IRDA_ENABLE
1101
1102 #define __HAL_IRDA_GETCLOCKSOURCE       IRDA_GETCLOCKSOURCE
1103 #define __HAL_IRDA_MASK_COMPUTATION     IRDA_MASK_COMPUTATION
1104 #define __IRDA_GETCLOCKSOURCE           IRDA_GETCLOCKSOURCE
1105 #define __IRDA_MASK_COMPUTATION         IRDA_MASK_COMPUTATION
1106
1107 #define IS_IRDA_ONEBIT_SAMPLE           IS_IRDA_ONE_BIT_SAMPLE
1108
1109
1110 /**
1111   * @}
1112   */
1113
1114
1115 /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
1116   * @{
1117   */
1118 #define __HAL_IWDG_ENABLE_WRITE_ACCESS  IWDG_ENABLE_WRITE_ACCESS
1119 #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
1120 /**
1121   * @}
1122   */
1123
1124
1125 /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
1126   * @{
1127   */
1128
1129 #define __HAL_LPTIM_ENABLE_INTERRUPT    __HAL_LPTIM_ENABLE_IT
1130 #define __HAL_LPTIM_DISABLE_INTERRUPT   __HAL_LPTIM_DISABLE_IT
1131 #define __HAL_LPTIM_GET_ITSTATUS        __HAL_LPTIM_GET_IT_SOURCE
1132
1133 /**
1134   * @}
1135   */
1136
1137 /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
1138   * @{
1139   */
1140 #define __HAL_PVD_EVENT_DISABLE                                  __HAL_PWR_PVD_EXTI_DISABLE_EVENT
1141 #define __HAL_PVD_EVENT_ENABLE                                   __HAL_PWR_PVD_EXTI_ENABLE_EVENT
1142 #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
1143 #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
1144 #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
1145 #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
1146 #define __HAL_PVM_EVENT_DISABLE                                  __HAL_PWR_PVM_EVENT_DISABLE
1147 #define __HAL_PVM_EVENT_ENABLE                                   __HAL_PWR_PVM_EVENT_ENABLE
1148 #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
1149 #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
1150 #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
1151 #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
1152 #define __HAL_PWR_INTERNALWAKEUP_DISABLE                         HAL_PWREx_DisableInternalWakeUpLine
1153 #define __HAL_PWR_INTERNALWAKEUP_ENABLE                          HAL_PWREx_EnableInternalWakeUpLine
1154 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE                    HAL_PWREx_DisablePullUpPullDownConfig
1155 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE                     HAL_PWREx_EnablePullUpPullDownConfig
1156 #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()
1157 #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE                         __HAL_PWR_PVD_EXTI_DISABLE_EVENT
1158 #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE                          __HAL_PWR_PVD_EXTI_ENABLE_EVENT
1159 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE                __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
1160 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE                 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
1161 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE                 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
1162 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE                  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
1163 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
1164 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER               __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
1165 #define __HAL_PWR_PVM_DISABLE()                                  HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4()
1166 #define __HAL_PWR_PVM_ENABLE()                                   HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4()
1167 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE                  HAL_PWREx_DisableSRAM2ContentRetention
1168 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE                   HAL_PWREx_EnableSRAM2ContentRetention
1169 #define __HAL_PWR_VDDIO2_DISABLE                                 HAL_PWREx_DisableVddIO2
1170 #define __HAL_PWR_VDDIO2_ENABLE                                  HAL_PWREx_EnableVddIO2
1171 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER                 __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
1172 #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER           __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
1173 #define __HAL_PWR_VDDUSB_DISABLE                                 HAL_PWREx_DisableVddUSB
1174 #define __HAL_PWR_VDDUSB_ENABLE                                  HAL_PWREx_EnableVddUSB
1175
1176 #if defined (STM32F4)
1177 #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD)         __HAL_PWR_PVD_EXTI_ENABLE_IT()
1178 #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_DISABLE_IT()
1179 #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD)          __HAL_PWR_PVD_EXTI_GET_FLAG()
1180 #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
1181 #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD)     __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
1182 #else
1183 #define __HAL_PVD_EXTI_CLEAR_FLAG                                __HAL_PWR_PVD_EXTI_CLEAR_FLAG
1184 #define __HAL_PVD_EXTI_DISABLE_IT                                __HAL_PWR_PVD_EXTI_DISABLE_IT
1185 #define __HAL_PVD_EXTI_ENABLE_IT                                 __HAL_PWR_PVD_EXTI_ENABLE_IT
1186 #define __HAL_PVD_EXTI_GENERATE_SWIT                             __HAL_PWR_PVD_EXTI_GENERATE_SWIT
1187 #define __HAL_PVD_EXTI_GET_FLAG                                  __HAL_PWR_PVD_EXTI_GET_FLAG
1188 #endif /* STM32F4 */
1189 /**
1190   * @}
1191   */
1192
1193
1194 /** @defgroup HAL_RCC_Aliased_Macros HAL RCC Aliased Macros maintained for legacy purpose
1195   * @{
1196   */
1197 #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
1198 #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
1199 #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
1200 #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
1201 #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
1202 #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
1203 #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
1204 #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
1205 #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
1206 #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
1207 #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
1208 #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
1209 #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
1210 #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
1211 #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
1212 #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
1213 #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
1214 #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
1215 #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
1216 #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
1217 #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
1218 #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
1219 #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
1220 #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
1221 #define __CRYP_CLK_SLEEP_ENABLE      __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
1222 #define __CRYP_CLK_SLEEP_DISABLE  __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
1223 #define __CRYP_CLK_ENABLE  __HAL_RCC_CRYP_CLK_ENABLE
1224 #define __CRYP_CLK_DISABLE  __HAL_RCC_CRYP_CLK_DISABLE
1225 #define __CRYP_FORCE_RESET  __HAL_RCC_CRYP_FORCE_RESET
1226 #define __CRYP_RELEASE_RESET  __HAL_RCC_CRYP_RELEASE_RESET
1227 #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
1228 #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
1229 #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
1230 #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
1231 #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
1232 #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
1233 #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
1234 #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
1235 #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
1236 #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
1237 #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
1238 #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
1239 #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
1240 #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
1241 #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
1242 #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
1243 #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
1244 #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
1245 #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
1246 #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
1247 #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
1248 #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
1249 #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
1250 #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
1251 #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
1252 #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
1253 #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
1254 #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
1255 #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
1256 #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
1257 #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
1258 #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
1259 #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
1260 #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
1261 #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
1262 #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
1263 #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
1264 #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
1265 #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
1266 #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
1267 #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
1268 #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
1269 #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
1270 #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
1271 #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
1272 #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
1273 #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
1274 #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
1275 #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
1276 #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
1277 #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
1278 #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
1279 #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
1280 #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
1281 #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
1282 #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
1283 #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
1284 #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
1285 #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
1286 #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
1287 #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
1288 #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
1289 #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
1290 #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
1291 #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
1292 #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
1293 #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
1294 #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
1295 #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
1296 #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
1297 #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
1298 #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
1299 #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
1300 #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
1301 #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
1302 #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
1303 #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
1304 #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
1305 #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
1306 #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
1307 #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
1308 #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
1309 #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
1310 #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
1311 #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
1312 #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
1313 #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
1314 #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
1315 #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
1316 #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
1317 #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
1318 #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
1319 #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
1320 #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
1321 #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
1322 #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
1323 #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
1324 #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
1325 #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
1326 #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
1327 #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
1328 #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
1329 #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
1330 #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
1331 #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
1332 #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
1333 #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
1334 #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
1335 #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
1336 #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
1337 #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
1338 #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
1339 #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
1340 #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
1341 #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
1342 #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
1343 #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
1344 #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
1345 #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
1346 #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
1347 #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
1348 #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
1349 #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
1350 #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
1351 #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
1352 #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
1353 #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
1354 #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
1355 #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
1356 #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
1357 #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
1358 #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
1359 #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
1360 #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
1361 #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
1362 #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
1363 #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
1364 #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
1365 #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
1366 #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
1367 #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
1368 #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
1369 #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
1370 #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
1371 #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
1372 #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
1373 #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
1374 #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
1375 #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
1376 #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
1377 #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
1378 #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
1379 #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
1380 #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
1381 #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
1382 #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
1383 #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
1384 #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
1385 #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
1386 #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
1387 #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
1388 #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
1389 #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
1390 #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
1391 #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
1392 #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
1393 #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
1394 #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
1395 #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
1396 #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
1397 #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
1398 #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
1399 #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
1400 #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
1401 #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
1402 #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
1403 #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
1404 #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
1405 #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
1406 #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
1407 #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
1408 #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
1409 #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
1410 #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
1411 #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
1412 #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
1413 #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
1414 #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
1415 #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
1416 #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
1417 #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
1418 #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
1419 #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
1420 #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
1421 #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
1422 #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
1423 #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
1424 #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
1425 #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
1426 #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
1427 #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
1428 #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
1429 #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
1430 #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
1431 #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
1432 #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
1433 #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
1434 #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
1435 #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
1436 #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
1437 #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
1438 #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
1439 #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
1440 #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
1441 #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
1442 #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
1443 #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
1444 #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
1445 #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
1446 #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
1447 #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
1448 #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
1449 #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
1450 #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
1451 #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
1452 #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
1453 #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
1454 #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
1455 #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
1456 #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
1457 #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
1458 #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
1459 #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
1460 #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
1461 #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
1462 #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
1463 #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
1464 #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
1465 #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
1466 #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
1467 #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
1468 #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
1469 #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
1470 #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
1471 #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
1472 #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
1473 #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
1474 #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
1475 #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
1476 #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
1477 #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
1478 #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
1479 #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
1480 #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
1481 #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
1482 #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
1483 #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
1484 #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
1485 #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
1486 #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
1487 #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
1488 #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
1489 #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
1490 #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
1491 #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
1492 #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
1493 #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
1494 #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
1495 #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
1496 #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
1497 #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
1498 #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
1499 #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
1500 #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
1501 #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
1502 #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
1503 #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
1504 #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
1505 #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
1506 #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
1507 #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
1508 #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
1509 #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
1510 #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
1511 #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
1512 #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
1513 #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
1514 #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
1515 #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
1516 #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
1517 #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
1518 #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
1519 #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
1520 #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
1521 #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
1522 #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
1523 #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
1524 #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
1525 #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
1526 #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
1527 #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
1528 #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
1529 #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
1530 #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
1531 #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
1532 #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
1533 #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
1534 #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
1535 #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
1536 #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
1537 #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
1538 #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
1539 #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
1540 #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
1541 #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
1542 #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
1543 #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
1544 #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
1545 #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
1546 #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
1547 #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
1548 #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
1549 #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
1550 #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
1551 #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
1552 #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
1553 #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
1554 #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
1555 #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
1556 #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
1557 #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
1558 #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
1559 #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
1560 #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
1561 #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
1562 #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
1563 #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
1564 #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
1565 #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
1566 #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
1567 #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
1568 #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
1569 #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
1570 #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
1571 #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
1572 #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
1573 #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
1574 #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
1575 #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
1576 #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
1577 #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
1578 #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
1579 #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
1580 #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
1581 #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
1582 #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
1583 #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
1584 #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
1585 #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
1586 #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
1587 #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
1588 #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
1589 #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
1590 #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
1591 #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
1592 #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
1593 #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
1594 #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
1595 #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
1596 #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
1597 #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
1598 #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
1599 #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
1600 #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
1601 #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
1602 #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
1603 #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
1604 #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
1605 #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
1606 #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
1607 #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
1608 #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
1609 #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
1610 #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
1611 #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
1612 #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
1613 #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
1614 #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
1615 #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
1616 #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
1617 #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
1618 #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
1619 #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
1620 #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
1621 #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
1622 #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
1623 #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
1624 #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
1625 #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
1626 #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
1627 #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
1628 #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
1629 #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
1630 #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
1631 #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
1632 #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
1633 #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
1634 #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
1635 #define __TIM21_CLK_ENABLE   __HAL_RCC_TIM21_CLK_ENABLE
1636 #define __TIM21_CLK_DISABLE   __HAL_RCC_TIM21_CLK_DISABLE
1637 #define __TIM21_FORCE_RESET   __HAL_RCC_TIM21_FORCE_RESET
1638 #define __TIM21_RELEASE_RESET  __HAL_RCC_TIM21_RELEASE_RESET
1639 #define __TIM21_CLK_SLEEP_ENABLE   __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
1640 #define __TIM21_CLK_SLEEP_DISABLE   __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
1641 #define __TIM22_CLK_ENABLE   __HAL_RCC_TIM22_CLK_ENABLE
1642 #define __TIM22_CLK_DISABLE   __HAL_RCC_TIM22_CLK_DISABLE
1643 #define __TIM22_FORCE_RESET   __HAL_RCC_TIM22_FORCE_RESET
1644 #define __TIM22_RELEASE_RESET  __HAL_RCC_TIM22_RELEASE_RESET
1645 #define __TIM22_CLK_SLEEP_ENABLE   __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
1646 #define __TIM22_CLK_SLEEP_DISABLE   __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
1647 #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
1648 #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
1649 #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
1650 #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
1651 #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
1652 #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
1653 #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
1654 #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
1655
1656 #define __USB_OTG_FS_FORCE_RESET  __HAL_RCC_USB_OTG_FS_FORCE_RESET
1657 #define __USB_OTG_FS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
1658 #define __USB_OTG_FS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
1659 #define __USB_OTG_FS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
1660 #define __USB_OTG_HS_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_DISABLE
1661 #define __USB_OTG_HS_CLK_ENABLE          __HAL_RCC_USB_OTG_HS_CLK_ENABLE
1662 #define __USB_OTG_HS_ULPI_CLK_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
1663 #define __USB_OTG_HS_ULPI_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
1664 #define __FLITF_CLK_SLEEP_ENABLE  __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
1665 #define __FLITF_CLK_SLEEP_DISABLE  __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
1666 #define __ADC1_CLK_SLEEP_ENABLE          __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
1667 #define __TIM9_CLK_SLEEP_ENABLE          __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
1668 #define __TIM9_CLK_SLEEP_DISABLE  __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
1669 #define __TIM10_CLK_SLEEP_ENABLE  __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
1670 #define __TIM10_CLK_SLEEP_DISABLE  __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
1671 #define __TIM11_CLK_SLEEP_ENABLE  __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
1672 #define __TIM11_CLK_SLEEP_DISABLE  __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
1673 #define __ETHMACPTP_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
1674 #define __ETHMACPTP_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
1675 #define __ETHMACPTP_CLK_ENABLE          __HAL_RCC_ETHMACPTP_CLK_ENABLE
1676 #define __ETHMACPTP_CLK_DISABLE          __HAL_RCC_ETHMACPTP_CLK_DISABLE
1677 #define __HASH_CLK_ENABLE          __HAL_RCC_HASH_CLK_ENABLE
1678 #define __HASH_FORCE_RESET          __HAL_RCC_HASH_FORCE_RESET
1679 #define __HASH_RELEASE_RESET          __HAL_RCC_HASH_RELEASE_RESET
1680 #define __HASH_CLK_SLEEP_ENABLE          __HAL_RCC_HASH_CLK_SLEEP_ENABLE
1681 #define __HASH_CLK_SLEEP_DISABLE  __HAL_RCC_HASH_CLK_SLEEP_DISABLE
1682 #define __HASH_CLK_DISABLE            __HAL_RCC_HASH_CLK_DISABLE
1683 #define __SPI5_CLK_ENABLE          __HAL_RCC_SPI5_CLK_ENABLE
1684 #define __SPI5_CLK_DISABLE              __HAL_RCC_SPI5_CLK_DISABLE
1685 #define __SPI5_FORCE_RESET          __HAL_RCC_SPI5_FORCE_RESET
1686 #define __SPI5_RELEASE_RESET          __HAL_RCC_SPI5_RELEASE_RESET
1687 #define __SPI5_CLK_SLEEP_ENABLE          __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
1688 #define __SPI5_CLK_SLEEP_DISABLE  __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
1689 #define __SPI6_CLK_ENABLE          __HAL_RCC_SPI6_CLK_ENABLE
1690 #define __SPI6_CLK_DISABLE          __HAL_RCC_SPI6_CLK_DISABLE
1691 #define __SPI6_FORCE_RESET          __HAL_RCC_SPI6_FORCE_RESET
1692 #define __SPI6_RELEASE_RESET         __HAL_RCC_SPI6_RELEASE_RESET
1693 #define __SPI6_CLK_SLEEP_ENABLE          __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
1694 #define __SPI6_CLK_SLEEP_DISABLE  __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
1695 #define __LTDC_CLK_ENABLE          __HAL_RCC_LTDC_CLK_ENABLE
1696 #define __LTDC_CLK_DISABLE          __HAL_RCC_LTDC_CLK_DISABLE
1697 #define __LTDC_FORCE_RESET          __HAL_RCC_LTDC_FORCE_RESET
1698 #define __LTDC_RELEASE_RESET          __HAL_RCC_LTDC_RELEASE_RESET
1699 #define __LTDC_CLK_SLEEP_ENABLE          __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
1700 #define __ETHMAC_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
1701 #define __ETHMAC_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
1702 #define __ETHMACTX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
1703 #define __ETHMACTX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
1704 #define __ETHMACRX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
1705 #define __ETHMACRX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
1706 #define __TIM12_CLK_SLEEP_ENABLE  __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
1707 #define __TIM12_CLK_SLEEP_DISABLE  __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
1708 #define __TIM13_CLK_SLEEP_ENABLE  __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
1709 #define __TIM13_CLK_SLEEP_DISABLE  __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
1710 #define __TIM14_CLK_SLEEP_ENABLE  __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
1711 #define __TIM14_CLK_SLEEP_DISABLE  __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
1712 #define __BKPSRAM_CLK_ENABLE          __HAL_RCC_BKPSRAM_CLK_ENABLE
1713 #define __BKPSRAM_CLK_DISABLE          __HAL_RCC_BKPSRAM_CLK_DISABLE
1714 #define __BKPSRAM_CLK_SLEEP_ENABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
1715 #define __BKPSRAM_CLK_SLEEP_DISABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
1716 #define __CCMDATARAMEN_CLK_ENABLE  __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
1717 #define __CCMDATARAMEN_CLK_DISABLE  __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
1718 #define __USART6_CLK_ENABLE          __HAL_RCC_USART6_CLK_ENABLE
1719 #define __USART6_CLK_DISABLE          __HAL_RCC_USART6_CLK_DISABLE
1720 #define __USART6_FORCE_RESET        __HAL_RCC_USART6_FORCE_RESET
1721 #define __USART6_RELEASE_RESET        __HAL_RCC_USART6_RELEASE_RESET
1722 #define __USART6_CLK_SLEEP_ENABLE  __HAL_RCC_USART6_CLK_SLEEP_ENABLE
1723 #define __USART6_CLK_SLEEP_DISABLE  __HAL_RCC_USART6_CLK_SLEEP_DISABLE
1724 #define __SPI4_CLK_ENABLE          __HAL_RCC_SPI4_CLK_ENABLE
1725 #define __SPI4_CLK_DISABLE          __HAL_RCC_SPI4_CLK_DISABLE
1726 #define __SPI4_FORCE_RESET          __HAL_RCC_SPI4_FORCE_RESET
1727 #define __SPI4_RELEASE_RESET        __HAL_RCC_SPI4_RELEASE_RESET
1728 #define __SPI4_CLK_SLEEP_ENABLE   __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
1729 #define __SPI4_CLK_SLEEP_DISABLE  __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
1730 #define __GPIOI_CLK_ENABLE          __HAL_RCC_GPIOI_CLK_ENABLE
1731 #define __GPIOI_CLK_DISABLE          __HAL_RCC_GPIOI_CLK_DISABLE
1732 #define __GPIOI_FORCE_RESET          __HAL_RCC_GPIOI_FORCE_RESET
1733 #define __GPIOI_RELEASE_RESET          __HAL_RCC_GPIOI_RELEASE_RESET
1734 #define __GPIOI_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
1735 #define __GPIOI_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
1736 #define __GPIOJ_CLK_ENABLE          __HAL_RCC_GPIOJ_CLK_ENABLE
1737 #define __GPIOJ_CLK_DISABLE          __HAL_RCC_GPIOJ_CLK_DISABLE
1738 #define __GPIOJ_FORCE_RESET         __HAL_RCC_GPIOJ_FORCE_RESET
1739 #define __GPIOJ_RELEASE_RESET          __HAL_RCC_GPIOJ_RELEASE_RESET
1740 #define __GPIOJ_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
1741 #define __GPIOJ_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
1742 #define __GPIOK_CLK_ENABLE          __HAL_RCC_GPIOK_CLK_ENABLE
1743 #define __GPIOK_CLK_DISABLE          __HAL_RCC_GPIOK_CLK_DISABLE
1744 #define __GPIOK_RELEASE_RESET          __HAL_RCC_GPIOK_RELEASE_RESET
1745 #define __GPIOK_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
1746 #define __GPIOK_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
1747 #define __ETH_CLK_ENABLE          __HAL_RCC_ETH_CLK_ENABLE
1748 #define __ETH_CLK_DISABLE          __HAL_RCC_ETH_CLK_DISABLE
1749 #define __DCMI_CLK_ENABLE          __HAL_RCC_DCMI_CLK_ENABLE
1750 #define __DCMI_CLK_DISABLE          __HAL_RCC_DCMI_CLK_DISABLE
1751 #define __DCMI_FORCE_RESET          __HAL_RCC_DCMI_FORCE_RESET
1752 #define __DCMI_RELEASE_RESET          __HAL_RCC_DCMI_RELEASE_RESET
1753 #define __DCMI_CLK_SLEEP_ENABLE   __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
1754 #define __DCMI_CLK_SLEEP_DISABLE  __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
1755 #define __UART7_CLK_ENABLE          __HAL_RCC_UART7_CLK_ENABLE
1756 #define __UART7_CLK_DISABLE          __HAL_RCC_UART7_CLK_DISABLE
1757 #define __UART7_RELEASE_RESET       __HAL_RCC_UART7_RELEASE_RESET
1758 #define __UART7_FORCE_RESET       __HAL_RCC_UART7_FORCE_RESET
1759 #define __UART7_CLK_SLEEP_ENABLE  __HAL_RCC_UART7_CLK_SLEEP_ENABLE
1760 #define __UART7_CLK_SLEEP_DISABLE  __HAL_RCC_UART7_CLK_SLEEP_DISABLE
1761 #define __UART8_CLK_ENABLE          __HAL_RCC_UART8_CLK_ENABLE
1762 #define __UART8_CLK_DISABLE          __HAL_RCC_UART8_CLK_DISABLE
1763 #define __UART8_FORCE_RESET          __HAL_RCC_UART8_FORCE_RESET
1764 #define __UART8_RELEASE_RESET          __HAL_RCC_UART8_RELEASE_RESET
1765 #define __UART8_CLK_SLEEP_ENABLE  __HAL_RCC_UART8_CLK_SLEEP_ENABLE
1766 #define __UART8_CLK_SLEEP_DISABLE  __HAL_RCC_UART8_CLK_SLEEP_DISABLE
1767 #define __OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE
1768 #define __OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE
1769 #define __OTGHS_FORCE_RESET          __HAL_RCC_OTGHS_FORCE_RESET
1770 #define __OTGHS_RELEASE_RESET          __HAL_RCC_OTGHS_RELEASE_RESET
1771 #define __OTGHSULPI_CLK_SLEEP_ENABLE  __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE
1772 #define __OTGHSULPI_CLK_SLEEP_DISABLE  __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE
1773 #define __CRYP_FORCE_RESET          __HAL_RCC_CRYP_FORCE_RESET
1774 #define __SRAM3_CLK_SLEEP_ENABLE  __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
1775 #define __CAN2_CLK_SLEEP_ENABLE          __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
1776 #define __CAN2_CLK_SLEEP_DISABLE  __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
1777 #define __DAC_CLK_SLEEP_ENABLE          __HAL_RCC_DAC_CLK_SLEEP_ENABLE
1778 #define __DAC_CLK_SLEEP_DISABLE   __HAL_RCC_DAC_CLK_SLEEP_DISABLE
1779 #define __ADC2_CLK_SLEEP_ENABLE   __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
1780 #define __ADC2_CLK_SLEEP_DISABLE  __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
1781 #define __ADC3_CLK_SLEEP_ENABLE          __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
1782 #define __ADC3_CLK_SLEEP_DISABLE  __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
1783 #define __FSMC_FORCE_RESET          __HAL_RCC_FSMC_FORCE_RESET
1784 #define __FSMC_RELEASE_RESET          __HAL_RCC_FSMC_RELEASE_RESET
1785 #define __FSMC_CLK_SLEEP_ENABLE          __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
1786 #define __FSMC_CLK_SLEEP_DISABLE  __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
1787 #define __SDIO_FORCE_RESET          __HAL_RCC_SDIO_FORCE_RESET
1788 #define __SDIO_RELEASE_RESET          __HAL_RCC_SDIO_RELEASE_RESET
1789 #define __SDIO_CLK_SLEEP_DISABLE  __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
1790 #define __SDIO_CLK_SLEEP_ENABLE          __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
1791 #define __DMA2D_CLK_ENABLE          __HAL_RCC_DMA2D_CLK_ENABLE
1792 #define __DMA2D_CLK_DISABLE          __HAL_RCC_DMA2D_CLK_DISABLE
1793 #define __DMA2D_FORCE_RESET          __HAL_RCC_DMA2D_FORCE_RESET
1794 #define __DMA2D_RELEASE_RESET          __HAL_RCC_DMA2D_RELEASE_RESET
1795 #define __DMA2D_CLK_SLEEP_ENABLE  __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
1796 #define __DMA2D_CLK_SLEEP_DISABLE  __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
1797
1798 /* alias define maintained for legacy */
1799 #define __HAL_RCC_OTGFS_FORCE_RESET    __HAL_RCC_USB_OTG_FS_FORCE_RESET
1800 #define __HAL_RCC_OTGFS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
1801
1802 #define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG
1803 #define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG
1804
1805 #define __RCC_PLLSRC           RCC_GET_PLL_OSCSOURCE
1806
1807 #define HSION_BitNumber        RCC_HSION_BIT_NUMBER
1808 #define CSSON_BitNumber        RCC_CSSON_BIT_NUMBER
1809 #define PLLON_BitNumber        RCC_PLLON_BIT_NUMBER
1810 #define PLLI2SON_BitNumber     RCC_PLLI2SON_BIT_NUMBER
1811 #define I2SSRC_BitNumber       RCC_I2SSRC_BIT_NUMBER
1812 #define RTCEN_BitNumber        RCC_RTCEN_BIT_NUMBER
1813 #define BDRST_BitNumber        RCC_BDRST_BIT_NUMBER
1814 #define LSION_BitNumber        RCC_LSION_BIT_NUMBER
1815 #define PLLSAION_BitNumber     RCC_PLLSAION_BIT_NUMBER
1816 #define TIMPRE_BitNumber       RCC_TIMPRE_BIT_NUMBER
1817
1818 #define CR_BYTE2_ADDRESS       RCC_CR_BYTE2_ADDRESS
1819 #define CIR_BYTE1_ADDRESS      RCC_CIR_BYTE1_ADDRESS
1820 #define CIR_BYTE2_ADDRESS      RCC_CIR_BYTE2_ADDRESS
1821 #define BDCR_BYTE0_ADDRESS     RCC_BDCR_BYTE0_ADDRESS
1822 #define DBP_TIMEOUT_VALUE      RCC_DBP_TIMEOUT_VALUE
1823 #define LSE_TIMEOUT_VALUE      RCC_LSE_TIMEOUT_VALUE
1824
1825 #define CR_HSION_BB            RCC_CR_HSION_BB
1826 #define CR_CSSON_BB            RCC_CR_CSSON_BB
1827 #define CR_PLLON_BB            RCC_CR_PLLON_BB
1828 #define CR_PLLI2SON_BB         RCC_CR_PLLI2SON_BB
1829 #define CFGR_I2SSRC_BB         RCC_CFGR_I2SSRC_BB
1830 #define BDCR_RTCEN_BB          RCC_BDCR_RTCEN_BB
1831 #define BDCR_BDRST_BB          RCC_BDCR_BDRST_BB
1832 #define CSR_LSION_BB           RCC_CSR_LSION_BB
1833 #define CR_PLLSAION_BB         RCC_CR_PLLSAION_BB
1834 #define DCKCFGR_TIMPRE_BB      RCC_DCKCFGR_TIMPRE_BB
1835
1836 /**
1837   * @}
1838   */
1839
1840 /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
1841   * @{
1842   */
1843 #define  HAL_RNG_ReadyCallback(__HANDLE__)  HAL_RNG_ReadyDataCallback(__HANDLE__, uint32_t random32bit)
1844
1845 /**
1846   * @}
1847   */
1848
1849 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
1850   * @{
1851   */
1852
1853 #define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG
1854 #define __HAL_RTC_DISABLE_IT                      __HAL_RTC_EXTI_DISABLE_IT
1855 #define __HAL_RTC_ENABLE_IT                       __HAL_RTC_EXTI_ENABLE_IT
1856 #if defined (RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
1857 #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__)  ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
1858 ((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
1859                                                       __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
1860 #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__)   ((__EXTI_LINE__  == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
1861                                                   ((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
1862                                                       __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
1863 #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__)  ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
1864                                                   ((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
1865                                                       __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
1866 #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__)    ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
1867                                                   ((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
1868                                                       __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
1869 #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__)   ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
1870                                                       ((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() :  \
1871                                                           __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
1872
1873 #else
1874 #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
1875
1876 #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_ENABLE_IT()
1877
1878 #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_DISABLE_IT()
1879
1880 #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT)    __HAL_RTC_ALARM_EXTI_GET_FLAG()
1881
1882 #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
1883
1884 #endif
1885
1886 #define IS_ALARM                                  IS_RTC_ALARM
1887 #define IS_ALARM_MASK                             IS_RTC_ALARM_MASK
1888 #define IS_TAMPER                                 IS_RTC_TAMPER
1889 #define IS_TAMPER_ERASE_MODE                      IS_RTC_TAMPER_ERASE_MODE
1890 #define IS_TAMPER_FILTER                          IS_RTC_TAMPER_FILTER
1891 #define IS_TAMPER_INTERRUPT                       IS_RTC_TAMPER_INTERRUPT
1892 #define IS_TAMPER_MASKFLAG_STATE                  IS_RTC_TAMPER_MASKFLAG_STATE
1893 #define IS_TAMPER_PRECHARGE_DURATION              IS_RTC_TAMPER_PRECHARGE_DURATION
1894 #define IS_TAMPER_PULLUP_STATE                    IS_RTC_TAMPER_PULLUP_STATE
1895 #define IS_TAMPER_SAMPLING_FREQ                   IS_RTC_TAMPER_SAMPLING_FREQ
1896 #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION     IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
1897 #define IS_TAMPER_TRIGGER                         IS_RTC_TAMPER_TRIGGER
1898 #define IS_WAKEUP_CLOCK                           IS_RTC_WAKEUP_CLOCK
1899 #define IS_WAKEUP_COUNTER                         IS_RTC_WAKEUP_COUNTER
1900
1901 #define __RTC_WRITEPROTECTION_ENABLE  __HAL_RTC_WRITEPROTECTION_ENABLE
1902 #define __RTC_WRITEPROTECTION_DISABLE  __HAL_RTC_WRITEPROTECTION_DISABLE
1903
1904 /**
1905   * @}
1906   */
1907
1908 /** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
1909   * @{
1910   */
1911
1912 #define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE
1913 #define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS
1914
1915 /**
1916   * @}
1917   */
1918
1919 /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
1920   * @{
1921   */
1922
1923 #define __SMARTCARD_ENABLE_IT           __HAL_SMARTCARD_ENABLE_IT
1924 #define __SMARTCARD_DISABLE_IT          __HAL_SMARTCARD_DISABLE_IT
1925 #define __SMARTCARD_ENABLE              __HAL_SMARTCARD_ENABLE
1926 #define __SMARTCARD_DISABLE             __HAL_SMARTCARD_DISABLE
1927 #define __SMARTCARD_DMA_REQUEST_ENABLE  __HAL_SMARTCARD_DMA_REQUEST_ENABLE
1928 #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
1929
1930 #define __HAL_SMARTCARD_GETCLOCKSOURCE  SMARTCARD_GETCLOCKSOURCE
1931 #define __SMARTCARD_GETCLOCKSOURCE      SMARTCARD_GETCLOCKSOURCE
1932
1933 #define IS_SMARTCARD_ONEBIT_SAMPLING    IS_SMARTCARD_ONE_BIT_SAMPLE
1934
1935 /**
1936   * @}
1937   */
1938
1939 /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
1940   * @{
1941   */
1942 #define __HAL_SMBUS_RESET_CR1           SMBUS_RESET_CR1
1943 #define __HAL_SMBUS_RESET_CR2           SMBUS_RESET_CR2
1944 #define __HAL_SMBUS_GENERATE_START      SMBUS_GENERATE_START
1945 #define __HAL_SMBUS_GET_ADDR_MATCH      SMBUS_GET_ADDR_MATCH
1946 #define __HAL_SMBUS_GET_DIR             SMBUS_GET_DIR
1947 #define __HAL_SMBUS_GET_STOP_MODE       SMBUS_GET_STOP_MODE
1948 #define __HAL_SMBUS_GET_PEC_MODE        SMBUS_GET_PEC_MODE
1949 #define __HAL_SMBUS_GET_ALERT_ENABLED   SMBUS_GET_ALERT_ENABLED
1950 /**
1951   * @}
1952   */
1953
1954 /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
1955   * @{
1956   */
1957
1958 #define __HAL_SPI_1LINE_TX              SPI_1LINE_TX
1959 #define __HAL_SPI_1LINE_RX              SPI_1LINE_RX
1960 #define __HAL_SPI_RESET_CRC             SPI_RESET_CRC
1961
1962 /**
1963   * @}
1964   */
1965
1966 /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
1967   * @{
1968   */
1969
1970 #define __HAL_UART_GETCLOCKSOURCE       UART_GETCLOCKSOURCE
1971 #define __HAL_UART_MASK_COMPUTATION     UART_MASK_COMPUTATION
1972 #define __UART_GETCLOCKSOURCE           UART_GETCLOCKSOURCE
1973 #define __UART_MASK_COMPUTATION         UART_MASK_COMPUTATION
1974
1975 #define IS_UART_WAKEUPMETHODE           IS_UART_WAKEUPMETHOD
1976
1977 #define IS_UART_ONEBIT_SAMPLE           IS_UART_ONE_BIT_SAMPLE
1978 #define IS_UART_ONEBIT_SAMPLING         IS_UART_ONE_BIT_SAMPLE
1979
1980 /**
1981   * @}
1982   */
1983
1984
1985 /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
1986   * @{
1987   */
1988
1989 #define __USART_ENABLE_IT               __HAL_USART_ENABLE_IT
1990 #define __USART_DISABLE_IT              __HAL_USART_DISABLE_IT
1991 #define __USART_ENABLE                  __HAL_USART_ENABLE
1992 #define __USART_DISABLE                 __HAL_USART_DISABLE
1993
1994 #define __HAL_USART_GETCLOCKSOURCE      USART_GETCLOCKSOURCE
1995 #define __USART_GETCLOCKSOURCE          USART_GETCLOCKSOURCE
1996
1997 /**
1998   * @}
1999   */
2000
2001 /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
2002   * @{
2003   */
2004 #define USB_EXTI_LINE_WAKEUP                               USB_WAKEUP_EXTI_LINE
2005
2006 #define USB_FS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
2007 #define USB_FS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
2008 #define USB_FS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
2009 #define USB_FS_EXTI_LINE_WAKEUP                            USB_OTG_FS_WAKEUP_EXTI_LINE
2010
2011 #define USB_HS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
2012 #define USB_HS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
2013 #define USB_HS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
2014 #define USB_HS_EXTI_LINE_WAKEUP                            USB_OTG_HS_WAKEUP_EXTI_LINE
2015
2016 #define __HAL_USB_EXTI_ENABLE_IT                           __HAL_USB_WAKEUP_EXTI_ENABLE_IT
2017 #define __HAL_USB_EXTI_DISABLE_IT                          __HAL_USB_WAKEUP_EXTI_DISABLE_IT
2018 #define __HAL_USB_EXTI_GET_FLAG                            __HAL_USB_WAKEUP_EXTI_GET_FLAG
2019 #define __HAL_USB_EXTI_CLEAR_FLAG                          __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
2020 #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER             __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
2021 #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER            __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
2022 #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER           __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
2023
2024 #define __HAL_USB_FS_EXTI_ENABLE_IT                        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
2025 #define __HAL_USB_FS_EXTI_DISABLE_IT                       __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
2026 #define __HAL_USB_FS_EXTI_GET_FLAG                         __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
2027 #define __HAL_USB_FS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
2028 #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
2029 #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
2030 #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
2031 #define __HAL_USB_FS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
2032
2033 #define __HAL_USB_HS_EXTI_ENABLE_IT                        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
2034 #define __HAL_USB_HS_EXTI_DISABLE_IT                       __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
2035 #define __HAL_USB_HS_EXTI_GET_FLAG                         __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
2036 #define __HAL_USB_HS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
2037 #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
2038 #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
2039 #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
2040 #define __HAL_USB_HS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
2041
2042 #define HAL_PCD_ActiveRemoteWakeup                         HAL_PCD_ActivateRemoteWakeup
2043 #define HAL_PCD_DeActiveRemoteWakeup                       HAL_PCD_DeActivateRemoteWakeup
2044
2045 #define HAL_PCD_SetTxFiFo                                  HAL_PCDEx_SetTxFiFo
2046 #define HAL_PCD_SetRxFiFo                                  HAL_PCDEx_SetRxFiFo
2047 /**
2048   * @}
2049   */
2050
2051 /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
2052   * @{
2053   */
2054 #define __HAL_TIM_SetICPrescalerValue   TIM_SET_ICPRESCALERVALUE
2055 #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
2056
2057 #define TIM_GET_ITSTATUS                __HAL_TIM_GET_IT_SOURCE
2058 #define TIM_GET_CLEAR_IT                __HAL_TIM_CLEAR_IT
2059
2060 #define __HAL_TIM_DIRECTION_STATUS      __HAL_TIM_IS_TIM_COUNTING_DOWN
2061 #define __HAL_TIM_PRESCALER             __HAL_TIM_SET_PRESCALER
2062 #define __HAL_TIM_SetCounter            __HAL_TIM_SET_COUNTER
2063 #define __HAL_TIM_GetCounter            __HAL_TIM_GET_COUNTER
2064 #define __HAL_TIM_SetAutoreload         __HAL_TIM_SET_AUTORELOAD
2065 #define __HAL_TIM_GetAutoreload         __HAL_TIM_GET_AUTORELOAD
2066 #define __HAL_TIM_SetClockDivision      __HAL_TIM_SET_CLOCKDIVISION
2067 #define __HAL_TIM_GetClockDivision      __HAL_TIM_GET_CLOCKDIVISION
2068 #define __HAL_TIM_SetICPrescaler        __HAL_TIM_SET_ICPRESCALER
2069 #define __HAL_TIM_GetICPrescaler        __HAL_TIM_GET_ICPRESCALER
2070 #define __HAL_TIM_SetCompare            __HAL_TIM_SET_COMPARE
2071 #define __HAL_TIM_GetCompare            __HAL_TIM_GET_COMPARE
2072
2073 #define TIM_TS_ITR0                        ((uint32_t)0x0000)
2074 #define TIM_TS_ITR1                        ((uint32_t)0x0010)
2075 #define TIM_TS_ITR2                        ((uint32_t)0x0020)
2076 #define TIM_TS_ITR3                        ((uint32_t)0x0030)
2077 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
2078                                                       ((SELECTION) == TIM_TS_ITR1) || \
2079                                                       ((SELECTION) == TIM_TS_ITR2) || \
2080                                                       ((SELECTION) == TIM_TS_ITR3))
2081
2082 #define TIM_CHANNEL_1                      ((uint32_t)0x0000)
2083 #define TIM_CHANNEL_2                      ((uint32_t)0x0004)
2084 #define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
2085                                        ((CHANNEL) == TIM_CHANNEL_2))
2086
2087 #define TIM_OUTPUTNSTATE_DISABLE            ((uint32_t)0x0000)
2088 #define TIM_OUTPUTNSTATE_ENABLE             (TIM_CCER_CC1NE)
2089
2090 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
2091                                      ((STATE) == TIM_OUTPUTNSTATE_ENABLE))
2092
2093 #define TIM_OUTPUTSTATE_DISABLE            ((uint32_t)0x0000)
2094 #define TIM_OUTPUTSTATE_ENABLE             (TIM_CCER_CC1E)
2095
2096 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
2097                                     ((STATE) == TIM_OUTPUTSTATE_ENABLE))
2098 /**
2099   * @}
2100   */
2101
2102 /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
2103   * @{
2104   */
2105
2106 #define __HAL_ETH_EXTI_ENABLE_IT                   __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
2107 #define __HAL_ETH_EXTI_DISABLE_IT                  __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
2108 #define __HAL_ETH_EXTI_GET_FLAG                    __HAL_ETH_WAKEUP_EXTI_GET_FLAG
2109 #define __HAL_ETH_EXTI_CLEAR_FLAG                  __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
2110 #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER     __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
2111 #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER    __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
2112 #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER   __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
2113
2114 #define ETH_PROMISCIOUSMODE_ENABLE   ETH_PROMISCUOUS_MODE_ENABLE
2115 #define ETH_PROMISCIOUSMODE_DISABLE  ETH_PROMISCUOUS_MODE_DISABLE
2116 #define IS_ETH_PROMISCIOUS_MODE      IS_ETH_PROMISCUOUS_MODE
2117 /**
2118   * @}
2119   */
2120
2121 /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
2122   * @{
2123   */
2124 #define __HAL_LTDC_LAYER LTDC_LAYER
2125 /**
2126   * @}
2127   */
2128
2129 /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
2130   * @{
2131   */
2132 #define SAI_OUTPUTDRIVE_DISABLED          SAI_OUTPUTDRIVE_DISABLE
2133 #define SAI_OUTPUTDRIVE_ENABLED           SAI_OUTPUTDRIVE_ENABLE
2134 #define SAI_MASTERDIVIDER_ENABLED         SAI_MASTERDIVIDER_ENABLE
2135 #define SAI_MASTERDIVIDER_DISABLED        SAI_MASTERDIVIDER_DISABLE
2136 #define SAI_STREOMODE                     SAI_STEREOMODE
2137 #define SAI_FIFOStatus_Empty              SAI_FIFOSTATUS_EMPTY
2138 #define SAI_FIFOStatus_Less1QuarterFull   SAI_FIFOSTATUS_LESS1QUARTERFULL
2139 #define SAI_FIFOStatus_1QuarterFull       SAI_FIFOSTATUS_1QUARTERFULL
2140 #define SAI_FIFOStatus_HalfFull           SAI_FIFOSTATUS_HALFFULL
2141 #define SAI_FIFOStatus_3QuartersFull      SAI_FIFOSTATUS_3QUARTERFULL
2142 #define SAI_FIFOStatus_Full               SAI_FIFOSTATUS_FULL
2143 #define IS_SAI_BLOCK_MONO_STREO_MODE     IS_SAI_BLOCK_MONO_STEREO_MODE
2144
2145 /**
2146   * @}
2147   */
2148
2149
2150 /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
2151   * @{
2152   */
2153
2154 /**
2155   * @}
2156   */
2157
2158 #ifdef __cplusplus
2159 }
2160 #endif
2161
2162 #endif /* ___STM32_HAL_LEGACY */
2163
2164 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2165