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1 /**
2 ******************************************************************************
3 * @file stm32f1xx_hal_adc_ex.c
4 * @author MCD Application Team
5 * @version V1.0.0
6 * @date 15-December-2014
7 * @brief This file provides firmware functions to manage the following
8 * functionalities of the Analog to Digital Convertor (ADC)
9 * peripheral:
10 * + Operation functions
11 * ++ Start, stop, get result of conversions of injected
12 * group, using 2 possible modes: polling, interruption.
13 * ++ Multimode feature (available on devices with 2 ADCs or more)
14 * ++ Calibration (ADC automatic self-calibration)
15 * + Control functions
16 * ++ Channels configuration on injected group
17 * Other functions (generic functions) are available in file
18 * "stm32f1xx_hal_adc.c".
19 *
20 @verbatim
21 [..]
22 (@) Sections "ADC peripheral features" and "How to use this driver" are
23 available in file of generic functions "stm32f1xx_hal_adc.c".
24 [..]
25 @endverbatim
26 ******************************************************************************
27 * @attention
28 *
29 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
30 *
31 * Redistribution and use in source and binary forms, with or without modification,
32 * are permitted provided that the following conditions are met:
33 * 1. Redistributions of source code must retain the above copyright notice,
34 * this list of conditions and the following disclaimer.
35 * 2. Redistributions in binary form must reproduce the above copyright notice,
36 * this list of conditions and the following disclaimer in the documentation
37 * and/or other materials provided with the distribution.
38 * 3. Neither the name of STMicroelectronics nor the names of its contributors
39 * may be used to endorse or promote products derived from this software
40 * without specific prior written permission.
41 *
42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
43 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
44 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
45 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
46 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
47 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
48 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
49 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
50 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
51 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
52 *
53 ******************************************************************************
54 */
55
56 /* Includes ------------------------------------------------------------------*/
57 #include "stm32f1xx_hal.h"
58
59 /** @addtogroup STM32F1xx_HAL_Driver
60 * @{
61 */
62
63 /** @defgroup ADCEx ADCEx
64 * @brief ADC Extension HAL module driver
65 * @{
66 */
67
68 #ifdef HAL_ADC_MODULE_ENABLED
69
70 /* Private typedef -----------------------------------------------------------*/
71 /* Private define ------------------------------------------------------------*/
72 /** @defgroup ADCEx_Private_Constants ADCEx Private Constants
73 * @{
74 */
75
76 /* Delay for ADC calibration: */
77 /* Hardware prerequisite before starting a calibration: the ADC must have */
78 /* been in power-on state for at least two ADC clock cycles. */
79 /* Unit: ADC clock cycles */
80 #define ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ((uint32_t) 2)
81
82 /* Timeout value for ADC calibration */
83 /* Value defined to be higher than worst cases: low clocks freq, */
84 /* maximum prescaler. */
85 /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
86 /* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */
87 /* Unit: ms */
88 #define ADC_CALIBRATION_TIMEOUT ((uint32_t) 10)
89
90 /* Delay for temperature sensor stabilization time. */
91 /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
92 /* Unit: us */
93 #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)
94
95 /**
96 * @}
97 */
98
99 /* Private macro -------------------------------------------------------------*/
100 /* Private variables ---------------------------------------------------------*/
101 /* Private function prototypes -----------------------------------------------*/
102 /* Private functions ---------------------------------------------------------*/
103
104 /** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions
105 * @{
106 */
107
108 /** @defgroup ADCEx_Exported_Functions_Group1 Extended Extended IO operation functions
109 * @brief Extended Extended Input and Output operation functions
110 *
111 @verbatim
112 ===============================================================================
113 ##### IO operation functions #####
114 ===============================================================================
115 [..] This section provides functions allowing to:
116 (+) Start conversion of injected group.
117 (+) Stop conversion of injected group.
118 (+) Poll for conversion complete on injected group.
119 (+) Get result of injected channel conversion.
120 (+) Start conversion of injected group and enable interruptions.
121 (+) Stop conversion of injected group and disable interruptions.
122
123 (+) Start multimode and enable DMA transfer.
124 (+) Stop multimode and disable ADC DMA transfer.
125 (+) Get result of multimode conversion.
126
127 (+) Perform the ADC self-calibration for single or differential ending.
128 (+) Get calibration factors for single or differential ending.
129 (+) Set calibration factors for single or differential ending.
130
131 @endverbatim
132 * @{
133 */
134
135 /**
136 * @brief Perform an ADC automatic self-calibration
137 * Calibration prerequisite: ADC must be disabled (execute this
138 * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
139 * During calibration process, ADC is enabled. ADC is let enabled at
140 * the completion of this function.
141 * @param hadc: ADC handle
142 * @retval HAL status
143 */
144 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
145 {
146 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
147 uint32_t tickstart;
148 __IO uint32_t wait_loop_index = 0;
149
150 /* Check the parameters */
151 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
152
153 /* Process locked */
154 __HAL_LOCK(hadc);
155
156 /* 1. Calibration prerequisite: */
157 /* - ADC must be disabled for at least two ADC clock cycles in disable */
158 /* mode before ADC enable */
159 /* Stop potential conversion on going, on regular and injected groups */
160 /* Disable ADC peripheral */
161 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
162
163 /* Check if ADC is effectively disabled */
164 if (tmp_hal_status != HAL_ERROR)
165 {
166 /* Hardware prerequisite: delay before starting the calibration. */
167 /* - Computation of CPU clock cycles corresponding to ADC clock cycles. */
168 /* - Wait for the expected ADC clock cycles delay */
169 wait_loop_index = ((SystemCoreClock
170 / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
171 * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES );
172
173 while(wait_loop_index != 0)
174 {
175 wait_loop_index--;
176 }
177
178 /* 2. Enable the ADC peripheral */
179 ADC_Enable(hadc);
180
181
182 /* 3. Resets ADC calibration registers */
183 SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL);
184
185 tickstart = HAL_GetTick();
186
187 /* Wait for calibration reset completion */
188 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL))
189 {
190 if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
191 {
192 /* Update ADC state machine to error */
193 hadc->State = HAL_ADC_STATE_ERROR;
194
195 /* Process unlocked */
196 __HAL_UNLOCK(hadc);
197
198 return HAL_ERROR;
199 }
200 }
201
202
203 /* 4. Start ADC calibration */
204 SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL);
205
206 tickstart = HAL_GetTick();
207
208 /* Wait for calibration completion */
209 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL))
210 {
211 if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
212 {
213 /* Update ADC state machine to error */
214 hadc->State = HAL_ADC_STATE_ERROR;
215
216 /* Process unlocked */
217 __HAL_UNLOCK(hadc);
218
219 return HAL_ERROR;
220 }
221 }
222
223 }
224
225 /* Process unlocked */
226 __HAL_UNLOCK(hadc);
227
228 /* Return function status */
229 return tmp_hal_status;
230 }
231
232 /**
233 * @brief Enables ADC, starts conversion of injected group.
234 * Interruptions enabled in this function: None.
235 * @param hadc: ADC handle
236 * @retval HAL status
237 */
238 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
239 {
240 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
241
242 /* Check the parameters */
243 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
244
245 /* Process locked */
246 __HAL_LOCK(hadc);
247
248 /* Enable the ADC peripheral */
249 tmp_hal_status = ADC_Enable(hadc);
250
251 /* Start conversion if ADC is effectively enabled */
252 if (tmp_hal_status != HAL_ERROR)
253 {
254 /* Check if a regular conversion is ongoing */
255 if(hadc->State == HAL_ADC_STATE_BUSY_REG)
256 {
257 /* Change ADC state */
258 hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
259 }
260 else
261 {
262 /* Change ADC state */
263 hadc->State = HAL_ADC_STATE_BUSY_INJ;
264 }
265
266 /* Process unlocked */
267 /* Unlock before starting ADC conversions: in case of potential */
268 /* interruption, to let the process to ADC IRQ Handler. */
269 __HAL_UNLOCK(hadc);
270
271 /* Set ADC error code to none */
272 ADC_CLEAR_ERRORCODE(hadc);
273
274 /* Clear injected group conversion flag */
275 /* (To ensure of no unknown state from potential previous ADC operations) */
276 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
277
278 /* Enable conversion of injected group. */
279 /* If software start has been selected, conversion starts immediately. */
280 /* If external trigger has been selected, conversion will start at next */
281 /* trigger event. */
282 /* If automatic injected conversion is enabled, conversion will start */
283 /* after next regular group conversion. */
284 /* Case of multimode enabled (for devices with several ADCs): if ADC is */
285 /* slave, ADC is enabled only (conversion is not started). If ADC is */
286 /* master, ADC is enabled and conversion is started. */
287 if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO))
288 {
289 if (ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
290 ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) )
291 {
292 /* Start ADC conversion on injected group with SW start */
293 SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
294 }
295 else
296 {
297 /* Start ADC conversion on injected group with external trigger */
298 SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG);
299 }
300 }
301 }
302 else
303 {
304 /* Process unlocked */
305 __HAL_UNLOCK(hadc);
306 }
307
308 /* Return function status */
309 return tmp_hal_status;
310 }
311
312 /**
313 * @brief Stop conversion of injected channels. Disable ADC peripheral if
314 * no regular conversion is on going.
315 * @note If ADC must be disabled and if conversion is on going on
316 * regular group, function HAL_ADC_Stop must be used to stop both
317 * injected and regular groups, and disable the ADC.
318 * @note In case of auto-injection mode, HAL_ADC_Stop must be used.
319 * @param hadc: ADC handle
320 * @retval None
321 */
322 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
323 {
324 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
325
326 /* Check the parameters */
327 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
328
329 /* Process locked */
330 __HAL_LOCK(hadc);
331
332 /* Stop potential conversion and disable ADC peripheral */
333 /* Conditioned to: */
334 /* - No conversion on the other group (regular group) is intended to */
335 /* continue (injected and regular groups stop conversion and ADC disable */
336 /* are common) */
337 /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
338 if((hadc->State != HAL_ADC_STATE_BUSY_REG) &&
339 (hadc->State != HAL_ADC_STATE_BUSY_INJ_REG) &&
340 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
341 {
342 /* Stop potential conversion on going, on regular and injected groups */
343 /* Disable ADC peripheral */
344 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
345
346 /* Check if ADC is effectively disabled */
347 if (tmp_hal_status != HAL_ERROR)
348 {
349 /* Change ADC state */
350 hadc->State = HAL_ADC_STATE_READY;
351 }
352 }
353 else
354 {
355 /* Update ADC state machine to error */
356 hadc->State = HAL_ADC_STATE_ERROR;
357
358 tmp_hal_status = HAL_ERROR;
359 }
360
361 /* Process unlocked */
362 __HAL_UNLOCK(hadc);
363
364 /* Return function status */
365 return tmp_hal_status;
366 }
367
368 /**
369 * @brief Wait for injected group conversion to be completed.
370 * @param hadc: ADC handle
371 * @param Timeout: Timeout value in millisecond.
372 * @retval HAL status
373 */
374 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
375 {
376 uint32_t tickstart;
377
378 /* Variables for polling in case of scan mode enabled and polling for each */
379 /* conversion. */
380 __IO uint32_t Conversion_Timeout_CPU_cycles = 0;
381 uint32_t Conversion_Timeout_CPU_cycles_max = 0;
382
383 /* Check the parameters */
384 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
385
386 /* Get timeout */
387 tickstart = HAL_GetTick();
388
389 /* Polling for end of conversion: differentiation if single/sequence */
390 /* conversion. */
391 /* For injected group, flag JEOC is set only at the end of the sequence, */
392 /* not for each conversion within the sequence. */
393 /* - If single conversion for injected group (scan mode disabled or */
394 /* InjectedNbrOfConversion ==1), flag jEOC is used to determine the */
395 /* conversion completion. */
396 /* - If sequence conversion for injected group (scan mode enabled and */
397 /* InjectedNbrOfConversion >=2), flag JEOC is set only at the end of the */
398 /* sequence. */
399 /* To poll for each conversion, the maximum conversion time is computed */
400 /* from ADC conversion time (selected sampling time + conversion time of */
401 /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */
402 /* settings, conversion time range can be from 28 to 32256 CPU cycles). */
403 if ((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET)
404 {
405 /* Wait until End of Conversion flag is raised */
406 while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC))
407 {
408 /* Check if timeout is disabled (set to infinite wait) */
409 if(Timeout != HAL_MAX_DELAY)
410 {
411 if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
412 {
413 /* Update ADC state machine to timeout */
414 hadc->State = HAL_ADC_STATE_TIMEOUT;
415
416 /* Process unlocked */
417 __HAL_UNLOCK(hadc);
418
419 return HAL_ERROR;
420 }
421 }
422 }
423 }
424 else
425 {
426 /* Poll with maximum conversion time */
427 /* - Computation of CPU clock cycles corresponding to ADC clock cycles */
428 /* and ADC maximum conversion cycles on all channels. */
429 /* - Wait for the expected ADC clock cycles delay */
430 Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock
431 / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
432 * ADC_CONVCYCLES_MAX_RANGE(hadc) );
433
434 while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
435 {
436 /* Check if timeout is disabled (set to infinite wait) */
437 if(Timeout != HAL_MAX_DELAY)
438 {
439 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
440 {
441 /* Update ADC state machine to timeout */
442 hadc->State = HAL_ADC_STATE_TIMEOUT;
443
444 /* Process unlocked */
445 __HAL_UNLOCK(hadc);
446
447 return HAL_ERROR;
448 }
449 }
450 Conversion_Timeout_CPU_cycles ++;
451 }
452 }
453
454 /* Clear injected group conversion flag (and regular conversion flag raised */
455 /* simultaneously) */
456 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC | ADC_FLAG_EOC);
457
458 /* Update state machine on conversion status if not in error state */
459 if(hadc->State != HAL_ADC_STATE_ERROR)
460 {
461 /* Update ADC state machine */
462 if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG)
463 {
464
465 if(hadc->State == HAL_ADC_STATE_EOC_REG)
466 {
467 /* Change ADC state */
468 hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
469 }
470 else
471 {
472 /* Change ADC state */
473 hadc->State = HAL_ADC_STATE_EOC_INJ;
474 }
475 }
476 }
477
478 /* Return ADC state */
479 return HAL_OK;
480 }
481
482 /**
483 * @brief Enables ADC, starts conversion of injected group with interruption.
484 * - JEOC (end of conversion of injected group)
485 * Each of these interruptions has its dedicated callback function.
486 * @param hadc: ADC handle
487 * @retval HAL status.
488 */
489 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
490 {
491 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
492
493 /* Check the parameters */
494 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
495
496 /* Process locked */
497 __HAL_LOCK(hadc);
498
499 /* Enable the ADC peripheral */
500 tmp_hal_status = ADC_Enable(hadc);
501
502 /* Start conversion if ADC is effectively enabled */
503 if (tmp_hal_status != HAL_ERROR)
504 {
505 /* Check if a regular conversion is ongoing */
506 if(hadc->State == HAL_ADC_STATE_BUSY_REG)
507 {
508 /* Change ADC state */
509 hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
510 }
511 else
512 {
513 /* Change ADC state */
514 hadc->State = HAL_ADC_STATE_BUSY_INJ;
515 }
516
517 /* Process unlocked */
518 /* Unlock before starting ADC conversions: in case of potential */
519 /* interruption, to let the process to ADC IRQ Handler. */
520 __HAL_UNLOCK(hadc);
521
522 /* Set ADC error code to none */
523 ADC_CLEAR_ERRORCODE(hadc);
524
525 /* Clear injected group conversion flag */
526 /* (To ensure of no unknown state from potential previous ADC operations) */
527 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
528
529 /* Enable end of conversion interrupt for injected channels */
530 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
531
532 /* Start conversion of injected group if software start has been selected */
533 /* and if automatic injected conversion is disabled. */
534 /* If external trigger has been selected, conversion will start at next */
535 /* trigger event. */
536 /* If automatic injected conversion is enabled, conversion will start */
537 /* after next regular group conversion. */
538 if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO))
539 {
540 if (ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
541 ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) )
542 {
543 /* Start ADC conversion on injected group with SW start */
544 SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
545 }
546 else
547 {
548 /* Start ADC conversion on injected group with external trigger */
549 SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG);
550 }
551 }
552 }
553 else
554 {
555 /* Process unlocked */
556 __HAL_UNLOCK(hadc);
557 }
558
559 /* Return function status */
560 return tmp_hal_status;
561 }
562
563 /**
564 * @brief Stop conversion of injected channels, disable interruption of
565 * end-of-conversion. Disable ADC peripheral if no regular conversion
566 * is on going.
567 * @note If ADC must be disabled and if conversion is on going on
568 * regular group, function HAL_ADC_Stop must be used to stop both
569 * injected and regular groups, and disable the ADC.
570 * @param hadc: ADC handle
571 * @retval None
572 */
573 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
574 {
575 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
576
577 /* Check the parameters */
578 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
579
580 /* Process locked */
581 __HAL_LOCK(hadc);
582
583 /* Stop potential conversion and disable ADC peripheral */
584 /* Conditioned to: */
585 /* - No conversion on the other group (regular group) is intended to */
586 /* continue (injected and regular groups stop conversion and ADC disable */
587 /* are common) */
588 /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
589 if((hadc->State != HAL_ADC_STATE_BUSY_REG) &&
590 (hadc->State != HAL_ADC_STATE_BUSY_INJ_REG) &&
591 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
592 {
593 /* Stop potential conversion on going, on regular and injected groups */
594 /* Disable ADC peripheral */
595 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
596
597 /* Check if ADC is effectively disabled */
598 if (tmp_hal_status != HAL_ERROR)
599 {
600 /* Disable ADC end of conversion interrupt for injected channels */
601 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
602
603 /* Change ADC state */
604 hadc->State = HAL_ADC_STATE_READY;
605 }
606 }
607 else
608 {
609 /* Update ADC state machine to error */
610 hadc->State = HAL_ADC_STATE_ERROR;
611
612 tmp_hal_status = HAL_ERROR;
613 }
614
615 /* Process unlocked */
616 __HAL_UNLOCK(hadc);
617
618 /* Return function status */
619 return tmp_hal_status;
620 }
621
622 #if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
623 /**
624 * @brief Enables ADC, starts conversion of regular group and transfers result
625 * through DMA.
626 * Multimode must have been previously configured using
627 * HAL_ADCEx_MultiModeConfigChannel() function.
628 * Interruptions enabled in this function:
629 * - DMA transfer complete
630 * - DMA half transfer
631 * Each of these interruptions has its dedicated callback function.
632 * @note: On STM32F1 devices, ADC slave regular group must be configured
633 * with conversion trigger ADC_SOFTWARE_START.
634 * @note: ADC slave can be enabled preliminarily using single-mode
635 * HAL_ADC_Start() function.
636 * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
637 * @param pData: The destination Buffer address.
638 * @param Length: The length of data to be transferred from ADC peripheral to memory.
639 * @retval None
640 */
641 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
642 {
643 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
644 ADC_HandleTypeDef tmphadcSlave;
645
646 /* Check the parameters */
647 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
648 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
649
650 /* Process locked */
651 __HAL_LOCK(hadc);
652
653 /* Set a temporary handle of the ADC slave associated to the ADC master */
654 ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
655
656 /* On STM32F1 devices, ADC slave regular group must be configured with */
657 /* conversion trigger ADC_SOFTWARE_START. */
658 /* Note: External trigger of ADC slave must be enabled, it is already done */
659 /* into function "HAL_ADC_Init()". */
660 if ((tmphadcSlave.Instance == NULL) ||
661 (! ADC_IS_SOFTWARE_START_REGULAR(&tmphadcSlave)) )
662 {
663 /* Update ADC state machine to error */
664 hadc->State = HAL_ADC_STATE_ERROR;
665
666 /* Process unlocked */
667 __HAL_UNLOCK(hadc);
668
669 return HAL_ERROR;
670 }
671
672 /* Enable the ADC peripherals: master and slave (in case if not already */
673 /* enabled previously) */
674 tmp_hal_status = ADC_Enable(hadc);
675 if (tmp_hal_status != HAL_ERROR)
676 {
677 tmp_hal_status = ADC_Enable(&tmphadcSlave);
678 }
679
680 /* Start conversion all ADCs of multimode are effectively enabled */
681 if (tmp_hal_status != HAL_ERROR)
682 {
683 /* State machine update (ADC master): Check if an injected conversion is */
684 /* ongoing. */
685 if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
686 {
687 /* Change ADC state */
688 hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
689 }
690 else
691 {
692 /* Change ADC state */
693 hadc->State = HAL_ADC_STATE_BUSY_REG;
694 }
695
696 /* Process unlocked */
697 /* Unlock before starting ADC conversions: in case of potential */
698 /* interruption, to let the process to ADC IRQ Handler. */
699 __HAL_UNLOCK(hadc);
700
701 /* Set ADC error code to none */
702 ADC_CLEAR_ERRORCODE(hadc);
703
704
705 /* Set the DMA transfer complete callback */
706 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
707
708 /* Set the DMA half transfer complete callback */
709 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
710
711 /* Set the DMA error callback */
712 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
713
714
715 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
716 /* start (in case of SW start): */
717
718 /* Clear regular group conversion flag and overrun flag */
719 /* (To ensure of no unknown state from potential previous ADC operations) */
720 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
721
722 /* Enable ADC DMA mode of ADC master */
723 SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
724
725 /* Start the DMA channel */
726 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
727
728 /* Start conversion of regular group if software start has been selected. */
729 /* If external trigger has been selected, conversion will start at next */
730 /* trigger event. */
731 /* Note: Alternate trigger for single conversion could be to force an */
732 /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
733 if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
734 {
735 /* Start ADC conversion on regular group with SW start */
736 SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
737 }
738 else
739 {
740 /* Start ADC conversion on regular group with external trigger */
741 SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
742 }
743 }
744 else
745 {
746 /* Process unlocked */
747 __HAL_UNLOCK(hadc);
748 }
749
750 /* Return function status */
751 return tmp_hal_status;
752 }
753
754 /**
755 * @brief Stop ADC conversion of regular group (and injected channels in
756 * case of auto_injection mode), disable ADC DMA transfer, disable
757 * ADC peripheral.
758 * @note Multimode is kept enabled after this function. To disable multimode
759 * (set with HAL_ADCEx_MultiModeConfigChannel(), ADC must be
760 * reinitialized using HAL_ADC_Init() or HAL_ADC_ReInit().
761 * @note In case of DMA configured in circular mode, function
762 * HAL_ADC_Stop_DMA must be called after this function with handle of
763 * ADC slave, to properly disable the DMA channel.
764 * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
765 * @retval None
766 */
767 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
768 {
769 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
770 ADC_HandleTypeDef tmphadcSlave;
771
772 /* Check the parameters */
773 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
774
775 /* Process locked */
776 __HAL_LOCK(hadc);
777
778
779 /* Stop potential conversion on going, on regular and injected groups */
780 /* Disable ADC master peripheral */
781 tmp_hal_status = ADC_ConversionStop_Disable(hadc);
782
783 /* Check if ADC is effectively disabled */
784 if (tmp_hal_status != HAL_ERROR)
785 {
786 /* Set a temporary handle of the ADC slave associated to the ADC master */
787 ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
788
789 if (tmphadcSlave.Instance == NULL)
790 {
791 /* Update ADC state machine to error */
792 hadc->State = HAL_ADC_STATE_ERROR;
793
794 /* Process unlocked */
795 __HAL_UNLOCK(hadc);
796
797 return HAL_ERROR;
798 }
799 else
800 {
801 /* Disable ADC slave peripheral */
802 tmp_hal_status = ADC_ConversionStop_Disable(&tmphadcSlave);
803
804 /* Check if ADC is effectively disabled */
805 if (tmp_hal_status != HAL_OK)
806 {
807 /* Update ADC state machine to error */
808 hadc->State = HAL_ADC_STATE_ERROR;
809
810 /* Process unlocked */
811 __HAL_UNLOCK(hadc);
812
813 return HAL_ERROR;
814 }
815 }
816
817 /* Disable ADC DMA mode */
818 CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
819
820 /* Reset configuration of ADC DMA continuous request for dual mode */
821 CLEAR_BIT(hadc->Instance->CR1, ADC_CR1_DUALMOD);
822
823 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
824 /* while DMA transfer is on going) */
825 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
826
827
828 /* Check if DMA channel effectively disabled */
829 if (tmp_hal_status != HAL_ERROR)
830 {
831 /* Change ADC state (ADC master) */
832 hadc->State = HAL_ADC_STATE_READY;
833 }
834 else
835 {
836 /* Update ADC state machine to error */
837 hadc->State = HAL_ADC_STATE_ERROR;
838 }
839 }
840
841 /* Process unlocked */
842 __HAL_UNLOCK(hadc);
843
844 /* Return function status */
845 return tmp_hal_status;
846 }
847 #endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
848
849 /**
850 * @brief Get ADC injected group conversion result.
851 * @param hadc: ADC handle
852 * @param InjectedRank: the converted ADC injected rank.
853 * This parameter can be one of the following values:
854 * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
855 * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
856 * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
857 * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
858 * @retval None
859 */
860 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
861 {
862 uint32_t tmp_jdr = 0;
863
864 /* Check the parameters */
865 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
866 assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
867
868 /* Clear injected group conversion flag to have similar behaviour as */
869 /* regular group: reading data register also clears end of conversion flag. */
870 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
871
872 /* Get ADC converted value */
873 switch(InjectedRank)
874 {
875 case ADC_INJECTED_RANK_4:
876 tmp_jdr = hadc->Instance->JDR4;
877 break;
878 case ADC_INJECTED_RANK_3:
879 tmp_jdr = hadc->Instance->JDR3;
880 break;
881 case ADC_INJECTED_RANK_2:
882 tmp_jdr = hadc->Instance->JDR2;
883 break;
884 case ADC_INJECTED_RANK_1:
885 default:
886 tmp_jdr = hadc->Instance->JDR1;
887 break;
888 }
889
890 /* Return ADC converted value */
891 return tmp_jdr;
892 }
893
894 #if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
895 /**
896 * @brief Returns the last ADC Master&Slave regular conversions results data
897 * in the selected multi mode.
898 * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
899 * @retval The converted data value.
900 */
901 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
902 {
903 uint32_t tmpDR = 0;
904
905 /* Check the parameters */
906 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
907
908 /* Check the parameters */
909 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
910
911 /* Note: EOC flag is not cleared here by software because automatically */
912 /* cleared by hardware when reading register DR. */
913
914 /* On STM32F1 devices, ADC1 data register DR contains ADC2 conversions */
915 /* only if ADC1 DMA mode is enabled. */
916 tmpDR = hadc->Instance->DR;
917
918 if (HAL_IS_BIT_CLR(ADC1->CR2, ADC_CR2_DMA))
919 {
920 tmpDR |= (ADC2->DR << 16);
921 }
922
923 /* Return ADC converted value */
924 return tmpDR;
925 }
926 #endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
927
928 /**
929 * @brief Injected conversion complete callback in non blocking mode
930 * @param hadc: ADC handle
931 * @retval None
932 */
933 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
934 {
935 /* NOTE : This function Should not be modified, when the callback is needed,
936 the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file
937 */
938 }
939
940 /**
941 * @}
942 */
943
944 /** @defgroup ADCEx_Exported_Functions_Group2 Extended Peripheral Control functions
945 * @brief Extended Peripheral Control functions
946 *
947 @verbatim
948 ===============================================================================
949 ##### Peripheral Control functions #####
950 ===============================================================================
951 [..] This section provides functions allowing to:
952 (+) Configure channels on injected group
953 (+) Configure multimode
954
955 @endverbatim
956 * @{
957 */
958
959 /**
960 * @brief Configures the ADC injected group and the selected channel to be
961 * linked to the injected group.
962 * @note Possibility to update parameters on the fly:
963 * This function initializes injected group, following calls to this
964 * function can be used to reconfigure some parameters of structure
965 * "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC.
966 * The setting of these parameters is conditioned to ADC state:
967 * this function must be called when ADC is not under conversion.
968 * @param hadc: ADC handle
969 * @param sConfigInjected: Structure of ADC injected group and ADC channel for
970 * injected group.
971 * @retval None
972 */
973 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
974 {
975 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
976 __IO uint32_t wait_loop_index = 0;
977
978 /* Check the parameters */
979 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
980 assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
981 assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
982 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
983 assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
984 assert_param(IS_ADC_RANGE(sConfigInjected->InjectedOffset));
985
986 if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
987 {
988 assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
989 assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
990 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
991 }
992
993 /* Process locked */
994 __HAL_LOCK(hadc);
995
996 /* Configuration of injected group sequencer: */
997 /* - if scan mode is disabled, injected channels sequence length is set to */
998 /* 0x00: 1 channel converted (channel on regular rank 1) */
999 /* Parameter "InjectedNbrOfConversion" is discarded. */
1000 /* Note: Scan mode is present by hardware on this device and, if */
1001 /* disabled, discards automatically nb of conversions. Anyway, nb of */
1002 /* conversions is forced to 0x00 for alignment over all STM32 devices. */
1003 /* - if scan mode is enabled, injected channels sequence length is set to */
1004 /* parameter "InjectedNbrOfConversion". */
1005 if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
1006 {
1007 if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
1008 {
1009 /* Clear the old SQx bits for all injected ranks */
1010 MODIFY_REG(hadc->Instance->JSQR ,
1011 ADC_JSQR_JL |
1012 ADC_JSQR_JSQ4 |
1013 ADC_JSQR_JSQ3 |
1014 ADC_JSQR_JSQ2 |
1015 ADC_JSQR_JSQ1 ,
1016 ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
1017 ADC_INJECTED_RANK_1,
1018 0x01) );
1019 }
1020 /* If another injected rank than rank1 was intended to be set, and could */
1021 /* not due to ScanConvMode disabled, error is reported. */
1022 else
1023 {
1024 /* Update ADC state machine to error */
1025 hadc->State = HAL_ADC_STATE_ERROR;
1026
1027 tmp_hal_status = HAL_ERROR;
1028 }
1029 }
1030 else
1031 {
1032 /* Since injected channels rank conv. order depends on total number of */
1033 /* injected conversions, selected rank must be below or equal to total */
1034 /* number of injected conversions to be updated. */
1035 if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion)
1036 {
1037 /* Clear the old SQx bits for the selected rank */
1038 /* Set the SQx bits for the selected rank */
1039 MODIFY_REG(hadc->Instance->JSQR ,
1040
1041 ADC_JSQR_JL |
1042 ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,
1043 sConfigInjected->InjectedRank,
1044 sConfigInjected->InjectedNbrOfConversion) ,
1045
1046 ADC_JSQR_JL_SHIFT(sConfigInjected->InjectedNbrOfConversion) |
1047 ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
1048 sConfigInjected->InjectedRank,
1049 sConfigInjected->InjectedNbrOfConversion) );
1050 }
1051 else
1052 {
1053 /* Clear the old SQx bits for the selected rank */
1054 MODIFY_REG(hadc->Instance->JSQR ,
1055
1056 ADC_JSQR_JL |
1057 ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,
1058 sConfigInjected->InjectedRank,
1059 sConfigInjected->InjectedNbrOfConversion) ,
1060
1061 0x00000000 );
1062 }
1063 }
1064
1065 /* Configuration of injected group */
1066 /* Parameters update conditioned to ADC state: */
1067 /* Parameters that can be updated only when ADC is disabled: */
1068 /* - external trigger to start conversion */
1069 /* Parameters update not conditioned to ADC state: */
1070 /* - Automatic injected conversion */
1071 /* - Injected discontinuous mode */
1072 /* Note: In case of ADC already enabled, caution to not launch an unwanted */
1073 /* conversion while modifying register CR2 by writing 1 to bit ADON. */
1074 if (ADC_IS_ENABLE(hadc) == RESET)
1075 {
1076 MODIFY_REG(hadc->Instance->CR2 ,
1077 ADC_CR2_JEXTSEL |
1078 ADC_CR2_ADON ,
1079 ADC_CFGR_JEXTSEL(hadc, sConfigInjected->ExternalTrigInjecConv) );
1080 }
1081
1082
1083 /* Configuration of injected group */
1084 /* - Automatic injected conversion */
1085 /* - Injected discontinuous mode */
1086
1087 /* Automatic injected conversion can be enabled if injected group */
1088 /* external triggers are disabled. */
1089 if (sConfigInjected->AutoInjectedConv == ENABLE)
1090 {
1091 if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
1092 {
1093 SET_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO);
1094 }
1095 else
1096 {
1097 /* Update ADC state machine to error */
1098 hadc->State = HAL_ADC_STATE_ERROR;
1099
1100 tmp_hal_status = HAL_ERROR;
1101 }
1102 }
1103
1104 /* Injected discontinuous can be enabled only if auto-injected mode is */
1105 /* disabled. */
1106 if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
1107 {
1108 if (sConfigInjected->AutoInjectedConv == DISABLE)
1109 {
1110 SET_BIT(hadc->Instance->CR1, ADC_CR1_JDISCEN);
1111 }
1112 else
1113 {
1114 /* Update ADC state machine to error */
1115 hadc->State = HAL_ADC_STATE_ERROR;
1116
1117 tmp_hal_status = HAL_ERROR;
1118 }
1119 }
1120
1121
1122 /* InjectedChannel sampling time configuration */
1123 /* For channels 10 to 17 */
1124 if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10)
1125 {
1126 MODIFY_REG(hadc->Instance->SMPR1 ,
1127 ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel) ,
1128 ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
1129 }
1130 else /* For channels 0 to 9 */
1131 {
1132 MODIFY_REG(hadc->Instance->SMPR2 ,
1133 ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel) ,
1134 ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
1135 }
1136
1137 /* If ADC1 InjectedChannel_16 or InjectedChannel_17 is selected, enable Temperature sensor */
1138 /* and VREFINT measurement path. */
1139 if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) ||
1140 (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) )
1141 {
1142 SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
1143 }
1144
1145
1146 /* Configure the offset: offset enable/disable, InjectedChannel, offset value */
1147 switch(sConfigInjected->InjectedRank)
1148 {
1149 case 1:
1150 /* Set injected channel 1 offset */
1151 MODIFY_REG(hadc->Instance->JOFR1,
1152 ADC_JOFR1_JOFFSET1,
1153 sConfigInjected->InjectedOffset);
1154 break;
1155 case 2:
1156 /* Set injected channel 2 offset */
1157 MODIFY_REG(hadc->Instance->JOFR2,
1158 ADC_JOFR2_JOFFSET2,
1159 sConfigInjected->InjectedOffset);
1160 break;
1161 case 3:
1162 /* Set injected channel 3 offset */
1163 MODIFY_REG(hadc->Instance->JOFR3,
1164 ADC_JOFR3_JOFFSET3,
1165 sConfigInjected->InjectedOffset);
1166 break;
1167 case 4:
1168 default:
1169 MODIFY_REG(hadc->Instance->JOFR4,
1170 ADC_JOFR4_JOFFSET4,
1171 sConfigInjected->InjectedOffset);
1172 break;
1173 }
1174
1175 /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
1176 /* and VREFINT measurement path. */
1177 if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) ||
1178 (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) )
1179 {
1180 /* For STM32F1 devices with several ADC: Only ADC1 can access internal */
1181 /* measurement channels (VrefInt/TempSensor). If these channels are */
1182 /* intended to be set on other ADC instances, an error is reported. */
1183 if (hadc->Instance == ADC1)
1184 {
1185 if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
1186 {
1187 SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
1188
1189 if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR))
1190 {
1191 /* Delay for temperature sensor stabilization time */
1192 /* Compute number of CPU cycles to wait for */
1193 wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
1194 while(wait_loop_index != 0)
1195 {
1196 wait_loop_index--;
1197 }
1198 }
1199 }
1200 }
1201 else
1202 {
1203 /* Update ADC state machine to error */
1204 hadc->State = HAL_ADC_STATE_ERROR;
1205
1206 tmp_hal_status = HAL_ERROR;
1207 }
1208 }
1209
1210 /* Process unlocked */
1211 __HAL_UNLOCK(hadc);
1212
1213 /* Return function status */
1214 return tmp_hal_status;
1215 }
1216
1217 #if defined (STM32F101xG) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
1218 /**
1219 * @brief Enable ADC multimode and configure multimode parameters
1220 * @note Possibility to update parameters on the fly:
1221 * This function initializes multimode parameters, following
1222 * calls to this function can be used to reconfigure some parameters
1223 * of structure "ADC_MultiModeTypeDef" on the fly, without reseting
1224 * the ADCs (both ADCs of the common group).
1225 * The setting of these parameters is conditioned to ADC state.
1226 * For parameters constraints, see comments of structure
1227 * "ADC_MultiModeTypeDef".
1228 * @note To change back configuration from multimode to single mode, ADC must
1229 * be reset (using function HAL_ADC_Init() ).
1230 * @param hadc: ADC handle
1231 * @param multimode: Structure of ADC multimode configuration
1232 * @retval HAL status
1233 */
1234 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
1235 {
1236 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
1237 ADC_HandleTypeDef tmphadcSlave;
1238
1239 /* Check the parameters */
1240 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
1241 assert_param(IS_ADC_MODE(multimode->Mode));
1242
1243 /* Process locked */
1244 __HAL_LOCK(hadc);
1245
1246 /* Set a temporary handle of the ADC slave associated to the ADC master */
1247 ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
1248
1249 /* Parameters update conditioned to ADC state: */
1250 /* Parameters that can be updated when ADC is disabled or enabled without */
1251 /* conversion on going on regular group: */
1252 /* - ADC master and ADC slave DMA configuration */
1253 /* Parameters that can be updated only when ADC is disabled: */
1254 /* - Multimode mode selection */
1255 /* To optimize code, all multimode settings can be set when both ADCs of */
1256 /* the common group are in state: disabled. */
1257 if ((ADC_IS_ENABLE(hadc) == RESET) &&
1258 (ADC_IS_ENABLE(&tmphadcSlave) == RESET) &&
1259 (IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)) )
1260 {
1261 MODIFY_REG(hadc->Instance->CR1,
1262 ADC_CR1_DUALMOD ,
1263 multimode->Mode );
1264 }
1265 /* If one of the ADC sharing the same common group is enabled, no update */
1266 /* could be done on neither of the multimode structure parameters. */
1267 else
1268 {
1269 /* Update ADC state machine to error */
1270 hadc->State = HAL_ADC_STATE_ERROR;
1271
1272 tmp_hal_status = HAL_ERROR;
1273 }
1274
1275
1276 /* Process unlocked */
1277 __HAL_UNLOCK(hadc);
1278
1279 /* Return function status */
1280 return tmp_hal_status;
1281 }
1282 #endif /* STM32F101xG || defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
1283 /**
1284 * @}
1285 */
1286
1287 /**
1288 * @}
1289 */
1290
1291 #endif /* HAL_ADC_MODULE_ENABLED */
1292 /**
1293 * @}
1294 */
1295
1296 /**
1297 * @}
1298 */
1299
1300 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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