]> git.gir.st - tmk_keyboard.git/blob - tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_cortex.c
Squashed 'tmk_core/' changes from 7967731..b9e0ea0
[tmk_keyboard.git] / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_STM / TARGET_STM32F1 / stm32f1xx_hal_cortex.c
1 /**
2 ******************************************************************************
3 * @file stm32f1xx_hal_cortex.c
4 * @author MCD Application Team
5 * @version V1.0.0
6 * @date 15-December-2014
7 * @brief CORTEX HAL module driver.
8 *
9 * This file provides firmware functions to manage the following
10 * functionalities of the CORTEX:
11 * + Initialization and de-initialization functions
12 * + Peripheral Control functions
13 *
14 * @verbatim
15 ==============================================================================
16 ##### How to use this driver #####
17 ==============================================================================
18
19 [..]
20 *** How to configure Interrupts using Cortex HAL driver ***
21 ===========================================================
22 [..]
23 This section provide functions allowing to configure the NVIC interrupts (IRQ).
24 The Cortex-M3 exceptions are managed by CMSIS functions.
25
26 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
27 function according to the following table.
28
29 The table below gives the allowed values of the pre-emption priority and subpriority according
30 to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
31 ==========================================================================================================================
32 NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
33 ==========================================================================================================================
34 NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bits for pre-emption priority
35 | | | 4 bits for subpriority
36 --------------------------------------------------------------------------------------------------------------------------
37 NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
38 | | | 3 bits for subpriority
39 --------------------------------------------------------------------------------------------------------------------------
40 NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
41 | | | 2 bits for subpriority
42 --------------------------------------------------------------------------------------------------------------------------
43 NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
44 | | | 1 bits for subpriority
45 --------------------------------------------------------------------------------------------------------------------------
46 NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
47 | | | 0 bits for subpriority
48 ==========================================================================================================================
49 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
50
51 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
52
53
54 -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
55 The pending IRQ priority will be managed only by the sub priority.
56
57 -@- IRQ priority order (sorted by highest to lowest priority):
58 (+@) Lowest pre-emption priority
59 (+@) Lowest sub priority
60 (+@) Lowest hardware priority (IRQ number)
61
62 [..]
63 *** How to configure Systick using Cortex HAL driver ***
64 ========================================================
65 [..]
66 Setup SysTick Timer for 1 msec interrupts.
67
68 (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
69 is a CMSIS function that:
70 (++) Configures the SysTick Reload register with value passed as function parameter.
71 (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
72 (++) Resets the SysTick Counter register.
73 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
74 (++) Enables the SysTick Interrupt.
75 (++) Starts the SysTick Counter.
76
77 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
78 __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
79 HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
80 inside the stm32f1xx_hal_cortex.h file.
81
82 (+) You can change the SysTick IRQ priority by calling the
83 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
84 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
85
86 (+) To adjust the SysTick time base, use the following formula:
87
88 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
89 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
90 (++) Reload Value should not exceed 0xFFFFFF
91
92 @endverbatim
93 ******************************************************************************
94 * @attention
95 *
96 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
97 *
98 * Redistribution and use in source and binary forms, with or without modification,
99 * are permitted provided that the following conditions are met:
100 * 1. Redistributions of source code must retain the above copyright notice,
101 * this list of conditions and the following disclaimer.
102 * 2. Redistributions in binary form must reproduce the above copyright notice,
103 * this list of conditions and the following disclaimer in the documentation
104 * and/or other materials provided with the distribution.
105 * 3. Neither the name of STMicroelectronics nor the names of its contributors
106 * may be used to endorse or promote products derived from this software
107 * without specific prior written permission.
108 *
109 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
110 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
111 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
112 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
113 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
114 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
115 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
116 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
117 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
118 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
119 *
120 ******************************************************************************
121 */
122
123 /* Includes ------------------------------------------------------------------*/
124 #include "stm32f1xx_hal.h"
125
126 /** @addtogroup STM32F1xx_HAL_Driver
127 * @{
128 */
129
130 /** @defgroup CORTEX CORTEX
131 * @brief CORTEX HAL module driver
132 * @{
133 */
134
135 #ifdef HAL_CORTEX_MODULE_ENABLED
136
137 /* Private typedef -----------------------------------------------------------*/
138 /* Private define ------------------------------------------------------------*/
139 /* Private macro -------------------------------------------------------------*/
140 /* Private variables ---------------------------------------------------------*/
141 /* Private function prototypes -----------------------------------------------*/
142 /* Private functions ---------------------------------------------------------*/
143
144 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
145 * @{
146 */
147
148
149 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
150 * @brief Initialization and Configuration functions
151 *
152 @verbatim
153 ==============================================================================
154 ##### Initialization and de-initialization functions #####
155 ==============================================================================
156 [..]
157 This section provide the Cortex HAL driver functions allowing to configure Interrupts
158 Systick functionalities
159
160 @endverbatim
161 * @{
162 */
163
164
165 /**
166 * @brief Sets the priority grouping field (pre-emption priority and subpriority)
167 * using the required unlock sequence.
168 * @param PriorityGroup: The priority grouping bits length.
169 * This parameter can be one of the following values:
170 * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
171 * 4 bits for subpriority
172 * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
173 * 3 bits for subpriority
174 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
175 * 2 bits for subpriority
176 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
177 * 1 bits for subpriority
178 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
179 * 0 bits for subpriority
180 * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
181 * The pending IRQ priority will be managed only by the subpriority.
182 * @retval None
183 */
184 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
185 {
186 /* Check the parameters */
187 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
188
189 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
190 NVIC_SetPriorityGrouping(PriorityGroup);
191 }
192
193 /**
194 * @brief Sets the priority of an interrupt.
195 * @param IRQn: External interrupt number
196 * This parameter can be an enumerator of IRQn_Type enumeration
197 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
198 * @param PreemptPriority: The pre-emption priority for the IRQn channel.
199 * This parameter can be a value between 0 and 15
200 * A lower priority value indicates a higher priority
201 * @param SubPriority: the subpriority level for the IRQ channel.
202 * This parameter can be a value between 0 and 15
203 * A lower priority value indicates a higher priority.
204 * @retval None
205 */
206 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
207 {
208 uint32_t prioritygroup = 0x00;
209
210 /* Check the parameters */
211 assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
212 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
213
214 prioritygroup = NVIC_GetPriorityGrouping();
215
216 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
217 }
218
219 /**
220 * @brief Enables a device specific interrupt in the NVIC interrupt controller.
221 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
222 * function should be called before.
223 * @param IRQn External interrupt number
224 * This parameter can be an enumerator of IRQn_Type enumeration
225 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
226 * @retval None
227 */
228 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
229 {
230 /* Check the parameters */
231 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
232
233 /* Enable interrupt */
234 NVIC_EnableIRQ(IRQn);
235 }
236
237 /**
238 * @brief Disables a device specific interrupt in the NVIC interrupt controller.
239 * @param IRQn External interrupt number
240 * This parameter can be an enumerator of IRQn_Type enumeration
241 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
242 * @retval None
243 */
244 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
245 {
246 /* Check the parameters */
247 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
248
249
250 /* Disable interrupt */
251 NVIC_DisableIRQ(IRQn);
252 }
253
254 /**
255 * @brief Initiates a system reset request to reset the MCU.
256 * @retval None
257 */
258 void HAL_NVIC_SystemReset(void)
259 {
260 /* System Reset */
261 NVIC_SystemReset();
262 }
263
264 /**
265 * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
266 * Counter is in free running mode to generate periodic interrupts.
267 * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
268 * @retval status: - 0 Function succeeded.
269 * - 1 Function failed.
270 */
271 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
272 {
273 return SysTick_Config(TicksNumb);
274 }
275 /**
276 * @}
277 */
278
279 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
280 * @brief Cortex control functions
281 *
282 @verbatim
283 ==============================================================================
284 ##### Peripheral Control functions #####
285 ==============================================================================
286 [..]
287 This subsection provides a set of functions allowing to control the CORTEX
288 (NVIC, SYSTICK) functionalities.
289
290
291 @endverbatim
292 * @{
293 */
294
295 /**
296 * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
297 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
298 */
299 uint32_t HAL_NVIC_GetPriorityGrouping(void)
300 {
301 /* Get the PRIGROUP[10:8] field value */
302 return NVIC_GetPriorityGrouping();
303 }
304
305 /**
306 * @brief Gets the priority of an interrupt.
307 * @param IRQn: External interrupt number
308 * This parameter can be an enumerator of IRQn_Type enumeration
309 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
310 * @param PriorityGroup: the priority grouping bits length.
311 * This parameter can be one of the following values:
312 * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
313 * 4 bits for subpriority
314 * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
315 * 3 bits for subpriority
316 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
317 * 2 bits for subpriority
318 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
319 * 1 bits for subpriority
320 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
321 * 0 bits for subpriority
322 * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
323 * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
324 * @retval None
325 */
326 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
327 {
328 /* Check the parameters */
329 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
330 /* Get priority for Cortex-M system or device specific interrupts */
331 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
332 }
333
334 /**
335 * @brief Sets Pending bit of an external interrupt.
336 * @param IRQn External interrupt number
337 * This parameter can be an enumerator of IRQn_Type enumeration
338 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
339 * @retval None
340 */
341 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
342 {
343 /* Set interrupt pending */
344 NVIC_SetPendingIRQ(IRQn);
345 }
346
347 /**
348 * @brief Gets Pending Interrupt (reads the pending register in the NVIC
349 * and returns the pending bit for the specified interrupt).
350 * @param IRQn External interrupt number
351 * This parameter can be an enumerator of IRQn_Type enumeration
352 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
353 * @retval status: - 0 Interrupt status is not pending.
354 * - 1 Interrupt status is pending.
355 */
356 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
357 {
358 /* Return 1 if pending else 0 */
359 return NVIC_GetPendingIRQ(IRQn);
360 }
361
362 /**
363 * @brief Clears the pending bit of an external interrupt.
364 * @param IRQn External interrupt number
365 * This parameter can be an enumerator of IRQn_Type enumeration
366 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
367 * @retval None
368 */
369 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
370 {
371 /* Clear pending interrupt */
372 NVIC_ClearPendingIRQ(IRQn);
373 }
374
375 /**
376 * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
377 * @param IRQn External interrupt number
378 * This parameter can be an enumerator of IRQn_Type enumeration
379 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f10xxx.h))
380 * @retval status: - 0 Interrupt status is not pending.
381 * - 1 Interrupt status is pending.
382 */
383 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
384 {
385 /* Return 1 if active else 0 */
386 return NVIC_GetActive(IRQn);
387 }
388
389 /**
390 * @brief Configures the SysTick clock source.
391 * @param CLKSource: specifies the SysTick clock source.
392 * This parameter can be one of the following values:
393 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
394 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
395 * @retval None
396 */
397 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
398 {
399 /* Check the parameters */
400 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
401 if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
402 {
403 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
404 }
405 else
406 {
407 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
408 }
409 }
410
411 /**
412 * @brief This function handles SYSTICK interrupt request.
413 * @retval None
414 */
415 void HAL_SYSTICK_IRQHandler(void)
416 {
417 HAL_SYSTICK_Callback();
418 }
419
420 /**
421 * @brief SYSTICK callback.
422 * @retval None
423 */
424 __weak void HAL_SYSTICK_Callback(void)
425 {
426 /* NOTE : This function Should not be modified, when the callback is needed,
427 the HAL_SYSTICK_Callback could be implemented in the user file
428 */
429 }
430
431 /**
432 * @}
433 */
434
435 /**
436 * @}
437 */
438
439 #endif /* HAL_CORTEX_MODULE_ENABLED */
440 /**
441 * @}
442 */
443
444 /**
445 * @}
446 */
447
448 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Imprint / Impressum