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[tmk_keyboard.git] / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_STM / TARGET_STM32F1 / stm32f1xx_hal_eth.h
1 /**
2 ******************************************************************************
3 * @file stm32f1xx_hal_eth.h
4 * @author MCD Application Team
5 * @version V1.0.0
6 * @date 15-December-2014
7 * @brief Header file of ETH HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F1xx_HAL_ETH_H
40 #define __STM32F1xx_HAL_ETH_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f1xx_hal_def.h"
48
49 /** @addtogroup STM32F1xx_HAL_Driver
50 * @{
51 */
52 #if defined (STM32F107xC)
53
54 /** @addtogroup ETH
55 * @{
56 */
57
58 /** @addtogroup ETH_Private_Macros
59 * @{
60 */
61 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
62 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
63 ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
64 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
65 ((SPEED) == ETH_SPEED_100M))
66 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
67 ((MODE) == ETH_MODE_HALFDUPLEX))
68 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
69 ((MODE) == ETH_MODE_HALFDUPLEX))
70 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
71 ((MODE) == ETH_RXINTERRUPT_MODE))
72 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
73 ((MODE) == ETH_RXINTERRUPT_MODE))
74 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
75 ((MODE) == ETH_RXINTERRUPT_MODE))
76 #define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
77 ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
78 #define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
79 ((MODE) == ETH_MEDIA_INTERFACE_RMII))
80 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
81 ((CMD) == ETH_WATCHDOG_DISABLE))
82 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
83 ((CMD) == ETH_JABBER_DISABLE))
84 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
85 ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
86 ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
87 ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
88 ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
89 ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
90 ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
91 ((GAP) == ETH_INTERFRAMEGAP_40BIT))
92 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
93 ((CMD) == ETH_CARRIERSENCE_DISABLE))
94 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
95 ((CMD) == ETH_RECEIVEOWN_DISABLE))
96 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
97 ((CMD) == ETH_LOOPBACKMODE_DISABLE))
98 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
99 ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
100 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
101 ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
102 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
103 ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
104 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
105 ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
106 ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
107 ((LIMIT) == ETH_BACKOFFLIMIT_1))
108 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
109 ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
110 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
111 ((CMD) == ETH_RECEIVEAll_DISABLE))
112 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
113 ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
114 ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
115 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
116 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
117 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
118 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
119 ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
120 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
121 ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
122 #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
123 ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
124 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
125 ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
126 ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
127 ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
128 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
129 ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
130 ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
131 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
132 #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
133 ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
134 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
135 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
136 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
137 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
138 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
139 ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
140 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
141 ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
142 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
143 ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
144 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
145 ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
146 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
147 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
148 ((ADDRESS) == ETH_MAC_ADDRESS1) || \
149 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
150 ((ADDRESS) == ETH_MAC_ADDRESS3))
151 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
152 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
153 ((ADDRESS) == ETH_MAC_ADDRESS3))
154 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
155 ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
156 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
157 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
158 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
159 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
160 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
161 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
162 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
163 ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
164 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
165 ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
166 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
167 ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
168 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
169 ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
170 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
171 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
172 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
173 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
174 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
175 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
176 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
177 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
178 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
179 ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
180 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
181 ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
182 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
183 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
184 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
185 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
186 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
187 ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
188 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
189 ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
190 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
191 ((CMD) == ETH_FIXEDBURST_DISABLE))
192 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
193 ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
194 ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
195 ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
196 ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
197 ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
198 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
199 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
200 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
201 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
202 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
203 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
204 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
205 ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
206 ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
207 ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
208 ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
209 ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
210 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
211 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
212 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
213 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
214 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
215 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
216 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
217 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
218 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
219 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
220 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
221 ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
222
223 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
224 ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
225 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
226 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
227 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
228 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
229 #define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
230
231 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
232 ((BUFFER) == ETH_DMARXDESC_BUFFER2))
233
234 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
235 ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
236
237 /**
238 * @}
239 */
240
241 /** @addtogroup ETH_Private_Constants
242 * @{
243 */
244 /* Delay to wait when writing to some Ethernet registers */
245 #define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
246
247 /* ETHERNET Errors */
248 #define ETH_SUCCESS ((uint32_t)0)
249 #define ETH_ERROR ((uint32_t)1)
250
251 /* ETHERNET DMA Tx descriptors Collision Count Shift */
252 #define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
253
254 /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
255 #define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
256
257 /* ETHERNET DMA Rx descriptors Frame Length Shift */
258 #define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
259
260 /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
261 #define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
262
263 /* ETHERNET DMA Rx descriptors Frame length Shift */
264 #define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
265
266 /* ETHERNET MAC address offsets */
267 #define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
268 #define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
269
270 /* ETHERNET MACMIIAR register Mask */
271 #define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
272
273 /* ETHERNET MACCR register Mask */
274 #define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
275
276 /* ETHERNET MACFCR register Mask */
277 #define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
278
279 /* ETHERNET DMAOMR register Mask */
280 #define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
281
282 /* ETHERNET Remote Wake-up frame register length */
283 #define ETH_WAKEUP_REGISTER_LENGTH 8
284
285 /* ETHERNET Missed frames counter Shift */
286 #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
287 /**
288 * @}
289 */
290
291 /* Exported types ------------------------------------------------------------*/
292 /** @defgroup ETH_Exported_Types ETH Exported Types
293 * @{
294 */
295
296 /**
297 * @brief HAL State structures definition
298 */
299 typedef enum
300 {
301 HAL_ETH_STATE_RESET = 0x00, /*!< Peripheral not yet Initialized or disabled */
302 HAL_ETH_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
303 HAL_ETH_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
304 HAL_ETH_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
305 HAL_ETH_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
306 HAL_ETH_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
307 HAL_ETH_STATE_BUSY_WR = 0x42, /*!< Write process is ongoing */
308 HAL_ETH_STATE_BUSY_RD = 0x82, /*!< Read process is ongoing */
309 HAL_ETH_STATE_TIMEOUT = 0x03, /*!< Timeout state */
310 HAL_ETH_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
311 }HAL_ETH_StateTypeDef;
312
313 /**
314 * @brief ETH Init Structure definition
315 */
316
317 typedef struct
318 {
319 uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
320 The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
321 and the mode (half/full-duplex).
322 This parameter can be a value of @ref ETH_AutoNegotiation */
323
324 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
325 This parameter can be a value of @ref ETH_Speed */
326
327 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
328 This parameter can be a value of @ref ETH_Duplex_Mode */
329
330 uint16_t PhyAddress; /*!< Ethernet PHY address.
331 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
332
333 uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
334
335 uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
336 This parameter can be a value of @ref ETH_Rx_Mode */
337
338 uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
339 This parameter can be a value of @ref ETH_Checksum_Mode */
340
341 uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.
342 This parameter can be a value of @ref ETH_Media_Interface */
343
344 } ETH_InitTypeDef;
345
346
347 /**
348 * @brief ETH MAC Configuration Structure definition
349 */
350
351 typedef struct
352 {
353 uint32_t Watchdog; /*!< Selects or not the Watchdog timer
354 When enabled, the MAC allows no more then 2048 bytes to be received.
355 When disabled, the MAC can receive up to 16384 bytes.
356 This parameter can be a value of @ref ETH_Watchdog */
357
358 uint32_t Jabber; /*!< Selects or not Jabber timer
359 When enabled, the MAC allows no more then 2048 bytes to be sent.
360 When disabled, the MAC can send up to 16384 bytes.
361 This parameter can be a value of @ref ETH_Jabber */
362
363 uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
364 This parameter can be a value of @ref ETH_Inter_Frame_Gap */
365
366 uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
367 This parameter can be a value of @ref ETH_Carrier_Sense */
368
369 uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
370 ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
371 in Half-Duplex mode.
372 This parameter can be a value of @ref ETH_Receive_Own */
373
374 uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
375 This parameter can be a value of @ref ETH_Loop_Back_Mode */
376
377 uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
378 This parameter can be a value of @ref ETH_Checksum_Offload */
379
380 uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
381 when a collision occurs (Half-Duplex mode).
382 This parameter can be a value of @ref ETH_Retry_Transmission */
383
384 uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
385 This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
386
387 uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
388 This parameter can be a value of @ref ETH_Back_Off_Limit */
389
390 uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
391 This parameter can be a value of @ref ETH_Deferral_Check */
392
393 uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
394 This parameter can be a value of @ref ETH_Receive_All */
395
396 uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
397 This parameter can be a value of @ref ETH_Source_Addr_Filter */
398
399 uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
400 This parameter can be a value of @ref ETH_Pass_Control_Frames */
401
402 uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
403 This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
404
405 uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
406 This parameter can be a value of @ref ETH_Destination_Addr_Filter */
407
408 uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
409 This parameter can be a value of @ref ETH_Promiscuous_Mode */
410
411 uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
412 This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
413
414 uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
415 This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
416
417 uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
418 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
419
420 uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
421 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
422
423 uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
424 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
425
426 uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
427 This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
428
429 uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
430 automatic retransmission of PAUSE Frame.
431 This parameter can be a value of @ref ETH_Pause_Low_Threshold */
432
433 uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
434 unicast address and unique multicast address).
435 This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
436
437 uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
438 disable its transmitter for a specified time (Pause Time)
439 This parameter can be a value of @ref ETH_Receive_Flow_Control */
440
441 uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
442 or the MAC back-pressure operation (Half-Duplex mode)
443 This parameter can be a value of @ref ETH_Transmit_Flow_Control */
444
445 uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
446 comparison and filtering.
447 This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
448
449 uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
450
451 } ETH_MACInitTypeDef;
452
453
454 /**
455 * @brief ETH DMA Configuration Structure definition
456 */
457
458 typedef struct
459 {
460 uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
461 This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
462
463 uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
464 This parameter can be a value of @ref ETH_Receive_Store_Forward */
465
466 uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
467 This parameter can be a value of @ref ETH_Flush_Received_Frame */
468
469 uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
470 This parameter can be a value of @ref ETH_Transmit_Store_Forward */
471
472 uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
473 This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
474
475 uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
476 This parameter can be a value of @ref ETH_Forward_Error_Frames */
477
478 uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
479 and length less than 64 bytes) including pad-bytes and CRC)
480 This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
481
482 uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
483 This parameter can be a value of @ref ETH_Receive_Threshold_Control */
484
485 uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
486 frame of Transmit data even before obtaining the status for the first frame.
487 This parameter can be a value of @ref ETH_Second_Frame_Operate */
488
489 uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
490 This parameter can be a value of @ref ETH_Address_Aligned_Beats */
491
492 uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
493 This parameter can be a value of @ref ETH_Fixed_Burst */
494
495 uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
496 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
497
498 uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
499 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
500
501 uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
502 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
503
504 uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
505 This parameter can be a value of @ref ETH_DMA_Arbitration */
506 } ETH_DMAInitTypeDef;
507
508
509 /**
510 * @brief ETH DMA Descriptors data structure definition
511 */
512
513 typedef struct
514 {
515 __IO uint32_t Status; /*!< Status */
516
517 uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
518
519 uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
520
521 uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
522
523 } ETH_DMADescTypeDef;
524
525
526 /**
527 * @brief Received Frame Informations structure definition
528 */
529 typedef struct
530 {
531 ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */
532
533 ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */
534
535 uint32_t SegCount; /*!< Segment count */
536
537 uint32_t length; /*!< Frame length */
538
539 uint32_t buffer; /*!< Frame buffer */
540
541 } ETH_DMARxFrameInfos;
542
543
544 /**
545 * @brief ETH Handle Structure definition
546 */
547
548 typedef struct
549 {
550 ETH_TypeDef *Instance; /*!< Register base address */
551
552 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */
553
554 uint32_t LinkStatus; /*!< Ethernet link status */
555
556 ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */
557
558 ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */
559
560 ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */
561
562 __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */
563
564 HAL_LockTypeDef Lock; /*!< ETH Lock */
565
566 } ETH_HandleTypeDef;
567
568 /**
569 * @}
570 */
571
572 /* Exported constants --------------------------------------------------------*/
573 /** @defgroup ETH_Exported_Constants ETH Exported Constants
574 * @{
575 */
576
577 /** @defgroup ETH_Buffers_setting ETH Buffers setting
578 * @{
579 */
580 #define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
581 #define ETH_HEADER ((uint32_t)14) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
582 #define ETH_CRC ((uint32_t)4) /*!< Ethernet CRC */
583 #define ETH_EXTRA ((uint32_t)2) /*!< Extra bytes in some cases */
584 #define ETH_VLAN_TAG ((uint32_t)4) /*!< optional 802.1q VLAN Tag */
585 #define ETH_MIN_ETH_PAYLOAD ((uint32_t)46) /*!< Minimum Ethernet payload size */
586 #define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500) /*!< Maximum Ethernet payload size */
587 #define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /*!< Jumbo frame payload size */
588
589 /* Ethernet driver receive buffers are organized in a chained linked-list, when
590 an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
591 to the driver receive buffers memory.
592
593 Depending on the size of the received ethernet packet and the size of
594 each ethernet driver receive buffer, the received packet can take one or more
595 ethernet driver receive buffer.
596
597 In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
598 and the total count of the driver receive buffers ETH_RXBUFNB.
599
600 The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
601 example, they can be reconfigured in the application layer to fit the application
602 needs */
603
604 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
605 packet */
606 #ifndef ETH_RX_BUF_SIZE
607 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
608 #endif
609
610 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
611 #ifndef ETH_RXBUFNB
612 #define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
613 #endif
614
615
616 /* Ethernet driver transmit buffers are organized in a chained linked-list, when
617 an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
618 driver transmit buffers memory to the TxFIFO.
619
620 Depending on the size of the Ethernet packet to be transmitted and the size of
621 each ethernet driver transmit buffer, the packet to be transmitted can take
622 one or more ethernet driver transmit buffer.
623
624 In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
625 and the total count of the driver transmit buffers ETH_TXBUFNB.
626
627 The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
628 example, they can be reconfigured in the application layer to fit the application
629 needs */
630
631 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
632 packet */
633 #ifndef ETH_TX_BUF_SIZE
634 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
635 #endif
636
637 /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
638 #ifndef ETH_TXBUFNB
639 #define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
640 #endif
641
642 /**
643 * @}
644 */
645
646 /** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
647 * @{
648 */
649
650 /*
651 DMA Tx Desciptor
652 -----------------------------------------------------------------------------------------------
653 TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
654 -----------------------------------------------------------------------------------------------
655 TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
656 -----------------------------------------------------------------------------------------------
657 TDES2 | Buffer1 Address [31:0] |
658 -----------------------------------------------------------------------------------------------
659 TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
660 -----------------------------------------------------------------------------------------------
661 */
662
663 /**
664 * @brief Bit definition of TDES0 register: DMA Tx descriptor status register
665 */
666 #define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
667 #define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */
668 #define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /*!< Last Segment */
669 #define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /*!< First Segment */
670 #define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /*!< Disable CRC */
671 #define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /*!< Disable Padding */
672 #define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */
673 #define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */
674 #define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */
675 #define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */
676 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
677 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
678 #define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */
679 #define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */
680 #define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */
681 #define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /*!< IP Header Error */
682 #define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
683 #define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */
684 #define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
685 #define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */
686 #define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during transmission */
687 #define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the transceiver */
688 #define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */
689 #define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */
690 #define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /*!< VLAN Frame */
691 #define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /*!< Collision Count */
692 #define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */
693 #define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */
694 #define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /*!< Deferred Bit */
695
696 /**
697 * @brief Bit definition of TDES1 register
698 */
699 #define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */
700 #define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */
701
702 /**
703 * @brief Bit definition of TDES2 register
704 */
705 #define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
706
707 /**
708 * @brief Bit definition of TDES3 register
709 */
710 #define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
711
712 /**
713 * @}
714 */
715 /** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
716 * @{
717 */
718
719 /*
720 DMA Rx Descriptor
721 --------------------------------------------------------------------------------------------------------------------
722 RDES0 | OWN(31) | Status [30:0] |
723 ---------------------------------------------------------------------------------------------------------------------
724 RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
725 ---------------------------------------------------------------------------------------------------------------------
726 RDES2 | Buffer1 Address [31:0] |
727 ---------------------------------------------------------------------------------------------------------------------
728 RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
729 ---------------------------------------------------------------------------------------------------------------------
730 */
731
732 /**
733 * @brief Bit definition of RDES0 register: DMA Rx descriptor status register
734 */
735 #define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
736 #define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */
737 #define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */
738 #define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
739 #define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /*!< Descriptor error: no more descriptors for receive frame */
740 #define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */
741 #define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */
742 #define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */
743 #define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */
744 #define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */
745 #define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */
746 #define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
747 #define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */
748 #define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */
749 #define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
750 #define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */
751 #define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */
752 #define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /*!< CRC error */
753 #define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
754
755 /**
756 * @brief Bit definition of RDES1 register
757 */
758 #define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */
759 #define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */
760 #define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */
761 #define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */
762 #define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */
763
764 /**
765 * @brief Bit definition of RDES2 register
766 */
767 #define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
768
769 /**
770 * @brief Bit definition of RDES3 register
771 */
772 #define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
773
774 /**
775 * @}
776 */
777 /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
778 * @{
779 */
780 #define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)
781 #define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)
782
783 /**
784 * @}
785 */
786 /** @defgroup ETH_Speed ETH Speed
787 * @{
788 */
789 #define ETH_SPEED_10M ((uint32_t)0x00000000)
790 #define ETH_SPEED_100M ((uint32_t)0x00004000)
791
792 /**
793 * @}
794 */
795 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode
796 * @{
797 */
798 #define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)
799 #define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)
800 /**
801 * @}
802 */
803 /** @defgroup ETH_Rx_Mode ETH Rx Mode
804 * @{
805 */
806 #define ETH_RXPOLLING_MODE ((uint32_t)0x00000000)
807 #define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)
808 /**
809 * @}
810 */
811
812 /** @defgroup ETH_Checksum_Mode ETH Checksum Mode
813 * @{
814 */
815 #define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)
816 #define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)
817 /**
818 * @}
819 */
820
821 /** @defgroup ETH_Media_Interface ETH Media Interface
822 * @{
823 */
824 #define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)
825 #define ETH_MEDIA_INTERFACE_RMII ((uint32_t)AFIO_MAPR_MII_RMII_SEL)
826
827 /**
828 * @}
829 */
830
831 /** @defgroup ETH_Watchdog ETH Watchdog
832 * @{
833 */
834 #define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)
835 #define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)
836
837 /**
838 * @}
839 */
840
841 /** @defgroup ETH_Jabber ETH Jabber
842 * @{
843 */
844 #define ETH_JABBER_ENABLE ((uint32_t)0x00000000)
845 #define ETH_JABBER_DISABLE ((uint32_t)0x00400000)
846
847 /**
848 * @}
849 */
850
851 /** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
852 * @{
853 */
854 #define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */
855 #define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */
856 #define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */
857 #define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */
858 #define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */
859 #define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */
860 #define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */
861 #define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */
862
863 /**
864 * @}
865 */
866
867 /** @defgroup ETH_Carrier_Sense ETH Carrier Sense
868 * @{
869 */
870 #define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)
871 #define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
872
873 /**
874 * @}
875 */
876
877 /** @defgroup ETH_Receive_Own ETH Receive Own
878 * @{
879 */
880 #define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)
881 #define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
882
883 /**
884 * @}
885 */
886
887 /** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
888 * @{
889 */
890 #define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)
891 #define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)
892
893 /**
894 * @}
895 */
896
897 /** @defgroup ETH_Checksum_Offload ETH Checksum Offload
898 * @{
899 */
900 #define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)
901 #define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)
902
903 /**
904 * @}
905 */
906
907 /** @defgroup ETH_Retry_Transmission ETH Retry Transmission
908 * @{
909 */
910 #define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)
911 #define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)
912
913 /**
914 * @}
915 */
916
917 /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
918 * @{
919 */
920 #define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)
921 #define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)
922
923 /**
924 * @}
925 */
926
927 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
928 * @{
929 */
930 #define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)
931 #define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)
932 #define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)
933 #define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)
934
935 /**
936 * @}
937 */
938
939 /** @defgroup ETH_Deferral_Check ETH Deferral Check
940 * @{
941 */
942 #define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)
943 #define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)
944
945 /**
946 * @}
947 */
948
949 /** @defgroup ETH_Receive_All ETH Receive All
950 * @{
951 */
952 #define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)
953 #define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)
954
955 /**
956 * @}
957 */
958
959 /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
960 * @{
961 */
962 #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)
963 #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)
964 #define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)
965
966 /**
967 * @}
968 */
969
970 /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
971 * @{
972 */
973 #define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */
974 #define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */
975 #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */
976
977 /**
978 * @}
979 */
980
981 /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
982 * @{
983 */
984 #define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)
985 #define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)
986
987 /**
988 * @}
989 */
990
991 /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
992 * @{
993 */
994 #define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)
995 #define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)
996
997 /**
998 * @}
999 */
1000
1001 /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
1002 * @{
1003 */
1004 #define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001)
1005 #define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000)
1006
1007 /**
1008 * @}
1009 */
1010
1011 /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
1012 * @{
1013 */
1014 #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)
1015 #define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)
1016 #define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
1017 #define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)
1018
1019 /**
1020 * @}
1021 */
1022
1023 /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
1024 * @{
1025 */
1026 #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
1027 #define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)
1028 #define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
1029
1030 /**
1031 * @}
1032 */
1033
1034 /** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
1035 * @{
1036 */
1037 #define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
1038 #define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)
1039
1040 /**
1041 * @}
1042 */
1043
1044 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
1045 * @{
1046 */
1047 #define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */
1048 #define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */
1049 #define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */
1050 #define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */
1051
1052 /**
1053 * @}
1054 */
1055
1056 /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
1057 * @{
1058 */
1059 #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)
1060 #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
1061
1062 /**
1063 * @}
1064 */
1065
1066 /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
1067 * @{
1068 */
1069 #define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)
1070 #define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
1071
1072 /**
1073 * @}
1074 */
1075
1076 /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
1077 * @{
1078 */
1079 #define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)
1080 #define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
1081
1082 /**
1083 * @}
1084 */
1085
1086 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
1087 * @{
1088 */
1089 #define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)
1090 #define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)
1091
1092 /**
1093 * @}
1094 */
1095
1096 /** @defgroup ETH_MAC_addresses ETH MAC addresses
1097 * @{
1098 */
1099 #define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)
1100 #define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)
1101 #define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)
1102 #define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)
1103
1104 /**
1105 * @}
1106 */
1107
1108 /** @defgroup ETH_MAC_Addresses_Filter_SA_DA ETH MAC Addresses Filter SA DA
1109 * @{
1110 */
1111 #define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)
1112 #define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)
1113 /**
1114 * @}
1115 */
1116
1117 /** @defgroup ETH_MAC_Addresses_Filter_Mask_Bytes ETH_MAC Addresses Filter Mask Bytes
1118 * @{
1119 */
1120 #define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */
1121 #define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */
1122 #define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */
1123 #define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */
1124 #define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */
1125 #define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */
1126
1127 /**
1128 * @}
1129 */
1130
1131 /** @defgroup ETH_MAC_Debug_Flags ETH MAC Debug Flags
1132 * @{
1133 */
1134 #define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
1135 #define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
1136 #define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
1137 #define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
1138 #define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
1139 #define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
1140 #define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
1141 #define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
1142 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
1143 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
1144 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
1145 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
1146 #define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
1147 #define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
1148 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
1149 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
1150 #define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
1151 #define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000060) /* Rx FIFO read controller IDLE state */
1152 #define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame data */
1153 #define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame status (or time-stamp) */
1154 #define ETH_MAC_READCONTROLLER_ FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
1155 #define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
1156 #define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
1157 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
1158 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
1159 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
1160 #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
1161
1162 /**
1163 * @}
1164 */
1165
1166 /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
1167 * @{
1168 */
1169 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)
1170 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)
1171
1172 /**
1173 * @}
1174 */
1175
1176 /** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
1177 * @{
1178 */
1179 #define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)
1180 #define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)
1181
1182 /**
1183 * @}
1184 */
1185
1186 /** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
1187 * @{
1188 */
1189 #define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)
1190 #define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)
1191
1192 /**
1193 * @}
1194 */
1195
1196 /** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
1197 * @{
1198 */
1199 #define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)
1200 #define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)
1201
1202 /**
1203 * @}
1204 */
1205
1206 /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
1207 * @{
1208 */
1209 #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
1210 #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
1211 #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
1212 #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
1213 #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
1214 #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
1215 #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
1216 #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
1217
1218 /**
1219 * @}
1220 */
1221
1222 /** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
1223 * @{
1224 */
1225 #define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)
1226 #define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)
1227
1228 /**
1229 * @}
1230 */
1231
1232 /** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
1233 * @{
1234 */
1235 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)
1236 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)
1237
1238 /**
1239 * @}
1240 */
1241
1242 /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
1243 * @{
1244 */
1245 #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
1246 #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
1247 #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
1248 #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
1249
1250 /**
1251 * @}
1252 */
1253
1254 /** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
1255 * @{
1256 */
1257 #define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)
1258 #define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)
1259
1260 /**
1261 * @}
1262 */
1263
1264 /** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
1265 * @{
1266 */
1267 #define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)
1268 #define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)
1269
1270 /**
1271 * @}
1272 */
1273
1274 /** @defgroup ETH_Fixed_Burst ETH Fixed Burst
1275 * @{
1276 */
1277 #define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)
1278 #define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)
1279
1280 /**
1281 * @}
1282 */
1283
1284 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA_Burst Length
1285 * @{
1286 */
1287 #define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
1288 #define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
1289 #define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
1290 #define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
1291 #define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
1292 #define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
1293 #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
1294 #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
1295 #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
1296 #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
1297 #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
1298 #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
1299
1300 /**
1301 * @}
1302 */
1303
1304 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
1305 * @{
1306 */
1307 #define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
1308 #define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
1309 #define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
1310 #define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
1311 #define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
1312 #define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
1313 #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
1314 #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
1315 #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
1316 #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
1317 #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
1318 #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
1319
1320 /**
1321 * @}
1322 */
1323
1324 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
1325 * @{
1326 */
1327 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
1328 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)
1329 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
1330 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
1331 #define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)
1332
1333 /**
1334 * @}
1335 */
1336
1337 /** @defgroup ETH_DMA_Tx_Descriptor_Segment ETH DMA Tx Descriptor Segment
1338 * @{
1339 */
1340 #define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /*!< Last Segment */
1341 #define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /*!< First Segment */
1342
1343 /**
1344 * @}
1345 */
1346
1347 /** @defgroup ETH_DMA_Tx_Descriptor_Checksum_Insertion_Control ETH DMA Tx Descriptor Checksum Insertion Control
1348 * @{
1349 */
1350 #define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /*!< Checksum engine bypass */
1351 #define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */
1352 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
1353 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
1354
1355 /**
1356 * @}
1357 */
1358
1359 /** @defgroup ETH_DMA_Rx_Descriptor_Buffers ETH DMA Rx Descriptor Buffers
1360 * @{
1361 */
1362 #define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */
1363 #define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */
1364
1365 /**
1366 * @}
1367 */
1368
1369 /** @defgroup ETH_PMT_Flags ETH PMT Flags
1370 * @{
1371 */
1372 #define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Pointer Reset */
1373 #define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */
1374 #define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */
1375
1376 /**
1377 * @}
1378 */
1379
1380 /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
1381 * @{
1382 */
1383 #define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */
1384 #define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */
1385 #define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */
1386
1387 /**
1388 * @}
1389 */
1390
1391 /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
1392 * @{
1393 */
1394 #define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */
1395 #define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */
1396 #define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */
1397
1398 /**
1399 * @}
1400 */
1401
1402 /** @defgroup ETH_MAC_Flags ETH MAC Flags
1403 * @{
1404 */
1405 #define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */
1406 #define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */
1407 #define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */
1408 #define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */
1409 #define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */
1410
1411 /**
1412 * @}
1413 */
1414
1415 /** @defgroup ETH_DMA_Flags ETH DMA Flags
1416 * @{
1417 */
1418 #define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
1419 #define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
1420 #define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
1421 #define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */
1422 #define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /*!< Error bits 0-write trnsf, 1-read transfr */
1423 #define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */
1424 #define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */
1425 #define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */
1426 #define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */
1427 #define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */
1428 #define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */
1429 #define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */
1430 #define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */
1431 #define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */
1432 #define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */
1433 #define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */
1434 #define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */
1435 #define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */
1436 #define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */
1437 #define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */
1438 #define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */
1439
1440 /**
1441 * @}
1442 */
1443
1444 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
1445 * @{
1446 */
1447 #define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */
1448 #define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */
1449 #define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */
1450 #define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */
1451 #define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */
1452
1453 /**
1454 * @}
1455 */
1456
1457 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
1458 * @{
1459 */
1460 #define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
1461 #define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
1462 #define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
1463 #define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */
1464 #define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */
1465 #define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */
1466 #define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */
1467 #define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */
1468 #define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */
1469 #define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */
1470 #define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */
1471 #define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */
1472 #define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */
1473 #define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */
1474 #define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */
1475 #define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */
1476 #define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */
1477 #define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */
1478
1479 /**
1480 * @}
1481 */
1482
1483 /** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
1484 * @{
1485 */
1486 #define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */
1487 #define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */
1488 #define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /*!< Running - waiting for status */
1489 #define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */
1490 #define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /*!< Suspended - Tx Descriptor unavailable */
1491 #define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */
1492
1493 /**
1494 * @}
1495 */
1496
1497
1498 /** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
1499 * @{
1500 */
1501 #define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */
1502 #define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */
1503 #define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /*!< Running - waiting for packet */
1504 #define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /*!< Suspended - Rx Descriptor unavailable */
1505 #define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /*!< Running - closing descriptor */
1506 #define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /*!< Running - queuing the receive frame into host memory */
1507
1508 /**
1509 * @}
1510 */
1511
1512 /** @defgroup ETH_DMA_overflow ETH DMA overflow
1513 * @{
1514 */
1515 #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */
1516 #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */
1517
1518 /**
1519 * @}
1520 */
1521
1522 /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
1523 * @{
1524 */
1525 #define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the ETH EXTI Line */
1526
1527 /**
1528 * @}
1529 */
1530
1531 /**
1532 * @}
1533 */
1534
1535 /* Exported macro ------------------------------------------------------------*/
1536 /** @defgroup ETH_Exported_Macros ETH Exported Macros
1537 * @brief macros to handle interrupts and specific clock configurations
1538 * @{
1539 */
1540
1541 /** @brief Reset ETH handle state
1542 * @param __HANDLE__: specifies the ETH handle.
1543 * @retval None
1544 */
1545 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
1546
1547 /**
1548 * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
1549 * @param __HANDLE__: ETH Handle
1550 * @param __FLAG__: specifies the flag of TDES0 to check .
1551 * @retval the ETH_DMATxDescFlag (SET or RESET).
1552 */
1553 #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
1554
1555 /**
1556 * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
1557 * @param __HANDLE__: ETH Handle
1558 * @param __FLAG__: specifies the flag of RDES0 to check.
1559 * @retval the ETH_DMATxDescFlag (SET or RESET).
1560 */
1561 #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
1562
1563 /**
1564 * @brief Enables the specified DMA Rx Desc receive interrupt.
1565 * @param __HANDLE__: ETH Handle
1566 * @retval None
1567 */
1568 #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
1569
1570 /**
1571 * @brief Disables the specified DMA Rx Desc receive interrupt.
1572 * @param __HANDLE__: ETH Handle
1573 * @retval None
1574 */
1575 #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
1576
1577 /**
1578 * @brief Set the specified DMA Rx Desc Own bit.
1579 * @param __HANDLE__: ETH Handle
1580 * @retval None
1581 */
1582 #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
1583
1584 /**
1585 * @brief Returns the specified ETHERNET DMA Tx Desc collision count.
1586 * @param __HANDLE__: ETH Handle
1587 * @retval The Transmit descriptor collision counter value.
1588 */
1589 #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
1590
1591 /**
1592 * @brief Set the specified DMA Tx Desc Own bit.
1593 * @param __HANDLE__: ETH Handle
1594 * @retval None
1595 */
1596 #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
1597
1598 /**
1599 * @brief Enables the specified DMA Tx Desc Transmit interrupt.
1600 * @param __HANDLE__: ETH Handle
1601 * @retval None
1602 */
1603 #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
1604
1605 /**
1606 * @brief Disables the specified DMA Tx Desc Transmit interrupt.
1607 * @param __HANDLE__: ETH Handle
1608 * @retval None
1609 */
1610 #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
1611
1612 /**
1613 * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
1614 * @param __HANDLE__: ETH Handle
1615 * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
1616 * This parameter can be one of the following values:
1617 * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
1618 * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
1619 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
1620 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
1621 * @retval None
1622 */
1623 #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
1624
1625 /**
1626 * @brief Enables the DMA Tx Desc CRC.
1627 * @param __HANDLE__: ETH Handle
1628 * @retval None
1629 */
1630 #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
1631
1632 /**
1633 * @brief Disables the DMA Tx Desc CRC.
1634 * @param __HANDLE__: ETH Handle
1635 * @retval None
1636 */
1637 #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
1638
1639 /**
1640 * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
1641 * @param __HANDLE__: ETH Handle
1642 * @retval None
1643 */
1644 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
1645
1646 /**
1647 * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
1648 * @param __HANDLE__: ETH Handle
1649 * @retval None
1650 */
1651 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
1652
1653 /**
1654 * @brief Enables the specified ETHERNET MAC interrupts.
1655 * @param __HANDLE__ : ETH Handle
1656 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
1657 * enabled or disabled.
1658 * This parameter can be any combination of the following values:
1659 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
1660 * @arg ETH_MAC_IT_PMT : PMT interrupt
1661 * @retval None
1662 */
1663 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
1664
1665 /**
1666 * @brief Disables the specified ETHERNET MAC interrupts.
1667 * @param __HANDLE__ : ETH Handle
1668 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
1669 * enabled or disabled.
1670 * This parameter can be any combination of the following values:
1671 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
1672 * @arg ETH_MAC_IT_PMT : PMT interrupt
1673 * @retval None
1674 */
1675 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
1676
1677 /**
1678 * @brief Initiate a Pause Control Frame (Full-duplex only).
1679 * @param __HANDLE__: ETH Handle
1680 * @retval None
1681 */
1682 #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
1683
1684 /**
1685 * @brief Checks whether the ETHERNET flow control busy bit is set or not.
1686 * @param __HANDLE__: ETH Handle
1687 * @retval The new state of flow control busy status bit (SET or RESET).
1688 */
1689 #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
1690
1691 /**
1692 * @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
1693 * @param __HANDLE__: ETH Handle
1694 * @retval None
1695 */
1696 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
1697
1698 /**
1699 * @brief Disables the MAC BackPressure operation activation (Half-duplex only).
1700 * @param __HANDLE__: ETH Handle
1701 * @retval None
1702 */
1703 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
1704
1705 /**
1706 * @brief Checks whether the specified ETHERNET MAC flag is set or not.
1707 * @param __HANDLE__: ETH Handle
1708 * @param __FLAG__: specifies the flag to check.
1709 * This parameter can be one of the following values:
1710 * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
1711 * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
1712 * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
1713 * @arg ETH_MAC_FLAG_MMC : MMC flag
1714 * @arg ETH_MAC_FLAG_PMT : PMT flag
1715 * @retval The state of ETHERNET MAC flag.
1716 */
1717 #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
1718
1719 /**
1720 * @brief Enables the specified ETHERNET DMA interrupts.
1721 * @param __HANDLE__ : ETH Handle
1722 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
1723 * enabled @ref ETH_DMA_Interrupts
1724 * @retval None
1725 */
1726 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
1727
1728 /**
1729 * @brief Disables the specified ETHERNET DMA interrupts.
1730 * @param __HANDLE__ : ETH Handle
1731 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
1732 * disabled. @ref ETH_DMA_Interrupts
1733 * @retval None
1734 */
1735 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
1736
1737 /**
1738 * @brief Clears the ETHERNET DMA IT pending bit.
1739 * @param __HANDLE__ : ETH Handle
1740 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
1741 * @retval None
1742 */
1743 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
1744
1745 /**
1746 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
1747 * @param __HANDLE__: ETH Handle
1748 * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
1749 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
1750 */
1751 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
1752
1753 /**
1754 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
1755 * @param __HANDLE__: ETH Handle
1756 * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
1757 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
1758 */
1759 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
1760
1761 /**
1762 * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
1763 * @param __HANDLE__: ETH Handle
1764 * @param __OVERFLOW__: specifies the DMA overflow flag to check.
1765 * This parameter can be one of the following values:
1766 * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
1767 * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
1768 * @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
1769 */
1770 #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
1771
1772 /**
1773 * @brief Set the DMA Receive status watchdog timer register value
1774 * @param __HANDLE__: ETH Handle
1775 * @param __VALUE__: DMA Receive status watchdog timer register value
1776 * @retval None
1777 */
1778 #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
1779
1780 /**
1781 * @brief Enables any unicast packet filtered by the MAC address
1782 * recognition to be a wake-up frame.
1783 * @param __HANDLE__: ETH Handle.
1784 * @retval None
1785 */
1786 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
1787
1788 /**
1789 * @brief Disables any unicast packet filtered by the MAC address
1790 * recognition to be a wake-up frame.
1791 * @param __HANDLE__: ETH Handle.
1792 * @retval None
1793 */
1794 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
1795
1796 /**
1797 * @brief Enables the MAC Wake-Up Frame Detection.
1798 * @param __HANDLE__: ETH Handle.
1799 * @retval None
1800 */
1801 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
1802
1803 /**
1804 * @brief Disables the MAC Wake-Up Frame Detection.
1805 * @param __HANDLE__: ETH Handle.
1806 * @retval None
1807 */
1808 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
1809
1810 /**
1811 * @brief Enables the MAC Magic Packet Detection.
1812 * @param __HANDLE__: ETH Handle.
1813 * @retval None
1814 */
1815 #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
1816
1817 /**
1818 * @brief Disables the MAC Magic Packet Detection.
1819 * @param __HANDLE__: ETH Handle.
1820 * @retval None
1821 */
1822 #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
1823
1824 /**
1825 * @brief Enables the MAC Power Down.
1826 * @param __HANDLE__: ETH Handle
1827 * @retval None
1828 */
1829 #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
1830
1831 /**
1832 * @brief Disables the MAC Power Down.
1833 * @param __HANDLE__: ETH Handle
1834 * @retval None
1835 */
1836 #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
1837
1838 /**
1839 * @brief Checks whether the specified ETHERNET PMT flag is set or not.
1840 * @param __HANDLE__: ETH Handle.
1841 * @param __FLAG__: specifies the flag to check.
1842 * This parameter can be one of the following values:
1843 * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
1844 * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
1845 * @arg ETH_PMT_FLAG_MPR : Magic Packet Received
1846 * @retval The new state of ETHERNET PMT Flag (SET or RESET).
1847 */
1848 #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
1849
1850 /**
1851 * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
1852 * @param __HANDLE__: ETH Handle.
1853 * @retval None
1854 */
1855 #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
1856
1857 /**
1858 * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
1859 * @param __HANDLE__: ETH Handle.
1860 * @retval None
1861 */
1862 #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
1863 (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)
1864
1865 /**
1866 * @brief Enables the MMC Counter Freeze.
1867 * @param __HANDLE__: ETH Handle.
1868 * @retval None
1869 */
1870 #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
1871
1872 /**
1873 * @brief Disables the MMC Counter Freeze.
1874 * @param __HANDLE__: ETH Handle.
1875 * @retval None
1876 */
1877 #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
1878
1879 /**
1880 * @brief Enables the MMC Reset On Read.
1881 * @param __HANDLE__: ETH Handle.
1882 * @retval None
1883 */
1884 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
1885
1886 /**
1887 * @brief Disables the MMC Reset On Read.
1888 * @param __HANDLE__: ETH Handle.
1889 * @retval None
1890 */
1891 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
1892
1893 /**
1894 * @brief Enables the MMC Counter Stop Rollover.
1895 * @param __HANDLE__: ETH Handle.
1896 * @retval None
1897 */
1898 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
1899
1900 /**
1901 * @brief Disables the MMC Counter Stop Rollover.
1902 * @param __HANDLE__: ETH Handle.
1903 * @retval None
1904 */
1905 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
1906
1907 /**
1908 * @brief Resets the MMC Counters.
1909 * @param __HANDLE__: ETH Handle.
1910 * @retval None
1911 */
1912 #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
1913
1914 /**
1915 * @brief Enables the specified ETHERNET MMC Rx interrupts.
1916 * @param __HANDLE__: ETH Handle.
1917 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
1918 * This parameter can be one of the following values:
1919 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
1920 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
1921 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
1922 * @retval None
1923 */
1924 #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
1925 /**
1926 * @brief Disables the specified ETHERNET MMC Rx interrupts.
1927 * @param __HANDLE__: ETH Handle.
1928 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
1929 * This parameter can be one of the following values:
1930 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
1931 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
1932 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
1933 * @retval None
1934 */
1935 #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)
1936 /**
1937 * @brief Enables the specified ETHERNET MMC Tx interrupts.
1938 * @param __HANDLE__: ETH Handle.
1939 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
1940 * This parameter can be one of the following values:
1941 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
1942 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
1943 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
1944 * @retval None
1945 */
1946 #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
1947
1948 /**
1949 * @brief Disables the specified ETHERNET MMC Tx interrupts.
1950 * @param __HANDLE__: ETH Handle.
1951 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
1952 * This parameter can be one of the following values:
1953 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
1954 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
1955 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
1956 * @retval None
1957 */
1958 #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
1959
1960 /**
1961 * @brief Enables the ETH External interrupt line.
1962 * @retval None
1963 */
1964 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
1965
1966 /**
1967 * @brief Disables the ETH External interrupt line.
1968 * @retval None
1969 */
1970 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
1971
1972 /**
1973 * @brief Enable event on ETH External event line.
1974 * @retval None.
1975 */
1976 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
1977
1978 /**
1979 * @brief Disable event on ETH External event line
1980 * @retval None.
1981 */
1982 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
1983
1984 /**
1985 * @brief Get flag of the ETH External interrupt line.
1986 * @retval None
1987 */
1988 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
1989
1990 /**
1991 * @brief Clear flag of the ETH External interrupt line.
1992 * @retval None
1993 */
1994 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
1995
1996 /**
1997 * @brief Enables rising edge trigger to the ETH External interrupt line.
1998 * @retval None
1999 */
2000 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
2001
2002 /**
2003 * @brief Disables the rising edge trigger to the ETH External interrupt line.
2004 * @retval None
2005 */
2006 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
2007
2008 /**
2009 * @brief Enables falling edge trigger to the ETH External interrupt line.
2010 * @retval None
2011 */
2012 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
2013
2014 /**
2015 * @brief Disables falling edge trigger to the ETH External interrupt line.
2016 * @retval None
2017 */
2018 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
2019
2020
2021 /**
2022 * @brief Enables rising/falling edge trigger to the ETH External interrupt line.
2023 * @retval None
2024 */
2025 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
2026 EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP
2027
2028 /**
2029 * @brief Disables rising/falling edge trigger to the ETH External interrupt line.
2030 * @retval None
2031 */
2032 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
2033 EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
2034
2035 /**
2036 * @brief Generate a Software interrupt on selected EXTI line.
2037 * @retval None.
2038 */
2039 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
2040
2041 /**
2042 * @}
2043 */
2044
2045 /* Exported functions --------------------------------------------------------*/
2046
2047 /** @addtogroup ETH_Exported_Functions
2048 * @{
2049 */
2050
2051 /* Initialization and de-initialization functions ****************************/
2052
2053 /** @addtogroup ETH_Exported_Functions_Group1
2054 * @{
2055 */
2056
2057 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
2058 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
2059 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
2060 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
2061 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
2062 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
2063
2064 /**
2065 * @}
2066 */
2067
2068 /* IO operation functions ****************************************************/
2069
2070 /** @addtogroup ETH_Exported_Functions_Group2
2071 * @{
2072 */
2073 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
2074 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
2075 /* Communication with PHY functions*/
2076 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
2077 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
2078 /* Non-Blocking mode: Interrupt */
2079 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
2080 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
2081 /* Callback in non blocking modes (Interrupt) */
2082 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
2083 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
2084 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
2085
2086 /**
2087 * @}
2088 */
2089
2090 /* Peripheral Control functions **********************************************/
2091
2092 /** @addtogroup ETH_Exported_Functions_Group3
2093 * @{
2094 */
2095 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
2096 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
2097 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
2098 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
2099 /**
2100 * @}
2101 */
2102
2103 /* Peripheral State functions ************************************************/
2104
2105 /** @addtogroup ETH_Exported_Functions_Group4
2106 * @{
2107 */
2108 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
2109
2110 /**
2111 * @}
2112 */
2113
2114 /**
2115 * @}
2116 */
2117
2118 /**
2119 * @}
2120 */
2121
2122 #endif /* STM32F107xC */
2123 /**
2124 * @}
2125 */
2126
2127 #ifdef __cplusplus
2128 }
2129 #endif
2130
2131 #endif /* __STM32F1xx_HAL_ETH_H */
2132
2133
2134
2135 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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