tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_gpio.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f1xx_hal_gpio.c
   4   * @author  MCD Application Team
   5   * @version V1.0.0
   6   * @date    15-December-2014
   7   * @brief   GPIO HAL module driver.
   8   *         This file provides firmware functions to manage the following
   9   *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
  10   *           + Initialization and de-initialization functions
  11   *           + IO operation functions
  12   *
  13   @verbatim
  14   ==============================================================================
  15                     ##### GPIO Peripheral features #####
  16   ==============================================================================
  17   [..]
  18   Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
  19   port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
  20   in several modes:
  21   (+) Input mode
  22   (+) Analog mode
  23   (+) Output mode
  24   (+) Alternate function mode
  25   (+) External interrupt/event lines
  26
  27   [..]
  28   During and just after reset, the alternate functions and external interrupt
  29   lines are not active and the I/O ports are configured in input floating mode.
  30
  31   [..]
  32   All GPIO pins have weak internal pull-up and pull-down resistors, which can be
  33   activated or not.
  34
  35   [..]
  36   In Output or Alternate mode, each IO can be configured on open-drain or push-pull
  37   type and the IO speed can be selected depending on the VDD value.
  38
  39   [..]
  40   All ports have external interrupt/event capability. To use external interrupt
  41   lines, the port must be configured in input mode. All available GPIO pins are
  42   connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
  43
  44   [..]
  45   The external interrupt/event controller consists of up to 20 edge detectors in connectivity
  46   line devices, or 19 edge detectors in other devices for generating event/interrupt requests.
  47   Each input line can be independently configured to select the type (event or interrupt) and
  48   the corresponding trigger event (rising or falling or both). Each line can also masked
  49   independently. A pending register maintains the status line of the interrupt requests
  50
  51                      ##### How to use this driver #####
  52   ==============================================================================
  53  [..]
  54    (#) Enable the GPIO APB2 clock using the following function : __HAL_GPIOx_CLK_ENABLE().
  55
  56    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
  57        (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
  58        (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
  59             structure.
  60        (++) In case of Output or alternate function mode selection: the speed is
  61             configured through "Speed" member from GPIO_InitTypeDef structure
  62        (++) Analog mode is required when a pin is to be used as ADC channel
  63             or DAC output.
  64        (++) In case of external interrupt/event selection the "Mode" member from
  65             GPIO_InitTypeDef structure select the type (interrupt or event) and
  66             the corresponding trigger event (rising or falling or both).
  67
  68    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
  69        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
  70        HAL_NVIC_EnableIRQ().
  71
  72    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
  73
  74    (#) To set/reset the level of a pin configured in output mode use
  75        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
  76
  77    (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
  78
  79    (#) During and just after reset, the alternate functions are not
  80        active and the GPIO pins are configured in input floating mode (except JTAG
  81        pins).
  82
  83    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
  84        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
  85        priority over the GPIO function.
  86
  87    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
  88        general purpose PD0 and PD1, respectively, when the HSE oscillator is off.
  89        The HSE has priority over the GPIO function.
  90
  91   @endverbatim
  92   ******************************************************************************
  93   * @attention
  94   *
  95   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  96   *
  97   * Redistribution and use in source and binary forms, with or without modification,
  98   * are permitted provided that the following conditions are met:
  99   *   1. Redistributions of source code must retain the above copyright notice,
 100   *      this list of conditions and the following disclaimer.
 101   *   2. Redistributions in binary form must reproduce the above copyright notice,
 102   *      this list of conditions and the following disclaimer in the documentation
 103   *      and/or other materials provided with the distribution.
 104   *   3. Neither the name of STMicroelectronics nor the names of its contributors
 105   *      may be used to endorse or promote products derived from this software
 106   *      without specific prior written permission.
 107   *
 108   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 109   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 110   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 111   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 112   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 113   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 114   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 115   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 116   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 117   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 118   *
 119   ******************************************************************************
 120   */
 121
 122 /* Includes ------------------------------------------------------------------*/
 123 #include "stm32f1xx_hal.h"
 124
 125 /** @addtogroup STM32F1xx_HAL_Driver
 126   * @{
 127   */
 128
 129 /** @defgroup GPIO GPIO
 130   * @brief GPIO HAL module driver
 131   * @{
 132   */
 133
 134 #ifdef HAL_GPIO_MODULE_ENABLED
 135
 136 /* Private typedef -----------------------------------------------------------*/
 137 /* Private define ------------------------------------------------------------*/
 138 /** @defgroup GPIO_Private_Constants GPIO Private Constants
 139   * @{
 140   */
 141
 142 #define GPIO_MODE             ((uint32_t)0x00000003)
 143 #define EXTI_MODE             ((uint32_t)0x10000000)
 144 #define GPIO_MODE_IT          ((uint32_t)0x00010000)
 145 #define GPIO_MODE_EVT         ((uint32_t)0x00020000)
 146 #define RISING_EDGE           ((uint32_t)0x00100000)
 147 #define FALLING_EDGE          ((uint32_t)0x00200000)
 148 #define GPIO_OUTPUT_TYPE      ((uint32_t)0x00000010)
 149 #define GPIO_NUMBER           ((uint32_t)16)
 150
 151 /* Definitions for bit manipulation of CRL and CRH register */
 152 #define  GPIO_CR_MODE_INPUT         ((uint32_t)0x00000000) /*!< 00: Input mode (reset state)  */
 153 #define  GPIO_CR_CNF_ANALOG         ((uint32_t)0x00000000) /*!< 00: Analog mode  */
 154 #define  GPIO_CR_CNF_INPUT_FLOATING ((uint32_t)0x00000004) /*!< 01: Floating input (reset state)  */
 155 #define  GPIO_CR_CNF_INPUT_PU_PD    ((uint32_t)0x00000008) /*!< 10: Input with pull-up / pull-down  */
 156 #define  GPIO_CR_CNF_GP_OUTPUT_PP   ((uint32_t)0x00000000) /*!< 00: General purpose output push-pull  */
 157 #define  GPIO_CR_CNF_GP_OUTPUT_OD   ((uint32_t)0x00000004) /*!< 01: General purpose output Open-drain  */
 158 #define  GPIO_CR_CNF_AF_OUTPUT_PP   ((uint32_t)0x00000008) /*!< 10: Alternate function output Push-pull  */
 159 #define  GPIO_CR_CNF_AF_OUTPUT_OD   ((uint32_t)0x0000000C) /*!< 11: Alternate function output Open-drain  */
 160
 161 /**
 162   * @}
 163   */
 164
 165 /* Private macro -------------------------------------------------------------*/
 166 /* Private variables ---------------------------------------------------------*/
 167 /* Private function prototypes -----------------------------------------------*/
 168 /* Private functions ---------------------------------------------------------*/
 169
 170 /** @defgroup GPIO_Exported_Functions GPIO Exported Functions
 171   * @{
 172   */
 173
 174 /** @defgroup GPIO_Exported_Functions_Group1 Initialization and deinitialization functions
 175  *  @brief    Initialization and Configuration functions
 176  *
 177 @verbatim
 178  ===============================================================================
 179               ##### Initialization and deinitialization functions #####
 180  ===============================================================================
 181   [..]
 182     This section provides functions allowing to initialize and de-initialize the GPIOs
 183     to be ready for use.
 184
 185 @endverbatim
 186   * @{
 187   */
 188
 189 /**
 190   * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
 191   * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
 192   * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
 193   *         the configuration information for the specified GPIO peripheral.
 194   * @retval None
 195   */
 196 void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
 197 {
 198   uint32_t position;
 199   uint32_t ioposition = 0x00;
 200   uint32_t iocurrent = 0x00;
 201   uint32_t temp = 0x00;
 202   uint32_t config = 0x00;
 203   __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */
 204   uint32_t registeroffset = 0; /* offset used during computation of CNF and MODE bits placement inside CRL or CRH register */
 205
 206   /* Check the parameters */
 207   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
 208   assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
 209   assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
 210   assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
 211
 212   /* Configure the port pins */
 213   for (position = 0; position < GPIO_NUMBER; position++)
 214   {
 215     /* Get the IO position */
 216     ioposition = ((uint32_t)0x01) << position;
 217
 218     /* Get the current IO position */
 219     iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
 220
 221     if (iocurrent == ioposition)
 222     {
 223       /* Check the Alternate function parameters */
 224       assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
 225
 226       /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
 227       switch (GPIO_Init->Mode)
 228       {
 229         /* If we are configuring the pin in OUTPUT push-pull mode */
 230         case GPIO_MODE_OUTPUT_PP:
 231           /* Check the GPIO speed parameter */
 232           assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
 233           config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
 234           break;
 235
 236         /* If we are configuring the pin in OUTPUT open-drain mode */
 237         case GPIO_MODE_OUTPUT_OD:
 238           /* Check the GPIO speed parameter */
 239           assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
 240           config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
 241           break;
 242
 243         /* If we are configuring the pin in ALTERNATE FUNCTION push-pull mode */
 244         case GPIO_MODE_AF_PP:
 245           /* Check the GPIO speed parameter */
 246           assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
 247           config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
 248           break;
 249
 250         /* If we are configuring the pin in ALTERNATE FUNCTION open-drain mode */
 251         case GPIO_MODE_AF_OD:
 252           /* Check the GPIO speed parameter */
 253           assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
 254           config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
 255           break;
 256
 257         /* If we are configuring the pin in INPUT (also applicable to EVENT and IT mode) */
 258         case GPIO_MODE_INPUT:
 259         case GPIO_MODE_IT_RISING:
 260         case GPIO_MODE_IT_FALLING:
 261         case GPIO_MODE_IT_RISING_FALLING:
 262         case GPIO_MODE_EVT_RISING:
 263         case GPIO_MODE_EVT_FALLING:
 264         case GPIO_MODE_EVT_RISING_FALLING:
 265           /* Check the GPIO pull parameter */
 266           assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
 267           if(GPIO_Init->Pull == GPIO_NOPULL)
 268           {
 269             config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
 270           }
 271           else if(GPIO_Init->Pull == GPIO_PULLUP)
 272           {
 273             config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
 274
 275             /* Set the corresponding ODR bit */
 276             GPIOx->BSRR = ioposition;
 277           }
 278           else /* GPIO_PULLDOWN */
 279           {
 280             config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
 281
 282             /* Reset the corresponding ODR bit */
 283             GPIOx->BRR = ioposition;
 284           }
 285           break;
 286
 287         /* If we are configuring the pin in INPUT analog mode */
 288         case GPIO_MODE_ANALOG:
 289             config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
 290           break;
 291
 292         /* Parameters are checked with assert_param */
 293         default:
 294           break;
 295       }
 296
 297       /* Check if the current bit belongs to first half or last half of the pin count number
 298        in order to address CRH or CRL register*/
 299       configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL     : &GPIOx->CRH;
 300       registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2) : ((position - 8) << 2);
 301
 302       /* Apply the new configuration of the pin to the register */
 303       MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset ), (config << registeroffset));
 304
 305       /*--------------------- EXTI Mode Configuration ------------------------*/
 306       /* Configure the External Interrupt or event for the current IO */
 307       if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
 308       {
 309         /* Enable AFIO Clock */
 310         __HAL_RCC_AFIO_CLK_ENABLE();
 311         temp = AFIO->EXTICR[position >> 2];
 312         CLEAR_BIT(temp, ((uint32_t)0x0F) << (4 * (position & 0x03)));
 313         SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
 314         AFIO->EXTICR[position >> 2] = temp;
 315
 316
 317         /* Configure the interrupt mask */
 318         if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
 319         {
 320           SET_BIT(EXTI->IMR, iocurrent);
 321         }
 322         else
 323         {
 324           CLEAR_BIT(EXTI->IMR, iocurrent);
 325         }
 326
 327         /* Configure the event mask */
 328         if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
 329         {
 330           SET_BIT(EXTI->EMR, iocurrent);
 331         }
 332         else
 333         {
 334           CLEAR_BIT(EXTI->EMR, iocurrent);
 335         }
 336
 337         /* Enable or disable the rising trigger */
 338         if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
 339         {
 340           SET_BIT(EXTI->RTSR, iocurrent);
 341         }
 342         else
 343         {
 344           CLEAR_BIT(EXTI->RTSR, iocurrent);
 345         }
 346
 347         /* Enable or disable the falling trigger */
 348         if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
 349         {
 350           SET_BIT(EXTI->FTSR, iocurrent);
 351         }
 352         else
 353         {
 354           CLEAR_BIT(EXTI->FTSR, iocurrent);
 355         }
 356       }
 357     }
 358   }
 359 }
 360
 361 /**
 362   * @brief  De-initializes the GPIOx peripheral registers to their default reset values.
 363   * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
 364   * @param  GPIO_Pin: specifies the port bit to be written.
 365   *         This parameter can be one of GPIO_PIN_x where x can be (0..15).
 366   * @retval None
 367   */
 368 void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
 369 {
 370   uint32_t position = 0x00;
 371   uint32_t iocurrent = 0x00;
 372   uint32_t tmp = 0x00;
 373   __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */
 374   uint32_t registeroffset = 0;
 375
 376   /* Check the parameters */
 377   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
 378   assert_param(IS_GPIO_PIN(GPIO_Pin));
 379
 380   /* Configure the port pins */
 381   while ((GPIO_Pin >> position) != 0)
 382   {
 383     /* Get current io position */
 384     iocurrent = (GPIO_Pin) & ((uint32_t)1 << position);
 385
 386     if (iocurrent)
 387     {
 388       /*------------------------- GPIO Mode Configuration --------------------*/
 389       /* Check if the current bit belongs to first half or last half of the pin count number
 390        in order to address CRH or CRL register */
 391       configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL     : &GPIOx->CRH;
 392       registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2) : ((position - 8) << 2);
 393
 394       /* CRL/CRH default value is floating input(0x04) shifted to correct position */
 395       MODIFY_REG(*configregister, ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset ), GPIO_CRL_CNF0_0 << registeroffset);
 396
 397       /* ODR default value is 0 */
 398       CLEAR_BIT(GPIOx->ODR, iocurrent);
 399
 400       /*------------------------- EXTI Mode Configuration --------------------*/
 401       /* Clear the External Interrupt or Event for the current IO */
 402
 403       tmp = AFIO->EXTICR[position >> 2];
 404       tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
 405       if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))))
 406       {
 407         tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
 408         CLEAR_BIT(AFIO->EXTICR[position >> 2], tmp);
 409
 410         /* Clear EXTI line configuration */
 411         CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent);
 412         CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent);
 413
 414         /* Clear Rising Falling edge configuration */
 415         CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent);
 416         CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent);
 417       }
 418     }
 419
 420     position++;
 421   }
 422 }
 423
 424 /**
 425   * @}
 426   */
 427
 428 /** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
 429  *  @brief   GPIO Read and Write
 430  *
 431 @verbatim
 432  ===============================================================================
 433                        ##### IO operation functions #####
 434  ===============================================================================
 435   [..]
 436     This subsection provides a set of functions allowing to manage the GPIOs.
 437
 438 @endverbatim
 439   * @{
 440   */
 441 /**
 442   * @brief  Reads the specified input port pin.
 443   * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
 444   * @param  GPIO_Pin: specifies the port bit to read.
 445   *         This parameter can be GPIO_PIN_x where x can be (0..15).
 446   * @retval The input port pin value.
 447   */
 448 GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
 449 {
 450   GPIO_PinState bitstatus;
 451
 452   /* Check the parameters */
 453   assert_param(IS_GPIO_PIN(GPIO_Pin));
 454
 455   if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
 456   {
 457     bitstatus = GPIO_PIN_SET;
 458   }
 459   else
 460   {
 461     bitstatus = GPIO_PIN_RESET;
 462   }
 463   return bitstatus;
 464 }
 465
 466 /**
 467   * @brief  Sets or clears the selected data port bit.
 468   *
 469   * @note   This function uses GPIOx_BSRR register to allow atomic read/modify
 470   *         accesses. In this way, there is no risk of an IRQ occurring between
 471   *         the read and the modify access.
 472   *
 473   * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
 474   * @param  GPIO_Pin: specifies the port bit to be written.
 475   *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
 476   * @param  PinState: specifies the value to be written to the selected bit.
 477   *          This parameter can be one of the GPIO_PinState enum values:
 478   *            @arg GPIO_BIT_RESET: to clear the port pin
 479   *            @arg GPIO_BIT_SET: to set the port pin
 480   * @retval None
 481   */
 482 void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
 483 {
 484   /* Check the parameters */
 485   assert_param(IS_GPIO_PIN(GPIO_Pin));
 486   assert_param(IS_GPIO_PIN_ACTION(PinState));
 487
 488   if(PinState != GPIO_PIN_RESET)
 489   {
 490     GPIOx->BSRR = GPIO_Pin;
 491   }
 492   else
 493   {
 494     GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
 495   }
 496 }
 497
 498 /**
 499   * @brief  Toggles the specified GPIO pin
 500   * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
 501   * @param  GPIO_Pin: Specifies the pins to be toggled.
 502   * @retval None
 503   */
 504 void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
 505 {
 506   /* Check the parameters */
 507   assert_param(IS_GPIO_PIN(GPIO_Pin));
 508
 509   GPIOx->ODR ^= GPIO_Pin;
 510 }
 511
 512 /**
 513 * @brief  Locks GPIO Pins configuration registers.
 514 * @note   The locking mechanism allows the IO configuration to be frozen. When the LOCK sequence
 515 *         has been applied on a port bit, it is no longer possible to modify the value of the port bit until
 516 *         the next reset.
 517 * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
 518 * @param  GPIO_Pin: specifies the port bit to be locked.
 519 *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
 520 * @retval None
 521 */
 522 HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
 523 {
 524   __IO uint32_t tmp = GPIO_LCKR_LCKK;
 525
 526   /* Check the parameters */
 527   assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
 528   assert_param(IS_GPIO_PIN(GPIO_Pin));
 529
 530   /* Apply lock key write sequence */
 531   SET_BIT(tmp, GPIO_Pin);
 532   /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
 533   GPIOx->LCKR = tmp;
 534   /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
 535   GPIOx->LCKR = GPIO_Pin;
 536   /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
 537   GPIOx->LCKR = tmp;
 538   /* Read LCKK bit*/
 539   tmp = GPIOx->LCKR;
 540
 541   if((uint32_t)(GPIOx->LCKR & GPIO_LCKR_LCKK))
 542   {
 543     return HAL_OK;
 544   }
 545   else
 546   {
 547     return HAL_ERROR;
 548   }
 549 }
 550
 551 /**
 552   * @brief This function handles EXTI interrupt request.
 553   * @param GPIO_Pin: Specifies the pins connected EXTI line
 554   * @retval None
 555   */
 556 void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
 557 {
 558   /* EXTI line interrupt detected */
 559   if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
 560   {
 561     __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
 562     HAL_GPIO_EXTI_Callback(GPIO_Pin);
 563   }
 564 }
 565
 566 /**
 567   * @brief  EXTI line detection callback
 568   * @param GPIO_Pin: Specifies the pins connected EXTI line
 569   * @retval None
 570   */
 571 __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
 572 {
 573   /* NOTE : This function Should not be modified, when the callback is needed,
 574             the HAL_GPIO_EXTI_Callback could be implemented in the user file
 575    */
 576 }
 577
 578 /**
 579   * @}
 580   */
 581
 582
 583 /**
 584   * @}
 585   */
 586
 587 #endif /* HAL_GPIO_MODULE_ENABLED */
 588 /**
 589   * @}
 590   */
 591
 592 /**
 593   * @}
 594   */
 595
 596 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/