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[tmk_keyboard.git] / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_STM / TARGET_STM32F1 / stm32f1xx_hal_rcc.c
1 /**
2 ******************************************************************************
3 * @file stm32f1xx_hal_rcc.c
4 * @author MCD Application Team
5 * @version V1.0.0
6 * @date 15-December-2014
7 * @brief RCC HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the Reset and Clock Control (RCC) peripheral:
10 * + Initialization and de-initialization functions
11 * + Peripheral Control functions
12 *
13 @verbatim
14 ==============================================================================
15 ##### RCC specific features #####
16 ==============================================================================
17 [..]
18 After reset the device is running from Internal High Speed oscillator
19 (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
20 and all peripherals are off except internal SRAM, Flash and JTAG.
21 (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
22 all peripherals mapped on these busses are running at HSI speed.
23 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
24 (+) All GPIOs are in input floating state, except the JTAG pins which
25 are assigned to be used for debug purpose.
26
27 [..]
28 Once the device started from reset, the user application has to:
29 (+) Configure the clock source to be used to drive the System clock
30 (if the application needs higher frequency/performance)
31 (+) Configure the System clock frequency and Flash settings
32 (+) Configure the AHB and APB busses prescalers
33 (+) Enable the clock for the peripheral(s) to be used
34 (+) Configure the clock source(s) for peripherals whose clocks are not
35 derived from the System clock (I2S, RTC, ADC, USB OTG FS)
36
37 ##### RCC Limitations #####
38 ==============================================================================
39 [..]
40 A delay between an RCC peripheral clock enable and the effective peripheral
41 enabling should be taken into account in order to manage the peripheral read/write
42 from/to registers.
43 (+) This delay depends on the peripheral mapping.
44 (++) AHB & APB peripherals, 1 dummy read is necessary
45
46 [..]
47 Workarounds:
48 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
49 inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
50
51 @endverbatim
52 ******************************************************************************
53 * @attention
54 *
55 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
56 *
57 * Redistribution and use in source and binary forms, with or without modification,
58 * are permitted provided that the following conditions are met:
59 * 1. Redistributions of source code must retain the above copyright notice,
60 * this list of conditions and the following disclaimer.
61 * 2. Redistributions in binary form must reproduce the above copyright notice,
62 * this list of conditions and the following disclaimer in the documentation
63 * and/or other materials provided with the distribution.
64 * 3. Neither the name of STMicroelectronics nor the names of its contributors
65 * may be used to endorse or promote products derived from this software
66 * without specific prior written permission.
67 *
68 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
69 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
70 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
71 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
72 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
73 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
74 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
75 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
76 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
77 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
78 *
79 ******************************************************************************
80 */
81
82 /* Includes ------------------------------------------------------------------*/
83 #include "stm32f1xx_hal.h"
84
85 /** @addtogroup STM32F1xx_HAL_Driver
86 * @{
87 */
88
89 /** @defgroup RCC RCC
90 * @brief RCC HAL module driver
91 * @{
92 */
93
94 #ifdef HAL_RCC_MODULE_ENABLED
95
96 /* Private typedef -----------------------------------------------------------*/
97 /* Private define ------------------------------------------------------------*/
98 /** @defgroup RCC_Private_Constants RCC Private Constants
99 * @{
100 */
101 /**
102 * @}
103 */
104 /* Private macro -------------------------------------------------------------*/
105 /** @defgroup RCC_Private_Macros RCC Private Macros
106 * @{
107 */
108
109 #define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
110 #define MCO1_GPIO_PORT GPIOA
111 #define MCO1_PIN GPIO_PIN_8
112
113 /**
114 * @}
115 */
116
117 /* Private variables ---------------------------------------------------------*/
118 /** @defgroup RCC_Private_Variables RCC Private Variables
119 * @{
120 */
121 const uint8_t aAPBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
122
123 /**
124 * @}
125 */
126
127 /* Private function prototypes -----------------------------------------------*/
128 /* Private functions ---------------------------------------------------------*/
129
130 /** @defgroup RCC_Exported_Functions RCC Exported Functions
131 * @{
132 */
133
134 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
135 * @brief Initialization and Configuration functions
136 *
137 @verbatim
138 ===============================================================================
139 ##### Initialization and de-initialization functions #####
140 ===============================================================================
141 [..]
142 This section provide functions allowing to configure the internal/external oscillators
143 (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
144 and APB2).
145
146 [..] Internal/external clock and PLL configuration
147 (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
148 the PLL as System clock source.
149
150 (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC
151 clock source.
152
153 (#) HSE (high-speed external), 4 to 24 MHz (STM32F100xx) or 4 to 16 MHz (STM32F101x/STM32F102x/STM32F103x) or 3 to 25 MHz (STM32F105x/STM32F107x) crystal oscillator used directly or
154 through the PLL as System clock source. Can be used also as RTC clock source.
155
156 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
157
158 (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
159 (++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx)
160 (++) The second output is used to generate the clock for the USB OTG FS (48 MHz)
161
162 (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
163 and if a HSE clock failure occurs(HSE used directly or through PLL as System
164 clock source), the System clockis automatically switched to HSI and an interrupt
165 is generated if enabled. The interrupt is linked to the Cortex-M3 NMI
166 (Non-Maskable Interrupt) exception vector.
167
168 (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI,
169 HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x
170
171 [..] System, AHB and APB busses clocks configuration
172 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
173 HSE and PLL.
174 The AHB clock (HCLK) is derived from System clock through configurable
175 prescaler and used to clock the CPU, memory and peripherals mapped
176 on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
177 from AHB clock through configurable prescalers and used to clock
178 the peripherals mapped on these busses. You can use
179 "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
180
181 -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
182 (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock
183 divided by 128.
184 (+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz
185 to work correctly. This clock is derived of the main PLL through PLL Multiplier.
186 (+@) I2S interface on STM32F105x/STM32F107x can be derived from PLL3CLK
187 (+@) IWDG clock which is always the LSI clock.
188
189 (#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz.
190 For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz.
191 Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
192 +-----------------------------------------------+
193 | Latency | SYSCLK clock frequency (MHz) |
194 |---------------|-------------------------------|
195 |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
196 |---------------|-------------------------------|
197 |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
198 |---------------|-------------------------------|
199 |2WS(3CPU cycle)| 48 < SYSCLK <= 72 |
200 +-----------------------------------------------+
201 @endverbatim
202 * @{
203 */
204
205 /**
206 * @brief Resets the RCC clock configuration to the default reset state.
207 * @note The default reset state of the clock configuration is given below:
208 * - HSI ON and used as system clock source
209 * - HSE and PLL OFF
210 * - AHB, APB1 and APB2 prescaler set to 1.
211 * - CSS and MCO1 OFF
212 * - All interrupts disabled
213 * @note This function doesn't modify the configuration of the
214 * - Peripheral clocks
215 * - LSI, LSE and RTC clocks
216 * @retval None
217 */
218 __weak void HAL_RCC_DeInit(void)
219 {
220 /* Switch SYSCLK to HSI */
221 CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW);
222
223 /* Reset HSEON, CSSON, & PLLON bits */
224 CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
225
226 /* Reset HSEBYP bit */
227 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
228
229 /* Reset CFGR register */
230 CLEAR_REG(RCC->CFGR);
231
232 /* Set HSITRIM bits to the reset value */
233 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, ((uint32_t)0x10 << POSITION_VAL(RCC_CR_HSITRIM)));
234
235 /* Disable all interrupts */
236 CLEAR_REG(RCC->CIR);
237 }
238
239 /**
240 * @brief Initializes the RCC Oscillators according to the specified parameters in the
241 * RCC_OscInitTypeDef.
242 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
243 * contains the configuration information for the RCC Oscillators.
244 * @note The PLL is not disabled when used as system clock.
245 * @note The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS)
246 * @retval HAL status
247 */
248 __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
249 {
250 uint32_t tickstart = 0;
251
252 /* Check the parameters */
253 assert_param(RCC_OscInitStruct != NULL);
254 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
255
256 /*------------------------------- HSE Configuration ------------------------*/
257 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
258 {
259 /* Check the parameters */
260 assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
261
262 /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
263 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
264 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
265 {
266 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON) && (RCC_OscInitStruct->HSEState != RCC_HSE_BYPASS))
267 {
268 return HAL_ERROR;
269 }
270 }
271 else
272 {
273 /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
274 __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
275
276 /* Get Start Tick*/
277 tickstart = HAL_GetTick();
278
279 /* Wait till HSE is disabled */
280 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
281 {
282 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
283 {
284 return HAL_TIMEOUT;
285 }
286 }
287
288 /* Set the new HSE configuration ---------------------------------------*/
289 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
290
291 /* Check the HSE State */
292 if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
293 {
294 /* Get Start Tick*/
295 tickstart = HAL_GetTick();
296
297 /* Wait till HSE is ready */
298 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
299 {
300 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
301 {
302 return HAL_TIMEOUT;
303 }
304 }
305 }
306 else
307 {
308 /* Get Start Tick*/
309 tickstart = HAL_GetTick();
310
311 /* Wait till HSE is disabled */
312 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
313 {
314 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
315 {
316 return HAL_TIMEOUT;
317 }
318 }
319 }
320 }
321 }
322 /*----------------------------- HSI Configuration --------------------------*/
323 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
324 {
325 /* Check the parameters */
326 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
327 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
328
329 /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
330 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
331 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
332 {
333 /* When HSI is used as system clock it will not disabled */
334 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
335 {
336 return HAL_ERROR;
337 }
338 /* Otherwise, just the calibration is allowed */
339 else
340 {
341 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
342 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
343 }
344 }
345 else
346 {
347 /* Check the HSI State */
348 if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
349 {
350 /* Enable the Internal High Speed oscillator (HSI). */
351 __HAL_RCC_HSI_ENABLE();
352
353 /* Get Start Tick*/
354 tickstart = HAL_GetTick();
355
356 /* Wait till HSI is ready */
357 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
358 {
359 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
360 {
361 return HAL_TIMEOUT;
362 }
363 }
364
365 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
366 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
367 }
368 else
369 {
370 /* Disable the Internal High Speed oscillator (HSI). */
371 __HAL_RCC_HSI_DISABLE();
372
373 /* Get Start Tick*/
374 tickstart = HAL_GetTick();
375
376 /* Wait till HSI is disabled */
377 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
378 {
379 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
380 {
381 return HAL_TIMEOUT;
382 }
383 }
384 }
385 }
386 }
387 /*------------------------------ LSI Configuration -------------------------*/
388 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
389 {
390 /* Check the parameters */
391 assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
392
393 /* Check the LSI State */
394 if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
395 {
396 /* Enable the Internal Low Speed oscillator (LSI). */
397 __HAL_RCC_LSI_ENABLE();
398
399 /* Get Start Tick*/
400 tickstart = HAL_GetTick();
401
402 /* Wait till LSI is ready */
403 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
404 {
405 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
406 {
407 return HAL_TIMEOUT;
408 }
409 }
410 /* To have a fully stabilized clock in the specified range, a software temporization of 1ms
411 should be added.*/
412 HAL_Delay(1);
413 }
414 else
415 {
416 /* Disable the Internal Low Speed oscillator (LSI). */
417 __HAL_RCC_LSI_DISABLE();
418
419 /* Get Start Tick*/
420 tickstart = HAL_GetTick();
421
422 /* Wait till LSI is disabled */
423 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
424 {
425 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
426 {
427 return HAL_TIMEOUT;
428 }
429 }
430 }
431 }
432 /*------------------------------ LSE Configuration -------------------------*/
433 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
434 {
435 /* Check the parameters */
436 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
437
438 /* Enable Power Clock*/
439 __HAL_RCC_PWR_CLK_ENABLE();
440
441 /* Enable write access to Backup domain */
442 SET_BIT(PWR->CR, PWR_CR_DBP);
443
444 /* Wait for Backup domain Write protection disable */
445 tickstart = HAL_GetTick();
446
447 while((PWR->CR & PWR_CR_DBP) == RESET)
448 {
449 if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
450 {
451 return HAL_TIMEOUT;
452 }
453 }
454
455 /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
456 __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
457
458 /* Get Start Tick*/
459 tickstart = HAL_GetTick();
460
461 /* Wait till LSE is ready */
462 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
463 {
464 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
465 {
466 return HAL_TIMEOUT;
467 }
468 }
469
470 /* Set the new LSE configuration -----------------------------------------*/
471 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
472 /* Check the LSE State */
473 if((RCC_OscInitStruct->LSEState) == RCC_LSE_ON)
474 {
475 /* Get Start Tick*/
476 tickstart = HAL_GetTick();
477
478 /* Wait till LSE is ready */
479 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
480 {
481 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
482 {
483 return HAL_TIMEOUT;
484 }
485 }
486 }
487 else
488 {
489 /* Get Start Tick*/
490 tickstart = HAL_GetTick();
491
492 /* Wait till LSE is disabled */
493 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
494 {
495 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
496 {
497 return HAL_TIMEOUT;
498 }
499 }
500 }
501 }
502
503 /*-------------------------------- PLL Configuration -----------------------*/
504 /* Check the parameters */
505 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
506 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
507 {
508 /* Check if the PLL is used as system clock or not */
509 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
510 {
511 if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
512 {
513 /* Check the parameters */
514 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
515 assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
516
517 /* Disable the main PLL. */
518 __HAL_RCC_PLL_DISABLE();
519
520 /* Get Start Tick*/
521 tickstart = HAL_GetTick();
522
523 /* Wait till PLL is ready */
524 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
525 {
526 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
527 {
528 return HAL_TIMEOUT;
529 }
530 }
531
532 /* Configure the HSE prediv1 factor --------------------------------*/
533 /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
534 if(RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
535 {
536 /* Check the parameters */
537 assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue));
538
539 __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
540 }
541
542 /* Configure the main PLL clock source and multiplication factors. */
543 __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
544 RCC_OscInitStruct->PLL.PLLMUL);
545 /* Enable the main PLL. */
546 __HAL_RCC_PLL_ENABLE();
547
548 /* Get Start Tick*/
549 tickstart = HAL_GetTick();
550
551 /* Wait till PLL is ready */
552 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
553 {
554 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
555 {
556 return HAL_TIMEOUT;
557 }
558 }
559 }
560 else
561 {
562 /* Disable the main PLL. */
563 __HAL_RCC_PLL_DISABLE();
564
565 /* Get Start Tick*/
566 tickstart = HAL_GetTick();
567
568 /* Wait till PLL is disabled */
569 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
570 {
571 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
572 {
573 return HAL_TIMEOUT;
574 }
575 }
576 }
577 }
578 else
579 {
580 return HAL_ERROR;
581 }
582 }
583
584 return HAL_OK;
585 }
586
587 /**
588 * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
589 * parameters in the RCC_ClkInitStruct.
590 * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
591 * contains the configuration information for the RCC peripheral.
592 * @param FLatency: FLASH Latency
593 * This parameter can be one of the following values:
594 * @arg FLASH_LATENCY_0: FLASH 0 Latency cycle
595 * @arg FLASH_LATENCY_1: FLASH 1 Latency cycle
596 * @arg FLASH_LATENCY_2: FLASH 2 Latency cycle
597 *
598 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
599 * and updated by HAL_RCC_GetHCLKFreq() function called within this function
600 *
601 * @note The HSI is used (enabled by hardware) as system clock source after
602 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
603 * of failure of the HSE used directly or indirectly as system clock
604 * (if the Clock Security System CSS is enabled).
605 *
606 * @note A switch from one clock source to another occurs only if the target
607 * clock source is ready (clock stable after startup delay or PLL locked).
608 * If a clock source which is not yet ready is selected, the switch will
609 * occur when the clock source will be ready.
610 * You can use HAL_RCC_GetClockConfig() function to know which clock is
611 * currently used as system clock source.
612 * @retval None
613 */
614 __weak HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
615 {
616 uint32_t tickstart = 0;
617
618 /* Check the parameters */
619 assert_param(RCC_ClkInitStruct != NULL);
620 assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
621 assert_param(IS_FLASH_LATENCY(FLatency));
622
623 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
624 must be correctly programmed according to the frequency of the CPU clock
625 (HCLK) of the device. */
626
627 /*-------------------------- HCLK Configuration --------------------------*/
628 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
629 {
630 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
631 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
632 }
633
634 /*------------------------- SYSCLK Configuration ---------------------------*/
635 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
636 {
637 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
638
639 /* HSE is selected as System Clock Source */
640 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
641 {
642 /* Check the HSE ready flag */
643 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
644 {
645 return HAL_ERROR;
646 }
647 }
648 /* PLL is selected as System Clock Source */
649 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
650 {
651 /* Check the PLL ready flag */
652 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
653 {
654 return HAL_ERROR;
655 }
656 }
657 /* HSI is selected as System Clock Source */
658 else
659 {
660 /* Check the HSI ready flag */
661 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
662 {
663 return HAL_ERROR;
664 }
665 }
666
667 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
668
669 /* Get Start Tick*/
670 tickstart = HAL_GetTick();
671
672 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
673 {
674 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
675 {
676 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
677 {
678 return HAL_TIMEOUT;
679 }
680 }
681 }
682 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
683 {
684 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
685 {
686 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
687 {
688 return HAL_TIMEOUT;
689 }
690 }
691 }
692 else
693 {
694 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
695 {
696 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
697 {
698 return HAL_TIMEOUT;
699 }
700 }
701 }
702 }
703
704 /*-------------------------- PCLK1 Configuration ---------------------------*/
705 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
706 {
707 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
708 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
709 }
710
711 /*-------------------------- PCLK2 Configuration ---------------------------*/
712 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
713 {
714 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
715 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
716 }
717
718 /* Configure the source of time base considering new system clocks settings*/
719 HAL_InitTick (TICK_INT_PRIORITY);
720
721 return HAL_OK;
722 }
723
724 /**
725 * @}
726 */
727
728 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
729 * @brief RCC clocks control functions
730 *
731 @verbatim
732 ===============================================================================
733 ##### Peripheral Control functions #####
734 ===============================================================================
735 [..]
736 This subsection provides a set of functions allowing to control the RCC Clocks
737 frequencies.
738
739 @endverbatim
740 * @{
741 */
742
743 /**
744 * @brief Selects the clock source to output on MCO pin.
745 * @note MCO pin should be configured in alternate function mode.
746 * @param RCC_MCOx: specifies the output direction for the clock source.
747 * This parameter can be one of the following values:
748 * @arg RCC_MCO: Clock source to output on MCO1 pin(PA8).
749 * @param RCC_MCOSource: specifies the clock source to output.
750 * This parameter can be one of the following values:
751 * @arg RCC_MCO1SOURCE_NOCLOCK: No clock selected
752 * @arg RCC_MCO1SOURCE_SYSCLK: System clock selected as MCO source
753 * @arg RCC_MCO1SOURCE_HSI: HSI oscillator clock selected
754 * @arg RCC_MCO1SOURCE_HSE: HSE oscillator clock selected
755 * @arg RCC_MCO1SOURCE_PLLCLK: PLL clock divided by 2 selected as MCO source
756 * @arg RCC_MCO1SOURCE_PLL2CLK: PLL2 clock selected as MCO source (only for connectivity line devices)
757 * @arg RCC_MCO1SOURCE_PLL3CLK_DIV2: PLL3 clock divided by 2 selected as MCO source (only for connectivity line devices)
758 * @arg RCC_MCO1SOURCE_EXT_HSE: XT1 external 3-25 MHz oscillator clock selected as MCO source (only for connectivity line devices)
759 * @arg RCC_MCO1SOURCE_PLL3CLK: PLL3 clock selected as MCO source (only for connectivity line devices)
760 * @param RCC_MCODiv: specifies the MCO DIV.
761 * This parameter can be one of the following values:
762 * @arg RCC_MCODIV_1: no division applied to MCO clock
763 * @retval None
764 */
765 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
766 {
767 GPIO_InitTypeDef gpio;
768
769 /* Check the parameters */
770 assert_param(IS_RCC_MCO(RCC_MCOx));
771 assert_param(IS_RCC_MCODIV(RCC_MCODiv));
772 assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
773
774 /* MCO Clock Enable */
775 MCO1_CLK_ENABLE();
776
777 /* Configure the MCO1 pin in alternate function mode */
778 gpio.Pin = MCO1_PIN;
779 gpio.Mode = GPIO_MODE_AF_PP;
780 gpio.Speed = GPIO_SPEED_HIGH;
781 gpio.Pull = GPIO_NOPULL;
782 HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
783
784 /* Mask MCO and MCOPRE[2:0] bits then Select MCO clock source and prescaler */
785 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, RCC_MCOSource);
786 }
787
788 /**
789 * @brief Enables the Clock Security System.
790 * @note If a failure is detected on the HSE oscillator clock, this oscillator
791 * is automatically disabled and an interrupt is generated to inform the
792 * software about the failure (Clock Security System Interrupt, CSSI),
793 * allowing the MCU to perform rescue operations. The CSSI is linked to
794 * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
795 * @retval None
796 */
797 void HAL_RCC_EnableCSS(void)
798 {
799 *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
800 }
801
802 /**
803 * @brief Disables the Clock Security System.
804 * @retval None
805 */
806 void HAL_RCC_DisableCSS(void)
807 {
808 *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
809 }
810
811 /**
812 * @brief Returns the SYSCLK frequency
813 *
814 * @note The system frequency computed by this function is not the real
815 * frequency in the chip. It is calculated based on the predefined
816 * constant and the selected clock source:
817 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
818 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE
819 * divided by PREDIV factor(**)
820 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE
821 * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
822 * @note (*) HSI_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
823 * 8 MHz).
824 * @note (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
825 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
826 * frequency of the crystal used. Otherwise, this function may
827 * have wrong result.
828 *
829 * @note The result of this function could be not correct when using fractional
830 * value for HSE crystal.
831 *
832 * @note This function can be used by the user application to compute the
833 * baudrate for the communication peripherals or configure other parameters.
834 *
835 * @note Each time SYSCLK changes, this function must be called to update the
836 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
837 *
838 *
839 * @retval SYSCLK frequency
840 */
841 __weak uint32_t HAL_RCC_GetSysClockFreq(void)
842 {
843 const uint8_t aPLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
844 const uint8_t aPredivFactorTable[2] = { 1, 2};
845
846 uint32_t tmpreg = 0, prediv1 = 0, pllclk = 0, pllmul = 0;
847 uint32_t sysclockfreq = 0;
848
849 tmpreg = RCC->CFGR;
850
851 /* Get SYSCLK source -------------------------------------------------------*/
852 switch (tmpreg & RCC_CFGR_SWS)
853 {
854 case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
855 {
856 sysclockfreq = HSE_VALUE;
857 break;
858 }
859 case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
860 {
861 pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> POSITION_VAL(RCC_CFGR_PLLMULL)];
862 if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
863 {
864 prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> POSITION_VAL(RCC_CFGR_PLLXTPRE)];
865 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
866 pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
867 }
868 else
869 {
870 /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
871 pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
872 }
873 sysclockfreq = pllclk;
874 break;
875 }
876 case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
877 default: /* HSI used as system clock */
878 {
879 sysclockfreq = HSI_VALUE;
880 break;
881 }
882 }
883 return sysclockfreq;
884 }
885
886 /**
887 * @brief Returns the HCLK frequency
888 * @note Each time HCLK changes, this function must be called to update the
889 * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
890 *
891 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
892 * and updated within this function
893 * @retval HCLK frequency
894 */
895 uint32_t HAL_RCC_GetHCLKFreq(void)
896 {
897 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
898 return SystemCoreClock;
899 }
900
901 /**
902 * @brief Returns the PCLK1 frequency
903 * @note Each time PCLK1 changes, this function must be called to update the
904 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
905 * @retval PCLK1 frequency
906 */
907 uint32_t HAL_RCC_GetPCLK1Freq(void)
908 {
909 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
910 return (HAL_RCC_GetHCLKFreq() >> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
911 }
912
913 /**
914 * @brief Returns the PCLK2 frequency
915 * @note Each time PCLK2 changes, this function must be called to update the
916 * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
917 * @retval PCLK2 frequency
918 */
919 uint32_t HAL_RCC_GetPCLK2Freq(void)
920 {
921 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
922 return (HAL_RCC_GetHCLKFreq()>> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
923 }
924
925 /**
926 * @brief Configures the RCC_OscInitStruct according to the internal
927 * RCC configuration registers.
928 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
929 * will be configured.
930 * @retval None
931 */
932 __weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
933 {
934 /* Check the parameters */
935 assert_param(RCC_OscInitStruct != NULL);
936
937 /* Set all possible values for the Oscillator type parameter ---------------*/
938 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \
939 | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
940
941 /* Get the HSE configuration -----------------------------------------------*/
942 if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
943 {
944 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
945 }
946 else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
947 {
948 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
949 }
950 else
951 {
952 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
953 }
954
955 RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV();
956
957 /* Get the HSI configuration -----------------------------------------------*/
958 if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
959 {
960 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
961 }
962 else
963 {
964 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
965 }
966
967 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
968
969 /* Get the LSE configuration -----------------------------------------------*/
970 if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
971 {
972 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
973 }
974 else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
975 {
976 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
977 }
978 else
979 {
980 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
981 }
982
983 /* Get the LSI configuration -----------------------------------------------*/
984 if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
985 {
986 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
987 }
988 else
989 {
990 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
991 }
992
993 /* Get the PLL configuration -----------------------------------------------*/
994 if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
995 {
996 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
997 }
998 else
999 {
1000 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
1001 }
1002 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
1003 RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL);
1004 }
1005
1006 /**
1007 * @brief Configures the RCC_ClkInitStruct according to the internal
1008 * RCC configuration registers.
1009 * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
1010 * will be configured.
1011 * @param pFLatency: Pointer on the Flash Latency.
1012 * @retval None
1013 */
1014 __weak void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
1015 {
1016 /* Check the parameters */
1017 assert_param(RCC_ClkInitStruct != NULL);
1018 assert_param(pFLatency != NULL);
1019
1020 /* Set all possible values for the Clock type parameter --------------------*/
1021 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
1022
1023 /* Get the SYSCLK configuration --------------------------------------------*/
1024 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
1025
1026 /* Get the HCLK configuration ----------------------------------------------*/
1027 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
1028
1029 /* Get the APB1 configuration ----------------------------------------------*/
1030 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
1031
1032 /* Get the APB2 configuration ----------------------------------------------*/
1033 RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
1034
1035 /* For VALUE lines devices, only LATENCY_0 can be set*/
1036 *pFLatency = (uint32_t)FLASH_LATENCY_0;
1037 }
1038
1039 /**
1040 * @brief This function handles the RCC CSS interrupt request.
1041 * @note This API should be called under the NMI_Handler().
1042 * @retval None
1043 */
1044 void HAL_RCC_NMI_IRQHandler(void)
1045 {
1046 /* Check RCC CSSF flag */
1047 if(__HAL_RCC_GET_IT(RCC_IT_CSS))
1048 {
1049 /* RCC Clock Security System interrupt user callback */
1050 HAL_RCC_CSSCallback();
1051
1052 /* Clear RCC CSS pending bit */
1053 __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
1054 }
1055 }
1056
1057 /**
1058 * @brief RCC Clock Security System interrupt callback
1059 * @retval none
1060 */
1061 __weak void HAL_RCC_CSSCallback(void)
1062 {
1063 /* NOTE : This function Should not be modified, when the callback is needed,
1064 the HAL_RCC_CSSCallback could be implemented in the user file
1065 */
1066 }
1067
1068 /**
1069 * @}
1070 */
1071
1072 /**
1073 * @}
1074 */
1075
1076 #endif /* HAL_RCC_MODULE_ENABLED */
1077 /**
1078 * @}
1079 */
1080
1081 /**
1082 * @}
1083 */
1084
1085 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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