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[tmk_keyboard.git] / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_STM / TARGET_STM32F1 / stm32f1xx_hal_rcc_ex.c
1 /**
2 ******************************************************************************
3 * @file stm32f1xx_hal_rcc_ex.c
4 * @author MCD Application Team
5 * @version V1.0.0
6 * @date 15-December-2014
7 * @brief Extended RCC HAL module driver.
8 *
9 * This file provides firmware functions to manage the following
10 * functionalities RCC extension peripheral:
11 * + Extended Peripheral Control functions
12 *
13 ******************************************************************************
14 * @attention
15 *
16 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
17 *
18 * Redistribution and use in source and binary forms, with or without modification,
19 * are permitted provided that the following conditions are met:
20 * 1. Redistributions of source code must retain the above copyright notice,
21 * this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright notice,
23 * this list of conditions and the following disclaimer in the documentation
24 * and/or other materials provided with the distribution.
25 * 3. Neither the name of STMicroelectronics nor the names of its contributors
26 * may be used to endorse or promote products derived from this software
27 * without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
30 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
32 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
36 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
37 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 ******************************************************************************
41 */
42
43 /* Includes ------------------------------------------------------------------*/
44 #include "stm32f1xx_hal.h"
45
46 /** @addtogroup STM32F1xx_HAL_Driver
47 * @{
48 */
49
50 #ifdef HAL_RCC_MODULE_ENABLED
51
52 /** @defgroup RCCEx RCCEx
53 * @brief RCC Extension HAL module driver
54 * @{
55 */
56
57 /* Private typedef -----------------------------------------------------------*/
58 /* Private define ------------------------------------------------------------*/
59 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants
60 * @{
61 */
62 #define PLL2_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
63
64 /* Alias word address of PLL2ON bit */
65 #define PLL2ON_BITNUMBER POSITION_VAL(RCC_CR_PLL2ON)
66 #define CR_PLL2ON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLL2ON_BITNUMBER * 4)))
67
68
69 /**
70 * @}
71 */
72 /* Private macro -------------------------------------------------------------*/
73 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
74 * @{
75 */
76 /**
77 * @}
78 */
79
80 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
81 * @{
82 */
83
84 /**
85 * @}
86 */
87
88
89 /* Private variables ---------------------------------------------------------*/
90 /* Private function prototypes -----------------------------------------------*/
91 /* Private functions ---------------------------------------------------------*/
92
93 /**
94 * @}
95 */
96
97 /** @addtogroup RCC
98 * @{
99 */
100
101 /** @addtogroup RCC_Exported_Functions
102 * @{
103 */
104
105 #if defined(STM32F105xC) || defined(STM32F107xC) || defined (STM32F100xB) || defined (STM32F100xE)
106 /** @addtogroup RCC_Exported_Functions_Group1
107 * @{
108 */
109
110 /**
111 * @brief Resets the RCC clock configuration to the default reset state.
112 * @note The default reset state of the clock configuration is given below:
113 * - HSI ON and used as system clock source
114 * - HSE and PLL OFF
115 * - AHB, APB1 and APB2 prescaler set to 1.
116 * - CSS and MCO1 OFF
117 * - All interrupts disabled
118 * @note This function doesn't modify the configuration of the
119 * - Peripheral clocks
120 * - LSI, LSE and RTC clocks
121 * @retval None
122 */
123 void HAL_RCC_DeInit(void)
124 {
125 /* Switch SYSCLK to HSI */
126 CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW);
127
128 /* Reset HSEON, CSSON, & PLLON bits */
129 CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
130
131 /* Reset HSEBYP bit */
132 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
133
134 /* Reset CFGR register */
135 CLEAR_REG(RCC->CFGR);
136
137 /* Set HSITRIM bits to the reset value */
138 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, ((uint32_t)0x10 << POSITION_VAL(RCC_CR_HSITRIM)));
139
140 /* Reset CFGR2 register */
141 CLEAR_REG(RCC->CFGR2);
142
143 /* Disable all interrupts */
144 CLEAR_REG(RCC->CIR);
145 }
146 /**
147 * @}
148 */
149
150 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
151
152 #if defined(STM32F105xC) || defined(STM32F107xC)
153 /** @addtogroup RCC_Exported_Functions_Group1
154 * @{
155 */
156
157 /**
158 * @brief Initializes the RCC Oscillators according to the specified parameters in the
159 * RCC_OscInitTypeDef.
160 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
161 * contains the configuration information for the RCC Oscillators.
162 * @note The PLL is not disabled when used as system clock.
163 * @note The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS)
164 * @retval HAL status
165 */
166 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
167 {
168 uint32_t tickstart = 0;
169
170 /* Check the parameters */
171 assert_param(RCC_OscInitStruct != NULL);
172 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
173
174 /*------------------------------- HSE Configuration ------------------------*/
175 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
176 {
177 /* Check the parameters */
178 assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
179
180 /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
181 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
182 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
183 {
184 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON) && (RCC_OscInitStruct->HSEState != RCC_HSE_BYPASS))
185 {
186 return HAL_ERROR;
187 }
188 }
189 else
190 {
191 /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
192 __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
193
194 /* Get Start Tick*/
195 tickstart = HAL_GetTick();
196
197 /* Wait till HSE is disabled */
198 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
199 {
200 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
201 {
202 return HAL_TIMEOUT;
203 }
204 }
205
206 /* Set the new HSE configuration ---------------------------------------*/
207 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
208
209 /* Check the HSE State */
210 if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
211 {
212 /* Get Start Tick*/
213 tickstart = HAL_GetTick();
214
215 /* Wait till HSE is ready */
216 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
217 {
218 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
219 {
220 return HAL_TIMEOUT;
221 }
222 }
223 }
224 else
225 {
226 /* Get Start Tick*/
227 tickstart = HAL_GetTick();
228
229 /* Wait till HSE is disabled */
230 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
231 {
232 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
233 {
234 return HAL_TIMEOUT;
235 }
236 }
237 }
238 }
239 }
240 /*----------------------------- HSI Configuration --------------------------*/
241 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
242 {
243 /* Check the parameters */
244 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
245 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
246
247 /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
248 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
249 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
250 {
251 /* When HSI is used as system clock it will not disabled */
252 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
253 {
254 return HAL_ERROR;
255 }
256 /* Otherwise, just the calibration is allowed */
257 else
258 {
259 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
260 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
261 }
262 }
263 else
264 {
265 /* Check the HSI State */
266 if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
267 {
268 /* Enable the Internal High Speed oscillator (HSI). */
269 __HAL_RCC_HSI_ENABLE();
270
271 /* Get Start Tick*/
272 tickstart = HAL_GetTick();
273
274 /* Wait till HSI is ready */
275 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
276 {
277 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
278 {
279 return HAL_TIMEOUT;
280 }
281 }
282
283 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
284 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
285 }
286 else
287 {
288 /* Disable the Internal High Speed oscillator (HSI). */
289 __HAL_RCC_HSI_DISABLE();
290
291 /* Get Start Tick*/
292 tickstart = HAL_GetTick();
293
294 /* Wait till HSI is disabled */
295 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
296 {
297 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
298 {
299 return HAL_TIMEOUT;
300 }
301 }
302 }
303 }
304 }
305 /*------------------------------ LSI Configuration -------------------------*/
306 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
307 {
308 /* Check the parameters */
309 assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
310
311 /* Check the LSI State */
312 if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
313 {
314 /* Enable the Internal Low Speed oscillator (LSI). */
315 __HAL_RCC_LSI_ENABLE();
316
317 /* Get Start Tick*/
318 tickstart = HAL_GetTick();
319
320 /* Wait till LSI is ready */
321 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
322 {
323 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
324 {
325 return HAL_TIMEOUT;
326 }
327 }
328 /* To have a fully stabilized clock in the specified range, a software temporization of 1ms
329 should be added.*/
330 HAL_Delay(1);
331 }
332 else
333 {
334 /* Disable the Internal Low Speed oscillator (LSI). */
335 __HAL_RCC_LSI_DISABLE();
336
337 /* Get Start Tick*/
338 tickstart = HAL_GetTick();
339
340 /* Wait till LSI is disabled */
341 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
342 {
343 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
344 {
345 return HAL_TIMEOUT;
346 }
347 }
348 }
349 }
350 /*------------------------------ LSE Configuration -------------------------*/
351 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
352 {
353 /* Check the parameters */
354 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
355
356 /* Enable Power Clock*/
357 __HAL_RCC_PWR_CLK_ENABLE();
358
359 /* Enable write access to Backup domain */
360 SET_BIT(PWR->CR, PWR_CR_DBP);
361
362 /* Wait for Backup domain Write protection disable */
363 tickstart = HAL_GetTick();
364
365 while((PWR->CR & PWR_CR_DBP) == RESET)
366 {
367 if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
368 {
369 return HAL_TIMEOUT;
370 }
371 }
372
373 /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
374 __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
375
376 /* Get Start Tick*/
377 tickstart = HAL_GetTick();
378
379 /* Wait till LSE is disabled */
380 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
381 {
382 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
383 {
384 return HAL_TIMEOUT;
385 }
386 }
387
388 /* Set the new LSE configuration -----------------------------------------*/
389 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
390 /* Check the LSE State */
391 if((RCC_OscInitStruct->LSEState) == RCC_LSE_ON)
392 {
393 /* Get Start Tick*/
394 tickstart = HAL_GetTick();
395
396 /* Wait till LSE is ready */
397 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
398 {
399 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
400 {
401 return HAL_TIMEOUT;
402 }
403 }
404 }
405 else
406 {
407 /* Get Start Tick*/
408 tickstart = HAL_GetTick();
409
410 /* Wait till LSE is disabled */
411 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
412 {
413 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
414 {
415 return HAL_TIMEOUT;
416 }
417 }
418 }
419 }
420
421 /*-------------------------------- PLL2 Configuration -----------------------*/
422 /* Check the parameters */
423 assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State));
424 if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE)
425 {
426 /* This bit can not be cleared if the PLL2 clock is used indirectly as system
427 clock (i.e. it is used as PLL clock entry that is used as system clock). */
428 if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
429 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
430 ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
431 {
432 return HAL_ERROR;
433 }
434 else
435 {
436 if((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON)
437 {
438 /* Check the parameters */
439 assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL));
440 assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value));
441
442 /* Prediv2 can be written only when the PLLI2S is disabled. */
443 /* Return an error only if new value is different from the programmed value */
444 if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL3ON) && \
445 (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value))
446 {
447 return HAL_ERROR;
448 }
449
450 /* Disable the main PLL2. */
451 __HAL_RCC_PLL2_DISABLE();
452
453 /* Get Start Tick*/
454 tickstart = HAL_GetTick();
455
456 /* Wait till PLL2 is disabled */
457 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
458 {
459 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
460 {
461 return HAL_TIMEOUT;
462 }
463 }
464
465 /* Configure the HSE prediv2 factor --------------------------------*/
466 __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value);
467
468 /* Configure the main PLL2 multiplication factors. */
469 __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL);
470
471 /* Enable the main PLL2. */
472 __HAL_RCC_PLL2_ENABLE();
473
474 /* Get Start Tick*/
475 tickstart = HAL_GetTick();
476
477 /* Wait till PLL2 is ready */
478 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
479 {
480 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
481 {
482 return HAL_TIMEOUT;
483 }
484 }
485 }
486 else
487 {
488 /* Set PREDIV1 source to HSE */
489 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC);
490
491 /* Disable the main PLL2. */
492 __HAL_RCC_PLL2_DISABLE();
493
494 /* Get Start Tick*/
495 tickstart = HAL_GetTick();
496
497 /* Wait till PLL2 is disabled */
498 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
499 {
500 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
501 {
502 return HAL_TIMEOUT;
503 }
504 }
505 }
506 }
507 }
508
509 /*-------------------------------- PLL Configuration -----------------------*/
510 /* Check the parameters */
511 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
512 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
513 {
514 /* Check if the PLL is used as system clock or not */
515 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
516 {
517 if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
518 {
519 /* Check the parameters */
520 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
521 assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
522
523 /* Disable the main PLL. */
524 __HAL_RCC_PLL_DISABLE();
525
526 /* Get Start Tick*/
527 tickstart = HAL_GetTick();
528
529 /* Wait till PLL is disabled */
530 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
531 {
532 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
533 {
534 return HAL_TIMEOUT;
535 }
536 }
537
538 /* Configure the HSE prediv1 factor and source --------------------------------*/
539 /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
540 if(RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
541 {
542 /* Check the parameter */
543 assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source));
544 assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue));
545
546 /* Set PREDIV1 source */
547 SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
548
549 /* Set PREDIV1 Value */
550 __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
551 }
552
553 /* Configure the main PLL clock source and multiplication factors. */
554 __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
555 RCC_OscInitStruct->PLL.PLLMUL);
556 /* Enable the main PLL. */
557 __HAL_RCC_PLL_ENABLE();
558
559 /* Get Start Tick*/
560 tickstart = HAL_GetTick();
561
562 /* Wait till PLL is ready */
563 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
564 {
565 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
566 {
567 return HAL_TIMEOUT;
568 }
569 }
570 }
571 else
572 {
573 /* Disable the main PLL. */
574 __HAL_RCC_PLL_DISABLE();
575
576 /* Get Start Tick*/
577 tickstart = HAL_GetTick();
578
579 /* Wait till PLL is disabled */
580 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
581 {
582 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
583 {
584 return HAL_TIMEOUT;
585 }
586 }
587 }
588 }
589 else
590 {
591 return HAL_ERROR;
592 }
593 }
594
595 return HAL_OK;
596 }
597 /**
598 * @}
599 */
600
601 #endif /* STM32F105xC STM32F107xC */
602
603 #if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || \
604 defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || \
605 defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
606 /** @addtogroup RCC_Exported_Functions_Group1
607 * @{
608 */
609
610 /**
611 * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
612 * parameters in the RCC_ClkInitStruct.
613 * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
614 * contains the configuration information for the RCC peripheral.
615 * @param FLatency: FLASH Latency
616 * This parameter can be one of the following values:
617 * @arg FLASH_LATENCY_0: FLASH 0 Latency cycle
618 *
619 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
620 * and updated by HAL_RCC_GetHCLKFreq() function called within this function
621 *
622 * @note The HSI is used (enabled by hardware) as system clock source after
623 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
624 * of failure of the HSE used directly or indirectly as system clock
625 * (if the Clock Security System CSS is enabled).
626 *
627 * @note A switch from one clock source to another occurs only if the target
628 * clock source is ready (clock stable after startup delay or PLL locked).
629 * If a clock source which is not yet ready is selected, the switch will
630 * occur when the clock source will be ready.
631 * You can use HAL_RCC_GetClockConfig() function to know which clock is
632 * currently used as system clock source.
633 * @retval None
634 */
635 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
636 {
637 uint32_t tickstart = 0;
638
639 /* Check the parameters */
640 assert_param(RCC_ClkInitStruct != NULL);
641 assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
642 assert_param(IS_FLASH_LATENCY(FLatency));
643
644 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
645 must be correctly programmed according to the frequency of the CPU clock
646 (HCLK) of the device. */
647
648 /* Increasing the CPU frequency */
649 if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
650 {
651 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
652 __HAL_FLASH_SET_LATENCY(FLatency);
653
654 /* Check that the new number of wait states is taken into account to access the Flash
655 memory by reading the FLASH_ACR register */
656 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
657 {
658 return HAL_ERROR;
659 }
660 /*-------------------------- HCLK Configuration --------------------------*/
661 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
662 {
663 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
664 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
665 }
666
667 /*------------------------- SYSCLK Configuration ---------------------------*/
668 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
669 {
670 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
671
672 /* HSE is selected as System Clock Source */
673 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
674 {
675 /* Check the HSE ready flag */
676 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
677 {
678 return HAL_ERROR;
679 }
680 }
681 /* PLL is selected as System Clock Source */
682 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
683 {
684 /* Check the PLL ready flag */
685 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
686 {
687 return HAL_ERROR;
688 }
689 }
690 /* HSI is selected as System Clock Source */
691 else
692 {
693 /* Check the HSI ready flag */
694 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
695 {
696 return HAL_ERROR;
697 }
698 }
699
700 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
701
702 /* Get Start Tick*/
703 tickstart = HAL_GetTick();
704
705 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
706 {
707 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
708 {
709 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
710 {
711 return HAL_TIMEOUT;
712 }
713 }
714 }
715 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
716 {
717 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
718 {
719 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
720 {
721 return HAL_TIMEOUT;
722 }
723 }
724 }
725 else
726 {
727 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
728 {
729 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
730 {
731 return HAL_TIMEOUT;
732 }
733 }
734 }
735 }
736 }
737 /* Decreasing the CPU frequency */
738 else
739 {
740 /*-------------------------- HCLK Configuration --------------------------*/
741 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
742 {
743 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
744 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
745 }
746
747 /*------------------------- SYSCLK Configuration -------------------------*/
748 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
749 {
750 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
751
752 /* HSE is selected as System Clock Source */
753 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
754 {
755 /* Check the HSE ready flag */
756 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
757 {
758 return HAL_ERROR;
759 }
760 }
761 /* PLL is selected as System Clock Source */
762 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
763 {
764 /* Check the PLL ready flag */
765 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
766 {
767 return HAL_ERROR;
768 }
769 }
770 /* HSI is selected as System Clock Source */
771 else
772 {
773 /* Check the HSI ready flag */
774 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
775 {
776 return HAL_ERROR;
777 }
778 }
779
780 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
781
782 /* Get Start Tick*/
783 tickstart = HAL_GetTick();
784
785 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
786 {
787 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
788 {
789 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
790 {
791 return HAL_TIMEOUT;
792 }
793 }
794 }
795 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
796 {
797 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
798 {
799 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
800 {
801 return HAL_TIMEOUT;
802 }
803 }
804 }
805 else
806 {
807 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
808 {
809 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
810 {
811 return HAL_TIMEOUT;
812 }
813 }
814 }
815 }
816
817 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
818 __HAL_FLASH_SET_LATENCY(FLatency);
819
820 /* Check that the new number of wait states is taken into account to access the Flash
821 memory by reading the FLASH_ACR register */
822 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
823 {
824 return HAL_ERROR;
825 }
826 }
827
828 /*-------------------------- PCLK1 Configuration ---------------------------*/
829 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
830 {
831 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
832 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
833 }
834
835 /*-------------------------- PCLK2 Configuration ---------------------------*/
836 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
837 {
838 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
839 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
840 }
841
842 /* Configure the source of time base considering new system clocks settings*/
843 HAL_InitTick (TICK_INT_PRIORITY);
844
845 return HAL_OK;
846 }
847 /**
848 * @}
849 */
850
851 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
852
853 #if defined(STM32F105xC) || defined(STM32F107xC)
854 /** @addtogroup RCC_Exported_Functions_Group2
855 * @{
856 */
857
858 /**
859 * @brief Returns the SYSCLK frequency
860 *
861 * @note The system frequency computed by this function is not the real
862 * frequency in the chip. It is calculated based on the predefined
863 * constant and the selected clock source:
864 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
865 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE
866 * divided by PREDIV factor(**)
867 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE
868 * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
869 * @note (*) HSI_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
870 * 8 MHz).
871 * @note (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
872 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
873 * frequency of the crystal used. Otherwise, this function may
874 * have wrong result.
875 *
876 * @note The result of this function could be not correct when using fractional
877 * value for HSE crystal.
878 *
879 * @note This function can be used by the user application to compute the
880 * baudrate for the communication peripherals or configure other parameters.
881 *
882 * @note Each time SYSCLK changes, this function must be called to update the
883 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
884 *
885 *
886 * @retval SYSCLK frequency
887 */
888 uint32_t HAL_RCC_GetSysClockFreq(void)
889 {
890 const uint8_t aPLLMULFactorTable[12] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 13};
891 const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16};
892
893 uint32_t tmp_reg = 0, prediv1 = 0, pllclk = 0, pllmul = 0;
894 uint32_t sysclockfreq = 0;
895 uint32_t prediv2 = 0, pll2mul = 0;
896
897 tmp_reg = RCC->CFGR;
898
899 /* Get SYSCLK source -------------------------------------------------------*/
900 switch (tmp_reg & RCC_CFGR_SWS)
901 {
902 case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
903 {
904 sysclockfreq = HSE_VALUE;
905 break;
906 }
907 case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
908 {
909 pllmul = aPLLMULFactorTable[(uint32_t)(tmp_reg & RCC_CFGR_PLLMULL) >> POSITION_VAL(RCC_CFGR_PLLMULL)];
910
911 if ((tmp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
912 {
913 prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> POSITION_VAL(RCC_CFGR2_PREDIV1)];
914 if(HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
915 {
916 /* PLL2 selected as Prediv1 source */
917 /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
918 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1;
919 pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> POSITION_VAL(RCC_CFGR2_PLL2MUL)) + 2;
920 pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul);
921 }
922 else
923 {
924 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
925 pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
926 }
927
928 /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
929 /* In this case need to divide pllclk by 2 */
930 if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> POSITION_VAL(RCC_CFGR_PLLMULL)])
931 {
932 pllclk = pllclk / 2;
933 }
934 }
935 else
936 {
937 /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
938 pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
939 }
940 sysclockfreq = pllclk;
941 break;
942 }
943 case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
944 default: /* HSI used as system clock */
945 {
946 sysclockfreq = HSI_VALUE;
947 break;
948 }
949 }
950 return sysclockfreq;
951 }
952
953
954 /**
955 * @brief Configures the RCC_OscInitStruct according to the internal
956 * RCC configuration registers.
957 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
958 * will be configured.
959 * @retval None
960 */
961 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
962 {
963 /* Check the parameters */
964 assert_param(RCC_OscInitStruct != NULL);
965
966 /* Set all possible values for the Oscillator type parameter ---------------*/
967 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \
968 | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
969
970 /* Get the Prediv1 source --------------------------------------------------*/
971 RCC_OscInitStruct->Prediv1Source = READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC);
972
973 /* Get the HSE configuration -----------------------------------------------*/
974 if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
975 {
976 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
977 }
978 else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
979 {
980 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
981 }
982 else
983 {
984 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
985 }
986
987 RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV();
988
989 /* Get the HSI configuration -----------------------------------------------*/
990 if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
991 {
992 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
993 }
994 else
995 {
996 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
997 }
998
999 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
1000
1001 /* Get the LSE configuration -----------------------------------------------*/
1002 if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
1003 {
1004 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
1005 }
1006 else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
1007 {
1008 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
1009 }
1010 else
1011 {
1012 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
1013 }
1014
1015 /* Get the LSI configuration -----------------------------------------------*/
1016 if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
1017 {
1018 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
1019 }
1020 else
1021 {
1022 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
1023 }
1024
1025 /* Get the PLL configuration -----------------------------------------------*/
1026 if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
1027 {
1028 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
1029 }
1030 else
1031 {
1032 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
1033 }
1034 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
1035 RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL);
1036
1037 /* Get the PLL2 configuration -----------------------------------------------*/
1038 if((RCC->CR &RCC_CR_PLL2ON) == RCC_CR_PLL2ON)
1039 {
1040 RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_ON;
1041 }
1042 else
1043 {
1044 RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_OFF;
1045 }
1046 RCC_OscInitStruct->PLL2.HSEPrediv2Value = __HAL_RCC_HSE_GET_PREDIV2();
1047 RCC_OscInitStruct->PLL2.PLL2MUL = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PLL2MUL);
1048 }
1049
1050 /**
1051 * @}
1052 */
1053
1054 #endif /* STM32F105xC || STM32F107xC*/
1055
1056 #if defined (STM32F100xB) || defined (STM32F100xE)
1057 /** @addtogroup RCC_Exported_Functions_Group2
1058 * @{
1059 */
1060
1061 /**
1062 * @brief Returns the SYSCLK frequency
1063 *
1064 * @note The system frequency computed by this function is not the real
1065 * frequency in the chip. It is calculated based on the predefined
1066 * constant and the selected clock source:
1067 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
1068 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE
1069 * divided by PREDIV factor(**)
1070 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE
1071 * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
1072 * @note (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
1073 * 8 MHz).
1074 * @note (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
1075 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
1076 * frequency of the crystal used. Otherwise, this function may
1077 * have wrong result.
1078 *
1079 * @note The result of this function could be not correct when using fractional
1080 * value for HSE crystal.
1081 *
1082 * @note This function can be used by the user application to compute the
1083 * baudrate for the communication peripherals or configure other parameters.
1084 *
1085 * @note Each time SYSCLK changes, this function must be called to update the
1086 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
1087 *
1088 *
1089 * @retval SYSCLK frequency
1090 */
1091 uint32_t HAL_RCC_GetSysClockFreq(void)
1092 {
1093 const uint8_t aPLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
1094 const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16};
1095 uint32_t tmp_reg = 0, prediv1 = 0, pllclk = 0, pllmul = 0;
1096 uint32_t sysclockfreq = 0;
1097
1098 tmp_reg = RCC->CFGR;
1099
1100 /* Get SYSCLK source -------------------------------------------------------*/
1101 switch (tmp_reg & RCC_CFGR_SWS)
1102 {
1103 case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
1104 {
1105 sysclockfreq = HSE_VALUE;
1106 break;
1107 }
1108 case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
1109 {
1110 pllmul = aPLLMULFactorTable[(uint32_t)(tmp_reg & RCC_CFGR_PLLMULL) >> POSITION_VAL(RCC_CFGR_PLLMULL)];
1111 if ((tmp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
1112 {
1113 prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> POSITION_VAL(RCC_CFGR2_PREDIV1)];
1114 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
1115 pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
1116 }
1117 else
1118 {
1119 /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
1120 pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
1121 }
1122 sysclockfreq = pllclk;
1123 break;
1124 }
1125 case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
1126 default: /* HSI used as system clock */
1127 {
1128 sysclockfreq = HSI_VALUE;
1129 break;
1130 }
1131 }
1132 return sysclockfreq;
1133 }
1134 /**
1135 * @}
1136 */
1137
1138 #endif /* STM32F100xB || STM32F100xE*/
1139
1140 #if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || \
1141 defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || \
1142 defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
1143 /** @addtogroup RCC_Exported_Functions_Group2
1144 * @{
1145 */
1146
1147 /**
1148 * @brief Configures the RCC_ClkInitStruct according to the internal
1149 * RCC configuration registers.
1150 * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
1151 * will be configured.
1152 * @param pFLatency: Pointer on the Flash Latency.
1153 * @retval None
1154 */
1155 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
1156 {
1157 /* Check the parameters */
1158 assert_param(RCC_ClkInitStruct != NULL);
1159 assert_param(pFLatency != NULL);
1160
1161 /* Set all possible values for the Clock type parameter --------------------*/
1162 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
1163
1164 /* Get the SYSCLK configuration --------------------------------------------*/
1165 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
1166
1167 /* Get the HCLK configuration ----------------------------------------------*/
1168 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
1169
1170 /* Get the APB1 configuration ----------------------------------------------*/
1171 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
1172
1173 /* Get the APB2 configuration ----------------------------------------------*/
1174 RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
1175
1176 /* Get the Flash Wait State (Latency) configuration ------------------------*/
1177 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
1178 }
1179 /**
1180 * @}
1181 */
1182
1183 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
1184
1185 /**
1186 * @}
1187 */
1188
1189 /**
1190 * @}
1191 */
1192
1193 /** @addtogroup RCCEx
1194 * @{
1195 */
1196
1197 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
1198 * @{
1199 */
1200
1201 /** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions
1202 * @brief Extended Peripheral Control functions
1203 *
1204 @verbatim
1205 ===============================================================================
1206 ##### Extended Peripheral Control functions #####
1207 ===============================================================================
1208 [..]
1209 This subsection provides a set of functions allowing to control the RCC Clocks
1210 frequencies.
1211 [..]
1212 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
1213 select the RTC clock source; in this case the Backup domain will be reset in
1214 order to modify the RTC Clock source, as consequence RTC registers (including
1215 the backup registers) and RCC_BDCR register are set to their reset values.
1216
1217 @endverbatim
1218 * @{
1219 */
1220
1221 /**
1222 * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
1223 * RCC_PeriphCLKInitTypeDef.
1224 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
1225 * contains the configuration information for the Extended Peripherals clocks(RTC clock).
1226 *
1227 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
1228 * the RTC clock source; in this case the Backup domain will be reset in
1229 * order to modify the RTC Clock source, as consequence RTC registers (including
1230 * the backup registers) are set to their reset values.
1231 *
1232 * @note In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on
1233 * one of 2 I2S interfaces. When PLLI2S is enabled, you need to call HAL_RCCEx_DisablePLLI2S to
1234 * manually disable it.
1235 *
1236 * @retval HAL status
1237 */
1238 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
1239 {
1240 uint32_t tickstart = 0, tmp_reg = 0;
1241 #if defined(STM32F105xC) || defined(STM32F107xC)
1242 uint32_t pllactive = 0;
1243 #endif /* STM32F105xC || STM32F107xC */
1244
1245 /* Check the parameters */
1246 assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
1247
1248 /*------------------------------- RTC/LCD Configuration ------------------------*/
1249 if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
1250 {
1251 /* Enable Power Controller clock */
1252 __HAL_RCC_PWR_CLK_ENABLE();
1253
1254 /* Enable write access to Backup domain */
1255 SET_BIT(PWR->CR, PWR_CR_DBP);
1256
1257 /* Wait for Backup domain Write protection disable */
1258 tickstart = HAL_GetTick();
1259
1260 while((PWR->CR & PWR_CR_DBP) == RESET)
1261 {
1262 if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
1263 {
1264 return HAL_TIMEOUT;
1265 }
1266 }
1267
1268 tmp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
1269 /* Reset the Backup domain only if the RTC Clock source selection is modified */
1270 if((tmp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
1271 {
1272 /* Store the content of BDCR register before the reset of Backup Domain */
1273 tmp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
1274 /* RTC Clock selection can be changed only if the Backup Domain is reset */
1275 __HAL_RCC_BACKUPRESET_FORCE();
1276 __HAL_RCC_BACKUPRESET_RELEASE();
1277 /* Restore the Content of BDCR register */
1278 RCC->BDCR = tmp_reg;
1279 }
1280
1281 /* If LSE is selected as RTC clock source, wait for LSE reactivation */
1282 if ((PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE))
1283 {
1284 /* Get timeout */
1285 tickstart = HAL_GetTick();
1286
1287 /* Wait till LSE is ready */
1288 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
1289 {
1290 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
1291 {
1292 return HAL_TIMEOUT;
1293 }
1294 }
1295 }
1296
1297 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
1298 }
1299
1300 /*------------------------------ ADC clock Configuration ------------------*/
1301 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
1302 {
1303 /* Check the parameters */
1304 assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
1305
1306 /* Configure the ADC clock source */
1307 __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
1308 }
1309
1310 #if defined(STM32F105xC) || defined(STM32F107xC)
1311 /*------------------------------ I2S2 Configuration ------------------------*/
1312 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2)
1313 {
1314 /* Check the parameters */
1315 assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection));
1316
1317 /* Configure the I2S2 clock source */
1318 __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection);
1319 }
1320
1321 /*------------------------------ I2S3 Configuration ------------------------*/
1322 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3)
1323 {
1324 /* Check the parameters */
1325 assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection));
1326
1327 /* Configure the I2S3 clock source */
1328 __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection);
1329 }
1330
1331 /*------------------------------ PLL I2S Configuration ----------------------*/
1332 /* Check that PLLI2S need to be enabled */
1333 if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
1334 {
1335 /* Update flag to indicate that PLL I2S should be active */
1336 pllactive = 1;
1337 }
1338
1339 /* Check if PLL I2S need to be enabled */
1340 if (pllactive == 1)
1341 {
1342 /* Enable PLL I2S only if not active */
1343 if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON))
1344 {
1345 /* Check the parameters */
1346 assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL));
1347 assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value));
1348
1349 /* Prediv2 can be written only when the PLL2 is disabled. */
1350 /* Return an error only if new value is different from the programmed value */
1351 if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL2ON) && \
1352 (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value))
1353 {
1354 return HAL_ERROR;
1355 }
1356
1357 /* Configure the HSE prediv2 factor --------------------------------*/
1358 __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value);
1359
1360 /* Configure the main PLLI2S multiplication factors. */
1361 __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL);
1362
1363 /* Enable the main PLLI2S. */
1364 __HAL_RCC_PLLI2S_ENABLE();
1365
1366 /* Get Start Tick*/
1367 tickstart = HAL_GetTick();
1368
1369 /* Wait till PLLI2S is ready */
1370 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
1371 {
1372 if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
1373 {
1374 return HAL_TIMEOUT;
1375 }
1376 }
1377 }
1378 else
1379 {
1380 /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */
1381 if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL)
1382 {
1383 return HAL_ERROR;
1384 }
1385 }
1386 }
1387 #endif /* STM32F105xC || STM32F107xC */
1388
1389 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
1390 defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
1391 /*------------------------------ USB clock Configuration ------------------*/
1392 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
1393 {
1394 /* Check the parameters */
1395 assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
1396
1397 /* Configure the USB clock source */
1398 __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
1399 }
1400 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
1401
1402 return HAL_OK;
1403 }
1404
1405 /**
1406 * @brief Get the PeriphClkInit according to the internal
1407 * RCC configuration registers.
1408 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
1409 * returns the configuration information for the Extended Peripherals clocks(RTC, I2S, ADC clocks).
1410 * @retval None
1411 */
1412 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
1413 {
1414 uint32_t srcclk = 0;
1415
1416 /* Set all possible values for the extended clock type parameter------------*/
1417 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC;
1418
1419 /* Get the RTC configuration -----------------------------------------------*/
1420 srcclk = __HAL_RCC_GET_RTC_SOURCE();
1421 /* Source clock is LSE or LSI*/
1422 PeriphClkInit->RTCClockSelection = srcclk;
1423
1424 /* Get the ADC clock configuration -----------------------------------------*/
1425 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC;
1426 PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
1427
1428 #if defined(STM32F105xC) || defined(STM32F107xC)
1429 /* Get the I2S2 clock configuration -----------------------------------------*/
1430 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2;
1431 PeriphClkInit->I2s2ClockSelection = __HAL_RCC_GET_I2S2_SOURCE();
1432
1433 /* Get the I2S3 clock configuration -----------------------------------------*/
1434 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3;
1435 PeriphClkInit->I2s3ClockSelection = __HAL_RCC_GET_I2S3_SOURCE();
1436
1437 #endif /* STM32F105xC || STM32F107xC */
1438
1439 #if defined(STM32F103xE) || defined(STM32F103xG)
1440 /* Get the I2S2 clock configuration -----------------------------------------*/
1441 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2;
1442 PeriphClkInit->I2s2ClockSelection = RCC_I2S2CLKSOURCE_SYSCLK;
1443
1444 /* Get the I2S3 clock configuration -----------------------------------------*/
1445 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3;
1446 PeriphClkInit->I2s3ClockSelection = RCC_I2S3CLKSOURCE_SYSCLK;
1447
1448 #endif /* STM32F103xE || STM32F103xG */
1449
1450 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
1451 defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
1452 /* Get the USB clock configuration -----------------------------------------*/
1453 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
1454 PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
1455 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
1456 }
1457
1458 /**
1459 * @brief Returns the peripheral clock frequency
1460 * @note Returns 0 if peripheral clock is unknown
1461 * @param PeriphClk: Peripheral clock identifier
1462 * This parameter can be one of the following values:
1463 * @arg RCC_PERIPHCLK_RTC: RTC peripheral clock
1464 * @arg RCC_PERIPHCLK_ADC: ADC peripheral clock
1465 * @arg RCC_PERIPHCLK_I2S2: I2S2 peripheral clock (STM32F103xE, STM32F103xG, STM32F105xC & STM32F107xC)
1466 * @arg RCC_PERIPHCLK_I2S3: I2S3 peripheral clock (STM32F103xE, STM32F103xG, STM32F105xC & STM32F107xC)
1467 * @arg RCC_PERIPHCLK_USB: USB peripheral clock (STM32F102xx, STM32F103xx, STM32F105xC & STM32F107xC)
1468 * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
1469 */
1470 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
1471 {
1472 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
1473 defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
1474 #if defined(STM32F105xC) || defined(STM32F107xC)
1475 const uint8_t aPLLMULFactorTable[12] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 13};
1476 const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16};
1477 #else
1478 const uint8_t aPLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
1479 const uint8_t aPredivFactorTable[2] = { 1, 2};
1480 #endif
1481 #endif
1482 uint32_t tmp_reg = 0, frequency = 0;
1483 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
1484 defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
1485 uint32_t prediv1 = 0, pllclk = 0, pllmul = 0;
1486 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
1487 #if defined(STM32F105xC) || defined(STM32F107xC)
1488 uint32_t pll2mul = 0, pll3mul = 0, prediv2 = 0;
1489 #endif /* STM32F105xC || STM32F107xC */
1490
1491 /* Check the parameters */
1492 assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
1493
1494 switch (PeriphClk)
1495 {
1496 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
1497 defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
1498 case RCC_PERIPHCLK_USB:
1499 {
1500 /* Get RCC configuration ------------------------------------------------------*/
1501 tmp_reg = RCC->CFGR;
1502
1503 /* Check if PLL is enabled */
1504 if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLLON))
1505 {
1506 pllmul = aPLLMULFactorTable[(uint32_t)(tmp_reg & RCC_CFGR_PLLMULL) >> POSITION_VAL(RCC_CFGR_PLLMULL)];
1507 if ((tmp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
1508 {
1509 #if defined(STM32F105xC) || defined(STM32F107xC) || defined (STM32F100xB) || defined (STM32F100xE)
1510 prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> POSITION_VAL(RCC_CFGR2_PREDIV1)];
1511 #else
1512 prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> POSITION_VAL(RCC_CFGR_PLLXTPRE)];
1513 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
1514
1515 #if defined(STM32F105xC) || defined(STM32F107xC)
1516 if(HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
1517 {
1518 /* PLL2 selected as Prediv1 source */
1519 /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
1520 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1;
1521 pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> POSITION_VAL(RCC_CFGR2_PLL2MUL)) + 2;
1522 pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul);
1523 }
1524 else
1525 {
1526 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
1527 pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
1528 }
1529
1530 /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
1531 /* In this case need to divide pllclk by 2 */
1532 if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> POSITION_VAL(RCC_CFGR_PLLMULL)])
1533 {
1534 pllclk = pllclk / 2;
1535 }
1536 #else
1537 if ((tmp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
1538 {
1539 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
1540 pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
1541 }
1542 #endif /* STM32F105xC || STM32F107xC */
1543 }
1544 else
1545 {
1546 /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
1547 pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
1548 }
1549
1550 /* Calcul of the USB frequency*/
1551 #if defined(STM32F105xC) || defined(STM32F107xC)
1552 /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */
1553 if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBPLLCLK_DIV2)
1554 {
1555 /* Prescaler of 2 selected for USB */
1556 frequency = pllclk;
1557 }
1558 else
1559 {
1560 /* Prescaler of 3 selected for USB */
1561 frequency = (2 * pllclk) / 3;
1562 }
1563 #else
1564 /* USBCLK = PLLCLK / USB prescaler */
1565 if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBPLLCLK_DIV1)
1566 {
1567 /* No prescaler selected for USB */
1568 frequency = pllclk;
1569 }
1570 else
1571 {
1572 /* Prescaler of 1.5 selected for USB */
1573 frequency = (pllclk * 2) / 3;
1574 }
1575 #endif
1576 }
1577 break;
1578 }
1579 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
1580 #if defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
1581 case RCC_PERIPHCLK_I2S2:
1582 {
1583 #if defined (STM32F103xE) || defined (STM32F103xG)
1584 /* SYSCLK used as source clock for I2S2 */
1585 frequency = HAL_RCC_GetSysClockFreq();
1586 #else
1587 if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK)
1588 {
1589 /* SYSCLK used as source clock for I2S2 */
1590 frequency = HAL_RCC_GetSysClockFreq();
1591 }
1592 else
1593 {
1594 /* Check if PLLI2S is enabled */
1595 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON))
1596 {
1597 /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
1598 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1;
1599 pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> POSITION_VAL(RCC_CFGR2_PLL3MUL)) + 2;
1600 frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
1601 }
1602 }
1603 #endif /* STM32F103xE || STM32F103xG */
1604 break;
1605 }
1606 case RCC_PERIPHCLK_I2S3:
1607 {
1608 #if defined (STM32F103xE) || defined (STM32F103xG)
1609 /* SYSCLK used as source clock for I2S3 */
1610 frequency = HAL_RCC_GetSysClockFreq();
1611 #else
1612 if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK)
1613 {
1614 /* SYSCLK used as source clock for I2S3 */
1615 frequency = HAL_RCC_GetSysClockFreq();
1616 }
1617 else
1618 {
1619 /* Check if PLLI2S is enabled */
1620 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON))
1621 {
1622 /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
1623 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1;
1624 pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> POSITION_VAL(RCC_CFGR2_PLL3MUL)) + 2;
1625 frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
1626 }
1627 }
1628 #endif /* STM32F103xE || STM32F103xG */
1629 break;
1630 }
1631 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
1632 case RCC_PERIPHCLK_RTC:
1633 {
1634 /* Get RCC BDCR configuration ------------------------------------------------------*/
1635 tmp_reg = RCC->BDCR;
1636
1637 /* Check if LSE is ready if RTC clock selection is LSE */
1638 if (((tmp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(tmp_reg, RCC_BDCR_LSERDY)))
1639 {
1640 frequency = LSE_VALUE;
1641 }
1642 /* Check if LSI is ready if RTC clock selection is LSI */
1643 else if (((tmp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
1644 {
1645 frequency = LSI_VALUE;
1646 }
1647 else if (((tmp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
1648 {
1649 frequency = HSE_VALUE / 128;
1650 }
1651 /* Clock not enabled for RTC*/
1652 else
1653 {
1654 frequency = 0;
1655 }
1656 break;
1657 }
1658 case RCC_PERIPHCLK_ADC:
1659 {
1660 frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> POSITION_VAL(RCC_CFGR_ADCPRE_DIV4)) + 1) * 2);
1661 break;
1662 }
1663 default:
1664 {
1665 break;
1666 }
1667 }
1668 return(frequency);
1669 }
1670
1671 /**
1672 * @}
1673 */
1674
1675 #if defined(STM32F105xC) || defined(STM32F107xC)
1676 /** @defgroup RCCEx_Exported_Functions_Group2 PLLI2S Management function
1677 * @brief PLLI2S Management functions
1678 *
1679 @verbatim
1680 ===============================================================================
1681 ##### Extended PLLI2S Management functions #####
1682 ===============================================================================
1683 [..]
1684 This subsection provides a set of functions allowing to control the PLLI2S
1685 activation or deactivation
1686 @endverbatim
1687 * @{
1688 */
1689
1690 /**
1691 * @brief Enable PLLI2S
1692 * @param PLLI2SInit: pointer to an RCC_PLLI2SInitTypeDef structure that
1693 * contains the configuration information for the PLLI2S
1694 * @note The PLLI2S configuration not modified if used by I2S2 or I2S3 Interface.
1695 * @retval HAL status
1696 */
1697 HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit)
1698 {
1699 uint32_t tickstart = 0;
1700
1701 /* Check that PLL I2S has not been already enabled by I2S2 or I2S3*/
1702 if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
1703 {
1704 /* Check the parameters */
1705 assert_param(IS_RCC_PLLI2S_MUL(PLLI2SInit->PLLI2SMUL));
1706 assert_param(IS_RCC_HSE_PREDIV2(PLLI2SInit->HSEPrediv2Value));
1707
1708 /* Prediv2 can be written only when the PLL2 is disabled. */
1709 /* Return an error only if new value is different from the programmed value */
1710 if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL2ON) && \
1711 (__HAL_RCC_HSE_GET_PREDIV2() != PLLI2SInit->HSEPrediv2Value))
1712 {
1713 return HAL_ERROR;
1714 }
1715
1716 /* Disable the main PLLI2S. */
1717 __HAL_RCC_PLLI2S_DISABLE();
1718
1719 /* Get Start Tick*/
1720 tickstart = HAL_GetTick();
1721
1722 /* Wait till PLLI2S is ready */
1723 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
1724 {
1725 if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
1726 {
1727 return HAL_TIMEOUT;
1728 }
1729 }
1730
1731 /* Configure the HSE prediv2 factor --------------------------------*/
1732 __HAL_RCC_HSE_PREDIV2_CONFIG(PLLI2SInit->HSEPrediv2Value);
1733
1734
1735 /* Configure the main PLLI2S multiplication factors. */
1736 __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SMUL);
1737
1738 /* Enable the main PLLI2S. */
1739 __HAL_RCC_PLLI2S_ENABLE();
1740
1741 /* Get Start Tick*/
1742 tickstart = HAL_GetTick();
1743
1744 /* Wait till PLLI2S is ready */
1745 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
1746 {
1747 if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
1748 {
1749 return HAL_TIMEOUT;
1750 }
1751 }
1752 }
1753 else
1754 {
1755 /* PLLI2S cannot be modified as already used by I2S2 or I2S3 */
1756 return HAL_ERROR;
1757 }
1758
1759 return HAL_OK;
1760 }
1761
1762 /**
1763 * @brief Disable PLLI2S
1764 * @note PLLI2S is not disabled if used by I2S2 or I2S3 Interface.
1765 * @retval HAL status
1766 */
1767 HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
1768 {
1769 uint32_t tickstart = 0;
1770
1771 /* Disable PLL I2S as not requested by I2S2 or I2S3*/
1772 if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
1773 {
1774 /* Disable the main PLLI2S. */
1775 __HAL_RCC_PLLI2S_DISABLE();
1776
1777 /* Get Start Tick*/
1778 tickstart = HAL_GetTick();
1779
1780 /* Wait till PLLI2S is ready */
1781 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
1782 {
1783 if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
1784 {
1785 return HAL_TIMEOUT;
1786 }
1787 }
1788 }
1789 else
1790 {
1791 /* PLLI2S is currently used by I2S2 or I2S3. Cannot be disabled.*/
1792 return HAL_ERROR;
1793 }
1794
1795 return HAL_OK;
1796 }
1797
1798 /**
1799 * @}
1800 */
1801
1802 /** @defgroup RCCEx_Exported_Functions_Group3 PLL2 Management function
1803 * @brief PLL2 Management functions
1804 *
1805 @verbatim
1806 ===============================================================================
1807 ##### Extended PLL2 Management functions #####
1808 ===============================================================================
1809 [..]
1810 This subsection provides a set of functions allowing to control the PLL2
1811 activation or deactivation
1812 @endverbatim
1813 * @{
1814 */
1815
1816 /**
1817 * @brief Enable PLL2
1818 * @param PLL2Init: pointer to an RCC_PLL2InitTypeDef structure that
1819 * contains the configuration information for the PLL2
1820 * @note The PLL2 configuration not modified if used indirectly as system clock.
1821 * @retval HAL status
1822 */
1823 HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init)
1824 {
1825 uint32_t tickstart = 0;
1826
1827 /* This bit can not be cleared if the PLL2 clock is used indirectly as system
1828 clock (i.e. it is used as PLL clock entry that is used as system clock). */
1829 if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
1830 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
1831 ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
1832 {
1833 return HAL_ERROR;
1834 }
1835 else
1836 {
1837 /* Check the parameters */
1838 assert_param(IS_RCC_PLL2_MUL(PLL2Init->PLL2MUL));
1839 assert_param(IS_RCC_HSE_PREDIV2(PLL2Init->HSEPrediv2Value));
1840
1841 /* Prediv2 can be written only when the PLLI2S is disabled. */
1842 /* Return an error only if new value is different from the programmed value */
1843 if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL3ON) && \
1844 (__HAL_RCC_HSE_GET_PREDIV2() != PLL2Init->HSEPrediv2Value))
1845 {
1846 return HAL_ERROR;
1847 }
1848
1849 /* Disable the main PLL2. */
1850 __HAL_RCC_PLL2_DISABLE();
1851
1852 /* Get Start Tick*/
1853 tickstart = HAL_GetTick();
1854
1855 /* Wait till PLL2 is disabled */
1856 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
1857 {
1858 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
1859 {
1860 return HAL_TIMEOUT;
1861 }
1862 }
1863
1864 /* Configure the HSE prediv2 factor --------------------------------*/
1865 __HAL_RCC_HSE_PREDIV2_CONFIG(PLL2Init->HSEPrediv2Value);
1866
1867 /* Configure the main PLL2 multiplication factors. */
1868 __HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2MUL);
1869
1870 /* Enable the main PLL2. */
1871 __HAL_RCC_PLL2_ENABLE();
1872
1873 /* Get Start Tick*/
1874 tickstart = HAL_GetTick();
1875
1876 /* Wait till PLL2 is ready */
1877 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
1878 {
1879 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
1880 {
1881 return HAL_TIMEOUT;
1882 }
1883 }
1884 }
1885
1886 return HAL_OK;
1887 }
1888
1889 /**
1890 * @brief Disable PLL2
1891 * @note PLL2 is not disabled if used indirectly as system clock.
1892 * @retval HAL status
1893 */
1894 HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void)
1895 {
1896 uint32_t tickstart = 0;
1897
1898 /* This bit can not be cleared if the PLL2 clock is used indirectly as system
1899 clock (i.e. it is used as PLL clock entry that is used as system clock). */
1900 if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
1901 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
1902 ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
1903 {
1904 return HAL_ERROR;
1905 }
1906 else
1907 {
1908 /* Disable the main PLL2. */
1909 __HAL_RCC_PLL2_DISABLE();
1910
1911 /* Get Start Tick*/
1912 tickstart = HAL_GetTick();
1913
1914 /* Wait till PLL2 is disabled */
1915 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
1916 {
1917 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
1918 {
1919 return HAL_TIMEOUT;
1920 }
1921 }
1922 }
1923
1924 return HAL_OK;
1925 }
1926
1927 /**
1928 * @}
1929 */
1930 #endif /* STM32F105xC || STM32F107xC */
1931
1932 /**
1933 * @}
1934 */
1935
1936 /**
1937 * @}
1938 */
1939
1940 #endif /* HAL_RCC_MODULE_ENABLED */
1941 /**
1942 * @}
1943 */
1944
1945 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1946
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