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[tmk_keyboard.git] / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_STM / TARGET_STM32F1 / stm32f1xx_hal_rcc_ex.h
1 /**
2 ******************************************************************************
3 * @file stm32f1xx_hal_rcc_ex.h
4 * @author MCD Application Team
5 * @version V1.0.0
6 * @date 15-December-2014
7 * @brief Header file of RCC HAL Extension module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F1xx_HAL_RCC_EX_H
40 #define __STM32F1xx_HAL_RCC_EX_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f1xx_hal_def.h"
48
49 /** @addtogroup STM32F1xx_HAL_Driver
50 * @{
51 */
52
53 /** @addtogroup RCCEx
54 * @{
55 */
56
57 /** @addtogroup RCCEx_Private_Constants
58 * @{
59 */
60
61 #if defined(STM32F105xC) || defined(STM32F107xC)
62
63 /* Alias word address of PLLI2SON bit */
64 #define PLLI2SON_BITNUMBER POSITION_VAL(RCC_CR_PLL3ON)
65 #define RCC_CR_PLLI2SON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLLI2SON_BITNUMBER * 4)))
66
67 /** @defgroup RCCEx_PLL_Timeout PLL I2S Timeout
68 * @{
69 */
70 #define PLLI2S_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
71 /**
72 * @}
73 */
74
75 #endif /* STM32F105xC || STM32F107xC */
76
77 #define CR_REG_INDEX ((uint8_t)1)
78
79 /**
80 * @}
81 */
82
83 /** @addtogroup RCCEx_Private_Macros
84 * @{
85 */
86
87 #if defined(STM32F105xC) || defined(STM32F107xC)
88 #define IS_RCC_PREDIV1_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_PREDIV1_SOURCE_HSE) || \
89 ((__SOURCE__) == RCC_PREDIV1_SOURCE_PLL2))
90 #endif /* STM32F105xC || STM32F107xC */
91
92 #if defined(STM32F105xC) || defined(STM32F107xC) || defined (STM32F100xB) || defined (STM32F100xE)
93 #define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2) || \
94 ((__DIV__) == RCC_HSE_PREDIV_DIV3) || ((__DIV__) == RCC_HSE_PREDIV_DIV4) || \
95 ((__DIV__) == RCC_HSE_PREDIV_DIV5) || ((__DIV__) == RCC_HSE_PREDIV_DIV6) || \
96 ((__DIV__) == RCC_HSE_PREDIV_DIV7) || ((__DIV__) == RCC_HSE_PREDIV_DIV8) || \
97 ((__DIV__) == RCC_HSE_PREDIV_DIV9) || ((__DIV__) == RCC_HSE_PREDIV_DIV10) || \
98 ((__DIV__) == RCC_HSE_PREDIV_DIV11) || ((__DIV__) == RCC_HSE_PREDIV_DIV12) || \
99 ((__DIV__) == RCC_HSE_PREDIV_DIV13) || ((__DIV__) == RCC_HSE_PREDIV_DIV14) || \
100 ((__DIV__) == RCC_HSE_PREDIV_DIV15) || ((__DIV__) == RCC_HSE_PREDIV_DIV16))
101
102 #else
103 #define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2))
104 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
105
106 #if defined(STM32F105xC) || defined(STM32F107xC)
107 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \
108 ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \
109 ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \
110 ((__MUL__) == RCC_PLL_MUL6_5))
111
112 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \
113 || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \
114 || ((__SOURCE__) == RCC_MCO1SOURCE_PLL2CLK) || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK) \
115 || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK_DIV2) || ((__SOURCE__) == RCC_MCO1SOURCE_EXT_HSE) \
116 || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
117
118 #else
119 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \
120 ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \
121 ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \
122 ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \
123 ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \
124 ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \
125 ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \
126 ((__MUL__) == RCC_PLL_MUL16))
127
128 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \
129 || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \
130 || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
131
132 #endif /* STM32F105xC || STM32F107xC*/
133
134 #define IS_RCC_ADCPLLCLK_DIV(__ADCCLK__) (((__ADCCLK__) == RCC_ADCPCLK2_DIV2) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV4) || \
135 ((__ADCCLK__) == RCC_ADCPCLK2_DIV6) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV8))
136
137 #if defined(STM32F105xC) || defined(STM32F107xC)
138 #define IS_RCC_I2S2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLLI2S_VCO))
139
140 #define IS_RCC_I2S3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S3CLKSOURCE_PLLI2S_VCO))
141
142 #define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBPLLCLK_DIV2) || ((__USBCLK__) == RCC_USBPLLCLK_DIV3))
143
144 #define IS_RCC_PLLI2S_MUL(__MUL__) (((__MUL__) == RCC_PLLI2S_MUL8) || ((__MUL__) == RCC_PLLI2S_MUL9) || \
145 ((__MUL__) == RCC_PLLI2S_MUL10) || ((__MUL__) == RCC_PLLI2S_MUL11) || \
146 ((__MUL__) == RCC_PLLI2S_MUL12) || ((__MUL__) == RCC_PLLI2S_MUL13) || \
147 ((__MUL__) == RCC_PLLI2S_MUL14) || ((__MUL__) == RCC_PLLI2S_MUL16) || \
148 ((__MUL__) == RCC_PLLI2S_MUL20))
149
150 #define IS_RCC_HSE_PREDIV2(__DIV__) (((__DIV__) == RCC_HSE_PREDIV2_DIV1) || ((__DIV__) == RCC_HSE_PREDIV2_DIV2) || \
151 ((__DIV__) == RCC_HSE_PREDIV2_DIV3) || ((__DIV__) == RCC_HSE_PREDIV2_DIV4) || \
152 ((__DIV__) == RCC_HSE_PREDIV2_DIV5) || ((__DIV__) == RCC_HSE_PREDIV2_DIV6) || \
153 ((__DIV__) == RCC_HSE_PREDIV2_DIV7) || ((__DIV__) == RCC_HSE_PREDIV2_DIV8) || \
154 ((__DIV__) == RCC_HSE_PREDIV2_DIV9) || ((__DIV__) == RCC_HSE_PREDIV2_DIV10) || \
155 ((__DIV__) == RCC_HSE_PREDIV2_DIV11) || ((__DIV__) == RCC_HSE_PREDIV2_DIV12) || \
156 ((__DIV__) == RCC_HSE_PREDIV2_DIV13) || ((__DIV__) == RCC_HSE_PREDIV2_DIV14) || \
157 ((__DIV__) == RCC_HSE_PREDIV2_DIV15) || ((__DIV__) == RCC_HSE_PREDIV2_DIV16))
158
159 #define IS_RCC_PLL2(__PLL__) (((__PLL__) == RCC_PLL2_NONE) || ((__PLL__) == RCC_PLL2_OFF) || \
160 ((__PLL__) == RCC_PLL2_ON))
161
162 #define IS_RCC_PLL2_MUL(__MUL__) (((__MUL__) == RCC_PLL2_MUL8) || ((__MUL__) == RCC_PLL2_MUL9) || \
163 ((__MUL__) == RCC_PLL2_MUL10) || ((__MUL__) == RCC_PLL2_MUL11) || \
164 ((__MUL__) == RCC_PLL2_MUL12) || ((__MUL__) == RCC_PLL2_MUL13) || \
165 ((__MUL__) == RCC_PLL2_MUL14) || ((__MUL__) == RCC_PLL2_MUL16) || \
166 ((__MUL__) == RCC_PLL2_MUL20))
167
168 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
169 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
170 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
171 (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \
172 (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \
173 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
174
175 #elif defined(STM32F103xE) || defined(STM32F103xG)
176
177 #define IS_RCC_I2S2CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK)
178
179 #define IS_RCC_I2S3CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK)
180
181 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
182 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
183 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
184 (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \
185 (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \
186 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
187
188
189 #elif defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB)
190
191 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
192 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
193 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
194 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
195
196 #else
197
198 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
199 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
200 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC))
201
202 #endif /* STM32F105xC || STM32F107xC */
203
204 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
205
206 #define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBPLLCLK_DIV1) || ((__USBCLK__) == RCC_USBPLLCLK_DIV1_5))
207
208 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
209
210 /**
211 * @}
212 */
213
214 /* Exported types ------------------------------------------------------------*/
215
216 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
217 * @{
218 */
219
220 #if defined(STM32F105xC) || defined(STM32F107xC)
221 /**
222 * @brief RCC PLL2 configuration structure definition
223 */
224 typedef struct
225 {
226 uint32_t PLL2State; /*!< The new state of the PLL2.
227 This parameter can be a value of @ref RCCEx_PLL2_Config */
228
229 uint32_t PLL2MUL; /*!< PLL2MUL: Multiplication factor for PLL2 VCO input clock
230 This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/
231
232 #if defined(STM32F105xC) || defined(STM32F107xC)
233 uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value.
234 This parameter can be a value of @ref RCCEx_Prediv2_Factor */
235
236 #endif /* STM32F105xC || STM32F107xC */
237 } RCC_PLL2InitTypeDef;
238
239 #endif /* STM32F105xC || STM32F107xC */
240
241 /**
242 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
243 */
244 typedef struct
245 {
246 uint32_t OscillatorType; /*!< The oscillators to be configured.
247 This parameter can be a value of @ref RCC_Oscillator_Type */
248
249 #if defined(STM32F105xC) || defined(STM32F107xC)
250 uint32_t Prediv1Source; /*!< The Prediv1 source value.
251 This parameter can be a value of @ref RCCEx_Prediv1_Source */
252 #endif /* STM32F105xC || STM32F107xC */
253
254 uint32_t HSEState; /*!< The new state of the HSE.
255 This parameter can be a value of @ref __HAL_RCC_HSE_CONFIG */
256
257 uint32_t HSEPredivValue; /*!< The Prediv1 factor value (named PREDIV1 or PLLXTPRE in RM)
258 This parameter can be a value of @ref RCCEx_Prediv1_Factor */
259
260 uint32_t LSEState; /*!< The new state of the LSE.
261 This parameter can be a value of @ref __HAL_RCC_LSE_CONFIG */
262
263 uint32_t HSIState; /*!< The new state of the HSI.
264 This parameter can be a value of @ref RCC_HSI_Config */
265
266 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
267 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
268
269 uint32_t LSIState; /*!< The new state of the LSI.
270 This parameter can be a value of @ref RCC_LSI_Config */
271
272 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
273
274 #if defined(STM32F105xC) || defined(STM32F107xC)
275 RCC_PLL2InitTypeDef PLL2; /*!< PLL2 structure parameters */
276 #endif /* STM32F105xC || STM32F107xC */
277 } RCC_OscInitTypeDef;
278
279 #if defined(STM32F105xC) || defined(STM32F107xC)
280 /**
281 * @brief RCC PLLI2S configuration structure definition
282 */
283 typedef struct
284 {
285 uint32_t PLLI2SMUL; /*!< PLLI2SMUL: Multiplication factor for PLLI2S VCO input clock
286 This parameter must be a value of @ref RCCEx_PLLI2S_Multiplication_Factor*/
287
288 #if defined(STM32F105xC) || defined(STM32F107xC)
289 uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value.
290 This parameter can be a value of @ref RCCEx_Prediv2_Factor */
291
292 #endif /* STM32F105xC || STM32F107xC */
293 } RCC_PLLI2SInitTypeDef;
294 #endif /* STM32F105xC || STM32F107xC */
295
296 /**
297 * @brief RCC extended clocks structure definition
298 */
299 typedef struct
300 {
301 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
302 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
303
304 uint32_t RTCClockSelection; /*!< specifies the RTC clock source.
305 This parameter can be a value of @ref RCC_RTC_Clock_Source */
306
307 uint32_t AdcClockSelection; /*!< ADC clock source
308 This parameter can be a value of @ref RCCEx_ADC_Prescaler */
309
310 #if defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
311 uint32_t I2s2ClockSelection; /*!< I2S2 clock source
312 This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */
313
314 uint32_t I2s3ClockSelection; /*!< I2S3 clock source
315 This parameter can be a value of @ref RCCEx_I2S3_Clock_Source */
316
317 #if defined (STM32F105xC) || defined (STM32F107xC)
318 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters
319 This parameter will be used only when PLLI2S is selected as Clock Source I2S2 or I2S3 */
320
321 #endif /* STM32F105xC || STM32F107xC */
322 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
323
324 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
325 defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
326 uint32_t UsbClockSelection; /*!< USB clock source
327 This parameter can be a value of @ref RCCEx_USB_Prescaler */
328
329 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
330 } RCC_PeriphCLKInitTypeDef;
331
332 /**
333 * @}
334 */
335
336 /* Exported constants --------------------------------------------------------*/
337
338 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
339 * @{
340 */
341
342 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
343 * @{
344 */
345 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000001)
346 #define RCC_PERIPHCLK_ADC ((uint32_t)0x00000002)
347 #if defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
348 #define RCC_PERIPHCLK_I2S2 ((uint32_t)0x00000004)
349 #define RCC_PERIPHCLK_I2S3 ((uint32_t)0x00000008)
350 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
351 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
352 defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
353 #define RCC_PERIPHCLK_USB ((uint32_t)0x00000010)
354 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
355
356 /**
357 * @}
358 */
359
360 /** @defgroup RCCEx_ADC_Prescaler ADC Prescaler
361 * @{
362 */
363 #define RCC_ADCPCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
364 #define RCC_ADCPCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
365 #define RCC_ADCPCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
366 #define RCC_ADCPCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8
367
368 /**
369 * @}
370 */
371
372 #if defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
373 /** @defgroup RCCEx_I2S2_Clock_Source I2S2 Clock Source
374 * @{
375 */
376 #define RCC_I2S2CLKSOURCE_SYSCLK ((uint32_t)0x00000000)
377 #if defined(STM32F105xC) || defined(STM32F107xC)
378 #define RCC_I2S2CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S2SRC
379 #endif /* STM32F105xC || STM32F107xC */
380
381 /**
382 * @}
383 */
384
385 /** @defgroup RCCEx_I2S3_Clock_Source I2S3 Clock Source
386 * @{
387 */
388 #define RCC_I2S3CLKSOURCE_SYSCLK ((uint32_t)0x00000000)
389 #if defined(STM32F105xC) || defined(STM32F107xC)
390 #define RCC_I2S3CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S3SRC
391 #endif /* STM32F105xC || STM32F107xC */
392
393 /**
394 * @}
395 */
396
397 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
398
399 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
400
401 /** @defgroup RCCEx_USB_Prescaler USB Prescaler
402 * @{
403 */
404 #define RCC_USBPLLCLK_DIV1 RCC_CFGR_USBPRE
405 #define RCC_USBPLLCLK_DIV1_5 ((uint32_t)0x00000000)
406
407 /**
408 * @}
409 */
410
411 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
412
413
414 #if defined(STM32F105xC) || defined(STM32F107xC)
415 /** @defgroup RCCEx_USB_Prescaler USB Prescaler
416 * @{
417 */
418 #define RCC_USBPLLCLK_DIV2 RCC_CFGR_OTGFSPRE
419 #define RCC_USBPLLCLK_DIV3 ((uint32_t)0x00000000)
420
421 /**
422 * @}
423 */
424
425 /** @defgroup RCCEx_PLLI2S_Multiplication_Factor PLLI2S Multiplication Factor
426 * @{
427 */
428
429 #define RCC_PLLI2S_MUL8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */
430 #define RCC_PLLI2S_MUL9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */
431 #define RCC_PLLI2S_MUL10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */
432 #define RCC_PLLI2S_MUL11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */
433 #define RCC_PLLI2S_MUL12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */
434 #define RCC_PLLI2S_MUL13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */
435 #define RCC_PLLI2S_MUL14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */
436 #define RCC_PLLI2S_MUL16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */
437 #define RCC_PLLI2S_MUL20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */
438
439 /**
440 * @}
441 */
442 #endif /* STM32F105xC || STM32F107xC */
443
444 #if defined(STM32F105xC) || defined(STM32F107xC)
445 /** @defgroup RCCEx_Prediv1_Source Prediv1 Source
446 * @{
447 */
448
449 #define RCC_PREDIV1_SOURCE_HSE RCC_CFGR2_PREDIV1SRC_HSE
450 #define RCC_PREDIV1_SOURCE_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2
451
452 /**
453 * @}
454 */
455 #endif /* STM32F105xC || STM32F107xC */
456
457 /** @defgroup RCCEx_Prediv1_Factor HSE Prediv1 Factor
458 * @{
459 */
460
461 #define RCC_HSE_PREDIV_DIV1 ((uint32_t)0x00000000)
462
463 #if defined(STM32F105xC) || defined(STM32F107xC) || defined (STM32F100xB) || defined (STM32F100xE)
464 #define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV1_DIV2
465 #define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV1_DIV3
466 #define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV1_DIV4
467 #define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV1_DIV5
468 #define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV1_DIV6
469 #define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV1_DIV7
470 #define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV1_DIV8
471 #define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV1_DIV9
472 #define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV1_DIV10
473 #define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV1_DIV11
474 #define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV1_DIV12
475 #define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV1_DIV13
476 #define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV1_DIV14
477 #define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV1_DIV15
478 #define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV1_DIV16
479 #else
480 #define RCC_HSE_PREDIV_DIV2 RCC_CFGR_PLLXTPRE
481 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
482
483 /**
484 * @}
485 */
486
487 #if defined(STM32F105xC) || defined(STM32F107xC)
488 /** @defgroup RCCEx_Prediv2_Factor HSE Prediv2 Factor
489 * @{
490 */
491
492 #define RCC_HSE_PREDIV2_DIV1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */
493 #define RCC_HSE_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */
494 #define RCC_HSE_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */
495 #define RCC_HSE_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */
496 #define RCC_HSE_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */
497 #define RCC_HSE_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */
498 #define RCC_HSE_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */
499 #define RCC_HSE_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */
500 #define RCC_HSE_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */
501 #define RCC_HSE_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */
502 #define RCC_HSE_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */
503 #define RCC_HSE_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */
504 #define RCC_HSE_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */
505 #define RCC_HSE_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */
506 #define RCC_HSE_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */
507 #define RCC_HSE_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */
508
509 /**
510 * @}
511 */
512
513 /** @defgroup RCCEx_PLL2_Config PLL Config
514 * @{
515 */
516 #define RCC_PLL2_NONE ((uint32_t)0x00000000)
517 #define RCC_PLL2_OFF ((uint32_t)0x00000001)
518 #define RCC_PLL2_ON ((uint32_t)0x00000002)
519
520 /**
521 * @}
522 */
523
524 /** @defgroup RCCEx_PLL2_Multiplication_Factor PLL2 Multiplication Factor
525 * @{
526 */
527
528 #define RCC_PLL2_MUL8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */
529 #define RCC_PLL2_MUL9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */
530 #define RCC_PLL2_MUL10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */
531 #define RCC_PLL2_MUL11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */
532 #define RCC_PLL2_MUL12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */
533 #define RCC_PLL2_MUL13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */
534 #define RCC_PLL2_MUL14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */
535 #define RCC_PLL2_MUL16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */
536 #define RCC_PLL2_MUL20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */
537
538 /**
539 * @}
540 */
541
542 #endif /* STM32F105xC || STM32F107xC */
543
544 /** @defgroup RCCEx_PLL_Multiplication_Factor PLL Multiplication Factor
545 * @{
546 */
547
548 #if defined(STM32F105xC) || defined(STM32F107xC)
549 #else
550 #define RCC_PLL_MUL2 RCC_CFGR_PLLMULL2
551 #define RCC_PLL_MUL3 RCC_CFGR_PLLMULL3
552 #endif /* STM32F105xC || STM32F107xC */
553 #define RCC_PLL_MUL4 RCC_CFGR_PLLMULL4
554 #define RCC_PLL_MUL5 RCC_CFGR_PLLMULL5
555 #define RCC_PLL_MUL6 RCC_CFGR_PLLMULL6
556 #define RCC_PLL_MUL7 RCC_CFGR_PLLMULL7
557 #define RCC_PLL_MUL8 RCC_CFGR_PLLMULL8
558 #define RCC_PLL_MUL9 RCC_CFGR_PLLMULL9
559 #if defined(STM32F105xC) || defined(STM32F107xC)
560 #define RCC_PLL_MUL6_5 RCC_CFGR_PLLMULL6_5
561 #else
562 #define RCC_PLL_MUL10 RCC_CFGR_PLLMULL10
563 #define RCC_PLL_MUL11 RCC_CFGR_PLLMULL11
564 #define RCC_PLL_MUL12 RCC_CFGR_PLLMULL12
565 #define RCC_PLL_MUL13 RCC_CFGR_PLLMULL13
566 #define RCC_PLL_MUL14 RCC_CFGR_PLLMULL14
567 #define RCC_PLL_MUL15 RCC_CFGR_PLLMULL15
568 #define RCC_PLL_MUL16 RCC_CFGR_PLLMULL16
569 #endif /* STM32F105xC || STM32F107xC */
570
571 /**
572 * @}
573 */
574
575 /** @defgroup RCCEx_MCO1_Clock_Source MCO1 Clock Source
576 * @{
577 */
578 #define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK)
579 #define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK)
580 #define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI)
581 #define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE)
582 #define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2)
583 #if defined(STM32F105xC) || defined(STM32F107xC)
584 #define RCC_MCO1SOURCE_PLL2CLK ((uint32_t)RCC_CFGR_MCO_PLL2CLK)
585 #define RCC_MCO1SOURCE_PLL3CLK_DIV2 ((uint32_t)RCC_CFGR_MCO_PLL3CLK_DIV2)
586 #define RCC_MCO1SOURCE_EXT_HSE ((uint32_t)RCC_CFGR_MCO_EXT_HSE)
587 #define RCC_MCO1SOURCE_PLL3CLK ((uint32_t)RCC_CFGR_MCO_PLL3CLK)
588 #endif /* STM32F105xC || STM32F107xC*/
589 /**
590 * @}
591 */
592
593 #if defined(STM32F105xC) || defined(STM32F107xC)
594 /** @defgroup RCCEx_Interrupt RCCEx Interrupt
595 * @{
596 */
597 #define RCC_IT_PLL2RDY ((uint8_t)RCC_CIR_PLL2RDYF)
598 #define RCC_IT_PLLI2SRDY ((uint8_t)RCC_CIR_PLL3RDYF)
599 /**
600 * @}
601 */
602
603 /** @defgroup RCCEx_Flag RCCEx Flag
604 * Elements values convention: 0XXYYYYYb
605 * - YYYYY : Flag position in the register
606 * - XX : Register index
607 * - 01: CR register
608 * @{
609 */
610 /* Flags in the CR register */
611 #define RCC_FLAG_PLL2RDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLL2RDY)))
612 #define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLL3RDY)))
613 /**
614 * @}
615 */
616 #endif /* STM32F105xC || STM32F107xC*/
617
618 /**
619 * @}
620 */
621
622 /* Exported macro ------------------------------------------------------------*/
623 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
624 * @{
625 */
626
627 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
628 * @brief Enable or disable the AHB1 peripheral clock.
629 * @note After reset, the peripheral clock (used for registers read/write access)
630 * is disabled and the application software has to enable this clock before
631 * using it.
632 * @{
633 */
634
635 #if defined (STM32F101xE) || defined (STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || \
636 defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F100xE)
637 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
638 __IO uint32_t tmpreg; \
639 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
640 /* Delay after an RCC peripheral clock enabling */ \
641 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
642 UNUSED(tmpreg); \
643 } while(0)
644
645 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
646 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */
647
648 #if defined (STM32F101xE) || defined (STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined (STM32F100xE)
649 #define __HAL_RCC_FSMC_CLK_ENABLE() do { \
650 __IO uint32_t tmpreg; \
651 SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
652 /* Delay after an RCC peripheral clock enabling */ \
653 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
654 UNUSED(tmpreg); \
655 } while(0)
656
657 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))
658 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
659
660 #if defined (STM32F103xE) || defined(STM32F103xG)
661 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \
662 __IO uint32_t tmpreg; \
663 SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
664 /* Delay after an RCC peripheral clock enabling */ \
665 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
666 UNUSED(tmpreg); \
667 } while(0)
668
669
670 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN))
671 #endif /* STM32F103xE || STM32F103xG */
672
673 #if defined(STM32F105xC) || defined(STM32F107xC)
674 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
675 __IO uint32_t tmpreg; \
676 SET_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
677 /* Delay after an RCC peripheral clock enabling */ \
678 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
679 UNUSED(tmpreg); \
680 } while(0)
681
682
683 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_OTGFSEN))
684 #endif /* STM32F105xC || STM32F107xC*/
685
686 #if defined(STM32F107xC)
687 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
688 __IO uint32_t tmpreg; \
689 SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\
690 /* Delay after an RCC peripheral clock enabling */ \
691 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\
692 UNUSED(tmpreg); \
693 } while(0)
694
695 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
696 __IO uint32_t tmpreg; \
697 SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\
698 /* Delay after an RCC peripheral clock enabling */ \
699 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\
700 UNUSED(tmpreg); \
701 } while(0)
702
703 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
704 __IO uint32_t tmpreg; \
705 SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\
706 /* Delay after an RCC peripheral clock enabling */ \
707 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\
708 UNUSED(tmpreg); \
709 } while(0)
710
711 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN))
712 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACTXEN))
713 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACRXEN))
714
715 /**
716 * @brief Enable ETHERNET clock.
717 */
718 #define __HAL_RCC_ETH_CLK_ENABLE() do { \
719 __HAL_RCC_ETHMAC_CLK_ENABLE(); \
720 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
721 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
722 } while(0)
723 /**
724 * @brief Disable ETHERNET clock.
725 */
726 #define __HAL_RCC_ETH_CLK_DISABLE() do { \
727 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
728 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
729 __HAL_RCC_ETHMAC_CLK_DISABLE(); \
730 } while(0)
731
732 #endif /* STM32F107xC*/
733
734 /**
735 * @}
736 */
737
738 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
739 * @brief Get the enable or disable status of the AHB1 peripheral clock.
740 * @note After reset, the peripheral clock (used for registers read/write access)
741 * is disabled and the application software has to enable this clock before
742 * using it.
743 * @{
744 */
745
746 #if defined (STM32F101xE) || defined (STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || \
747 defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F100xE)
748 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
749 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
750 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */
751 #if defined (STM32F101xE) || defined (STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined (STM32F100xE)
752 #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET)
753 #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET)
754 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
755 #if defined (STM32F103xE) || defined(STM32F103xG)
756 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) != RESET)
757 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) == RESET)
758 #endif /* STM32F103xE || STM32F103xG */
759 #if defined(STM32F105xC) || defined(STM32F107xC)
760 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) != RESET)
761 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) == RESET)
762 #endif /* STM32F105xC || STM32F107xC*/
763 #if defined(STM32F107xC)
764 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) != RESET)
765 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) == RESET)
766 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) != RESET)
767 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) == RESET)
768 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) != RESET)
769 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) == RESET)
770 #endif /* STM32F107xC*/
771
772 /**
773 * @}
774 */
775
776 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
777 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
778 * @note After reset, the peripheral clock (used for registers read/write access)
779 * is disabled and the application software has to enable this clock before
780 * using it.
781 * @{
782 */
783
784 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
785 defined(STM32F105xC) ||defined (STM32F107xC)
786 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
787 __IO uint32_t tmpreg; \
788 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
789 /* Delay after an RCC peripheral clock enabling */ \
790 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
791 UNUSED(tmpreg); \
792 } while(0)
793
794 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
795 #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
796
797 #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE) || \
798 defined(STM32F101xG) || defined(STM32F102xB) || defined(STM32F103xB) || defined(STM32F103xE) || \
799 defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
800 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
801 __IO uint32_t tmpreg; \
802 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
803 /* Delay after an RCC peripheral clock enabling */ \
804 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
805 UNUSED(tmpreg); \
806 } while(0)
807
808 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
809 __IO uint32_t tmpreg; \
810 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
811 /* Delay after an RCC peripheral clock enabling */ \
812 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
813 UNUSED(tmpreg); \
814 } while(0)
815
816 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
817 __IO uint32_t tmpreg; \
818 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
819 /* Delay after an RCC peripheral clock enabling */ \
820 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
821 UNUSED(tmpreg); \
822 } while(0)
823
824 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
825 __IO uint32_t tmpreg; \
826 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
827 /* Delay after an RCC peripheral clock enabling */ \
828 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
829 UNUSED(tmpreg); \
830 } while(0)
831
832 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
833 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
834 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
835 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
836 #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
837
838 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
839 #define __HAL_RCC_USB_CLK_ENABLE() do { \
840 __IO uint32_t tmpreg; \
841 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
842 /* Delay after an RCC peripheral clock enabling */ \
843 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
844 UNUSED(tmpreg); \
845 } while(0)
846
847 #define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
848 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
849
850 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || \
851 defined(STM32F105xC) || defined(STM32F107xC)
852 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
853 __IO uint32_t tmpreg; \
854 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
855 /* Delay after an RCC peripheral clock enabling */ \
856 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
857 UNUSED(tmpreg); \
858 } while(0)
859
860 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
861 __IO uint32_t tmpreg; \
862 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
863 /* Delay after an RCC peripheral clock enabling */ \
864 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
865 UNUSED(tmpreg); \
866 } while(0)
867
868 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
869 __IO uint32_t tmpreg; \
870 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
871 /* Delay after an RCC peripheral clock enabling */ \
872 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
873 UNUSED(tmpreg); \
874 } while(0)
875
876 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
877 __IO uint32_t tmpreg; \
878 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
879 /* Delay after an RCC peripheral clock enabling */ \
880 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
881 UNUSED(tmpreg); \
882 } while(0)
883
884 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
885 __IO uint32_t tmpreg; \
886 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
887 /* Delay after an RCC peripheral clock enabling */ \
888 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
889 UNUSED(tmpreg); \
890 } while(0)
891
892 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
893 __IO uint32_t tmpreg; \
894 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
895 /* Delay after an RCC peripheral clock enabling */ \
896 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
897 UNUSED(tmpreg); \
898 } while(0)
899
900 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
901 __IO uint32_t tmpreg; \
902 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
903 /* Delay after an RCC peripheral clock enabling */ \
904 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
905 UNUSED(tmpreg); \
906 } while(0)
907
908 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
909 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
910 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
911 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
912 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
913 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
914 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
915 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
916
917 #if defined(STM32F100xB) || defined (STM32F100xE)
918 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
919 __IO uint32_t tmpreg; \
920 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
921 /* Delay after an RCC peripheral clock enabling */ \
922 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
923 UNUSED(tmpreg); \
924 } while(0)
925
926 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
927 __IO uint32_t tmpreg; \
928 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
929 /* Delay after an RCC peripheral clock enabling */ \
930 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
931 UNUSED(tmpreg); \
932 } while(0)
933
934 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
935 __IO uint32_t tmpreg; \
936 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
937 /* Delay after an RCC peripheral clock enabling */ \
938 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
939 UNUSED(tmpreg); \
940 } while(0)
941
942 #define __HAL_RCC_CEC_CLK_ENABLE() do { \
943 __IO uint32_t tmpreg; \
944 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
945 /* Delay after an RCC peripheral clock enabling */ \
946 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
947 UNUSED(tmpreg); \
948 } while(0)
949
950 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
951 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
952 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
953 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
954 #endif /* STM32F100xB || STM32F100xE */
955
956 #ifdef STM32F100xE
957 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
958 __IO uint32_t tmpreg; \
959 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
960 /* Delay after an RCC peripheral clock enabling */ \
961 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
962 UNUSED(tmpreg); \
963 } while(0)
964
965 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
966 __IO uint32_t tmpreg; \
967 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
968 /* Delay after an RCC peripheral clock enabling */ \
969 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
970 UNUSED(tmpreg); \
971 } while(0)
972
973 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
974 __IO uint32_t tmpreg; \
975 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
976 /* Delay after an RCC peripheral clock enabling */ \
977 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
978 UNUSED(tmpreg); \
979 } while(0)
980
981 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
982 __IO uint32_t tmpreg; \
983 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
984 /* Delay after an RCC peripheral clock enabling */ \
985 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
986 UNUSED(tmpreg); \
987 } while(0)
988
989 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
990 __IO uint32_t tmpreg; \
991 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
992 /* Delay after an RCC peripheral clock enabling */ \
993 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
994 UNUSED(tmpreg); \
995 } while(0)
996
997 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
998 __IO uint32_t tmpreg; \
999 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
1000 /* Delay after an RCC peripheral clock enabling */ \
1001 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
1002 UNUSED(tmpreg); \
1003 } while(0)
1004
1005 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
1006 __IO uint32_t tmpreg; \
1007 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
1008 /* Delay after an RCC peripheral clock enabling */ \
1009 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
1010 UNUSED(tmpreg); \
1011 } while(0)
1012
1013 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
1014 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
1015 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
1016 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
1017 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
1018 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
1019 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
1020 #endif /* STM32F100xE */
1021
1022 #if defined(STM32F105xC) || defined(STM32F107xC)
1023 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \
1024 __IO uint32_t tmpreg; \
1025 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
1026 /* Delay after an RCC peripheral clock enabling */ \
1027 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
1028 UNUSED(tmpreg); \
1029 } while(0)
1030
1031 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
1032 #endif /* STM32F105xC || STM32F107xC */
1033
1034 #if defined(STM32F101xG) || defined(STM32F103xG)
1035 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
1036 __IO uint32_t tmpreg; \
1037 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
1038 /* Delay after an RCC peripheral clock enabling */ \
1039 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
1040 UNUSED(tmpreg); \
1041 } while(0)
1042
1043 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
1044 __IO uint32_t tmpreg; \
1045 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
1046 /* Delay after an RCC peripheral clock enabling */ \
1047 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
1048 UNUSED(tmpreg); \
1049 } while(0)
1050
1051 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
1052 __IO uint32_t tmpreg; \
1053 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
1054 /* Delay after an RCC peripheral clock enabling */ \
1055 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
1056 UNUSED(tmpreg); \
1057 } while(0)
1058
1059 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
1060 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
1061 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
1062 #endif /* STM32F101xG || STM32F103xG*/
1063
1064 /**
1065 * @}
1066 */
1067
1068 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
1069 * @brief Get the enable or disable status of the APB1 peripheral clock.
1070 * @note After reset, the peripheral clock (used for registers read/write access)
1071 * is disabled and the application software has to enable this clock before
1072 * using it.
1073 * @{
1074 */
1075
1076 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
1077 defined(STM32F105xC) ||defined (STM32F107xC)
1078 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
1079 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
1080 #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
1081 #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE) || \
1082 defined(STM32F101xG) || defined(STM32F102xB) || defined(STM32F103xB) || defined(STM32F103xE) || \
1083 defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
1084 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
1085 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
1086 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
1087 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
1088 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
1089 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
1090 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
1091 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
1092 #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
1093 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
1094 #define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
1095 #define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
1096 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
1097 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || \
1098 defined(STM32F105xC) || defined(STM32F107xC)
1099 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
1100 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
1101 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
1102 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
1103 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
1104 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
1105 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
1106 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
1107 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
1108 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
1109 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
1110 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
1111 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
1112 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
1113 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
1114 #if defined(STM32F100xB) || defined (STM32F100xE)
1115 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
1116 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
1117 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
1118 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
1119 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
1120 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
1121 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
1122 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
1123 #endif /* STM32F100xB || STM32F100xE */
1124 #ifdef STM32F100xE
1125 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
1126 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
1127 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
1128 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
1129 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
1130 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
1131 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
1132 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
1133 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
1134 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
1135 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
1136 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
1137 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
1138 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
1139 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
1140 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
1141 #endif /* STM32F100xE */
1142 #if defined(STM32F105xC) || defined(STM32F107xC)
1143 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
1144 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
1145 #endif /* STM32F105xC || STM32F107xC */
1146 #if defined(STM32F101xG) || defined(STM32F103xG)
1147 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
1148 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
1149 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
1150 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
1151 #endif /* STM32F101xG || STM32F103xG*/
1152
1153 /**
1154 * @}
1155 */
1156
1157 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
1158 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
1159 * @note After reset, the peripheral clock (used for registers read/write access)
1160 * is disabled and the application software has to enable this clock before
1161 * using it.
1162 * @{
1163 */
1164
1165 #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || \
1166 defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
1167 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \
1168 __IO uint32_t tmpreg; \
1169 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
1170 /* Delay after an RCC peripheral clock enabling */ \
1171 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
1172 UNUSED(tmpreg); \
1173 } while(0)
1174
1175 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
1176 #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
1177
1178 #if defined (STM32F100xB) || defined (STM32F100xE)
1179 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \
1180 __IO uint32_t tmpreg; \
1181 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
1182 /* Delay after an RCC peripheral clock enabling */ \
1183 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
1184 UNUSED(tmpreg); \
1185 } while(0)
1186
1187 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \
1188 __IO uint32_t tmpreg; \
1189 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
1190 /* Delay after an RCC peripheral clock enabling */ \
1191 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
1192 UNUSED(tmpreg); \
1193 } while(0)
1194
1195 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \
1196 __IO uint32_t tmpreg; \
1197 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
1198 /* Delay after an RCC peripheral clock enabling */ \
1199 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
1200 UNUSED(tmpreg); \
1201 } while(0)
1202
1203 #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
1204 #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
1205 #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
1206 #endif /* STM32F100xB || STM32F100xE */
1207
1208 #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || \
1209 defined(STM32F100xB) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
1210 defined(STM32F105xC) || defined(STM32F107xC)
1211 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
1212 __IO uint32_t tmpreg; \
1213 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
1214 /* Delay after an RCC peripheral clock enabling */ \
1215 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
1216 UNUSED(tmpreg); \
1217 } while(0)
1218
1219 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN))
1220 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
1221
1222 #if defined (STM32F101xE) || defined (STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
1223 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
1224 __IO uint32_t tmpreg; \
1225 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
1226 /* Delay after an RCC peripheral clock enabling */ \
1227 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
1228 UNUSED(tmpreg); \
1229 } while(0)
1230
1231 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
1232 __IO uint32_t tmpreg; \
1233 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
1234 /* Delay after an RCC peripheral clock enabling */ \
1235 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
1236 UNUSED(tmpreg); \
1237 } while(0)
1238
1239 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
1240 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
1241 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
1242
1243 #if defined (STM32F103xE) || defined (STM32F103xG)
1244 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
1245 __IO uint32_t tmpreg; \
1246 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
1247 /* Delay after an RCC peripheral clock enabling */ \
1248 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
1249 UNUSED(tmpreg); \
1250 } while(0)
1251
1252 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \
1253 __IO uint32_t tmpreg; \
1254 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
1255 /* Delay after an RCC peripheral clock enabling */ \
1256 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
1257 UNUSED(tmpreg); \
1258 } while(0)
1259
1260 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
1261 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
1262 #endif /* STM32F103xE || STM32F103xG */
1263
1264 #if defined (STM32F100xE)
1265 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
1266 __IO uint32_t tmpreg; \
1267 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
1268 /* Delay after an RCC peripheral clock enabling */ \
1269 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
1270 UNUSED(tmpreg); \
1271 } while(0)
1272
1273 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
1274 __IO uint32_t tmpreg; \
1275 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
1276 /* Delay after an RCC peripheral clock enabling */ \
1277 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
1278 UNUSED(tmpreg); \
1279 } while(0)
1280
1281 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
1282 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
1283 #endif /* STM32F100xE */
1284
1285 #if defined(STM32F101xG) || defined(STM32F103xG)
1286 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \
1287 __IO uint32_t tmpreg; \
1288 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
1289 /* Delay after an RCC peripheral clock enabling */ \
1290 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
1291 UNUSED(tmpreg); \
1292 } while(0)
1293
1294 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
1295 __IO uint32_t tmpreg; \
1296 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
1297 /* Delay after an RCC peripheral clock enabling */ \
1298 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
1299 UNUSED(tmpreg); \
1300 } while(0)
1301
1302 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \
1303 __IO uint32_t tmpreg; \
1304 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
1305 /* Delay after an RCC peripheral clock enabling */ \
1306 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
1307 UNUSED(tmpreg); \
1308 } while(0)
1309
1310 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
1311 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
1312 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
1313 #endif /* STM32F101xG || STM32F103xG */
1314
1315 /**
1316 * @}
1317 */
1318
1319 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
1320 * @brief Get the enable or disable status of the APB2 peripheral clock.
1321 * @note After reset, the peripheral clock (used for registers read/write access)
1322 * is disabled and the application software has to enable this clock before
1323 * using it.
1324 * @{
1325 */
1326
1327 #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || \
1328 defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
1329 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
1330 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
1331 #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
1332 #if defined (STM32F100xB) || defined (STM32F100xE)
1333 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
1334 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
1335 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
1336 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
1337 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
1338 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
1339 #endif /* STM32F100xB || STM32F100xE */
1340 #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || \
1341 defined(STM32F100xB) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
1342 defined(STM32F105xC) || defined(STM32F107xC)
1343 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET)
1344 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET)
1345 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
1346 #if defined (STM32F101xE) || defined (STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
1347 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
1348 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
1349 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
1350 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
1351 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
1352 #if defined (STM32F103xE) || defined (STM32F103xG)
1353 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
1354 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
1355 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
1356 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
1357 #endif /* STM32F103xE || STM32F103xG */
1358 #if defined (STM32F100xE)
1359 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
1360 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
1361 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
1362 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
1363 #endif /* STM32F100xE */
1364 #if defined(STM32F101xG) || defined(STM32F103xG)
1365 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
1366 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
1367 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
1368 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
1369 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
1370 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
1371 #endif /* STM32F101xG || STM32F103xG */
1372
1373 /**
1374 * @}
1375 */
1376
1377 #if defined(STM32F105xC) || defined(STM32F107xC)
1378 /** @defgroup RCCEx_Peripheral_Clock_Force_Release Peripheral Clock Force Release
1379 * @brief Force or release AHB peripheral reset.
1380 * @{
1381 */
1382 #define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
1383 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_OTGFSRST))
1384 #if defined(STM32F107xC)
1385 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ETHMACRST))
1386 #endif /* STM32F107xC */
1387
1388 #define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
1389 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_OTGFSRST))
1390 #if defined(STM32F107xC)
1391 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ETHMACRST))
1392 #endif /* STM32F107xC */
1393
1394 /**
1395 * @}
1396 */
1397 #endif /* STM32F105xC || STM32F107xC */
1398
1399 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
1400 * @brief Force or release APB1 peripheral reset.
1401 * @{
1402 */
1403
1404 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
1405 defined(STM32F105xC) ||defined (STM32F107xC)
1406 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
1407
1408 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
1409 #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
1410
1411 #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE) || \
1412 defined(STM32F101xG) || defined(STM32F102xB) || defined(STM32F103xB) || defined(STM32F103xE) || \
1413 defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
1414 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
1415 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
1416 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
1417 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
1418
1419 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
1420 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
1421 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
1422 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
1423 #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
1424
1425 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
1426 #define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
1427 #define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
1428 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
1429
1430 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || \
1431 defined(STM32F105xC) || defined(STM32F107xC)
1432 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
1433 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
1434 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
1435 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
1436 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
1437 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
1438 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
1439
1440 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
1441 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
1442 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
1443 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
1444 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
1445 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
1446 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
1447 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
1448
1449 #if defined(STM32F100xB) || defined (STM32F100xE)
1450 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
1451 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
1452 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
1453 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
1454
1455 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
1456 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
1457 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
1458 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
1459 #endif /* STM32F100xB || STM32F100xE */
1460
1461 #if defined (STM32F100xE)
1462 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
1463 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
1464 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
1465 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
1466 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
1467 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
1468 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
1469
1470 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
1471 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
1472 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
1473 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
1474 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
1475 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
1476 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
1477 #endif /* STM32F100xE */
1478
1479 #if defined(STM32F105xC) || defined(STM32F107xC)
1480 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
1481
1482 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
1483 #endif /* STM32F105xC || STM32F107xC */
1484
1485 #if defined(STM32F101xG) || defined(STM32F103xG)
1486 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
1487 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
1488 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
1489
1490 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
1491 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
1492 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
1493 #endif /* STM32F101xG || STM32F103xG */
1494
1495 /**
1496 * @}
1497 */
1498
1499 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
1500 * @brief Force or release APB2 peripheral reset.
1501 * @{
1502 */
1503
1504 #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F105xC) || \
1505 defined(STM32F107xC) || defined(STM32F103xE) || defined(STM32F103xG)
1506 #define __HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST))
1507
1508 #define __HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST))
1509 #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
1510
1511 #if defined (STM32F100xB) || defined (STM32F100xE)
1512 #define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
1513 #define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
1514 #define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
1515
1516 #define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
1517 #define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
1518 #define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
1519 #endif /* STM32F100xB || STM32F100xE */
1520
1521 #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || \
1522 defined(STM32F100xB) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
1523 defined(STM32F105xC) || defined(STM32F107xC)
1524 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST))
1525
1526 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST))
1527 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
1528
1529 #if defined (STM32F101xE) || defined (STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
1530 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST))
1531 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST))
1532
1533 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
1534 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
1535 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
1536
1537 #if defined (STM32F103xE) || defined (STM32F103xG)
1538 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
1539 #define __HAL_RCC_ADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC3RST))
1540
1541 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
1542 #define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC3RST))
1543 #endif /* STM32F103xE || STM32F103xG */
1544
1545 #if defined (STM32F100xE)
1546 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST))
1547 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST))
1548
1549 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
1550 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
1551 #endif /* STM32F100xE */
1552
1553 #if defined(STM32F101xG) || defined(STM32F103xG)
1554 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
1555 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
1556 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
1557
1558 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
1559 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
1560 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
1561 #endif /* STM32F101xG || STM32F103xG*/
1562
1563 /**
1564 * @}
1565 */
1566
1567 /** @defgroup RCCEx_HSE_Configuration HSE Configuration
1568 * @{
1569 */
1570
1571 #if defined(STM32F105xC) || defined(STM32F107xC) || defined (STM32F100xB) || defined (STM32F100xE)
1572 /**
1573 * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
1574 * @note Predivision factor can not be changed if PLL is used as system clock
1575 * In this case, you have to select another source of the system clock, disable the PLL and
1576 * then change the HSE predivision factor.
1577 * @param __HSE_PREDIV_VALUE__: specifies the division value applied to HSE.
1578 * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
1579 */
1580 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (uint32_t)(__HSE_PREDIV_VALUE__))
1581 #else
1582 /**
1583 * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
1584 * @note Predivision factor can not be changed if PLL is used as system clock
1585 * In this case, you have to select another source of the system clock, disable the PLL and
1586 * then change the HSE predivision factor.
1587 * @param __HSE_PREDIV_VALUE__: specifies the division value applied to HSE.
1588 * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV2.
1589 */
1590 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
1591 MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__))
1592
1593 #endif /* STM32F105xC || STM32F107xC */
1594
1595 #if defined(STM32F105xC) || defined(STM32F107xC) || defined (STM32F100xB) || defined (STM32F100xE)
1596 /**
1597 * @brief Macro to get prediv1 factor for PLL.
1598 */
1599 #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1)
1600
1601 #else
1602 /**
1603 * @brief Macro to get prediv1 factor for PLL.
1604 */
1605 #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE)
1606
1607 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
1608
1609 /**
1610 * @}
1611 */
1612
1613 #if defined(STM32F105xC) || defined(STM32F107xC)
1614 /** @defgroup RCCEx_PLLI2S_Configuration PLLI2S Configuration
1615 * @{
1616 */
1617
1618 /** @brief Macros to enable the main PLLI2S.
1619 * @note After enabling the main PLLI2S, the application software should wait on
1620 * PLLI2SRDY flag to be set indicating that PLLI2S clock is stable and can
1621 * be used as system clock source.
1622 * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
1623 */
1624 #define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)
1625
1626 /** @brief Macros to disable the main PLLI2S.
1627 * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
1628 */
1629 #define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)
1630
1631 /** @brief macros to configure the main PLLI2S multiplication factor.
1632 * @note This function must be used only when the main PLLI2S is disabled.
1633 *
1634 * @param __PLLI2SMUL__: specifies the multiplication factor for PLLI2S VCO output clock
1635 * This parameter can be one of the following values:
1636 * @arg RCC_PLLI2S_MUL8: PLLI2SVCO = PLLI2S clock entry x 8
1637 * @arg RCC_PLLI2S_MUL9: PLLI2SVCO = PLLI2S clock entry x 9
1638 * @arg RCC_PLLI2S_MUL10: PLLI2SVCO = PLLI2S clock entry x 10
1639 * @arg RCC_PLLI2S_MUL11: PLLI2SVCO = PLLI2S clock entry x 11
1640 * @arg RCC_PLLI2S_MUL12: PLLI2SVCO = PLLI2S clock entry x 12
1641 * @arg RCC_PLLI2S_MUL13: PLLI2SVCO = PLLI2S clock entry x 13
1642 * @arg RCC_PLLI2S_MUL14: PLLI2SVCO = PLLI2S clock entry x 14
1643 * @arg RCC_PLLI2S_MUL16: PLLI2SVCO = PLLI2S clock entry x 16
1644 * @arg RCC_PLLI2S_MUL20: PLLI2SVCO = PLLI2S clock entry x 20
1645 *
1646 */
1647 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SMUL__)\
1648 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL3MUL,(__PLLI2SMUL__))
1649
1650 /**
1651 * @}
1652 */
1653
1654 #endif /* STM32F105xC || STM32F107xC */
1655
1656 /** @defgroup RCCEx_Peripheral_Configuration Peripheral Configuration
1657 * @brief Macros to configure clock source of different peripherals.
1658 * @{
1659 */
1660
1661 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
1662 /** @brief Macro to configure the USB clock.
1663 * @param __USBCLKSOURCE__: specifies the USB clock source.
1664 * This parameter can be one of the following values:
1665 * @arg RCC_USBPLLCLK_DIV1: PLL clock divided by 1 selected as USB clock
1666 * @arg RCC_USBPLLCLK_DIV1_5: PLL clock divided by 1.5 selected as USB clock
1667 */
1668 #define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
1669 MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__))
1670
1671 /** @brief Macro to get the USB clock (USBCLK).
1672 * @retval The clock source can be one of the following values:
1673 * @arg RCC_USBPLLCLK_DIV1: PLL clock divided by 1 selected as USB clock
1674 * @arg RCC_USBPLLCLK_DIV1_5: PLL clock divided by 1.5 selected as USB clock
1675 */
1676 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
1677
1678 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
1679
1680 #if defined(STM32F105xC) || defined(STM32F107xC)
1681
1682 /** @brief Macro to configure the USB OTSclock.
1683 * @param __USBCLKSOURCE__: specifies the USB clock source.
1684 * This parameter can be one of the following values:
1685 * @arg RCC_USBPLLCLK_DIV2: PLL clock divided by 2 selected as USB OTG FS clock
1686 * @arg RCC_USBPLLCLK_DIV3: PLL clock divided by 3 selected as USB OTG FS clock
1687 */
1688 #define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
1689 MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, (uint32_t)(__USBCLKSOURCE__))
1690
1691 /** @brief Macro to get the USB clock (USBCLK).
1692 * @retval The clock source can be one of the following values:
1693 * @arg RCC_USBPLLCLK_DIV2: PLL clock divided by 2 selected as USB OTG FS clock
1694 * @arg RCC_USBPLLCLK_DIV3: PLL clock divided by 3 selected as USB OTG FS clock
1695 */
1696 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_OTGFSPRE)))
1697
1698 #endif /* STM32F105xC || STM32F107xC */
1699
1700 /** @brief Macro to configure the ADCx clock (x=1 to 3 depending on devices).
1701 * @param __ADCCLKSOURCE__: specifies the ADC clock source.
1702 * This parameter can be one of the following values:
1703 * @arg RCC_ADCPCLK2_DIV2: PCLK2 clock divided by 2 selected as ADC clock
1704 * @arg RCC_ADCPCLK2_DIV4: PCLK2 clock divided by 4 selected as ADC clock
1705 * @arg RCC_ADCPCLK2_DIV6: PCLK2 clock divided by 6 selected as ADC clock
1706 * @arg RCC_ADCPCLK2_DIV8: PCLK2 clock divided by 8 selected as ADC clock
1707 */
1708 #define __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) \
1709 MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__))
1710
1711 /** @brief Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices).
1712 * @retval The clock source can be one of the following values:
1713 * @arg RCC_ADCPCLK2_DIV2: PCLK2 clock divided by 2 selected as ADC clock
1714 * @arg RCC_ADCPCLK2_DIV4: PCLK2 clock divided by 4 selected as ADC clock
1715 * @arg RCC_ADCPCLK2_DIV6: PCLK2 clock divided by 6 selected as ADC clock
1716 * @arg RCC_ADCPCLK2_DIV8: PCLK2 clock divided by 8 selected as ADC clock
1717 */
1718 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
1719
1720 /**
1721 * @}
1722 */
1723
1724 #if defined(STM32F105xC) || defined(STM32F107xC)
1725
1726 /** @addtogroup RCCEx_HSE_Configuration
1727 * @{
1728 */
1729
1730 /**
1731 * @brief Macro to configure the PLL2 & PLLI2S Predivision factor.
1732 * @note Predivision factor can not be changed if PLL2 is used indirectly as system clock
1733 * In this case, you have to select another source of the system clock, disable the PLL2 and PLLI2S and
1734 * then change the PREDIV2 factor.
1735 * @param __HSE_PREDIV2_VALUE__: specifies the PREDIV2 value applied to PLL2 & PLLI2S.
1736 * This parameter must be a number between RCC_HSE_PREDIV2_DIV1 and RCC_HSE_PREDIV2_DIV16.
1737 */
1738 #define __HAL_RCC_HSE_PREDIV2_CONFIG(__HSE_PREDIV2_VALUE__) \
1739 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2, (uint32_t)(__HSE_PREDIV2_VALUE__))
1740
1741 /**
1742 * @brief Macro to get prediv2 factor for PLL2 & PLL3.
1743 */
1744 #define __HAL_RCC_HSE_GET_PREDIV2() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2)
1745
1746 /**
1747 * @}
1748 */
1749
1750 /** @addtogroup RCCEx_PLLI2S_Configuration
1751 * @{
1752 */
1753
1754 /** @brief Macros to enable the main PLL2.
1755 * @note After enabling the main PLL2, the application software should wait on
1756 * PLL2RDY flag to be set indicating that PLL2 clock is stable and can
1757 * be used as system clock source.
1758 * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes.
1759 */
1760 #define __HAL_RCC_PLL2_ENABLE() (*(__IO uint32_t *) CR_PLL2ON_BB = ENABLE)
1761
1762 /** @brief Macros to disable the main PLL2.
1763 * @note The main PLL2 can not be disabled if it is used indirectly as system clock source
1764 * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes.
1765 */
1766 #define __HAL_RCC_PLL2_DISABLE() (*(__IO uint32_t *) CR_PLL2ON_BB = DISABLE)
1767
1768 /** @brief macros to configure the main PLL2 multiplication factor.
1769 * @note This function must be used only when the main PLL2 is disabled.
1770 *
1771 * @param __PLL2MUL__: specifies the multiplication factor for PLL2 VCO output clock
1772 * This parameter can be one of the following values:
1773 * @arg RCC_PLL2_MUL8: PLL2VCO = PLL2 clock entry x 8
1774 * @arg RCC_PLL2_MUL9: PLL2VCO = PLL2 clock entry x 9
1775 * @arg RCC_PLL2_MUL10: PLL2VCO = PLL2 clock entry x 10
1776 * @arg RCC_PLL2_MUL11: PLL2VCO = PLL2 clock entry x 11
1777 * @arg RCC_PLL2_MUL12: PLL2VCO = PLL2 clock entry x 12
1778 * @arg RCC_PLL2_MUL13: PLL2VCO = PLL2 clock entry x 13
1779 * @arg RCC_PLL2_MUL14: PLL2VCO = PLL2 clock entry x 14
1780 * @arg RCC_PLL2_MUL16: PLL2VCO = PLL2 clock entry x 16
1781 * @arg RCC_PLL2_MUL20: PLL2VCO = PLL2 clock entry x 20
1782 *
1783 */
1784 #define __HAL_RCC_PLL2_CONFIG(__PLL2MUL__)\
1785 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL2MUL,(__PLL2MUL__))
1786
1787 /**
1788 * @}
1789 */
1790
1791 /** @defgroup RCCEx_I2S_Configuration I2S Configuration
1792 * @brief Macros to configure clock source of I2S peripherals.
1793 * @{
1794 */
1795
1796 /** @brief Macro to configure the I2S2 clock.
1797 * @param __I2S2CLKSOURCE__: specifies the I2S2 clock source.
1798 * This parameter can be one of the following values:
1799 * @arg RCC_I2S2CLKSOURCE_SYSCLK: system clock selected as I2S3 clock entry
1800 * @arg RCC_I2S2CLKSOURCE_PLLI2S_VCO: PLLI2S VCO clock selected as I2S3 clock entry
1801 */
1802 #define __HAL_RCC_I2S2_CONFIG(__I2S2CLKSOURCE__) \
1803 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S2SRC, (uint32_t)(__I2S2CLKSOURCE__))
1804
1805 /** @brief Macro to get the I2S2 clock (I2S2CLK).
1806 * @retval The clock source can be one of the following values:
1807 * @arg RCC_I2S2CLKSOURCE_SYSCLK: system clock selected as I2S3 clock entry
1808 * @arg RCC_I2S2CLKSOURCE_PLLI2S_VCO: PLLI2S VCO clock selected as I2S3 clock entry
1809 */
1810 #define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S2SRC)))
1811
1812 /** @brief Macro to configure the I2S3 clock.
1813 * @param __I2S2CLKSOURCE__: specifies the I2S3 clock source.
1814 * This parameter can be one of the following values:
1815 * @arg RCC_I2S3CLKSOURCE_SYSCLK: system clock selected as I2S3 clock entry
1816 * @arg RCC_I2S3CLKSOURCE_PLLI2S_VCO: PLLI2S VCO clock selected as I2S3 clock entry
1817 */
1818 #define __HAL_RCC_I2S3_CONFIG(__I2S2CLKSOURCE__) \
1819 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S3SRC, (uint32_t)(__I2S2CLKSOURCE__))
1820
1821 /** @brief Macro to get the I2S3 clock (I2S3CLK).
1822 * @retval The clock source can be one of the following values:
1823 * @arg RCC_I2S3CLKSOURCE_SYSCLK: system clock selected as I2S3 clock entry
1824 * @arg RCC_I2S3CLKSOURCE_PLLI2S_VCO: PLLI2S VCO clock selected as I2S3 clock entry
1825 */
1826 #define __HAL_RCC_GET_I2S3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S3SRC)))
1827
1828 /**
1829 * @}
1830 */
1831
1832 #endif /* STM32F105xC || STM32F107xC */
1833 /**
1834 * @}
1835 */
1836
1837 /* Exported functions --------------------------------------------------------*/
1838 /** @addtogroup RCCEx_Exported_Functions
1839 * @{
1840 */
1841
1842 /** @addtogroup RCCEx_Exported_Functions_Group1
1843 * @{
1844 */
1845
1846 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
1847 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
1848 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
1849
1850 /**
1851 * @}
1852 */
1853
1854 #if defined(STM32F105xC) || defined(STM32F107xC)
1855 /** @addtogroup RCCEx_Exported_Functions_Group2
1856 * @{
1857 */
1858 HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit);
1859 HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);
1860
1861 /**
1862 * @}
1863 */
1864
1865 /** @addtogroup RCCEx_Exported_Functions_Group3
1866 * @{
1867 */
1868 HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init);
1869 HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void);
1870
1871 /**
1872 * @}
1873 */
1874 #endif /* STM32F105xC || STM32F107xC */
1875
1876 /**
1877 * @}
1878 */
1879
1880 /**
1881 * @}
1882 */
1883
1884 /**
1885 * @}
1886 */
1887
1888 #ifdef __cplusplus
1889 }
1890 #endif
1891
1892 #endif /* __STM32F1xx_HAL_RCC_EX_H */
1893
1894 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1895
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