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1 /**
2 ******************************************************************************
3 * @file stm32f1xx_hal_tim.c
4 * @author MCD Application Team
5 * @version V1.0.0
6 * @date 15-December-2014
7 * @brief TIM HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the Timer (TIM) peripheral:
10 * + Time Base Initialization
11 * + Time Base Start
12 * + Time Base Start Interruption
13 * + Time Base Start DMA
14 * + Time Output Compare/PWM Initialization
15 * + Time Output Compare/PWM Channel Configuration
16 * + Time Output Compare/PWM Start
17 * + Time Output Compare/PWM Start Interruption
18 * + Time Output Compare/PWM Start DMA
19 * + Time Input Capture Initialization
20 * + Time Input Capture Channel Configuration
21 * + Time Input Capture Start
22 * + Time Input Capture Start Interruption
23 * + Time Input Capture Start DMA
24 * + Time One Pulse Initialization
25 * + Time One Pulse Channel Configuration
26 * + Time One Pulse Start
27 * + Time Encoder Interface Initialization
28 * + Time Encoder Interface Start
29 * + Time Encoder Interface Start Interruption
30 * + Time Encoder Interface Start DMA
31 * + Commutation Event configuration with Interruption and DMA
32 * + Time OCRef clear configuration
33 * + Time External Clock configuration
34 @verbatim
35 ==============================================================================
36 ##### TIMER Generic features #####
37 ==============================================================================
38 [..] The Timer features include:
39 (#) 16-bit up, down, up/down auto-reload counter.
40 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
41 counter clock frequency either by any factor between 1 and 65536.
42 (#) Up to 4 independent channels for:
43 (++) Input Capture
44 (++) Output Compare
45 (++) PWM generation (Edge and Center-aligned Mode)
46 (++) One-pulse mode output
47
48 ##### How to use this driver #####
49 ==============================================================================
50 [..]
51 (#) Initialize the TIM low level resources by implementing the following functions
52 depending from feature used :
53 (++) Time Base : HAL_TIM_Base_MspInit()
54 (++) Input Capture : HAL_TIM_IC_MspInit()
55 (++) Output Compare : HAL_TIM_OC_MspInit()
56 (++) PWM generation : HAL_TIM_PWM_MspInit()
57 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
58 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
59
60 (#) Initialize the TIM low level resources :
61 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
62 (##) TIM pins configuration
63 (+++) Enable the clock for the TIM GPIOs using the following function:
64 __HAL_GPIOx_CLK_ENABLE();
65 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
66
67 (#) The external Clock can be configured, if needed (the default clock is the
68 internal clock from the APBx), using the following function:
69 HAL_TIM_ConfigClockSource, the clock configuration should be done before
70 any start function.
71
72 (#) Configure the TIM in the desired functioning mode using one of the
73 Initialization function of this driver:
74 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
75 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
76 Output Compare signal.
77 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
78 PWM signal.
79 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
80 external signal.
81 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
82 in One Pulse Mode.
83 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
84
85 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
86 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
87 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
88 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
89 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
90 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
91 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
92
93 (#) The DMA Burst is managed with the two following functions:
94 HAL_TIM_DMABurst_WriteStart()
95 HAL_TIM_DMABurst_ReadStart()
96
97 @endverbatim
98 ******************************************************************************
99 * @attention
100 *
101 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
102 *
103 * Redistribution and use in source and binary forms, with or without modification,
104 * are permitted provided that the following conditions are met:
105 * 1. Redistributions of source code must retain the above copyright notice,
106 * this list of conditions and the following disclaimer.
107 * 2. Redistributions in binary form must reproduce the above copyright notice,
108 * this list of conditions and the following disclaimer in the documentation
109 * and/or other materials provided with the distribution.
110 * 3. Neither the name of STMicroelectronics nor the names of its contributors
111 * may be used to endorse or promote products derived from this software
112 * without specific prior written permission.
113 *
114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
124 *
125 ******************************************************************************
126 */
127
128 /* Includes ------------------------------------------------------------------*/
129 #include "stm32f1xx_hal.h"
130
131 /** @addtogroup STM32F1xx_HAL_Driver
132 * @{
133 */
134
135 /** @defgroup TIM TIM
136 * @brief TIM HAL module driver
137 * @{
138 */
139
140 #ifdef HAL_TIM_MODULE_ENABLED
141
142 /* Private typedef -----------------------------------------------------------*/
143 /* Private define ------------------------------------------------------------*/
144 /* Private macro -------------------------------------------------------------*/
145 /* Private variables ---------------------------------------------------------*/
146 /* Private function prototypes -----------------------------------------------*/
147
148 /** @defgroup TIM_Private_Functions TIM Private Functions
149 * @{
150 */
151 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
152 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
153 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
154 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
155 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
156 uint32_t TIM_ICFilter);
157 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
158 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
159 uint32_t TIM_ICFilter);
160 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
161 uint32_t TIM_ICFilter);
162 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
163 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
164 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
165 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
166 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
167 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
168 TIM_SlaveConfigTypeDef * sSlaveConfig);
169
170 /**
171 * @}
172 */
173
174 /* Exported functions ---------------------------------------------------------*/
175
176 /** @defgroup TIM_Exported_Functions TIM Exported Functions
177 * @{
178 */
179
180 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions
181 * @brief Time Base functions
182 *
183 @verbatim
184 ==============================================================================
185 ##### Time Base functions #####
186 ==============================================================================
187 [..]
188 This section provides functions allowing to:
189 (+) Initialize and configure the TIM base.
190 (+) De-initialize the TIM base.
191 (+) Start the Time Base.
192 (+) Stop the Time Base.
193 (+) Start the Time Base and enable interrupt.
194 (+) Stop the Time Base and disable interrupt.
195 (+) Start the Time Base and enable DMA transfer.
196 (+) Stop the Time Base and disable DMA transfer.
197
198 @endverbatim
199 * @{
200 */
201 /**
202 * @brief Initializes the TIM Time base Unit according to the specified
203 * parameters in the TIM_HandleTypeDef and create the associated handle.
204 * @param htim : TIM Base handle
205 * @retval HAL status
206 */
207 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
208 {
209 /* Check the TIM handle allocation */
210 if(htim == NULL)
211 {
212 return HAL_ERROR;
213 }
214
215 /* Check the parameters */
216 assert_param(IS_TIM_INSTANCE(htim->Instance));
217 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
218 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
219
220 if(htim->State == HAL_TIM_STATE_RESET)
221 {
222 /* Allocate lock resource and initialize it */
223 htim-> Lock = HAL_UNLOCKED;
224
225 /* Init the low level hardware : GPIO, CLOCK, NVIC */
226 HAL_TIM_Base_MspInit(htim);
227 }
228
229 /* Set the TIM state */
230 htim->State= HAL_TIM_STATE_BUSY;
231
232 /* Set the Time Base configuration */
233 TIM_Base_SetConfig(htim->Instance, &htim->Init);
234
235 /* Initialize the TIM state*/
236 htim->State= HAL_TIM_STATE_READY;
237
238 return HAL_OK;
239 }
240
241 /**
242 * @brief DeInitializes the TIM Base peripheral
243 * @param htim : TIM Base handle
244 * @retval HAL status
245 */
246 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
247 {
248 /* Check the parameters */
249 assert_param(IS_TIM_INSTANCE(htim->Instance));
250
251 htim->State = HAL_TIM_STATE_BUSY;
252
253 /* Disable the TIM Peripheral Clock */
254 __HAL_TIM_DISABLE(htim);
255
256 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
257 HAL_TIM_Base_MspDeInit(htim);
258
259 /* Change TIM state */
260 htim->State = HAL_TIM_STATE_RESET;
261
262 /* Release Lock */
263 __HAL_UNLOCK(htim);
264
265 return HAL_OK;
266 }
267
268 /**
269 * @brief Initializes the TIM Base MSP.
270 * @param htim : TIM handle
271 * @retval None
272 */
273 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
274 {
275 /* NOTE : This function Should not be modified, when the callback is needed,
276 the HAL_TIM_Base_MspInit could be implemented in the user file
277 */
278 }
279
280 /**
281 * @brief DeInitializes TIM Base MSP.
282 * @param htim : TIM handle
283 * @retval None
284 */
285 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
286 {
287 /* NOTE : This function Should not be modified, when the callback is needed,
288 the HAL_TIM_Base_MspDeInit could be implemented in the user file
289 */
290 }
291
292
293 /**
294 * @brief Starts the TIM Base generation.
295 * @param htim : TIM handle
296 * @retval HAL status
297 */
298 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
299 {
300 /* Check the parameters */
301 assert_param(IS_TIM_INSTANCE(htim->Instance));
302
303 /* Set the TIM state */
304 htim->State= HAL_TIM_STATE_BUSY;
305
306 /* Enable the Peripheral */
307 __HAL_TIM_ENABLE(htim);
308
309 /* Change the TIM state*/
310 htim->State= HAL_TIM_STATE_READY;
311
312 /* Return function status */
313 return HAL_OK;
314 }
315
316 /**
317 * @brief Stops the TIM Base generation.
318 * @param htim : TIM handle
319 * @retval HAL status
320 */
321 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
322 {
323 /* Check the parameters */
324 assert_param(IS_TIM_INSTANCE(htim->Instance));
325
326 /* Set the TIM state */
327 htim->State= HAL_TIM_STATE_BUSY;
328
329 /* Disable the Peripheral */
330 __HAL_TIM_DISABLE(htim);
331
332 /* Change the TIM state*/
333 htim->State= HAL_TIM_STATE_READY;
334
335 /* Return function status */
336 return HAL_OK;
337 }
338
339 /**
340 * @brief Starts the TIM Base generation in interrupt mode.
341 * @param htim : TIM handle
342 * @retval HAL status
343 */
344 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
345 {
346 /* Check the parameters */
347 assert_param(IS_TIM_INSTANCE(htim->Instance));
348
349 /* Enable the TIM Update interrupt */
350 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
351
352 /* Enable the Peripheral */
353 __HAL_TIM_ENABLE(htim);
354
355 /* Return function status */
356 return HAL_OK;
357 }
358
359 /**
360 * @brief Stops the TIM Base generation in interrupt mode.
361 * @param htim : TIM handle
362 * @retval HAL status
363 */
364 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
365 {
366 /* Check the parameters */
367 assert_param(IS_TIM_INSTANCE(htim->Instance));
368 /* Disable the TIM Update interrupt */
369 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
370
371 /* Disable the Peripheral */
372 __HAL_TIM_DISABLE(htim);
373
374 /* Return function status */
375 return HAL_OK;
376 }
377
378 /**
379 * @brief Starts the TIM Base generation in DMA mode.
380 * @param htim : TIM handle
381 * @param pData : The source Buffer address.
382 * @param Length : The length of data to be transferred from memory to peripheral.
383 * @retval HAL status
384 */
385 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
386 {
387 /* Check the parameters */
388 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
389
390 if((htim->State == HAL_TIM_STATE_BUSY))
391 {
392 return HAL_BUSY;
393 }
394 else if((htim->State == HAL_TIM_STATE_READY))
395 {
396 if((pData == 0 ) && (Length > 0))
397 {
398 return HAL_ERROR;
399 }
400 else
401 {
402 htim->State = HAL_TIM_STATE_BUSY;
403 }
404 }
405 /* Set the DMA Period elapsed callback */
406 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
407
408 /* Set the DMA error callback */
409 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
410
411 /* Enable the DMA channel */
412 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
413
414 /* Enable the TIM Update DMA request */
415 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
416
417 /* Enable the Peripheral */
418 __HAL_TIM_ENABLE(htim);
419
420 /* Return function status */
421 return HAL_OK;
422 }
423
424 /**
425 * @brief Stops the TIM Base generation in DMA mode.
426 * @param htim : TIM handle
427 * @retval HAL status
428 */
429 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
430 {
431 /* Check the parameters */
432 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
433
434 /* Disable the TIM Update DMA request */
435 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
436
437 /* Disable the Peripheral */
438 __HAL_TIM_DISABLE(htim);
439
440 /* Change the htim state */
441 htim->State = HAL_TIM_STATE_READY;
442
443 /* Return function status */
444 return HAL_OK;
445 }
446
447 /**
448 * @}
449 */
450
451 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
452 * @brief Time Output Compare functions
453 *
454 @verbatim
455 ==============================================================================
456 ##### Time Output Compare functions #####
457 ==============================================================================
458 [..]
459 This section provides functions allowing to:
460 (+) Initialize and configure the TIM Output Compare.
461 (+) De-initialize the TIM Output Compare.
462 (+) Start the Time Output Compare.
463 (+) Stop the Time Output Compare.
464 (+) Start the Time Output Compare and enable interrupt.
465 (+) Stop the Time Output Compare and disable interrupt.
466 (+) Start the Time Output Compare and enable DMA transfer.
467 (+) Stop the Time Output Compare and disable DMA transfer.
468
469 @endverbatim
470 * @{
471 */
472 /**
473 * @brief Initializes the TIM Output Compare according to the specified
474 * parameters in the TIM_HandleTypeDef and create the associated handle.
475 * @param htim : TIM Output Compare handle
476 * @retval HAL status
477 */
478 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
479 {
480 /* Check the TIM handle allocation */
481 if(htim == NULL)
482 {
483 return HAL_ERROR;
484 }
485
486 /* Check the parameters */
487 assert_param(IS_TIM_INSTANCE(htim->Instance));
488 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
489 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
490
491 if(htim->State == HAL_TIM_STATE_RESET)
492 {
493 /* Allocate lock resource and initialize it */
494 htim-> Lock = HAL_UNLOCKED;
495
496 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
497 HAL_TIM_OC_MspInit(htim);
498 }
499
500 /* Set the TIM state */
501 htim->State= HAL_TIM_STATE_BUSY;
502
503 /* Init the base time for the Output Compare */
504 TIM_Base_SetConfig(htim->Instance, &htim->Init);
505
506 /* Initialize the TIM state*/
507 htim->State= HAL_TIM_STATE_READY;
508
509 return HAL_OK;
510 }
511
512 /**
513 * @brief DeInitializes the TIM peripheral
514 * @param htim : TIM Output Compare handle
515 * @retval HAL status
516 */
517 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
518 {
519 /* Check the parameters */
520 assert_param(IS_TIM_INSTANCE(htim->Instance));
521
522 htim->State = HAL_TIM_STATE_BUSY;
523
524 /* Disable the TIM Peripheral Clock */
525 __HAL_TIM_DISABLE(htim);
526
527 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
528 HAL_TIM_OC_MspDeInit(htim);
529
530 /* Change TIM state */
531 htim->State = HAL_TIM_STATE_RESET;
532
533 /* Release Lock */
534 __HAL_UNLOCK(htim);
535
536 return HAL_OK;
537 }
538
539 /**
540 * @brief Initializes the TIM Output Compare MSP.
541 * @param htim : TIM handle
542 * @retval None
543 */
544 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
545 {
546 /* NOTE : This function Should not be modified, when the callback is needed,
547 the HAL_TIM_OC_MspInit could be implemented in the user file
548 */
549 }
550
551 /**
552 * @brief DeInitializes TIM Output Compare MSP.
553 * @param htim : TIM handle
554 * @retval None
555 */
556 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
557 {
558 /* NOTE : This function Should not be modified, when the callback is needed,
559 the HAL_TIM_OC_MspDeInit could be implemented in the user file
560 */
561 }
562
563 /**
564 * @brief Starts the TIM Output Compare signal generation.
565 * @param htim : TIM Output Compare handle
566 * @param Channel : TIM Channel to be enabled
567 * This parameter can be one of the following values:
568 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
569 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
570 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
571 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
572 * @retval HAL status
573 */
574 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
575 {
576 /* Check the parameters */
577 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
578
579 /* Enable the Output compare channel */
580 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
581
582 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
583 {
584 /* Enable the main output */
585 __HAL_TIM_MOE_ENABLE(htim);
586 }
587
588 /* Enable the Peripheral */
589 __HAL_TIM_ENABLE(htim);
590
591 /* Return function status */
592 return HAL_OK;
593 }
594
595 /**
596 * @brief Stops the TIM Output Compare signal generation.
597 * @param htim : TIM handle
598 * @param Channel : TIM Channel to be disabled
599 * This parameter can be one of the following values:
600 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
601 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
602 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
603 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
604 * @retval HAL status
605 */
606 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
607 {
608 /* Check the parameters */
609 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
610
611 /* Disable the Output compare channel */
612 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
613
614 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
615 {
616 /* Disable the Main Ouput */
617 __HAL_TIM_MOE_DISABLE(htim);
618 }
619
620 /* Disable the Peripheral */
621 __HAL_TIM_DISABLE(htim);
622
623 /* Return function status */
624 return HAL_OK;
625 }
626
627 /**
628 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
629 * @param htim : TIM OC handle
630 * @param Channel : TIM Channel to be enabled
631 * This parameter can be one of the following values:
632 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
633 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
634 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
635 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
636 * @retval HAL status
637 */
638 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
639 {
640 /* Check the parameters */
641 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
642
643 switch (Channel)
644 {
645 case TIM_CHANNEL_1:
646 {
647 /* Enable the TIM Capture/Compare 1 interrupt */
648 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
649 }
650 break;
651
652 case TIM_CHANNEL_2:
653 {
654 /* Enable the TIM Capture/Compare 2 interrupt */
655 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
656 }
657 break;
658
659 case TIM_CHANNEL_3:
660 {
661 /* Enable the TIM Capture/Compare 3 interrupt */
662 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
663 }
664 break;
665
666 case TIM_CHANNEL_4:
667 {
668 /* Enable the TIM Capture/Compare 4 interrupt */
669 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
670 }
671 break;
672
673 default:
674 break;
675 }
676
677 /* Enable the Output compare channel */
678 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
679
680 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
681 {
682 /* Enable the main output */
683 __HAL_TIM_MOE_ENABLE(htim);
684 }
685
686 /* Enable the Peripheral */
687 __HAL_TIM_ENABLE(htim);
688
689 /* Return function status */
690 return HAL_OK;
691 }
692
693 /**
694 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
695 * @param htim : TIM Output Compare handle
696 * @param Channel : TIM Channel to be disabled
697 * This parameter can be one of the following values:
698 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
699 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
700 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
701 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
702 * @retval HAL status
703 */
704 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
705 {
706 /* Check the parameters */
707 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
708
709 switch (Channel)
710 {
711 case TIM_CHANNEL_1:
712 {
713 /* Disable the TIM Capture/Compare 1 interrupt */
714 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
715 }
716 break;
717
718 case TIM_CHANNEL_2:
719 {
720 /* Disable the TIM Capture/Compare 2 interrupt */
721 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
722 }
723 break;
724
725 case TIM_CHANNEL_3:
726 {
727 /* Disable the TIM Capture/Compare 3 interrupt */
728 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
729 }
730 break;
731
732 case TIM_CHANNEL_4:
733 {
734 /* Disable the TIM Capture/Compare 4 interrupt */
735 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
736 }
737 break;
738
739 default:
740 break;
741 }
742
743 /* Disable the Output compare channel */
744 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
745
746 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
747 {
748 /* Disable the Main Ouput */
749 __HAL_TIM_MOE_DISABLE(htim);
750 }
751
752 /* Disable the Peripheral */
753 __HAL_TIM_DISABLE(htim);
754
755 /* Return function status */
756 return HAL_OK;
757 }
758
759 /**
760 * @brief Starts the TIM Output Compare signal generation in DMA mode.
761 * @param htim : TIM Output Compare handle
762 * @param Channel : TIM Channel to be enabled
763 * This parameter can be one of the following values:
764 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
765 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
766 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
767 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
768 * @param pData : The source Buffer address.
769 * @param Length : The length of data to be transferred from memory to TIM peripheral
770 * @retval HAL status
771 */
772 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
773 {
774 /* Check the parameters */
775 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
776
777 if((htim->State == HAL_TIM_STATE_BUSY))
778 {
779 return HAL_BUSY;
780 }
781 else if((htim->State == HAL_TIM_STATE_READY))
782 {
783 if(((uint32_t)pData == 0 ) && (Length > 0))
784 {
785 return HAL_ERROR;
786 }
787 else
788 {
789 htim->State = HAL_TIM_STATE_BUSY;
790 }
791 }
792 switch (Channel)
793 {
794 case TIM_CHANNEL_1:
795 {
796 /* Set the DMA Period elapsed callback */
797 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
798
799 /* Set the DMA error callback */
800 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
801
802 /* Enable the DMA channel */
803 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
804
805 /* Enable the TIM Capture/Compare 1 DMA request */
806 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
807 }
808 break;
809
810 case TIM_CHANNEL_2:
811 {
812 /* Set the DMA Period elapsed callback */
813 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
814
815 /* Set the DMA error callback */
816 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
817
818 /* Enable the DMA channel */
819 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
820
821 /* Enable the TIM Capture/Compare 2 DMA request */
822 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
823 }
824 break;
825
826 case TIM_CHANNEL_3:
827 {
828 /* Set the DMA Period elapsed callback */
829 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
830
831 /* Set the DMA error callback */
832 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
833
834 /* Enable the DMA channel */
835 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
836
837 /* Enable the TIM Capture/Compare 3 DMA request */
838 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
839 }
840 break;
841
842 case TIM_CHANNEL_4:
843 {
844 /* Set the DMA Period elapsed callback */
845 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
846
847 /* Set the DMA error callback */
848 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
849
850 /* Enable the DMA channel */
851 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
852
853 /* Enable the TIM Capture/Compare 4 DMA request */
854 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
855 }
856 break;
857
858 default:
859 break;
860 }
861
862 /* Enable the Output compare channel */
863 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
864
865 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
866 {
867 /* Enable the main output */
868 __HAL_TIM_MOE_ENABLE(htim);
869 }
870
871 /* Enable the Peripheral */
872 __HAL_TIM_ENABLE(htim);
873
874 /* Return function status */
875 return HAL_OK;
876 }
877
878 /**
879 * @brief Stops the TIM Output Compare signal generation in DMA mode.
880 * @param htim : TIM Output Compare handle
881 * @param Channel : TIM Channel to be disabled
882 * This parameter can be one of the following values:
883 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
884 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
885 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
886 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
887 * @retval HAL status
888 */
889 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
890 {
891 /* Check the parameters */
892 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
893
894 switch (Channel)
895 {
896 case TIM_CHANNEL_1:
897 {
898 /* Disable the TIM Capture/Compare 1 DMA request */
899 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
900 }
901 break;
902
903 case TIM_CHANNEL_2:
904 {
905 /* Disable the TIM Capture/Compare 2 DMA request */
906 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
907 }
908 break;
909
910 case TIM_CHANNEL_3:
911 {
912 /* Disable the TIM Capture/Compare 3 DMA request */
913 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
914 }
915 break;
916
917 case TIM_CHANNEL_4:
918 {
919 /* Disable the TIM Capture/Compare 4 interrupt */
920 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
921 }
922 break;
923
924 default:
925 break;
926 }
927
928 /* Disable the Output compare channel */
929 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
930
931 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
932 {
933 /* Disable the Main Ouput */
934 __HAL_TIM_MOE_DISABLE(htim);
935 }
936
937 /* Disable the Peripheral */
938 __HAL_TIM_DISABLE(htim);
939
940 /* Change the htim state */
941 htim->State = HAL_TIM_STATE_READY;
942
943 /* Return function status */
944 return HAL_OK;
945 }
946
947 /**
948 * @}
949 */
950
951 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
952 * @brief Time PWM functions
953 *
954 @verbatim
955 ==============================================================================
956 ##### Time PWM functions #####
957 ==============================================================================
958 [..]
959 This section provides functions allowing to:
960 (+) Initialize and configure the TIM PWM.
961 (+) De-initialize the TIM PWM.
962 (+) Start the Time PWM.
963 (+) Stop the Time PWM.
964 (+) Start the Time PWM and enable interrupt.
965 (+) Stop the Time PWM and disable interrupt.
966 (+) Start the Time PWM and enable DMA transfer.
967 (+) Stop the Time PWM and disable DMA transfer.
968
969 @endverbatim
970 * @{
971 */
972 /**
973 * @brief Initializes the TIM PWM Time Base according to the specified
974 * parameters in the TIM_HandleTypeDef and create the associated handle.
975 * @param htim : TIM handle
976 * @retval HAL status
977 */
978 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
979 {
980 /* Check the TIM handle allocation */
981 if(htim == NULL)
982 {
983 return HAL_ERROR;
984 }
985
986 /* Check the parameters */
987 assert_param(IS_TIM_INSTANCE(htim->Instance));
988 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
989 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
990
991 if(htim->State == HAL_TIM_STATE_RESET)
992 {
993 /* Allocate lock resource and initialize it */
994 htim-> Lock = HAL_UNLOCKED;
995
996 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
997 HAL_TIM_PWM_MspInit(htim);
998 }
999
1000 /* Set the TIM state */
1001 htim->State= HAL_TIM_STATE_BUSY;
1002
1003 /* Init the base time for the PWM */
1004 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1005
1006 /* Initialize the TIM state*/
1007 htim->State= HAL_TIM_STATE_READY;
1008
1009 return HAL_OK;
1010 }
1011
1012 /**
1013 * @brief DeInitializes the TIM peripheral
1014 * @param htim : TIM handle
1015 * @retval HAL status
1016 */
1017 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
1018 {
1019 /* Check the parameters */
1020 assert_param(IS_TIM_INSTANCE(htim->Instance));
1021
1022 htim->State = HAL_TIM_STATE_BUSY;
1023
1024 /* Disable the TIM Peripheral Clock */
1025 __HAL_TIM_DISABLE(htim);
1026
1027 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1028 HAL_TIM_PWM_MspDeInit(htim);
1029
1030 /* Change TIM state */
1031 htim->State = HAL_TIM_STATE_RESET;
1032
1033 /* Release Lock */
1034 __HAL_UNLOCK(htim);
1035
1036 return HAL_OK;
1037 }
1038
1039 /**
1040 * @brief Initializes the TIM PWM MSP.
1041 * @param htim : TIM handle
1042 * @retval None
1043 */
1044 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1045 {
1046 /* NOTE : This function Should not be modified, when the callback is needed,
1047 the HAL_TIM_PWM_MspInit could be implemented in the user file
1048 */
1049 }
1050
1051 /**
1052 * @brief DeInitializes TIM PWM MSP.
1053 * @param htim : TIM handle
1054 * @retval None
1055 */
1056 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1057 {
1058 /* NOTE : This function Should not be modified, when the callback is needed,
1059 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1060 */
1061 }
1062
1063 /**
1064 * @brief Starts the PWM signal generation.
1065 * @param htim : TIM handle
1066 * @param Channel : TIM Channels to be enabled
1067 * This parameter can be one of the following values:
1068 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1069 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1070 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1071 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1072 * @retval HAL status
1073 */
1074 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1075 {
1076 /* Check the parameters */
1077 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1078
1079 /* Enable the Capture compare channel */
1080 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1081
1082 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1083 {
1084 /* Enable the main output */
1085 __HAL_TIM_MOE_ENABLE(htim);
1086 }
1087
1088 /* Enable the Peripheral */
1089 __HAL_TIM_ENABLE(htim);
1090
1091 /* Return function status */
1092 return HAL_OK;
1093 }
1094
1095 /**
1096 * @brief Stops the PWM signal generation.
1097 * @param htim : TIM handle
1098 * @param Channel : TIM Channels to be disabled
1099 * This parameter can be one of the following values:
1100 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1101 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1102 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1103 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1104 * @retval HAL status
1105 */
1106 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1107 {
1108 /* Check the parameters */
1109 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1110
1111 /* Disable the Capture compare channel */
1112 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1113
1114 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1115 {
1116 /* Disable the Main Ouput */
1117 __HAL_TIM_MOE_DISABLE(htim);
1118 }
1119
1120 /* Disable the Peripheral */
1121 __HAL_TIM_DISABLE(htim);
1122
1123 /* Change the htim state */
1124 htim->State = HAL_TIM_STATE_READY;
1125
1126 /* Return function status */
1127 return HAL_OK;
1128 }
1129
1130 /**
1131 * @brief Starts the PWM signal generation in interrupt mode.
1132 * @param htim : TIM handle
1133 * @param Channel : TIM Channel to be disabled
1134 * This parameter can be one of the following values:
1135 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1136 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1137 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1138 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1139 * @retval HAL status
1140 */
1141 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1142 {
1143 /* Check the parameters */
1144 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1145
1146 switch (Channel)
1147 {
1148 case TIM_CHANNEL_1:
1149 {
1150 /* Enable the TIM Capture/Compare 1 interrupt */
1151 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1152 }
1153 break;
1154
1155 case TIM_CHANNEL_2:
1156 {
1157 /* Enable the TIM Capture/Compare 2 interrupt */
1158 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1159 }
1160 break;
1161
1162 case TIM_CHANNEL_3:
1163 {
1164 /* Enable the TIM Capture/Compare 3 interrupt */
1165 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1166 }
1167 break;
1168
1169 case TIM_CHANNEL_4:
1170 {
1171 /* Enable the TIM Capture/Compare 4 interrupt */
1172 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1173 }
1174 break;
1175
1176 default:
1177 break;
1178 }
1179
1180 /* Enable the Capture compare channel */
1181 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1182
1183 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1184 {
1185 /* Enable the main output */
1186 __HAL_TIM_MOE_ENABLE(htim);
1187 }
1188
1189 /* Enable the Peripheral */
1190 __HAL_TIM_ENABLE(htim);
1191
1192 /* Return function status */
1193 return HAL_OK;
1194 }
1195
1196 /**
1197 * @brief Stops the PWM signal generation in interrupt mode.
1198 * @param htim : TIM handle
1199 * @param Channel : TIM Channels to be disabled
1200 * This parameter can be one of the following values:
1201 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1202 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1203 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1204 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1205 * @retval HAL status
1206 */
1207 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
1208 {
1209 /* Check the parameters */
1210 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1211
1212 switch (Channel)
1213 {
1214 case TIM_CHANNEL_1:
1215 {
1216 /* Disable the TIM Capture/Compare 1 interrupt */
1217 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1218 }
1219 break;
1220
1221 case TIM_CHANNEL_2:
1222 {
1223 /* Disable the TIM Capture/Compare 2 interrupt */
1224 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1225 }
1226 break;
1227
1228 case TIM_CHANNEL_3:
1229 {
1230 /* Disable the TIM Capture/Compare 3 interrupt */
1231 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1232 }
1233 break;
1234
1235 case TIM_CHANNEL_4:
1236 {
1237 /* Disable the TIM Capture/Compare 4 interrupt */
1238 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1239 }
1240 break;
1241
1242 default:
1243 break;
1244 }
1245
1246 /* Disable the Capture compare channel */
1247 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1248
1249 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1250 {
1251 /* Disable the Main Ouput */
1252 __HAL_TIM_MOE_DISABLE(htim);
1253 }
1254
1255 /* Disable the Peripheral */
1256 __HAL_TIM_DISABLE(htim);
1257
1258 /* Return function status */
1259 return HAL_OK;
1260 }
1261
1262 /**
1263 * @brief Starts the TIM PWM signal generation in DMA mode.
1264 * @param htim : TIM handle
1265 * @param Channel : TIM Channels to be enabled
1266 * This parameter can be one of the following values:
1267 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1268 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1269 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1270 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1271 * @param pData : The source Buffer address.
1272 * @param Length : The length of data to be transferred from memory to TIM peripheral
1273 * @retval HAL status
1274 */
1275 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1276 {
1277 /* Check the parameters */
1278 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1279
1280 if((htim->State == HAL_TIM_STATE_BUSY))
1281 {
1282 return HAL_BUSY;
1283 }
1284 else if((htim->State == HAL_TIM_STATE_READY))
1285 {
1286 if(((uint32_t)pData == 0 ) && (Length > 0))
1287 {
1288 return HAL_ERROR;
1289 }
1290 else
1291 {
1292 htim->State = HAL_TIM_STATE_BUSY;
1293 }
1294 }
1295 switch (Channel)
1296 {
1297 case TIM_CHANNEL_1:
1298 {
1299 /* Set the DMA Period elapsed callback */
1300 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1301
1302 /* Set the DMA error callback */
1303 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1304
1305 /* Enable the DMA channel */
1306 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
1307
1308 /* Enable the TIM Capture/Compare 1 DMA request */
1309 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1310 }
1311 break;
1312
1313 case TIM_CHANNEL_2:
1314 {
1315 /* Set the DMA Period elapsed callback */
1316 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1317
1318 /* Set the DMA error callback */
1319 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1320
1321 /* Enable the DMA channel */
1322 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
1323
1324 /* Enable the TIM Capture/Compare 2 DMA request */
1325 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1326 }
1327 break;
1328
1329 case TIM_CHANNEL_3:
1330 {
1331 /* Set the DMA Period elapsed callback */
1332 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1333
1334 /* Set the DMA error callback */
1335 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1336
1337 /* Enable the DMA channel */
1338 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
1339
1340 /* Enable the TIM Output Capture/Compare 3 request */
1341 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1342 }
1343 break;
1344
1345 case TIM_CHANNEL_4:
1346 {
1347 /* Set the DMA Period elapsed callback */
1348 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1349
1350 /* Set the DMA error callback */
1351 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1352
1353 /* Enable the DMA channel */
1354 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
1355
1356 /* Enable the TIM Capture/Compare 4 DMA request */
1357 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1358 }
1359 break;
1360
1361 default:
1362 break;
1363 }
1364
1365 /* Enable the Capture compare channel */
1366 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1367
1368 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1369 {
1370 /* Enable the main output */
1371 __HAL_TIM_MOE_ENABLE(htim);
1372 }
1373
1374 /* Enable the Peripheral */
1375 __HAL_TIM_ENABLE(htim);
1376
1377 /* Return function status */
1378 return HAL_OK;
1379 }
1380
1381 /**
1382 * @brief Stops the TIM PWM signal generation in DMA mode.
1383 * @param htim : TIM handle
1384 * @param Channel : TIM Channels to be disabled
1385 * This parameter can be one of the following values:
1386 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1387 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1388 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1389 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1390 * @retval HAL status
1391 */
1392 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1393 {
1394 /* Check the parameters */
1395 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1396
1397 switch (Channel)
1398 {
1399 case TIM_CHANNEL_1:
1400 {
1401 /* Disable the TIM Capture/Compare 1 DMA request */
1402 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1403 }
1404 break;
1405
1406 case TIM_CHANNEL_2:
1407 {
1408 /* Disable the TIM Capture/Compare 2 DMA request */
1409 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1410 }
1411 break;
1412
1413 case TIM_CHANNEL_3:
1414 {
1415 /* Disable the TIM Capture/Compare 3 DMA request */
1416 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1417 }
1418 break;
1419
1420 case TIM_CHANNEL_4:
1421 {
1422 /* Disable the TIM Capture/Compare 4 interrupt */
1423 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1424 }
1425 break;
1426
1427 default:
1428 break;
1429 }
1430
1431 /* Disable the Capture compare channel */
1432 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1433
1434 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1435 {
1436 /* Disable the Main Ouput */
1437 __HAL_TIM_MOE_DISABLE(htim);
1438 }
1439
1440 /* Disable the Peripheral */
1441 __HAL_TIM_DISABLE(htim);
1442
1443 /* Change the htim state */
1444 htim->State = HAL_TIM_STATE_READY;
1445
1446 /* Return function status */
1447 return HAL_OK;
1448 }
1449
1450 /**
1451 * @}
1452 */
1453
1454 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
1455 * @brief Time Input Capture functions
1456 *
1457 @verbatim
1458 ==============================================================================
1459 ##### Time Input Capture functions #####
1460 ==============================================================================
1461 [..]
1462 This section provides functions allowing to:
1463 (+) Initialize and configure the TIM Input Capture.
1464 (+) De-initialize the TIM Input Capture.
1465 (+) Start the Time Input Capture.
1466 (+) Stop the Time Input Capture.
1467 (+) Start the Time Input Capture and enable interrupt.
1468 (+) Stop the Time Input Capture and disable interrupt.
1469 (+) Start the Time Input Capture and enable DMA transfer.
1470 (+) Stop the Time Input Capture and disable DMA transfer.
1471
1472 @endverbatim
1473 * @{
1474 */
1475 /**
1476 * @brief Initializes the TIM Input Capture Time base according to the specified
1477 * parameters in the TIM_HandleTypeDef and create the associated handle.
1478 * @param htim : TIM Input Capture handle
1479 * @retval HAL status
1480 */
1481 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
1482 {
1483 /* Check the TIM handle allocation */
1484 if(htim == NULL)
1485 {
1486 return HAL_ERROR;
1487 }
1488
1489 /* Check the parameters */
1490 assert_param(IS_TIM_INSTANCE(htim->Instance));
1491 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1492 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1493
1494 if(htim->State == HAL_TIM_STATE_RESET)
1495 {
1496 /* Allocate lock resource and initialize it */
1497 htim-> Lock = HAL_UNLOCKED;
1498
1499 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1500 HAL_TIM_IC_MspInit(htim);
1501 }
1502
1503 /* Set the TIM state */
1504 htim->State= HAL_TIM_STATE_BUSY;
1505
1506 /* Init the base time for the input capture */
1507 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1508
1509 /* Initialize the TIM state*/
1510 htim->State= HAL_TIM_STATE_READY;
1511
1512 return HAL_OK;
1513 }
1514
1515 /**
1516 * @brief DeInitializes the TIM peripheral
1517 * @param htim : TIM Input Capture handle
1518 * @retval HAL status
1519 */
1520 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
1521 {
1522 /* Check the parameters */
1523 assert_param(IS_TIM_INSTANCE(htim->Instance));
1524
1525 htim->State = HAL_TIM_STATE_BUSY;
1526
1527 /* Disable the TIM Peripheral Clock */
1528 __HAL_TIM_DISABLE(htim);
1529
1530 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1531 HAL_TIM_IC_MspDeInit(htim);
1532
1533 /* Change TIM state */
1534 htim->State = HAL_TIM_STATE_RESET;
1535
1536 /* Release Lock */
1537 __HAL_UNLOCK(htim);
1538
1539 return HAL_OK;
1540 }
1541
1542 /**
1543 * @brief Initializes the TIM Input Capture MSP.
1544 * @param htim : TIM handle
1545 * @retval None
1546 */
1547 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
1548 {
1549 /* NOTE : This function Should not be modified, when the callback is needed,
1550 the HAL_TIM_IC_MspInit could be implemented in the user file
1551 */
1552 }
1553
1554 /**
1555 * @brief DeInitializes TIM Input Capture MSP.
1556 * @param htim : TIM handle
1557 * @retval None
1558 */
1559 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
1560 {
1561 /* NOTE : This function Should not be modified, when the callback is needed,
1562 the HAL_TIM_IC_MspDeInit could be implemented in the user file
1563 */
1564 }
1565
1566 /**
1567 * @brief Starts the TIM Input Capture measurement.
1568 * @param htim : TIM Input Capture handle
1569 * @param Channel : TIM Channels to be enabled
1570 * This parameter can be one of the following values:
1571 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1572 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1573 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1574 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1575 * @retval HAL status
1576 */
1577 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
1578 {
1579 /* Check the parameters */
1580 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1581
1582 /* Enable the Input Capture channel */
1583 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1584
1585 /* Enable the Peripheral */
1586 __HAL_TIM_ENABLE(htim);
1587
1588 /* Return function status */
1589 return HAL_OK;
1590 }
1591
1592 /**
1593 * @brief Stops the TIM Input Capture measurement.
1594 * @param htim : TIM handle
1595 * @param Channel : TIM Channels to be disabled
1596 * This parameter can be one of the following values:
1597 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1598 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1599 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1600 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1601 * @retval HAL status
1602 */
1603 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1604 {
1605 /* Check the parameters */
1606 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1607
1608 /* Disable the Input Capture channel */
1609 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1610
1611 /* Disable the Peripheral */
1612 __HAL_TIM_DISABLE(htim);
1613
1614 /* Return function status */
1615 return HAL_OK;
1616 }
1617
1618 /**
1619 * @brief Starts the TIM Input Capture measurement in interrupt mode.
1620 * @param htim : TIM Input Capture handle
1621 * @param Channel : TIM Channels to be enabled
1622 * This parameter can be one of the following values:
1623 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1624 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1625 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1626 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1627 * @retval HAL status
1628 */
1629 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
1630 {
1631 /* Check the parameters */
1632 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1633
1634 switch (Channel)
1635 {
1636 case TIM_CHANNEL_1:
1637 {
1638 /* Enable the TIM Capture/Compare 1 interrupt */
1639 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1640 }
1641 break;
1642
1643 case TIM_CHANNEL_2:
1644 {
1645 /* Enable the TIM Capture/Compare 2 interrupt */
1646 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1647 }
1648 break;
1649
1650 case TIM_CHANNEL_3:
1651 {
1652 /* Enable the TIM Capture/Compare 3 interrupt */
1653 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1654 }
1655 break;
1656
1657 case TIM_CHANNEL_4:
1658 {
1659 /* Enable the TIM Capture/Compare 4 interrupt */
1660 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1661 }
1662 break;
1663
1664 default:
1665 break;
1666 }
1667 /* Enable the Input Capture channel */
1668 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1669
1670 /* Enable the Peripheral */
1671 __HAL_TIM_ENABLE(htim);
1672
1673 /* Return function status */
1674 return HAL_OK;
1675 }
1676
1677 /**
1678 * @brief Stops the TIM Input Capture measurement in interrupt mode.
1679 * @param htim : TIM handle
1680 * @param Channel : TIM Channels to be disabled
1681 * This parameter can be one of the following values:
1682 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1683 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1684 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1685 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1686 * @retval HAL status
1687 */
1688 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1689 {
1690 /* Check the parameters */
1691 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1692
1693 switch (Channel)
1694 {
1695 case TIM_CHANNEL_1:
1696 {
1697 /* Disable the TIM Capture/Compare 1 interrupt */
1698 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1699 }
1700 break;
1701
1702 case TIM_CHANNEL_2:
1703 {
1704 /* Disable the TIM Capture/Compare 2 interrupt */
1705 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1706 }
1707 break;
1708
1709 case TIM_CHANNEL_3:
1710 {
1711 /* Disable the TIM Capture/Compare 3 interrupt */
1712 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1713 }
1714 break;
1715
1716 case TIM_CHANNEL_4:
1717 {
1718 /* Disable the TIM Capture/Compare 4 interrupt */
1719 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1720 }
1721 break;
1722
1723 default:
1724 break;
1725 }
1726
1727 /* Disable the Input Capture channel */
1728 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1729
1730 /* Disable the Peripheral */
1731 __HAL_TIM_DISABLE(htim);
1732
1733 /* Return function status */
1734 return HAL_OK;
1735 }
1736
1737 /**
1738 * @brief Starts the TIM Input Capture measurement in DMA mode.
1739 * @param htim : TIM Input Capture handle
1740 * @param Channel : TIM Channels to be enabled
1741 * This parameter can be one of the following values:
1742 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1743 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1744 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1745 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1746 * @param pData : The destination Buffer address.
1747 * @param Length : The length of data to be transferred from TIM peripheral to memory.
1748 * @retval HAL status
1749 */
1750 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1751 {
1752 /* Check the parameters */
1753 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1754 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
1755
1756 if((htim->State == HAL_TIM_STATE_BUSY))
1757 {
1758 return HAL_BUSY;
1759 }
1760 else if((htim->State == HAL_TIM_STATE_READY))
1761 {
1762 if((pData == 0 ) && (Length > 0))
1763 {
1764 return HAL_ERROR;
1765 }
1766 else
1767 {
1768 htim->State = HAL_TIM_STATE_BUSY;
1769 }
1770 }
1771
1772 switch (Channel)
1773 {
1774 case TIM_CHANNEL_1:
1775 {
1776 /* Set the DMA Period elapsed callback */
1777 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
1778
1779 /* Set the DMA error callback */
1780 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1781
1782 /* Enable the DMA channel */
1783 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
1784
1785 /* Enable the TIM Capture/Compare 1 DMA request */
1786 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1787 }
1788 break;
1789
1790 case TIM_CHANNEL_2:
1791 {
1792 /* Set the DMA Period elapsed callback */
1793 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
1794
1795 /* Set the DMA error callback */
1796 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1797
1798 /* Enable the DMA channel */
1799 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
1800
1801 /* Enable the TIM Capture/Compare 2 DMA request */
1802 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1803 }
1804 break;
1805
1806 case TIM_CHANNEL_3:
1807 {
1808 /* Set the DMA Period elapsed callback */
1809 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
1810
1811 /* Set the DMA error callback */
1812 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1813
1814 /* Enable the DMA channel */
1815 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
1816
1817 /* Enable the TIM Capture/Compare 3 DMA request */
1818 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1819 }
1820 break;
1821
1822 case TIM_CHANNEL_4:
1823 {
1824 /* Set the DMA Period elapsed callback */
1825 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
1826
1827 /* Set the DMA error callback */
1828 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1829
1830 /* Enable the DMA channel */
1831 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
1832
1833 /* Enable the TIM Capture/Compare 4 DMA request */
1834 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1835 }
1836 break;
1837
1838 default:
1839 break;
1840 }
1841
1842 /* Enable the Input Capture channel */
1843 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1844
1845 /* Enable the Peripheral */
1846 __HAL_TIM_ENABLE(htim);
1847
1848 /* Return function status */
1849 return HAL_OK;
1850 }
1851
1852 /**
1853 * @brief Stops the TIM Input Capture measurement in DMA mode.
1854 * @param htim : TIM Input Capture handle
1855 * @param Channel : TIM Channels to be disabled
1856 * This parameter can be one of the following values:
1857 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1858 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1859 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1860 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1861 * @retval HAL status
1862 */
1863 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1864 {
1865 /* Check the parameters */
1866 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1867 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
1868
1869 switch (Channel)
1870 {
1871 case TIM_CHANNEL_1:
1872 {
1873 /* Disable the TIM Capture/Compare 1 DMA request */
1874 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1875 }
1876 break;
1877
1878 case TIM_CHANNEL_2:
1879 {
1880 /* Disable the TIM Capture/Compare 2 DMA request */
1881 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1882 }
1883 break;
1884
1885 case TIM_CHANNEL_3:
1886 {
1887 /* Disable the TIM Capture/Compare 3 DMA request */
1888 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1889 }
1890 break;
1891
1892 case TIM_CHANNEL_4:
1893 {
1894 /* Disable the TIM Capture/Compare 4 DMA request */
1895 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1896 }
1897 break;
1898
1899 default:
1900 break;
1901 }
1902
1903 /* Disable the Input Capture channel */
1904 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1905
1906 /* Disable the Peripheral */
1907 __HAL_TIM_DISABLE(htim);
1908
1909 /* Change the htim state */
1910 htim->State = HAL_TIM_STATE_READY;
1911
1912 /* Return function status */
1913 return HAL_OK;
1914 }
1915 /**
1916 * @}
1917 */
1918
1919 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
1920 * @brief Time One Pulse functions
1921 *
1922 @verbatim
1923 ==============================================================================
1924 ##### Time One Pulse functions #####
1925 ==============================================================================
1926 [..]
1927 This section provides functions allowing to:
1928 (+) Initialize and configure the TIM One Pulse.
1929 (+) De-initialize the TIM One Pulse.
1930 (+) Start the Time One Pulse.
1931 (+) Stop the Time One Pulse.
1932 (+) Start the Time One Pulse and enable interrupt.
1933 (+) Stop the Time One Pulse and disable interrupt.
1934 (+) Start the Time One Pulse and enable DMA transfer.
1935 (+) Stop the Time One Pulse and disable DMA transfer.
1936
1937 @endverbatim
1938 * @{
1939 */
1940 /**
1941 * @brief Initializes the TIM One Pulse Time Base according to the specified
1942 * parameters in the TIM_HandleTypeDef and create the associated handle.
1943 * @param htim : TIM OnePulse handle
1944 * @param OnePulseMode : Select the One pulse mode.
1945 * This parameter can be one of the following values:
1946 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
1947 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
1948 * @retval HAL status
1949 */
1950 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
1951 {
1952 /* Check the TIM handle allocation */
1953 if(htim == NULL)
1954 {
1955 return HAL_ERROR;
1956 }
1957
1958 /* Check the parameters */
1959 assert_param(IS_TIM_INSTANCE(htim->Instance));
1960 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1961 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1962 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
1963
1964 if(htim->State == HAL_TIM_STATE_RESET)
1965 {
1966 /* Allocate lock resource and initialize it */
1967 htim-> Lock = HAL_UNLOCKED;
1968
1969 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1970 HAL_TIM_OnePulse_MspInit(htim);
1971 }
1972
1973 /* Set the TIM state */
1974 htim->State= HAL_TIM_STATE_BUSY;
1975
1976 /* Configure the Time base in the One Pulse Mode */
1977 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1978
1979 /* Reset the OPM Bit */
1980 htim->Instance->CR1 &= ~TIM_CR1_OPM;
1981
1982 /* Configure the OPM Mode */
1983 htim->Instance->CR1 |= OnePulseMode;
1984
1985 /* Initialize the TIM state*/
1986 htim->State= HAL_TIM_STATE_READY;
1987
1988 return HAL_OK;
1989 }
1990
1991 /**
1992 * @brief DeInitializes the TIM One Pulse
1993 * @param htim : TIM One Pulse handle
1994 * @retval HAL status
1995 */
1996 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
1997 {
1998 /* Check the parameters */
1999 assert_param(IS_TIM_INSTANCE(htim->Instance));
2000
2001 htim->State = HAL_TIM_STATE_BUSY;
2002
2003 /* Disable the TIM Peripheral Clock */
2004 __HAL_TIM_DISABLE(htim);
2005
2006 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2007 HAL_TIM_OnePulse_MspDeInit(htim);
2008
2009 /* Change TIM state */
2010 htim->State = HAL_TIM_STATE_RESET;
2011
2012 /* Release Lock */
2013 __HAL_UNLOCK(htim);
2014
2015 return HAL_OK;
2016 }
2017
2018 /**
2019 * @brief Initializes the TIM One Pulse MSP.
2020 * @param htim : TIM handle
2021 * @retval None
2022 */
2023 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
2024 {
2025 /* NOTE : This function Should not be modified, when the callback is needed,
2026 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
2027 */
2028 }
2029
2030 /**
2031 * @brief DeInitializes TIM One Pulse MSP.
2032 * @param htim : TIM handle
2033 * @retval None
2034 */
2035 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
2036 {
2037 /* NOTE : This function Should not be modified, when the callback is needed,
2038 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2039 */
2040 }
2041
2042 /**
2043 * @brief Starts the TIM One Pulse signal generation.
2044 * @param htim : TIM One Pulse handle
2045 * @param OutputChannel : TIM Channels to be enabled
2046 * This parameter can be one of the following values:
2047 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2048 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2049 * @retval HAL status
2050 */
2051 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2052 {
2053 /* Enable the Capture compare and the Input Capture channels
2054 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2055 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2056 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2057 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2058
2059 No need to enable the counter, it's enabled automatically by hardware
2060 (the counter starts in response to a stimulus and generate a pulse */
2061
2062 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2063 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2064
2065 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2066 {
2067 /* Enable the main output */
2068 __HAL_TIM_MOE_ENABLE(htim);
2069 }
2070
2071 /* Return function status */
2072 return HAL_OK;
2073 }
2074
2075 /**
2076 * @brief Stops the TIM One Pulse signal generation.
2077 * @param htim : TIM One Pulse handle
2078 * @param OutputChannel : TIM Channels to be disable
2079 * This parameter can be one of the following values:
2080 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2081 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2082 * @retval HAL status
2083 */
2084 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2085 {
2086 /* Disable the Capture compare and the Input Capture channels
2087 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2088 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2089 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2090 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2091
2092 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2093 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2094
2095 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2096 {
2097 /* Disable the Main Ouput */
2098 __HAL_TIM_MOE_DISABLE(htim);
2099 }
2100
2101 /* Disable the Peripheral */
2102 __HAL_TIM_DISABLE(htim);
2103
2104 /* Return function status */
2105 return HAL_OK;
2106 }
2107
2108 /**
2109 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2110 * @param htim : TIM One Pulse handle
2111 * @param OutputChannel : TIM Channels to be enabled
2112 * This parameter can be one of the following values:
2113 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2114 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2115 * @retval HAL status
2116 */
2117 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2118 {
2119 /* Enable the Capture compare and the Input Capture channels
2120 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2121 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2122 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2123 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2124
2125 No need to enable the counter, it's enabled automatically by hardware
2126 (the counter starts in response to a stimulus and generate a pulse */
2127
2128 /* Enable the TIM Capture/Compare 1 interrupt */
2129 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2130
2131 /* Enable the TIM Capture/Compare 2 interrupt */
2132 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2133
2134 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2135 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2136
2137 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2138 {
2139 /* Enable the main output */
2140 __HAL_TIM_MOE_ENABLE(htim);
2141 }
2142
2143 /* Return function status */
2144 return HAL_OK;
2145 }
2146
2147 /**
2148 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2149 * @param htim : TIM One Pulse handle
2150 * @param OutputChannel : TIM Channels to be enabled
2151 * This parameter can be one of the following values:
2152 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2153 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2154 * @retval HAL status
2155 */
2156 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2157 {
2158 /* Disable the TIM Capture/Compare 1 interrupt */
2159 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2160
2161 /* Disable the TIM Capture/Compare 2 interrupt */
2162 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2163
2164 /* Disable the Capture compare and the Input Capture channels
2165 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2166 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2167 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2168 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2169 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2170 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2171
2172 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2173 {
2174 /* Disable the Main Ouput */
2175 __HAL_TIM_MOE_DISABLE(htim);
2176 }
2177
2178 /* Disable the Peripheral */
2179 __HAL_TIM_DISABLE(htim);
2180
2181 /* Return function status */
2182 return HAL_OK;
2183 }
2184
2185 /**
2186 * @}
2187 */
2188
2189 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
2190 * @brief Time Encoder functions
2191 *
2192 @verbatim
2193 ==============================================================================
2194 ##### Time Encoder functions #####
2195 ==============================================================================
2196 [..]
2197 This section provides functions allowing to:
2198 (+) Initialize and configure the TIM Encoder.
2199 (+) De-initialize the TIM Encoder.
2200 (+) Start the Time Encoder.
2201 (+) Stop the Time Encoder.
2202 (+) Start the Time Encoder and enable interrupt.
2203 (+) Stop the Time Encoder and disable interrupt.
2204 (+) Start the Time Encoder and enable DMA transfer.
2205 (+) Stop the Time Encoder and disable DMA transfer.
2206
2207 @endverbatim
2208 * @{
2209 */
2210 /**
2211 * @brief Initializes the TIM Encoder Interface and create the associated handle.
2212 * @param htim : TIM Encoder Interface handle
2213 * @param sConfig : TIM Encoder Interface configuration structure
2214 * @retval HAL status
2215 */
2216 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
2217 {
2218 uint32_t tmpsmcr = 0;
2219 uint32_t tmpccmr1 = 0;
2220 uint32_t tmpccer = 0;
2221
2222 /* Check the TIM handle allocation */
2223 if(htim == NULL)
2224 {
2225 return HAL_ERROR;
2226 }
2227
2228 /* Check the parameters */
2229 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2230 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
2231 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
2232 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
2233 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
2234 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
2235 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
2236 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
2237 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
2238 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
2239
2240 if(htim->State == HAL_TIM_STATE_RESET)
2241 {
2242 /* Allocate lock resource and initialize it */
2243 htim-> Lock = HAL_UNLOCKED;
2244
2245 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2246 HAL_TIM_Encoder_MspInit(htim);
2247 }
2248
2249 /* Set the TIM state */
2250 htim->State= HAL_TIM_STATE_BUSY;
2251
2252 /* Reset the SMS bits */
2253 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
2254
2255 /* Configure the Time base in the Encoder Mode */
2256 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2257
2258 /* Get the TIMx SMCR register value */
2259 tmpsmcr = htim->Instance->SMCR;
2260
2261 /* Get the TIMx CCMR1 register value */
2262 tmpccmr1 = htim->Instance->CCMR1;
2263
2264 /* Get the TIMx CCER register value */
2265 tmpccer = htim->Instance->CCER;
2266
2267 /* Set the encoder Mode */
2268 tmpsmcr |= sConfig->EncoderMode;
2269
2270 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
2271 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
2272 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
2273
2274 /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
2275 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
2276 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
2277 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
2278 tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
2279
2280 /* Set the TI1 and the TI2 Polarities */
2281 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
2282 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
2283 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
2284
2285 /* Write to TIMx SMCR */
2286 htim->Instance->SMCR = tmpsmcr;
2287
2288 /* Write to TIMx CCMR1 */
2289 htim->Instance->CCMR1 = tmpccmr1;
2290
2291 /* Write to TIMx CCER */
2292 htim->Instance->CCER = tmpccer;
2293
2294 /* Initialize the TIM state*/
2295 htim->State= HAL_TIM_STATE_READY;
2296
2297 return HAL_OK;
2298 }
2299
2300
2301 /**
2302 * @brief DeInitializes the TIM Encoder interface
2303 * @param htim : TIM Encoder handle
2304 * @retval HAL status
2305 */
2306 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
2307 {
2308 /* Check the parameters */
2309 assert_param(IS_TIM_INSTANCE(htim->Instance));
2310
2311 htim->State = HAL_TIM_STATE_BUSY;
2312
2313 /* Disable the TIM Peripheral Clock */
2314 __HAL_TIM_DISABLE(htim);
2315
2316 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2317 HAL_TIM_Encoder_MspDeInit(htim);
2318
2319 /* Change TIM state */
2320 htim->State = HAL_TIM_STATE_RESET;
2321
2322 /* Release Lock */
2323 __HAL_UNLOCK(htim);
2324
2325 return HAL_OK;
2326 }
2327
2328 /**
2329 * @brief Initializes the TIM Encoder Interface MSP.
2330 * @param htim : TIM handle
2331 * @retval None
2332 */
2333 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
2334 {
2335 /* NOTE : This function Should not be modified, when the callback is needed,
2336 the HAL_TIM_Encoder_MspInit could be implemented in the user file
2337 */
2338 }
2339
2340 /**
2341 * @brief DeInitializes TIM Encoder Interface MSP.
2342 * @param htim : TIM handle
2343 * @retval None
2344 */
2345 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
2346 {
2347 /* NOTE : This function Should not be modified, when the callback is needed,
2348 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
2349 */
2350 }
2351
2352 /**
2353 * @brief Starts the TIM Encoder Interface.
2354 * @param htim : TIM Encoder Interface handle
2355 * @param Channel : TIM Channels to be enabled
2356 * This parameter can be one of the following values:
2357 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2358 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2359 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2360 * @retval HAL status
2361 */
2362 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2363 {
2364 /* Check the parameters */
2365 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2366
2367 /* Enable the encoder interface channels */
2368 switch (Channel)
2369 {
2370 case TIM_CHANNEL_1:
2371 {
2372 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2373 break;
2374 }
2375 case TIM_CHANNEL_2:
2376 {
2377 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2378 break;
2379 }
2380 default :
2381 {
2382 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2383 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2384 break;
2385 }
2386 }
2387 /* Enable the Peripheral */
2388 __HAL_TIM_ENABLE(htim);
2389
2390 /* Return function status */
2391 return HAL_OK;
2392 }
2393
2394 /**
2395 * @brief Stops the TIM Encoder Interface.
2396 * @param htim : TIM Encoder Interface handle
2397 * @param Channel : TIM Channels to be disabled
2398 * This parameter can be one of the following values:
2399 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2400 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2401 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2402 * @retval HAL status
2403 */
2404 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2405 {
2406 /* Check the parameters */
2407 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2408
2409 /* Disable the Input Capture channels 1 and 2
2410 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2411 switch (Channel)
2412 {
2413 case TIM_CHANNEL_1:
2414 {
2415 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2416 break;
2417 }
2418 case TIM_CHANNEL_2:
2419 {
2420 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2421 break;
2422 }
2423 default :
2424 {
2425 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2426 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2427 break;
2428 }
2429 }
2430
2431 /* Disable the Peripheral */
2432 __HAL_TIM_DISABLE(htim);
2433
2434 /* Return function status */
2435 return HAL_OK;
2436 }
2437
2438 /**
2439 * @brief Starts the TIM Encoder Interface in interrupt mode.
2440 * @param htim : TIM Encoder Interface handle
2441 * @param Channel : TIM Channels to be enabled
2442 * This parameter can be one of the following values:
2443 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2444 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2445 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2446 * @retval HAL status
2447 */
2448 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2449 {
2450 /* Check the parameters */
2451 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2452
2453 /* Enable the encoder interface channels */
2454 /* Enable the capture compare Interrupts 1 and/or 2 */
2455 switch (Channel)
2456 {
2457 case TIM_CHANNEL_1:
2458 {
2459 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2460 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2461 break;
2462 }
2463 case TIM_CHANNEL_2:
2464 {
2465 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2466 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2467 break;
2468 }
2469 default :
2470 {
2471 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2472 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2473 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2474 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2475 break;
2476 }
2477 }
2478
2479 /* Enable the Peripheral */
2480 __HAL_TIM_ENABLE(htim);
2481
2482 /* Return function status */
2483 return HAL_OK;
2484 }
2485
2486 /**
2487 * @brief Stops the TIM Encoder Interface in interrupt mode.
2488 * @param htim : TIM Encoder Interface handle
2489 * @param Channel : TIM Channels to be disabled
2490 * This parameter can be one of the following values:
2491 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2492 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2493 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2494 * @retval HAL status
2495 */
2496 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2497 {
2498 /* Check the parameters */
2499 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2500
2501 /* Disable the Input Capture channels 1 and 2
2502 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2503 if(Channel == TIM_CHANNEL_1)
2504 {
2505 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2506
2507 /* Disable the capture compare Interrupts 1 */
2508 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2509 }
2510 else if(Channel == TIM_CHANNEL_2)
2511 {
2512 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2513
2514 /* Disable the capture compare Interrupts 2 */
2515 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2516 }
2517 else
2518 {
2519 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2520 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2521
2522 /* Disable the capture compare Interrupts 1 and 2 */
2523 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2524 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2525 }
2526
2527 /* Disable the Peripheral */
2528 __HAL_TIM_DISABLE(htim);
2529
2530 /* Change the htim state */
2531 htim->State = HAL_TIM_STATE_READY;
2532
2533 /* Return function status */
2534 return HAL_OK;
2535 }
2536
2537 /**
2538 * @brief Starts the TIM Encoder Interface in DMA mode.
2539 * @param htim : TIM Encoder Interface handle
2540 * @param Channel : TIM Channels to be enabled
2541 * This parameter can be one of the following values:
2542 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2543 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2544 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2545 * @param pData1 : The destination Buffer address for IC1.
2546 * @param pData2 : The destination Buffer address for IC2.
2547 * @param Length : The length of data to be transferred from TIM peripheral to memory.
2548 * @retval HAL status
2549 */
2550 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
2551 {
2552 /* Check the parameters */
2553 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2554
2555 if((htim->State == HAL_TIM_STATE_BUSY))
2556 {
2557 return HAL_BUSY;
2558 }
2559 else if((htim->State == HAL_TIM_STATE_READY))
2560 {
2561 if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
2562 {
2563 return HAL_ERROR;
2564 }
2565 else
2566 {
2567 htim->State = HAL_TIM_STATE_BUSY;
2568 }
2569 }
2570
2571 switch (Channel)
2572 {
2573 case TIM_CHANNEL_1:
2574 {
2575 /* Set the DMA Period elapsed callback */
2576 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2577
2578 /* Set the DMA error callback */
2579 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2580
2581 /* Enable the DMA channel */
2582 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
2583
2584 /* Enable the TIM Input Capture DMA request */
2585 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2586
2587 /* Enable the Peripheral */
2588 __HAL_TIM_ENABLE(htim);
2589
2590 /* Enable the Capture compare channel */
2591 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2592 }
2593 break;
2594
2595 case TIM_CHANNEL_2:
2596 {
2597 /* Set the DMA Period elapsed callback */
2598 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2599
2600 /* Set the DMA error callback */
2601 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
2602 /* Enable the DMA channel */
2603 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
2604
2605 /* Enable the TIM Input Capture DMA request */
2606 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2607
2608 /* Enable the Peripheral */
2609 __HAL_TIM_ENABLE(htim);
2610
2611 /* Enable the Capture compare channel */
2612 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2613 }
2614 break;
2615
2616 case TIM_CHANNEL_ALL:
2617 {
2618 /* Set the DMA Period elapsed callback */
2619 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2620
2621 /* Set the DMA error callback */
2622 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2623
2624 /* Enable the DMA channel */
2625 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
2626
2627 /* Set the DMA Period elapsed callback */
2628 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2629
2630 /* Set the DMA error callback */
2631 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
2632
2633 /* Enable the DMA channel */
2634 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
2635
2636 /* Enable the Peripheral */
2637 __HAL_TIM_ENABLE(htim);
2638
2639 /* Enable the Capture compare channel */
2640 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2641 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2642
2643 /* Enable the TIM Input Capture DMA request */
2644 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2645 /* Enable the TIM Input Capture DMA request */
2646 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2647 }
2648 break;
2649
2650 default:
2651 break;
2652 }
2653 /* Return function status */
2654 return HAL_OK;
2655 }
2656
2657 /**
2658 * @brief Stops the TIM Encoder Interface in DMA mode.
2659 * @param htim : TIM Encoder Interface handle
2660 * @param Channel : TIM Channels to be enabled
2661 * This parameter can be one of the following values:
2662 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2663 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2664 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2665 * @retval HAL status
2666 */
2667 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2668 {
2669 /* Check the parameters */
2670 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2671
2672 /* Disable the Input Capture channels 1 and 2
2673 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2674 if(Channel == TIM_CHANNEL_1)
2675 {
2676 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2677
2678 /* Disable the capture compare DMA Request 1 */
2679 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2680 }
2681 else if(Channel == TIM_CHANNEL_2)
2682 {
2683 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2684
2685 /* Disable the capture compare DMA Request 2 */
2686 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2687 }
2688 else
2689 {
2690 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2691 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2692
2693 /* Disable the capture compare DMA Request 1 and 2 */
2694 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2695 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2696 }
2697
2698 /* Disable the Peripheral */
2699 __HAL_TIM_DISABLE(htim);
2700
2701 /* Change the htim state */
2702 htim->State = HAL_TIM_STATE_READY;
2703
2704 /* Return function status */
2705 return HAL_OK;
2706 }
2707
2708 /**
2709 * @}
2710 */
2711 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
2712 * @brief IRQ handler management
2713 *
2714 @verbatim
2715 ==============================================================================
2716 ##### IRQ handler management #####
2717 ==============================================================================
2718 [..]
2719 This section provides Timer IRQ handler function.
2720
2721 @endverbatim
2722 * @{
2723 */
2724 /**
2725 * @brief This function handles TIM interrupts requests.
2726 * @param htim : TIM handle
2727 * @retval None
2728 */
2729 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
2730 {
2731 /* Capture compare 1 event */
2732 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
2733 {
2734 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
2735 {
2736 {
2737 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
2738 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
2739
2740 /* Input capture event */
2741 if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
2742 {
2743 HAL_TIM_IC_CaptureCallback(htim);
2744 }
2745 /* Output compare event */
2746 else
2747 {
2748 HAL_TIM_OC_DelayElapsedCallback(htim);
2749 HAL_TIM_PWM_PulseFinishedCallback(htim);
2750 }
2751 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2752 }
2753 }
2754 }
2755 /* Capture compare 2 event */
2756 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
2757 {
2758 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
2759 {
2760 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
2761 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
2762 /* Input capture event */
2763 if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
2764 {
2765 HAL_TIM_IC_CaptureCallback(htim);
2766 }
2767 /* Output compare event */
2768 else
2769 {
2770 HAL_TIM_OC_DelayElapsedCallback(htim);
2771 HAL_TIM_PWM_PulseFinishedCallback(htim);
2772 }
2773 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2774 }
2775 }
2776 /* Capture compare 3 event */
2777 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
2778 {
2779 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
2780 {
2781 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
2782 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
2783 /* Input capture event */
2784 if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
2785 {
2786 HAL_TIM_IC_CaptureCallback(htim);
2787 }
2788 /* Output compare event */
2789 else
2790 {
2791 HAL_TIM_OC_DelayElapsedCallback(htim);
2792 HAL_TIM_PWM_PulseFinishedCallback(htim);
2793 }
2794 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2795 }
2796 }
2797 /* Capture compare 4 event */
2798 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
2799 {
2800 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
2801 {
2802 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
2803 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
2804 /* Input capture event */
2805 if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
2806 {
2807 HAL_TIM_IC_CaptureCallback(htim);
2808 }
2809 /* Output compare event */
2810 else
2811 {
2812 HAL_TIM_OC_DelayElapsedCallback(htim);
2813 HAL_TIM_PWM_PulseFinishedCallback(htim);
2814 }
2815 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2816 }
2817 }
2818 /* TIM Update event */
2819 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
2820 {
2821 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
2822 {
2823 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
2824 HAL_TIM_PeriodElapsedCallback(htim);
2825 }
2826 }
2827 /* TIM Break input event */
2828 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
2829 {
2830 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
2831 {
2832 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
2833 HAL_TIMEx_BreakCallback(htim);
2834 }
2835 }
2836 /* TIM Trigger detection event */
2837 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
2838 {
2839 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
2840 {
2841 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
2842 HAL_TIM_TriggerCallback(htim);
2843 }
2844 }
2845 /* TIM commutation event */
2846 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
2847 {
2848 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
2849 {
2850 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
2851 HAL_TIMEx_CommutationCallback(htim);
2852 }
2853 }
2854 }
2855
2856 /**
2857 * @}
2858 */
2859
2860 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
2861 * @brief Peripheral Control functions
2862 *
2863 @verbatim
2864 ==============================================================================
2865 ##### Peripheral Control functions #####
2866 ==============================================================================
2867 [..]
2868 This section provides functions allowing to:
2869 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
2870 (+) Configure External Clock source.
2871 (+) Configure Complementary channels, break features and dead time.
2872 (+) Configure Master and the Slave synchronization.
2873 (+) Configure the DMA Burst Mode.
2874
2875 @endverbatim
2876 * @{
2877 */
2878
2879 /**
2880 * @brief Initializes the TIM Output Compare Channels according to the specified
2881 * parameters in the TIM_OC_InitTypeDef.
2882 * @param htim : TIM Output Compare handle
2883 * @param sConfig : TIM Output Compare configuration structure
2884 * @param Channel : TIM Channels to be enabled
2885 * This parameter can be one of the following values:
2886 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2887 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2888 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2889 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2890 * @retval HAL status
2891 */
2892 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
2893 {
2894 /* Check the parameters */
2895 assert_param(IS_TIM_CHANNELS(Channel));
2896 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
2897 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
2898 assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
2899 assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
2900 assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
2901
2902 /* Check input state */
2903 __HAL_LOCK(htim);
2904
2905 htim->State = HAL_TIM_STATE_BUSY;
2906
2907 switch (Channel)
2908 {
2909 case TIM_CHANNEL_1:
2910 {
2911 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
2912 /* Configure the TIM Channel 1 in Output Compare */
2913 TIM_OC1_SetConfig(htim->Instance, sConfig);
2914 }
2915 break;
2916
2917 case TIM_CHANNEL_2:
2918 {
2919 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2920 /* Configure the TIM Channel 2 in Output Compare */
2921 TIM_OC2_SetConfig(htim->Instance, sConfig);
2922 }
2923 break;
2924
2925 case TIM_CHANNEL_3:
2926 {
2927 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
2928 /* Configure the TIM Channel 3 in Output Compare */
2929 TIM_OC3_SetConfig(htim->Instance, sConfig);
2930 }
2931 break;
2932
2933 case TIM_CHANNEL_4:
2934 {
2935 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
2936 /* Configure the TIM Channel 4 in Output Compare */
2937 TIM_OC4_SetConfig(htim->Instance, sConfig);
2938 }
2939 break;
2940
2941 default:
2942 break;
2943 }
2944 htim->State = HAL_TIM_STATE_READY;
2945
2946 __HAL_UNLOCK(htim);
2947
2948 return HAL_OK;
2949 }
2950
2951 /**
2952 * @brief Initializes the TIM Input Capture Channels according to the specified
2953 * parameters in the TIM_IC_InitTypeDef.
2954 * @param htim : TIM IC handle
2955 * @param sConfig : TIM Input Capture configuration structure
2956 * @param Channel : TIM Channels to be enabled
2957 * This parameter can be one of the following values:
2958 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2959 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2960 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2961 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2962 * @retval HAL status
2963 */
2964 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
2965 {
2966 /* Check the parameters */
2967 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
2968 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
2969 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
2970 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
2971 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
2972
2973 __HAL_LOCK(htim);
2974
2975 htim->State = HAL_TIM_STATE_BUSY;
2976
2977 if (Channel == TIM_CHANNEL_1)
2978 {
2979 /* TI1 Configuration */
2980 TIM_TI1_SetConfig(htim->Instance,
2981 sConfig->ICPolarity,
2982 sConfig->ICSelection,
2983 sConfig->ICFilter);
2984
2985 /* Reset the IC1PSC Bits */
2986 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
2987
2988 /* Set the IC1PSC value */
2989 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
2990 }
2991 else if (Channel == TIM_CHANNEL_2)
2992 {
2993 /* TI2 Configuration */
2994 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2995
2996 TIM_TI2_SetConfig(htim->Instance,
2997 sConfig->ICPolarity,
2998 sConfig->ICSelection,
2999 sConfig->ICFilter);
3000
3001 /* Reset the IC2PSC Bits */
3002 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
3003
3004 /* Set the IC2PSC value */
3005 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
3006 }
3007 else if (Channel == TIM_CHANNEL_3)
3008 {
3009 /* TI3 Configuration */
3010 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3011
3012 TIM_TI3_SetConfig(htim->Instance,
3013 sConfig->ICPolarity,
3014 sConfig->ICSelection,
3015 sConfig->ICFilter);
3016
3017 /* Reset the IC3PSC Bits */
3018 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
3019
3020 /* Set the IC3PSC value */
3021 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
3022 }
3023 else
3024 {
3025 /* TI4 Configuration */
3026 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3027
3028 TIM_TI4_SetConfig(htim->Instance,
3029 sConfig->ICPolarity,
3030 sConfig->ICSelection,
3031 sConfig->ICFilter);
3032
3033 /* Reset the IC4PSC Bits */
3034 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
3035
3036 /* Set the IC4PSC value */
3037 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
3038 }
3039
3040 htim->State = HAL_TIM_STATE_READY;
3041
3042 __HAL_UNLOCK(htim);
3043
3044 return HAL_OK;
3045 }
3046
3047 /**
3048 * @brief Initializes the TIM PWM channels according to the specified
3049 * parameters in the TIM_OC_InitTypeDef.
3050 * @param htim : TIM handle
3051 * @param sConfig : TIM PWM configuration structure
3052 * @param Channel : TIM Channels to be enabled
3053 * This parameter can be one of the following values:
3054 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3055 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3056 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3057 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3058 * @retval HAL status
3059 */
3060 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
3061 {
3062 __HAL_LOCK(htim);
3063
3064 /* Check the parameters */
3065 assert_param(IS_TIM_CHANNELS(Channel));
3066 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
3067 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
3068 assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
3069 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
3070 assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
3071 assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
3072
3073 htim->State = HAL_TIM_STATE_BUSY;
3074
3075 switch (Channel)
3076 {
3077 case TIM_CHANNEL_1:
3078 {
3079 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3080 /* Configure the Channel 1 in PWM mode */
3081 TIM_OC1_SetConfig(htim->Instance, sConfig);
3082
3083 /* Set the Preload enable bit for channel1 */
3084 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
3085
3086 /* Configure the Output Fast mode */
3087 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
3088 htim->Instance->CCMR1 |= sConfig->OCFastMode;
3089 }
3090 break;
3091
3092 case TIM_CHANNEL_2:
3093 {
3094 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3095 /* Configure the Channel 2 in PWM mode */
3096 TIM_OC2_SetConfig(htim->Instance, sConfig);
3097
3098 /* Set the Preload enable bit for channel2 */
3099 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
3100
3101 /* Configure the Output Fast mode */
3102 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
3103 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
3104 }
3105 break;
3106
3107 case TIM_CHANNEL_3:
3108 {
3109 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3110 /* Configure the Channel 3 in PWM mode */
3111 TIM_OC3_SetConfig(htim->Instance, sConfig);
3112
3113 /* Set the Preload enable bit for channel3 */
3114 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
3115
3116 /* Configure the Output Fast mode */
3117 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
3118 htim->Instance->CCMR2 |= sConfig->OCFastMode;
3119 }
3120 break;
3121
3122 case TIM_CHANNEL_4:
3123 {
3124 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3125 /* Configure the Channel 4 in PWM mode */
3126 TIM_OC4_SetConfig(htim->Instance, sConfig);
3127
3128 /* Set the Preload enable bit for channel4 */
3129 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
3130
3131 /* Configure the Output Fast mode */
3132 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
3133 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
3134 }
3135 break;
3136
3137 default:
3138 break;
3139 }
3140
3141 htim->State = HAL_TIM_STATE_READY;
3142
3143 __HAL_UNLOCK(htim);
3144
3145 return HAL_OK;
3146 }
3147
3148 /**
3149 * @brief Initializes the TIM One Pulse Channels according to the specified
3150 * parameters in the TIM_OnePulse_InitTypeDef.
3151 * @param htim : TIM One Pulse handle
3152 * @param sConfig : TIM One Pulse configuration structure
3153 * @param OutputChannel : TIM Channels to be enabled
3154 * This parameter can be one of the following values:
3155 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3156 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3157 * @param InputChannel : TIM Channels to be enabled
3158 * This parameter can be one of the following values:
3159 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3160 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3161 * @retval HAL status
3162 */
3163 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
3164 {
3165 TIM_OC_InitTypeDef temp1;
3166
3167 /* Check the parameters */
3168 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
3169 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
3170
3171 if(OutputChannel != InputChannel)
3172 {
3173 __HAL_LOCK(htim);
3174
3175 htim->State = HAL_TIM_STATE_BUSY;
3176
3177 /* Extract the Ouput compare configuration from sConfig structure */
3178 temp1.OCMode = sConfig->OCMode;
3179 temp1.Pulse = sConfig->Pulse;
3180 temp1.OCPolarity = sConfig->OCPolarity;
3181 temp1.OCNPolarity = sConfig->OCNPolarity;
3182 temp1.OCIdleState = sConfig->OCIdleState;
3183 temp1.OCNIdleState = sConfig->OCNIdleState;
3184
3185 switch (OutputChannel)
3186 {
3187 case TIM_CHANNEL_1:
3188 {
3189 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3190
3191 TIM_OC1_SetConfig(htim->Instance, &temp1);
3192 }
3193 break;
3194 case TIM_CHANNEL_2:
3195 {
3196 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3197
3198 TIM_OC2_SetConfig(htim->Instance, &temp1);
3199 }
3200 break;
3201 default:
3202 break;
3203 }
3204 switch (InputChannel)
3205 {
3206 case TIM_CHANNEL_1:
3207 {
3208 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3209
3210 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
3211 sConfig->ICSelection, sConfig->ICFilter);
3212
3213 /* Reset the IC1PSC Bits */
3214 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
3215
3216 /* Select the Trigger source */
3217 htim->Instance->SMCR &= ~TIM_SMCR_TS;
3218 htim->Instance->SMCR |= TIM_TS_TI1FP1;
3219
3220 /* Select the Slave Mode */
3221 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3222 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
3223 }
3224 break;
3225 case TIM_CHANNEL_2:
3226 {
3227 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3228
3229 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
3230 sConfig->ICSelection, sConfig->ICFilter);
3231
3232 /* Reset the IC2PSC Bits */
3233 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
3234
3235 /* Select the Trigger source */
3236 htim->Instance->SMCR &= ~TIM_SMCR_TS;
3237 htim->Instance->SMCR |= TIM_TS_TI2FP2;
3238
3239 /* Select the Slave Mode */
3240 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3241 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
3242 }
3243 break;
3244
3245 default:
3246 break;
3247 }
3248
3249 htim->State = HAL_TIM_STATE_READY;
3250
3251 __HAL_UNLOCK(htim);
3252
3253 return HAL_OK;
3254 }
3255 else
3256 {
3257 return HAL_ERROR;
3258 }
3259 }
3260
3261 /**
3262 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
3263 * @param htim : TIM handle
3264 * @param BurstBaseAddress : TIM Base address from where the DMA will start the Data write
3265 * This parameter can be one of the following values:
3266 * @arg TIM_DMABASE_CR1
3267 * @arg TIM_DMABASE_CR2
3268 * @arg TIM_DMABASE_SMCR
3269 * @arg TIM_DMABASE_DIER
3270 * @arg TIM_DMABASE_SR
3271 * @arg TIM_DMABASE_EGR
3272 * @arg TIM_DMABASE_CCMR1
3273 * @arg TIM_DMABASE_CCMR2
3274 * @arg TIM_DMABASE_CCER
3275 * @arg TIM_DMABASE_CNT
3276 * @arg TIM_DMABASE_PSC
3277 * @arg TIM_DMABASE_ARR
3278 * @arg TIM_DMABASE_RCR
3279 * @arg TIM_DMABASE_CCR1
3280 * @arg TIM_DMABASE_CCR2
3281 * @arg TIM_DMABASE_CCR3
3282 * @arg TIM_DMABASE_CCR4
3283 * @arg TIM_DMABASE_BDTR
3284 * @arg TIM_DMABASE_DCR
3285 * @param BurstRequestSrc : TIM DMA Request sources
3286 * This parameter can be one of the following values:
3287 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
3288 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
3289 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
3290 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
3291 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
3292 * @arg TIM_DMA_COM: TIM Commutation DMA source
3293 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
3294 * @param BurstBuffer : The Buffer address.
3295 * @param BurstLength : DMA Burst length. This parameter can be one value
3296 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
3297 * @retval HAL status
3298 */
3299 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
3300 uint32_t* BurstBuffer, uint32_t BurstLength)
3301 {
3302 /* Check the parameters */
3303 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
3304 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
3305 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3306 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
3307
3308 if((htim->State == HAL_TIM_STATE_BUSY))
3309 {
3310 return HAL_BUSY;
3311 }
3312 else if((htim->State == HAL_TIM_STATE_READY))
3313 {
3314 if((BurstBuffer == 0 ) && (BurstLength > 0))
3315 {
3316 return HAL_ERROR;
3317 }
3318 else
3319 {
3320 htim->State = HAL_TIM_STATE_BUSY;
3321 }
3322 }
3323 switch(BurstRequestSrc)
3324 {
3325 case TIM_DMA_UPDATE:
3326 {
3327 /* Set the DMA Period elapsed callback */
3328 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
3329
3330 /* Set the DMA error callback */
3331 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
3332
3333 /* Enable the DMA channel */
3334 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3335 }
3336 break;
3337 case TIM_DMA_CC1:
3338 {
3339 /* Set the DMA Period elapsed callback */
3340 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
3341
3342 /* Set the DMA error callback */
3343 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3344
3345 /* Enable the DMA channel */
3346 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3347 }
3348 break;
3349 case TIM_DMA_CC2:
3350 {
3351 /* Set the DMA Period elapsed callback */
3352 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
3353
3354 /* Set the DMA error callback */
3355 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3356
3357 /* Enable the DMA channel */
3358 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3359 }
3360 break;
3361 case TIM_DMA_CC3:
3362 {
3363 /* Set the DMA Period elapsed callback */
3364 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
3365
3366 /* Set the DMA error callback */
3367 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
3368
3369 /* Enable the DMA channel */
3370 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3371 }
3372 break;
3373 case TIM_DMA_CC4:
3374 {
3375 /* Set the DMA Period elapsed callback */
3376 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
3377
3378 /* Set the DMA error callback */
3379 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
3380
3381 /* Enable the DMA channel */
3382 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3383 }
3384 break;
3385 case TIM_DMA_COM:
3386 {
3387 /* Set the DMA Period elapsed callback */
3388 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
3389
3390 /* Set the DMA error callback */
3391 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
3392
3393 /* Enable the DMA channel */
3394 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3395 }
3396 break;
3397 case TIM_DMA_TRIGGER:
3398 {
3399 /* Set the DMA Period elapsed callback */
3400 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
3401
3402 /* Set the DMA error callback */
3403 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
3404
3405 /* Enable the DMA channel */
3406 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3407 }
3408 break;
3409 default:
3410 break;
3411 }
3412 /* configure the DMA Burst Mode */
3413 htim->Instance->DCR = BurstBaseAddress | BurstLength;
3414
3415 /* Enable the TIM DMA Request */
3416 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
3417
3418 htim->State = HAL_TIM_STATE_READY;
3419
3420 /* Return function status */
3421 return HAL_OK;
3422 }
3423
3424 /**
3425 * @brief Stops the TIM DMA Burst mode
3426 * @param htim : TIM handle
3427 * @param BurstRequestSrc : TIM DMA Request sources to disable
3428 * @retval HAL status
3429 */
3430 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
3431 {
3432 /* Check the parameters */
3433 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3434
3435 /* Abort the DMA transfer (at least disable the DMA channel) */
3436 switch(BurstRequestSrc)
3437 {
3438 case TIM_DMA_UPDATE:
3439 {
3440 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
3441 }
3442 break;
3443 case TIM_DMA_CC1:
3444 {
3445 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
3446 }
3447 break;
3448 case TIM_DMA_CC2:
3449 {
3450 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
3451 }
3452 break;
3453 case TIM_DMA_CC3:
3454 {
3455 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
3456 }
3457 break;
3458 case TIM_DMA_CC4:
3459 {
3460 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
3461 }
3462 break;
3463 case TIM_DMA_COM:
3464 {
3465 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
3466 }
3467 break;
3468 case TIM_DMA_TRIGGER:
3469 {
3470 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
3471 }
3472 break;
3473 default:
3474 break;
3475 }
3476
3477 /* Disable the TIM Update DMA request */
3478 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
3479
3480 /* Return function status */
3481 return HAL_OK;
3482 }
3483
3484 /**
3485 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
3486 * @param htim : TIM handle
3487 * @param BurstBaseAddress : TIM Base address from where the DMA will starts the Data read
3488 * This parameter can be one of the following values:
3489 * @arg TIM_DMABASE_CR1
3490 * @arg TIM_DMABASE_CR2
3491 * @arg TIM_DMABASE_SMCR
3492 * @arg TIM_DMABASE_DIER
3493 * @arg TIM_DMABASE_SR
3494 * @arg TIM_DMABASE_EGR
3495 * @arg TIM_DMABASE_CCMR1
3496 * @arg TIM_DMABASE_CCMR2
3497 * @arg TIM_DMABASE_CCER
3498 * @arg TIM_DMABASE_CNT
3499 * @arg TIM_DMABASE_PSC
3500 * @arg TIM_DMABASE_ARR
3501 * @arg TIM_DMABASE_RCR
3502 * @arg TIM_DMABASE_CCR1
3503 * @arg TIM_DMABASE_CCR2
3504 * @arg TIM_DMABASE_CCR3
3505 * @arg TIM_DMABASE_CCR4
3506 * @arg TIM_DMABASE_BDTR
3507 * @arg TIM_DMABASE_DCR
3508 * @param BurstRequestSrc : TIM DMA Request sources
3509 * This parameter can be one of the following values:
3510 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
3511 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
3512 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
3513 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
3514 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
3515 * @arg TIM_DMA_COM: TIM Commutation DMA source
3516 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
3517 * @param BurstBuffer : The Buffer address.
3518 * @param BurstLength : DMA Burst length. This parameter can be one value
3519 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
3520 * @retval HAL status
3521 */
3522 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
3523 uint32_t *BurstBuffer, uint32_t BurstLength)
3524 {
3525 /* Check the parameters */
3526 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
3527 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
3528 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3529 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
3530
3531 if((htim->State == HAL_TIM_STATE_BUSY))
3532 {
3533 return HAL_BUSY;
3534 }
3535 else if((htim->State == HAL_TIM_STATE_READY))
3536 {
3537 if((BurstBuffer == 0 ) && (BurstLength > 0))
3538 {
3539 return HAL_ERROR;
3540 }
3541 else
3542 {
3543 htim->State = HAL_TIM_STATE_BUSY;
3544 }
3545 }
3546 switch(BurstRequestSrc)
3547 {
3548 case TIM_DMA_UPDATE:
3549 {
3550 /* Set the DMA Period elapsed callback */
3551 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
3552
3553 /* Set the DMA error callback */
3554 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
3555
3556 /* Enable the DMA channel */
3557 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3558 }
3559 break;
3560 case TIM_DMA_CC1:
3561 {
3562 /* Set the DMA Period elapsed callback */
3563 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3564
3565 /* Set the DMA error callback */
3566 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3567
3568 /* Enable the DMA channel */
3569 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3570 }
3571 break;
3572 case TIM_DMA_CC2:
3573 {
3574 /* Set the DMA Period elapsed callback */
3575 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3576
3577 /* Set the DMA error callback */
3578 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3579
3580 /* Enable the DMA channel */
3581 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3582 }
3583 break;
3584 case TIM_DMA_CC3:
3585 {
3586 /* Set the DMA Period elapsed callback */
3587 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
3588
3589 /* Set the DMA error callback */
3590 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
3591
3592 /* Enable the DMA channel */
3593 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3594 }
3595 break;
3596 case TIM_DMA_CC4:
3597 {
3598 /* Set the DMA Period elapsed callback */
3599 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
3600
3601 /* Set the DMA error callback */
3602 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
3603
3604 /* Enable the DMA channel */
3605 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3606 }
3607 break;
3608 case TIM_DMA_COM:
3609 {
3610 /* Set the DMA Period elapsed callback */
3611 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
3612
3613 /* Set the DMA error callback */
3614 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
3615
3616 /* Enable the DMA channel */
3617 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3618 }
3619 break;
3620 case TIM_DMA_TRIGGER:
3621 {
3622 /* Set the DMA Period elapsed callback */
3623 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
3624
3625 /* Set the DMA error callback */
3626 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
3627
3628 /* Enable the DMA channel */
3629 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3630 }
3631 break;
3632 default:
3633 break;
3634 }
3635
3636 /* configure the DMA Burst Mode */
3637 htim->Instance->DCR = BurstBaseAddress | BurstLength;
3638
3639 /* Enable the TIM DMA Request */
3640 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
3641
3642 htim->State = HAL_TIM_STATE_READY;
3643
3644 /* Return function status */
3645 return HAL_OK;
3646 }
3647
3648 /**
3649 * @brief Stop the DMA burst reading
3650 * @param htim : TIM handle
3651 * @param BurstRequestSrc : TIM DMA Request sources to disable.
3652 * @retval HAL status
3653 */
3654 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
3655 {
3656 /* Check the parameters */
3657 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3658
3659 /* Abort the DMA transfer (at least disable the DMA channel) */
3660 switch(BurstRequestSrc)
3661 {
3662 case TIM_DMA_UPDATE:
3663 {
3664 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
3665 }
3666 break;
3667 case TIM_DMA_CC1:
3668 {
3669 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
3670 }
3671 break;
3672 case TIM_DMA_CC2:
3673 {
3674 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
3675 }
3676 break;
3677 case TIM_DMA_CC3:
3678 {
3679 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
3680 }
3681 break;
3682 case TIM_DMA_CC4:
3683 {
3684 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
3685 }
3686 break;
3687 case TIM_DMA_COM:
3688 {
3689 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
3690 }
3691 break;
3692 case TIM_DMA_TRIGGER:
3693 {
3694 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
3695 }
3696 break;
3697 default:
3698 break;
3699 }
3700
3701 /* Disable the TIM Update DMA request */
3702 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
3703
3704 /* Return function status */
3705 return HAL_OK;
3706 }
3707
3708 /**
3709 * @brief Generate a software event
3710 * @param htim : TIM handle
3711 * @param EventSource : specifies the event source.
3712 * This parameter can be one of the following values:
3713 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
3714 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
3715 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
3716 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
3717 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
3718 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
3719 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
3720 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
3721 * @note TIM6 and TIM7 can only generate an update event.
3722 * @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1, TIM15, TIM16 and TIM17.
3723 * @retval HAL status
3724 */
3725
3726 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
3727 {
3728 /* Check the parameters */
3729 assert_param(IS_TIM_INSTANCE(htim->Instance));
3730 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
3731
3732 /* Process Locked */
3733 __HAL_LOCK(htim);
3734
3735 /* Change the TIM state */
3736 htim->State = HAL_TIM_STATE_BUSY;
3737
3738 /* Set the event sources */
3739 htim->Instance->EGR = EventSource;
3740
3741 /* Change the TIM state */
3742 htim->State = HAL_TIM_STATE_READY;
3743
3744 __HAL_UNLOCK(htim);
3745
3746 /* Return function status */
3747 return HAL_OK;
3748 }
3749
3750 /**
3751 * @brief Configures the OCRef clear feature
3752 * @param htim : TIM handle
3753 * @param sClearInputConfig : pointer to a TIM_ClearInputConfigTypeDef structure that
3754 * contains the OCREF clear feature and parameters for the TIM peripheral.
3755 * @param Channel : specifies the TIM Channel
3756 * This parameter can be one of the following values:
3757 * @arg TIM_Channel_1: TIM Channel 1
3758 * @arg TIM_Channel_2: TIM Channel 2
3759 * @arg TIM_Channel_3: TIM Channel 3
3760 * @arg TIM_Channel_4: TIM Channel 4
3761 * @retval HAL status
3762 */
3763 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
3764 {
3765 uint32_t tmpsmcr = 0;
3766
3767 /* Check the parameters */
3768 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
3769 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
3770 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
3771 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
3772 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
3773
3774 /* Process Locked */
3775 __HAL_LOCK(htim);
3776
3777 htim->State = HAL_TIM_STATE_BUSY;
3778
3779 switch (sClearInputConfig->ClearInputSource)
3780 {
3781 case TIM_CLEARINPUTSOURCE_NONE:
3782 {
3783 /* Clear the OCREF clear selection bit */
3784 tmpsmcr &= ~TIM_SMCR_OCCS;
3785
3786 /* Clear the ETR Bits */
3787 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
3788
3789 /* Set TIMx_SMCR */
3790 htim->Instance->SMCR = tmpsmcr;
3791 }
3792 break;
3793
3794 case TIM_CLEARINPUTSOURCE_ETR:
3795 {
3796 TIM_ETR_SetConfig(htim->Instance,
3797 sClearInputConfig->ClearInputPrescaler,
3798 sClearInputConfig->ClearInputPolarity,
3799 sClearInputConfig->ClearInputFilter);
3800
3801 /* Set the OCREF clear selection bit */
3802 htim->Instance->SMCR |= TIM_SMCR_OCCS;
3803 }
3804 break;
3805 default:
3806 break;
3807 }
3808
3809 switch (Channel)
3810 {
3811 case TIM_CHANNEL_1:
3812 {
3813 if(sClearInputConfig->ClearInputState != RESET)
3814 {
3815 /* Enable the Ocref clear feature for Channel 1 */
3816 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
3817 }
3818 else
3819 {
3820 /* Disable the Ocref clear feature for Channel 1 */
3821 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
3822 }
3823 }
3824 break;
3825 case TIM_CHANNEL_2:
3826 {
3827 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3828 if(sClearInputConfig->ClearInputState != RESET)
3829 {
3830 /* Enable the Ocref clear feature for Channel 2 */
3831 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
3832 }
3833 else
3834 {
3835 /* Disable the Ocref clear feature for Channel 2 */
3836 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
3837 }
3838 }
3839 break;
3840 case TIM_CHANNEL_3:
3841 {
3842 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3843 if(sClearInputConfig->ClearInputState != RESET)
3844 {
3845 /* Enable the Ocref clear feature for Channel 3 */
3846 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
3847 }
3848 else
3849 {
3850 /* Disable the Ocref clear feature for Channel 3 */
3851 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
3852 }
3853 }
3854 break;
3855 case TIM_CHANNEL_4:
3856 {
3857 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3858 if(sClearInputConfig->ClearInputState != RESET)
3859 {
3860 /* Enable the Ocref clear feature for Channel 4 */
3861 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
3862 }
3863 else
3864 {
3865 /* Disable the Ocref clear feature for Channel 4 */
3866 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
3867 }
3868 }
3869 break;
3870 default:
3871 break;
3872 }
3873
3874 htim->State = HAL_TIM_STATE_READY;
3875
3876 __HAL_UNLOCK(htim);
3877
3878 return HAL_OK;
3879 }
3880
3881 /**
3882 * @brief Configures the clock source to be used
3883 * @param htim : TIM handle
3884 * @param sClockSourceConfig : pointer to a TIM_ClockConfigTypeDef structure that
3885 * contains the clock source information for the TIM peripheral.
3886 * @retval HAL status
3887 */
3888 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
3889 {
3890 uint32_t tmpsmcr = 0;
3891
3892 /* Process Locked */
3893 __HAL_LOCK(htim);
3894
3895 htim->State = HAL_TIM_STATE_BUSY;
3896
3897 /* Check the parameters */
3898 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
3899 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
3900 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
3901 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
3902
3903 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
3904 tmpsmcr = htim->Instance->SMCR;
3905 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
3906 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
3907 htim->Instance->SMCR = tmpsmcr;
3908
3909 switch (sClockSourceConfig->ClockSource)
3910 {
3911 case TIM_CLOCKSOURCE_INTERNAL:
3912 {
3913 assert_param(IS_TIM_INSTANCE(htim->Instance));
3914 /* Disable slave mode to clock the prescaler directly with the internal clock */
3915 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3916 }
3917 break;
3918
3919 case TIM_CLOCKSOURCE_ETRMODE1:
3920 {
3921 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
3922 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
3923
3924 /* Configure the ETR Clock source */
3925 TIM_ETR_SetConfig(htim->Instance,
3926 sClockSourceConfig->ClockPrescaler,
3927 sClockSourceConfig->ClockPolarity,
3928 sClockSourceConfig->ClockFilter);
3929 /* Get the TIMx SMCR register value */
3930 tmpsmcr = htim->Instance->SMCR;
3931 /* Reset the SMS and TS Bits */
3932 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
3933 /* Select the External clock mode1 and the ETRF trigger */
3934 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
3935 /* Write to TIMx SMCR */
3936 htim->Instance->SMCR = tmpsmcr;
3937 }
3938 break;
3939
3940 case TIM_CLOCKSOURCE_ETRMODE2:
3941 {
3942 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
3943 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
3944
3945 /* Configure the ETR Clock source */
3946 TIM_ETR_SetConfig(htim->Instance,
3947 sClockSourceConfig->ClockPrescaler,
3948 sClockSourceConfig->ClockPolarity,
3949 sClockSourceConfig->ClockFilter);
3950 /* Enable the External clock mode2 */
3951 htim->Instance->SMCR |= TIM_SMCR_ECE;
3952 }
3953 break;
3954
3955 case TIM_CLOCKSOURCE_TI1:
3956 {
3957 /* Check whether or not the timer instance supports external clock mode 1 */
3958 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
3959
3960 TIM_TI1_ConfigInputStage(htim->Instance,
3961 sClockSourceConfig->ClockPolarity,
3962 sClockSourceConfig->ClockFilter);
3963 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
3964 }
3965 break;
3966 case TIM_CLOCKSOURCE_TI2:
3967 {
3968 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
3969 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
3970
3971 TIM_TI2_ConfigInputStage(htim->Instance,
3972 sClockSourceConfig->ClockPolarity,
3973 sClockSourceConfig->ClockFilter);
3974 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
3975 }
3976 break;
3977 case TIM_CLOCKSOURCE_TI1ED:
3978 {
3979 /* Check whether or not the timer instance supports external clock mode 1 */
3980 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
3981
3982 TIM_TI1_ConfigInputStage(htim->Instance,
3983 sClockSourceConfig->ClockPolarity,
3984 sClockSourceConfig->ClockFilter);
3985 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
3986 }
3987 break;
3988 case TIM_CLOCKSOURCE_ITR0:
3989 {
3990 /* Check whether or not the timer instance supports external clock mode 1 */
3991 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
3992
3993 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
3994 }
3995 break;
3996 case TIM_CLOCKSOURCE_ITR1:
3997 {
3998 /* Check whether or not the timer instance supports external clock mode 1 */
3999 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
4000
4001 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
4002 }
4003 break;
4004 case TIM_CLOCKSOURCE_ITR2:
4005 {
4006 /* Check whether or not the timer instance supports external clock mode 1 */
4007 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
4008
4009 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
4010 }
4011 break;
4012 case TIM_CLOCKSOURCE_ITR3:
4013 {
4014 /* Check whether or not the timer instance supports external clock mode 1 */
4015 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
4016
4017 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
4018 }
4019 break;
4020
4021 default:
4022 break;
4023 }
4024 htim->State = HAL_TIM_STATE_READY;
4025
4026 __HAL_UNLOCK(htim);
4027
4028 return HAL_OK;
4029 }
4030
4031 /**
4032 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
4033 * or a XOR combination between CH1_input, CH2_input & CH3_input
4034 * @param htim : TIM handle.
4035 * @param TI1_Selection : Indicate whether or not channel 1 is connected to the
4036 * output of a XOR gate.
4037 * This parameter can be one of the following values:
4038 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
4039 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
4040 * pins are connected to the TI1 input (XOR combination)
4041 * @retval HAL status
4042 */
4043 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
4044 {
4045 uint32_t tmpcr2 = 0;
4046
4047 /* Check the parameters */
4048 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
4049 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
4050
4051 /* Get the TIMx CR2 register value */
4052 tmpcr2 = htim->Instance->CR2;
4053
4054 /* Reset the TI1 selection */
4055 tmpcr2 &= ~TIM_CR2_TI1S;
4056
4057 /* Set the the TI1 selection */
4058 tmpcr2 |= TI1_Selection;
4059
4060 /* Write to TIMxCR2 */
4061 htim->Instance->CR2 = tmpcr2;
4062
4063 return HAL_OK;
4064 }
4065
4066 /**
4067 * @brief Configures the TIM in Slave mode
4068 * @param htim : TIM handle.
4069 * @param sSlaveConfig : pointer to a TIM_SlaveConfigTypeDef structure that
4070 * contains the selected trigger (internal trigger input, filtered
4071 * timer input or external trigger input) and the ) and the Slave
4072 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
4073 * @retval HAL status
4074 */
4075 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
4076 {
4077 /* Check the parameters */
4078 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
4079 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
4080 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
4081
4082 __HAL_LOCK(htim);
4083
4084 htim->State = HAL_TIM_STATE_BUSY;
4085
4086 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
4087
4088 /* Disable Trigger Interrupt */
4089 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
4090
4091 /* Disable Trigger DMA request */
4092 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
4093
4094 htim->State = HAL_TIM_STATE_READY;
4095
4096 __HAL_UNLOCK(htim);
4097
4098 return HAL_OK;
4099 }
4100
4101 /**
4102 * @brief Configures the TIM in Slave mode in interrupt mode
4103 * @param htim: TIM handle.
4104 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
4105 * contains the selected trigger (internal trigger input, filtered
4106 * timer input or external trigger input) and the ) and the Slave
4107 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
4108 * @retval HAL status
4109 */
4110 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
4111 TIM_SlaveConfigTypeDef * sSlaveConfig)
4112 {
4113 /* Check the parameters */
4114 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
4115 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
4116 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
4117
4118 __HAL_LOCK(htim);
4119
4120 htim->State = HAL_TIM_STATE_BUSY;
4121
4122 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
4123
4124 /* Enable Trigger Interrupt */
4125 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
4126
4127 /* Disable Trigger DMA request */
4128 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
4129
4130 htim->State = HAL_TIM_STATE_READY;
4131
4132 __HAL_UNLOCK(htim);
4133
4134 return HAL_OK;
4135 }
4136
4137 /**
4138 * @brief Read the captured value from Capture Compare unit
4139 * @param htim : TIM handle.
4140 * @param Channel : TIM Channels to be enabled
4141 * This parameter can be one of the following values:
4142 * @arg TIM_CHANNEL_1 : TIM Channel 1 selected
4143 * @arg TIM_CHANNEL_2 : TIM Channel 2 selected
4144 * @arg TIM_CHANNEL_3 : TIM Channel 3 selected
4145 * @arg TIM_CHANNEL_4 : TIM Channel 4 selected
4146 * @retval Captured value
4147 */
4148 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
4149 {
4150 uint32_t tmpreg = 0;
4151
4152 __HAL_LOCK(htim);
4153
4154 switch (Channel)
4155 {
4156 case TIM_CHANNEL_1:
4157 {
4158 /* Check the parameters */
4159 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4160
4161 /* Return the capture 1 value */
4162 tmpreg = htim->Instance->CCR1;
4163
4164 break;
4165 }
4166 case TIM_CHANNEL_2:
4167 {
4168 /* Check the parameters */
4169 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4170
4171 /* Return the capture 2 value */
4172 tmpreg = htim->Instance->CCR2;
4173
4174 break;
4175 }
4176
4177 case TIM_CHANNEL_3:
4178 {
4179 /* Check the parameters */
4180 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4181
4182 /* Return the capture 3 value */
4183 tmpreg = htim->Instance->CCR3;
4184
4185 break;
4186 }
4187
4188 case TIM_CHANNEL_4:
4189 {
4190 /* Check the parameters */
4191 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4192
4193 /* Return the capture 4 value */
4194 tmpreg = htim->Instance->CCR4;
4195
4196 break;
4197 }
4198
4199 default:
4200 break;
4201 }
4202
4203 __HAL_UNLOCK(htim);
4204 return tmpreg;
4205 }
4206
4207 /**
4208 * @}
4209 */
4210
4211 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
4212 * @brief TIM Callbacks functions
4213 *
4214 @verbatim
4215 ==============================================================================
4216 ##### TIM Callbacks functions #####
4217 ==============================================================================
4218 [..]
4219 This section provides TIM callback functions:
4220 (+) Timer Period elapsed callback
4221 (+) Timer Output Compare callback
4222 (+) Timer Input capture callback
4223 (+) Timer Trigger callback
4224 (+) Timer Error callback
4225
4226 @endverbatim
4227 * @{
4228 */
4229
4230 /**
4231 * @brief Period elapsed callback in non blocking mode
4232 * @param htim : TIM handle
4233 * @retval None
4234 */
4235 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
4236 {
4237 /* NOTE : This function Should not be modified, when the callback is needed,
4238 the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
4239 */
4240
4241 }
4242 /**
4243 * @brief Output Compare callback in non blocking mode
4244 * @param htim : TIM OC handle
4245 * @retval None
4246 */
4247 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
4248 {
4249 /* NOTE : This function Should not be modified, when the callback is needed,
4250 the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
4251 */
4252 }
4253 /**
4254 * @brief Input Capture callback in non blocking mode
4255 * @param htim : TIM IC handle
4256 * @retval None
4257 */
4258 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
4259 {
4260 /* NOTE : This function Should not be modified, when the callback is needed,
4261 the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
4262 */
4263 }
4264
4265 /**
4266 * @brief PWM Pulse finished callback in non blocking mode
4267 * @param htim : TIM handle
4268 * @retval None
4269 */
4270 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
4271 {
4272 /* NOTE : This function Should not be modified, when the callback is needed,
4273 the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
4274 */
4275 }
4276
4277 /**
4278 * @brief Hall Trigger detection callback in non blocking mode
4279 * @param htim : TIM handle
4280 * @retval None
4281 */
4282 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
4283 {
4284 /* NOTE : This function Should not be modified, when the callback is needed,
4285 the HAL_TIM_TriggerCallback could be implemented in the user file
4286 */
4287 }
4288
4289 /**
4290 * @brief Timer error callback in non blocking mode
4291 * @param htim : TIM handle
4292 * @retval None
4293 */
4294 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
4295 {
4296 /* NOTE : This function Should not be modified, when the callback is needed,
4297 the HAL_TIM_ErrorCallback could be implemented in the user file
4298 */
4299 }
4300
4301 /**
4302 * @}
4303 */
4304
4305 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
4306 * @brief Peripheral State functions
4307 *
4308 @verbatim
4309 ==============================================================================
4310 ##### Peripheral State functions #####
4311 ==============================================================================
4312 [..]
4313 This subsection permit to get in run-time the status of the peripheral
4314 and the data flow.
4315
4316 @endverbatim
4317 * @{
4318 */
4319
4320 /**
4321 * @brief Return the TIM Base state
4322 * @param htim : TIM Base handle
4323 * @retval HAL state
4324 */
4325 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
4326 {
4327 return htim->State;
4328 }
4329
4330 /**
4331 * @brief Return the TIM OC state
4332 * @param htim : TIM Ouput Compare handle
4333 * @retval HAL state
4334 */
4335 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
4336 {
4337 return htim->State;
4338 }
4339
4340 /**
4341 * @brief Return the TIM PWM state
4342 * @param htim : TIM handle
4343 * @retval HAL state
4344 */
4345 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
4346 {
4347 return htim->State;
4348 }
4349
4350 /**
4351 * @brief Return the TIM Input Capture state
4352 * @param htim : TIM IC handle
4353 * @retval HAL state
4354 */
4355 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
4356 {
4357 return htim->State;
4358 }
4359
4360 /**
4361 * @brief Return the TIM One Pulse Mode state
4362 * @param htim : TIM OPM handle
4363 * @retval HAL state
4364 */
4365 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
4366 {
4367 return htim->State;
4368 }
4369
4370 /**
4371 * @brief Return the TIM Encoder Mode state
4372 * @param htim : TIM Encoder handle
4373 * @retval HAL state
4374 */
4375 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
4376 {
4377 return htim->State;
4378 }
4379
4380 /**
4381 * @}
4382 */
4383
4384 /**
4385 * @}
4386 */
4387
4388 /** @addtogroup TIM_Private_Functions TIM_Private_Functions
4389 * @{
4390 */
4391
4392 /**
4393 * @brief TIM DMA error callback
4394 * @param hdma : pointer to DMA handle.
4395 * @retval None
4396 */
4397 void TIM_DMAError(DMA_HandleTypeDef *hdma)
4398 {
4399 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4400
4401 htim->State= HAL_TIM_STATE_READY;
4402
4403 HAL_TIM_ErrorCallback(htim);
4404 }
4405
4406 /**
4407 * @brief TIM DMA Delay Pulse complete callback.
4408 * @param hdma : pointer to DMA handle.
4409 * @retval None
4410 */
4411 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
4412 {
4413 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4414
4415 htim->State= HAL_TIM_STATE_READY;
4416
4417 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
4418 {
4419 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
4420 }
4421 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
4422 {
4423 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
4424 }
4425 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
4426 {
4427 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
4428 }
4429 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
4430 {
4431 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
4432 }
4433
4434 HAL_TIM_PWM_PulseFinishedCallback(htim);
4435
4436 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
4437 }
4438 /**
4439 * @brief TIM DMA Capture complete callback.
4440 * @param hdma : pointer to DMA handle.
4441 * @retval None
4442 */
4443 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
4444 {
4445 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4446
4447 htim->State= HAL_TIM_STATE_READY;
4448
4449 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
4450 {
4451 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
4452 }
4453 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
4454 {
4455 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
4456 }
4457 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
4458 {
4459 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
4460 }
4461 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
4462 {
4463 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
4464 }
4465
4466 HAL_TIM_IC_CaptureCallback(htim);
4467
4468 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
4469 }
4470
4471 /**
4472 * @brief TIM DMA Period Elapse complete callback.
4473 * @param hdma : pointer to DMA handle.
4474 * @retval None
4475 */
4476 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
4477 {
4478 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4479
4480 htim->State= HAL_TIM_STATE_READY;
4481
4482 HAL_TIM_PeriodElapsedCallback(htim);
4483 }
4484
4485 /**
4486 * @brief TIM DMA Trigger callback.
4487 * @param hdma : pointer to DMA handle.
4488 * @retval None
4489 */
4490 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
4491 {
4492 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4493
4494 htim->State= HAL_TIM_STATE_READY;
4495
4496 HAL_TIM_TriggerCallback(htim);
4497 }
4498
4499 /**
4500 * @brief Time Base configuration
4501 * @param TIMx : TIM periheral
4502 * @param Structure : TIM Base configuration structure
4503 * @retval None
4504 */
4505 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
4506 {
4507 uint32_t tmpcr1 = 0;
4508 tmpcr1 = TIMx->CR1;
4509
4510 /* Set TIM Time Base Unit parameters ---------------------------------------*/
4511 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
4512 {
4513 /* Select the Counter Mode */
4514 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
4515 tmpcr1 |= Structure->CounterMode;
4516 }
4517
4518 if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
4519 {
4520 /* Set the clock division */
4521 tmpcr1 &= ~TIM_CR1_CKD;
4522 tmpcr1 |= (uint32_t)Structure->ClockDivision;
4523 }
4524
4525 TIMx->CR1 = tmpcr1;
4526
4527 /* Set the Autoreload value */
4528 TIMx->ARR = (uint32_t)Structure->Period ;
4529
4530 /* Set the Prescaler value */
4531 TIMx->PSC = (uint32_t)Structure->Prescaler;
4532
4533 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
4534 {
4535 /* Set the Repetition Counter value */
4536 TIMx->RCR = Structure->RepetitionCounter;
4537 }
4538
4539 /* Generate an update event to reload the Prescaler
4540 and the repetition counter(only for TIM1 and TIM8) value immediatly */
4541 TIMx->EGR = TIM_EGR_UG;
4542 }
4543
4544 /**
4545 * @brief Time Ouput Compare 1 configuration
4546 * @param TIMx to select the TIM peripheral
4547 * @param OC_Config : The ouput configuration structure
4548 * @retval None
4549 */
4550 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4551 {
4552 uint32_t tmpccmrx = 0;
4553 uint32_t tmpccer = 0;
4554 uint32_t tmpcr2 = 0;
4555
4556 /* Disable the Channel 1: Reset the CC1E Bit */
4557 TIMx->CCER &= ~TIM_CCER_CC1E;
4558
4559 /* Get the TIMx CCER register value */
4560 tmpccer = TIMx->CCER;
4561 /* Get the TIMx CR2 register value */
4562 tmpcr2 = TIMx->CR2;
4563
4564 /* Get the TIMx CCMR1 register value */
4565 tmpccmrx = TIMx->CCMR1;
4566
4567 /* Reset the Output Compare Mode Bits */
4568 tmpccmrx &= ~TIM_CCMR1_OC1M;
4569 tmpccmrx &= ~TIM_CCMR1_CC1S;
4570 /* Select the Output Compare Mode */
4571 tmpccmrx |= OC_Config->OCMode;
4572
4573 /* Reset the Output Polarity level */
4574 tmpccer &= ~TIM_CCER_CC1P;
4575 /* Set the Output Compare Polarity */
4576 tmpccer |= OC_Config->OCPolarity;
4577
4578 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
4579 {
4580 /* Check parameters */
4581 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
4582
4583 /* Reset the Output N Polarity level */
4584 tmpccer &= ~TIM_CCER_CC1NP;
4585 /* Set the Output N Polarity */
4586 tmpccer |= OC_Config->OCNPolarity;
4587 /* Reset the Output N State */
4588 tmpccer &= ~TIM_CCER_CC1NE;
4589 }
4590
4591 if(IS_TIM_BREAK_INSTANCE(TIMx))
4592 {
4593 /* Check parameters */
4594 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
4595 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
4596
4597 /* Reset the Output Compare and Output Compare N IDLE State */
4598 tmpcr2 &= ~TIM_CR2_OIS1;
4599 tmpcr2 &= ~TIM_CR2_OIS1N;
4600 /* Set the Output Idle state */
4601 tmpcr2 |= OC_Config->OCIdleState;
4602 /* Set the Output N Idle state */
4603 tmpcr2 |= OC_Config->OCNIdleState;
4604 }
4605 /* Write to TIMx CR2 */
4606 TIMx->CR2 = tmpcr2;
4607
4608 /* Write to TIMx CCMR1 */
4609 TIMx->CCMR1 = tmpccmrx;
4610
4611 /* Set the Capture Compare Register value */
4612 TIMx->CCR1 = OC_Config->Pulse;
4613
4614 /* Write to TIMx CCER */
4615 TIMx->CCER = tmpccer;
4616 }
4617
4618 /**
4619 * @brief Time Ouput Compare 2 configuration
4620 * @param TIMx to select the TIM peripheral
4621 * @param OC_Config : The ouput configuration structure
4622 * @retval None
4623 */
4624 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4625 {
4626 uint32_t tmpccmrx = 0;
4627 uint32_t tmpccer = 0;
4628 uint32_t tmpcr2 = 0;
4629
4630 /* Disable the Channel 2: Reset the CC2E Bit */
4631 TIMx->CCER &= ~TIM_CCER_CC2E;
4632
4633 /* Get the TIMx CCER register value */
4634 tmpccer = TIMx->CCER;
4635 /* Get the TIMx CR2 register value */
4636 tmpcr2 = TIMx->CR2;
4637
4638 /* Get the TIMx CCMR1 register value */
4639 tmpccmrx = TIMx->CCMR1;
4640
4641 /* Reset the Output Compare mode and Capture/Compare selection Bits */
4642 tmpccmrx &= ~TIM_CCMR1_OC2M;
4643 tmpccmrx &= ~TIM_CCMR1_CC2S;
4644
4645 /* Select the Output Compare Mode */
4646 tmpccmrx |= (OC_Config->OCMode << 8);
4647
4648 /* Reset the Output Polarity level */
4649 tmpccer &= ~TIM_CCER_CC2P;
4650 /* Set the Output Compare Polarity */
4651 tmpccer |= (OC_Config->OCPolarity << 4);
4652
4653 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
4654 {
4655 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
4656 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
4657 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
4658
4659 /* Reset the Output N Polarity level */
4660 tmpccer &= ~TIM_CCER_CC2NP;
4661 /* Set the Output N Polarity */
4662 tmpccer |= (OC_Config->OCNPolarity << 4);
4663 /* Reset the Output N State */
4664 tmpccer &= ~TIM_CCER_CC2NE;
4665
4666 }
4667
4668 if(IS_TIM_BREAK_INSTANCE(TIMx))
4669 {
4670 /* Check parameters */
4671 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
4672 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
4673
4674 /* Reset the Output Compare and Output Compare N IDLE State */
4675 tmpcr2 &= ~TIM_CR2_OIS2;
4676 tmpcr2 &= ~TIM_CR2_OIS2N;
4677 /* Set the Output Idle state */
4678 tmpcr2 |= (OC_Config->OCIdleState << 2);
4679 /* Set the Output N Idle state */
4680 tmpcr2 |= (OC_Config->OCNIdleState << 2);
4681 }
4682
4683 /* Write to TIMx CR2 */
4684 TIMx->CR2 = tmpcr2;
4685
4686 /* Write to TIMx CCMR1 */
4687 TIMx->CCMR1 = tmpccmrx;
4688
4689 /* Set the Capture Compare Register value */
4690 TIMx->CCR2 = OC_Config->Pulse;
4691
4692 /* Write to TIMx CCER */
4693 TIMx->CCER = tmpccer;
4694 }
4695
4696 /**
4697 * @brief Time Ouput Compare 3 configuration
4698 * @param TIMx to select the TIM peripheral
4699 * @param OC_Config : The ouput configuration structure
4700 * @retval None
4701 */
4702 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4703 {
4704 uint32_t tmpccmrx = 0;
4705 uint32_t tmpccer = 0;
4706 uint32_t tmpcr2 = 0;
4707
4708 /* Disable the Channel 3: Reset the CC2E Bit */
4709 TIMx->CCER &= ~TIM_CCER_CC3E;
4710
4711 /* Get the TIMx CCER register value */
4712 tmpccer = TIMx->CCER;
4713 /* Get the TIMx CR2 register value */
4714 tmpcr2 = TIMx->CR2;
4715
4716 /* Get the TIMx CCMR2 register value */
4717 tmpccmrx = TIMx->CCMR2;
4718
4719 /* Reset the Output Compare mode and Capture/Compare selection Bits */
4720 tmpccmrx &= ~TIM_CCMR2_OC3M;
4721 tmpccmrx &= ~TIM_CCMR2_CC3S;
4722 /* Select the Output Compare Mode */
4723 tmpccmrx |= OC_Config->OCMode;
4724
4725 /* Reset the Output Polarity level */
4726 tmpccer &= ~TIM_CCER_CC3P;
4727 /* Set the Output Compare Polarity */
4728 tmpccer |= (OC_Config->OCPolarity << 8);
4729
4730 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
4731 {
4732 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
4733 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
4734 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
4735
4736 /* Reset the Output N Polarity level */
4737 tmpccer &= ~TIM_CCER_CC3NP;
4738 /* Set the Output N Polarity */
4739 tmpccer |= (OC_Config->OCNPolarity << 8);
4740 /* Reset the Output N State */
4741 tmpccer &= ~TIM_CCER_CC3NE;
4742 }
4743
4744 if(IS_TIM_BREAK_INSTANCE(TIMx))
4745 {
4746 /* Check parameters */
4747 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
4748 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
4749
4750 /* Reset the Output Compare and Output Compare N IDLE State */
4751 tmpcr2 &= ~TIM_CR2_OIS3;
4752 tmpcr2 &= ~TIM_CR2_OIS3N;
4753 /* Set the Output Idle state */
4754 tmpcr2 |= (OC_Config->OCIdleState << 4);
4755 /* Set the Output N Idle state */
4756 tmpcr2 |= (OC_Config->OCNIdleState << 4);
4757 }
4758
4759 /* Write to TIMx CR2 */
4760 TIMx->CR2 = tmpcr2;
4761
4762 /* Write to TIMx CCMR2 */
4763 TIMx->CCMR2 = tmpccmrx;
4764
4765 /* Set the Capture Compare Register value */
4766 TIMx->CCR3 = OC_Config->Pulse;
4767
4768 /* Write to TIMx CCER */
4769 TIMx->CCER = tmpccer;
4770 }
4771
4772 /**
4773 * @brief Time Ouput Compare 4 configuration
4774 * @param TIMx to select the TIM peripheral
4775 * @param OC_Config : The ouput configuration structure
4776 * @retval None
4777 */
4778 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4779 {
4780 uint32_t tmpccmrx = 0;
4781 uint32_t tmpccer = 0;
4782 uint32_t tmpcr2 = 0;
4783
4784 /* Disable the Channel 4: Reset the CC4E Bit */
4785 TIMx->CCER &= ~TIM_CCER_CC4E;
4786
4787 /* Get the TIMx CCER register value */
4788 tmpccer = TIMx->CCER;
4789 /* Get the TIMx CR2 register value */
4790 tmpcr2 = TIMx->CR2;
4791
4792 /* Get the TIMx CCMR2 register value */
4793 tmpccmrx = TIMx->CCMR2;
4794
4795 /* Reset the Output Compare mode and Capture/Compare selection Bits */
4796 tmpccmrx &= ~TIM_CCMR2_OC4M;
4797 tmpccmrx &= ~TIM_CCMR2_CC4S;
4798
4799 /* Select the Output Compare Mode */
4800 tmpccmrx |= (OC_Config->OCMode << 8);
4801
4802 /* Reset the Output Polarity level */
4803 tmpccer &= ~TIM_CCER_CC4P;
4804 /* Set the Output Compare Polarity */
4805 tmpccer |= (OC_Config->OCPolarity << 12);
4806
4807 if(IS_TIM_BREAK_INSTANCE(TIMx))
4808 {
4809 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
4810
4811 /* Reset the Output Compare IDLE State */
4812 tmpcr2 &= ~TIM_CR2_OIS4;
4813 /* Set the Output Idle state */
4814 tmpcr2 |= (OC_Config->OCIdleState << 6);
4815 }
4816
4817 /* Write to TIMx CR2 */
4818 TIMx->CR2 = tmpcr2;
4819
4820 /* Write to TIMx CCMR2 */
4821 TIMx->CCMR2 = tmpccmrx;
4822
4823 /* Set the Capture Compare Register value */
4824 TIMx->CCR4 = OC_Config->Pulse;
4825
4826 /* Write to TIMx CCER */
4827 TIMx->CCER = tmpccer;
4828 }
4829
4830 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
4831 TIM_SlaveConfigTypeDef * sSlaveConfig)
4832 {
4833 uint32_t tmpsmcr = 0;
4834 uint32_t tmpccmr1 = 0;
4835 uint32_t tmpccer = 0;
4836
4837 /* Get the TIMx SMCR register value */
4838 tmpsmcr = htim->Instance->SMCR;
4839
4840 /* Reset the Trigger Selection Bits */
4841 tmpsmcr &= ~TIM_SMCR_TS;
4842 /* Set the Input Trigger source */
4843 tmpsmcr |= sSlaveConfig->InputTrigger;
4844
4845 /* Reset the slave mode Bits */
4846 tmpsmcr &= ~TIM_SMCR_SMS;
4847 /* Set the slave mode */
4848 tmpsmcr |= sSlaveConfig->SlaveMode;
4849
4850 /* Write to TIMx SMCR */
4851 htim->Instance->SMCR = tmpsmcr;
4852
4853 /* Configure the trigger prescaler, filter, and polarity */
4854 switch (sSlaveConfig->InputTrigger)
4855 {
4856 case TIM_TS_ETRF:
4857 {
4858 /* Check the parameters */
4859 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
4860 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
4861 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
4862 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
4863 /* Configure the ETR Trigger source */
4864 TIM_ETR_SetConfig(htim->Instance,
4865 sSlaveConfig->TriggerPrescaler,
4866 sSlaveConfig->TriggerPolarity,
4867 sSlaveConfig->TriggerFilter);
4868 }
4869 break;
4870
4871 case TIM_TS_TI1F_ED:
4872 {
4873 /* Check the parameters */
4874 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4875 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
4876 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
4877
4878 /* Disable the Channel 1: Reset the CC1E Bit */
4879 tmpccer = htim->Instance->CCER;
4880 htim->Instance->CCER &= ~TIM_CCER_CC1E;
4881 tmpccmr1 = htim->Instance->CCMR1;
4882
4883 /* Set the filter */
4884 tmpccmr1 &= ~TIM_CCMR1_IC1F;
4885 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
4886
4887 /* Write to TIMx CCMR1 and CCER registers */
4888 htim->Instance->CCMR1 = tmpccmr1;
4889 htim->Instance->CCER = tmpccer;
4890
4891 }
4892 break;
4893
4894 case TIM_TS_TI1FP1:
4895 {
4896 /* Check the parameters */
4897 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4898 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
4899 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
4900
4901 /* Configure TI1 Filter and Polarity */
4902 TIM_TI1_ConfigInputStage(htim->Instance,
4903 sSlaveConfig->TriggerPolarity,
4904 sSlaveConfig->TriggerFilter);
4905 }
4906 break;
4907
4908 case TIM_TS_TI2FP2:
4909 {
4910 /* Check the parameters */
4911 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4912 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
4913 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
4914
4915 /* Configure TI2 Filter and Polarity */
4916 TIM_TI2_ConfigInputStage(htim->Instance,
4917 sSlaveConfig->TriggerPolarity,
4918 sSlaveConfig->TriggerFilter);
4919 }
4920 break;
4921
4922 case TIM_TS_ITR0:
4923 {
4924 /* Check the parameter */
4925 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4926 }
4927 break;
4928
4929 case TIM_TS_ITR1:
4930 {
4931 /* Check the parameter */
4932 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4933 }
4934 break;
4935
4936 case TIM_TS_ITR2:
4937 {
4938 /* Check the parameter */
4939 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4940 }
4941 break;
4942
4943 case TIM_TS_ITR3:
4944 {
4945 /* Check the parameter */
4946 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4947 }
4948 break;
4949
4950 default:
4951 break;
4952 }
4953 }
4954
4955 /**
4956 * @brief Configure the TI1 as Input.
4957 * @param TIMx to select the TIM peripheral.
4958 * @param TIM_ICPolarity : The Input Polarity.
4959 * This parameter can be one of the following values:
4960 * @arg TIM_ICPolarity_Rising
4961 * @arg TIM_ICPolarity_Falling
4962 * @arg TIM_ICPolarity_BothEdge
4963 * @param TIM_ICSelection : specifies the input to be used.
4964 * This parameter can be one of the following values:
4965 * @arg TIM_ICSelection_DirectTI : TIM Input 1 is selected to be connected to IC1.
4966 * @arg TIM_ICSelection_IndirectTI : TIM Input 1 is selected to be connected to IC2.
4967 * @arg TIM_ICSelection_TRC : TIM Input 1 is selected to be connected to TRC.
4968 * @param TIM_ICFilter : Specifies the Input Capture Filter.
4969 * This parameter must be a value between 0x00 and 0x0F.
4970 * @retval None
4971 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
4972 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
4973 * protected against un-initialized filter and polarity values.
4974 */
4975 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
4976 uint32_t TIM_ICFilter)
4977 {
4978 uint32_t tmpccmr1 = 0;
4979 uint32_t tmpccer = 0;
4980
4981 /* Disable the Channel 1: Reset the CC1E Bit */
4982 TIMx->CCER &= ~TIM_CCER_CC1E;
4983 tmpccmr1 = TIMx->CCMR1;
4984 tmpccer = TIMx->CCER;
4985
4986 /* Select the Input */
4987 if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
4988 {
4989 tmpccmr1 &= ~TIM_CCMR1_CC1S;
4990 tmpccmr1 |= TIM_ICSelection;
4991 }
4992 else
4993 {
4994 tmpccmr1 |= TIM_CCMR1_CC1S_0;
4995 }
4996
4997 /* Set the filter */
4998 tmpccmr1 &= ~TIM_CCMR1_IC1F;
4999 tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
5000
5001 /* Select the Polarity and set the CC1E Bit */
5002 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
5003 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
5004
5005 /* Write to TIMx CCMR1 and CCER registers */
5006 TIMx->CCMR1 = tmpccmr1;
5007 TIMx->CCER = tmpccer;
5008 }
5009
5010 /**
5011 * @brief Configure the Polarity and Filter for TI1.
5012 * @param TIMx to select the TIM peripheral.
5013 * @param TIM_ICPolarity : The Input Polarity.
5014 * This parameter can be one of the following values:
5015 * @arg TIM_ICPolarity_Rising
5016 * @arg TIM_ICPolarity_Falling
5017 * @arg TIM_ICPolarity_BothEdge
5018 * @param TIM_ICFilter : Specifies the Input Capture Filter.
5019 * This parameter must be a value between 0x00 and 0x0F.
5020 * @retval None
5021 */
5022 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
5023 {
5024 uint32_t tmpccmr1 = 0;
5025 uint32_t tmpccer = 0;
5026
5027 /* Disable the Channel 1: Reset the CC1E Bit */
5028 tmpccer = TIMx->CCER;
5029 TIMx->CCER &= ~TIM_CCER_CC1E;
5030 tmpccmr1 = TIMx->CCMR1;
5031
5032 /* Set the filter */
5033 tmpccmr1 &= ~TIM_CCMR1_IC1F;
5034 tmpccmr1 |= (TIM_ICFilter << 4);
5035
5036 /* Select the Polarity and set the CC1E Bit */
5037 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
5038 tmpccer |= TIM_ICPolarity;
5039
5040 /* Write to TIMx CCMR1 and CCER registers */
5041 TIMx->CCMR1 = tmpccmr1;
5042 TIMx->CCER = tmpccer;
5043 }
5044
5045 /**
5046 * @brief Configure the TI2 as Input.
5047 * @param TIMx to select the TIM peripheral
5048 * @param TIM_ICPolarity : The Input Polarity.
5049 * This parameter can be one of the following values:
5050 * @arg TIM_ICPolarity_Rising
5051 * @arg TIM_ICPolarity_Falling
5052 * @arg TIM_ICPolarity_BothEdge
5053 * @param TIM_ICSelection : specifies the input to be used.
5054 * This parameter can be one of the following values:
5055 * @arg TIM_ICSelection_DirectTI : TIM Input 2 is selected to be connected to IC2.
5056 * @arg TIM_ICSelection_IndirectTI : TIM Input 2 is selected to be connected to IC1.
5057 * @arg TIM_ICSelection_TRC : TIM Input 2 is selected to be connected to TRC.
5058 * @param TIM_ICFilter : Specifies the Input Capture Filter.
5059 * This parameter must be a value between 0x00 and 0x0F.
5060 * @retval None
5061 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
5062 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
5063 * protected against un-initialized filter and polarity values.
5064 */
5065 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
5066 uint32_t TIM_ICFilter)
5067 {
5068 uint32_t tmpccmr1 = 0;
5069 uint32_t tmpccer = 0;
5070
5071 /* Disable the Channel 2: Reset the CC2E Bit */
5072 TIMx->CCER &= ~TIM_CCER_CC2E;
5073 tmpccmr1 = TIMx->CCMR1;
5074 tmpccer = TIMx->CCER;
5075
5076 /* Select the Input */
5077 tmpccmr1 &= ~TIM_CCMR1_CC2S;
5078 tmpccmr1 |= (TIM_ICSelection << 8);
5079
5080 /* Set the filter */
5081 tmpccmr1 &= ~TIM_CCMR1_IC2F;
5082 tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
5083
5084 /* Select the Polarity and set the CC2E Bit */
5085 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
5086 tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
5087
5088 /* Write to TIMx CCMR1 and CCER registers */
5089 TIMx->CCMR1 = tmpccmr1 ;
5090 TIMx->CCER = tmpccer;
5091 }
5092
5093 /**
5094 * @brief Configure the Polarity and Filter for TI2.
5095 * @param TIMx to select the TIM peripheral.
5096 * @param TIM_ICPolarity : The Input Polarity.
5097 * This parameter can be one of the following values:
5098 * @arg TIM_ICPolarity_Rising
5099 * @arg TIM_ICPolarity_Falling
5100 * @arg TIM_ICPolarity_BothEdge
5101 * @param TIM_ICFilter : Specifies the Input Capture Filter.
5102 * This parameter must be a value between 0x00 and 0x0F.
5103 * @retval None
5104 */
5105 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
5106 {
5107 uint32_t tmpccmr1 = 0;
5108 uint32_t tmpccer = 0;
5109
5110 /* Disable the Channel 2: Reset the CC2E Bit */
5111 TIMx->CCER &= ~TIM_CCER_CC2E;
5112 tmpccmr1 = TIMx->CCMR1;
5113 tmpccer = TIMx->CCER;
5114
5115 /* Set the filter */
5116 tmpccmr1 &= ~TIM_CCMR1_IC2F;
5117 tmpccmr1 |= (TIM_ICFilter << 12);
5118
5119 /* Select the Polarity and set the CC2E Bit */
5120 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
5121 tmpccer |= (TIM_ICPolarity << 4);
5122
5123 /* Write to TIMx CCMR1 and CCER registers */
5124 TIMx->CCMR1 = tmpccmr1 ;
5125 TIMx->CCER = tmpccer;
5126 }
5127
5128 /**
5129 * @brief Configure the TI3 as Input.
5130 * @param TIMx to select the TIM peripheral
5131 * @param TIM_ICPolarity : The Input Polarity.
5132 * This parameter can be one of the following values:
5133 * @arg TIM_ICPolarity_Rising
5134 * @arg TIM_ICPolarity_Falling
5135 * @arg TIM_ICPolarity_BothEdge
5136 * @param TIM_ICSelection : specifies the input to be used.
5137 * This parameter can be one of the following values:
5138 * @arg TIM_ICSelection_DirectTI : TIM Input 3 is selected to be connected to IC3.
5139 * @arg TIM_ICSelection_IndirectTI : TIM Input 3 is selected to be connected to IC4.
5140 * @arg TIM_ICSelection_TRC : TIM Input 3 is selected to be connected to TRC.
5141 * @param TIM_ICFilter : Specifies the Input Capture Filter.
5142 * This parameter must be a value between 0x00 and 0x0F.
5143 * @retval None
5144 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
5145 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
5146 * protected against un-initialized filter and polarity values.
5147 */
5148 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
5149 uint32_t TIM_ICFilter)
5150 {
5151 uint32_t tmpccmr2 = 0;
5152 uint32_t tmpccer = 0;
5153
5154 /* Disable the Channel 3: Reset the CC3E Bit */
5155 TIMx->CCER &= ~TIM_CCER_CC3E;
5156 tmpccmr2 = TIMx->CCMR2;
5157 tmpccer = TIMx->CCER;
5158
5159 /* Select the Input */
5160 tmpccmr2 &= ~TIM_CCMR2_CC3S;
5161 tmpccmr2 |= TIM_ICSelection;
5162
5163 /* Set the filter */
5164 tmpccmr2 &= ~TIM_CCMR2_IC3F;
5165 tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
5166
5167 /* Select the Polarity and set the CC3E Bit */
5168 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
5169 tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
5170
5171 /* Write to TIMx CCMR2 and CCER registers */
5172 TIMx->CCMR2 = tmpccmr2;
5173 TIMx->CCER = tmpccer;
5174 }
5175
5176 /**
5177 * @brief Configure the TI4 as Input.
5178 * @param TIMx to select the TIM peripheral
5179 * @param TIM_ICPolarity : The Input Polarity.
5180 * This parameter can be one of the following values:
5181 * @arg TIM_ICPolarity_Rising
5182 * @arg TIM_ICPolarity_Falling
5183 * @arg TIM_ICPolarity_BothEdge
5184 * @param TIM_ICSelection : specifies the input to be used.
5185 * This parameter can be one of the following values:
5186 * @arg TIM_ICSelection_DirectTI : TIM Input 4 is selected to be connected to IC4.
5187 * @arg TIM_ICSelection_IndirectTI : TIM Input 4 is selected to be connected to IC3.
5188 * @arg TIM_ICSelection_TRC : TIM Input 4 is selected to be connected to TRC.
5189 * @param TIM_ICFilter : Specifies the Input Capture Filter.
5190 * This parameter must be a value between 0x00 and 0x0F.
5191 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
5192 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
5193 * protected against un-initialized filter and polarity values.
5194 * @retval None
5195 */
5196 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
5197 uint32_t TIM_ICFilter)
5198 {
5199 uint32_t tmpccmr2 = 0;
5200 uint32_t tmpccer = 0;
5201
5202 /* Disable the Channel 4: Reset the CC4E Bit */
5203 TIMx->CCER &= ~TIM_CCER_CC4E;
5204 tmpccmr2 = TIMx->CCMR2;
5205 tmpccer = TIMx->CCER;
5206
5207 /* Select the Input */
5208 tmpccmr2 &= ~TIM_CCMR2_CC4S;
5209 tmpccmr2 |= (TIM_ICSelection << 8);
5210
5211 /* Set the filter */
5212 tmpccmr2 &= ~TIM_CCMR2_IC4F;
5213 tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
5214
5215 /* Select the Polarity and set the CC4E Bit */
5216 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
5217 tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
5218
5219 /* Write to TIMx CCMR2 and CCER registers */
5220 TIMx->CCMR2 = tmpccmr2;
5221 TIMx->CCER = tmpccer ;
5222 }
5223
5224 /**
5225 * @brief Selects the Input Trigger source
5226 * @param TIMx to select the TIM peripheral
5227 * @param InputTriggerSource : The Input Trigger source.
5228 * This parameter can be one of the following values:
5229 * @arg TIM_TS_ITR0 : Internal Trigger 0
5230 * @arg TIM_TS_ITR1 : Internal Trigger 1
5231 * @arg TIM_TS_ITR2 : Internal Trigger 2
5232 * @arg TIM_TS_ITR3 : Internal Trigger 3
5233 * @arg TIM_TS_TI1F_ED : TI1 Edge Detector
5234 * @arg TIM_TS_TI1FP1 : Filtered Timer Input 1
5235 * @arg TIM_TS_TI2FP2 : Filtered Timer Input 2
5236 * @arg TIM_TS_ETRF : External Trigger input
5237 * @retval None
5238 */
5239 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
5240 {
5241 uint32_t tmpsmcr = 0;
5242
5243 /* Get the TIMx SMCR register value */
5244 tmpsmcr = TIMx->SMCR;
5245 /* Reset the TS Bits */
5246 tmpsmcr &= ~TIM_SMCR_TS;
5247 /* Set the Input Trigger source and the slave mode*/
5248 tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
5249 /* Write to TIMx SMCR */
5250 TIMx->SMCR = tmpsmcr;
5251 }
5252 /**
5253 * @brief Configures the TIMx External Trigger (ETR).
5254 * @param TIMx to select the TIM peripheral
5255 * @param TIM_ExtTRGPrescaler : The external Trigger Prescaler.
5256 * This parameter can be one of the following values:
5257 * @arg TIM_ExtTRGPSC_DIV1 : ETRP Prescaler OFF.
5258 * @arg TIM_ExtTRGPSC_DIV2 : ETRP frequency divided by 2.
5259 * @arg TIM_ExtTRGPSC_DIV4 : ETRP frequency divided by 4.
5260 * @arg TIM_ExtTRGPSC_DIV8 : ETRP frequency divided by 8.
5261 * @param TIM_ExtTRGPolarity : The external Trigger Polarity.
5262 * This parameter can be one of the following values:
5263 * @arg TIM_ExtTRGPolarity_Inverted : active low or falling edge active.
5264 * @arg TIM_ExtTRGPolarity_NonInverted : active high or rising edge active.
5265 * @param ExtTRGFilter : External Trigger Filter.
5266 * This parameter must be a value between 0x00 and 0x0F
5267 * @retval None
5268 */
5269 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
5270 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
5271 {
5272 uint32_t tmpsmcr = 0;
5273
5274 tmpsmcr = TIMx->SMCR;
5275
5276 /* Reset the ETR Bits */
5277 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
5278
5279 /* Set the Prescaler, the Filter value and the Polarity */
5280 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
5281
5282 /* Write to TIMx SMCR */
5283 TIMx->SMCR = tmpsmcr;
5284 }
5285
5286 /**
5287 * @brief Enables or disables the TIM Capture Compare Channel x.
5288 * @param TIMx to select the TIM peripheral
5289 * @param Channel : specifies the TIM Channel
5290 * This parameter can be one of the following values:
5291 * @arg TIM_Channel_1 : TIM Channel 1
5292 * @arg TIM_Channel_2 : TIM Channel 2
5293 * @arg TIM_Channel_3 : TIM Channel 3
5294 * @arg TIM_Channel_4 : TIM Channel 4
5295 * @param ChannelState : specifies the TIM Channel CCxE bit new state.
5296 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
5297 * @retval None
5298 */
5299 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
5300 {
5301 uint32_t tmp = 0;
5302
5303 /* Check the parameters */
5304 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
5305 assert_param(IS_TIM_CHANNELS(Channel));
5306
5307 tmp = TIM_CCER_CC1E << Channel;
5308
5309 /* Reset the CCxE Bit */
5310 TIMx->CCER &= ~tmp;
5311
5312 /* Set or reset the CCxE Bit */
5313 TIMx->CCER |= (uint32_t)(ChannelState << Channel);
5314 }
5315
5316
5317 /**
5318 * @}
5319 */
5320
5321 #endif /* HAL_TIM_MODULE_ENABLED */
5322 /**
5323 * @}
5324 */
5325
5326 /**
5327 * @}
5328 */
5329 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
custom keymap for my minivan; forked from http://github.com/evangs/tmk_keyboard
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