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[tmk_keyboard.git] / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_STM / TARGET_STM32F3 / TARGET_DISCO_F303VC / stm32f303xc.h
1 /**
2 ******************************************************************************
3 * @file stm32f303xc.h
4 * @author MCD Application Team
5 * @version V2.0.1
6 * @date 18-June-2014
7 * @brief CMSIS STM32F303xB/STM32F303xC Devices Peripheral Access Layer Header File.
8 *
9 * This file contains:
10 * - Data structures and the address mapping for all peripherals
11 * - Peripheral's registers declarations and bits definition
12 * - Macros to access peripheral\92s registers hardware
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
18 *
19 * Redistribution and use in source and binary forms, with or without modification,
20 * are permitted provided that the following conditions are met:
21 * 1. Redistributions of source code must retain the above copyright notice,
22 * this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright notice,
24 * this list of conditions and the following disclaimer in the documentation
25 * and/or other materials provided with the distribution.
26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 ******************************************************************************
42 */
43
44 /** @addtogroup CMSIS_Device
45 * @{
46 */
47
48 /** @addtogroup stm32f303xc
49 * @{
50 */
51
52 #ifndef __STM32F303xC_H
53 #define __STM32F303xC_H
54
55 #ifdef __cplusplus
56 extern "C" {
57 #endif /* __cplusplus */
58
59 /** @addtogroup Configuration_section_for_CMSIS
60 * @{
61 */
62
63 /**
64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
65 */
66 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
67 #define __MPU_PRESENT 1 /*!< STM32F303xB/STM32F303xC devices provide an MPU */
68 #define __NVIC_PRIO_BITS 4 /*!< STM32F303xB/STM32F303xC devices use 4 Bits for the Priority Levels */
69 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
70 #define __FPU_PRESENT 1 /*!< STM32F303xB/STM32F303xC devices provide an FPU */
71
72 /**
73 * @}
74 */
75
76 /** @addtogroup Peripheral_interrupt_number_definition
77 * @{
78 */
79
80 /**
81 * @brief STM32F303xB/STM32F303xC devices Interrupt Number Definition, according to the selected device
82 * in @ref Library_configuration_section
83 */
84 typedef enum
85 {
86 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
87 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
88 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
89 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
90 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
91 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
92 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
93 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
94 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
95 /****** STM32 specific Interrupt Numbers **********************************************************************/
96 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
97 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
98 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */
99 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */
100 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
101 RCC_IRQn = 5, /*!< RCC global Interrupt */
102 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
103 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
104 EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */
105 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
106 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
107 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
108 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
109 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
110 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
111 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
112 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
113 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
114 ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
115 USB_HP_CAN_TX_IRQn = 19, /*!< USB Device High Priority or CAN TX Interrupts */
116 USB_LP_CAN_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN RX0 Interrupts */
117 CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
118 CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
119 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
120 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
121 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
122 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
123 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
124 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
125 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
126 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
127 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
128 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
129 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */
130 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
131 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
132 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
133 USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
134 USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
135 USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
136 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
137 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
138 USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */
139 TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
140 TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
141 TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
142 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
143 ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
144 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
145 UART4_IRQn = 52, /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */
146 UART5_IRQn = 53, /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */
147 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC channel 1&2 underrun error interrupts */
148 TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
149 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
150 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
151 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
152 DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
153 DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
154 ADC4_IRQn = 61, /*!< ADC4 global Interrupt */
155 COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt via EXTI Line21, 22 and 29*/
156 COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 global Interrupt via EXTI Line30, 31 and 32*/
157 COMP7_IRQn = 66, /*!< COMP7 global Interrupt via EXTI Line33 */
158 USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt remap */
159 USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt remap */
160 USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */
161 FPU_IRQn = 81 /*!< Floating point Interrupt */
162 } IRQn_Type;
163
164 /**
165 * @}
166 */
167
168 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
169 #include "system_stm32f3xx.h" /* STM32F3xx System Header */
170 #include <stdint.h>
171
172 /** @addtogroup Peripheral_registers_structures
173 * @{
174 */
175
176 /**
177 * @brief Analog to Digital Converter
178 */
179
180 typedef struct
181 {
182 __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
183 __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
184 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
185 __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
186 uint32_t RESERVED0; /*!< Reserved, 0x010 */
187 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
188 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
189 uint32_t RESERVED1; /*!< Reserved, 0x01C */
190 __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */
191 __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */
192 __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */
193 uint32_t RESERVED2; /*!< Reserved, 0x02C */
194 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
195 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
196 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
197 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
198 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
199 uint32_t RESERVED3; /*!< Reserved, 0x044 */
200 uint32_t RESERVED4; /*!< Reserved, 0x048 */
201 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
202 uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
203 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
204 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
205 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
206 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
207 uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
208 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
209 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
210 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
211 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
212 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
213 __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
214 __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
215 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
216 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
217 __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */
218 __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */
219
220 } ADC_TypeDef;
221
222 typedef struct
223 {
224 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
225 uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
226 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
227 __IO uint32_t CDR; /*!< ADC common regular data register for dual
228 AND triple modes, Address offset: ADC1/3 base address + 0x30C */
229 } ADC_Common_TypeDef;
230
231 /**
232 * @brief Controller Area Network TxMailBox
233 */
234 typedef struct
235 {
236 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
237 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
238 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
239 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
240 } CAN_TxMailBox_TypeDef;
241
242 /**
243 * @brief Controller Area Network FIFOMailBox
244 */
245 typedef struct
246 {
247 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
248 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
249 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
250 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
251 } CAN_FIFOMailBox_TypeDef;
252
253 /**
254 * @brief Controller Area Network FilterRegister
255 */
256 typedef struct
257 {
258 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
259 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
260 } CAN_FilterRegister_TypeDef;
261
262 /**
263 * @brief Controller Area Network
264 */
265 typedef struct
266 {
267 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
268 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
269 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
270 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
271 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
272 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
273 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
274 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
275 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
276 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
277 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
278 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
279 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
280 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
281 uint32_t RESERVED2; /*!< Reserved, 0x208 */
282 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
283 uint32_t RESERVED3; /*!< Reserved, 0x210 */
284 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
285 uint32_t RESERVED4; /*!< Reserved, 0x218 */
286 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
287 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
288 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
289 } CAN_TypeDef;
290
291 /**
292 * @brief Analog Comparators
293 */
294
295 typedef struct
296 {
297 __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
298 } COMP_TypeDef;
299
300 /**
301 * @brief CRC calculation unit
302 */
303
304 typedef struct
305 {
306 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
307 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
308 uint8_t RESERVED0; /*!< Reserved, 0x05 */
309 uint16_t RESERVED1; /*!< Reserved, 0x06 */
310 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
311 uint32_t RESERVED2; /*!< Reserved, 0x0C */
312 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
313 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
314 } CRC_TypeDef;
315
316 /**
317 * @brief Digital to Analog Converter
318 */
319
320 typedef struct
321 {
322 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
323 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
324 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
325 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
326 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
327 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
328 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
329 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
330 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
331 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
332 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
333 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
334 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
335 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
336 } DAC_TypeDef;
337
338 /**
339 * @brief Debug MCU
340 */
341
342 typedef struct
343 {
344 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
345 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
346 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
347 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
348 }DBGMCU_TypeDef;
349
350 /**
351 * @brief DMA Controller
352 */
353
354 typedef struct
355 {
356 __IO uint32_t CCR; /*!< DMA channel x configuration register */
357 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
358 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
359 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
360 } DMA_Channel_TypeDef;
361
362 typedef struct
363 {
364 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
365 __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */
366 } DMA_TypeDef;
367
368 /**
369 * @brief External Interrupt/Event Controller
370 */
371
372 typedef struct
373 {
374 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
375 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
376 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
377 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
378 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
379 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
380 uint32_t RESERVED1; /*!< Reserved, 0x18 */
381 uint32_t RESERVED2; /*!< Reserved, 0x1C */
382 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
383 __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
384 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
385 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
386 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
387 __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
388 }EXTI_TypeDef;
389
390 /**
391 * @brief FLASH Registers
392 */
393
394 typedef struct
395 {
396 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
397 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
398 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
399 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
400 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
401 __IO uint32_t AR; /*!< FLASH address register, Address offset: 0x14 */
402 uint32_t RESERVED; /*!< Reserved, 0x18 */
403 __IO uint32_t OBR; /*!< FLASH Option byte register, Address offset: 0x1C */
404 __IO uint32_t WRPR; /*!< FLASH Write register, Address offset: 0x20 */
405
406 } FLASH_TypeDef;
407
408 /**
409 * @brief Option Bytes Registers
410 */
411 typedef struct
412 {
413 __IO uint16_t RDP; /*!<FLASH option byte Read protection, Address offset: 0x00 */
414 __IO uint16_t USER; /*!<FLASH option byte user options, Address offset: 0x02 */
415 uint16_t RESERVED0; /*!< Reserved, 0x04 */
416 uint16_t RESERVED1; /*!< Reserved, 0x06 */
417 __IO uint16_t WRP0; /*!<FLASH option byte write protection 0, Address offset: 0x08 */
418 __IO uint16_t WRP1; /*!<FLASH option byte write protection 1, Address offset: 0x0C */
419 __IO uint16_t WRP2; /*!<FLASH option byte write protection 2, Address offset: 0x10 */
420 __IO uint16_t WRP3; /*!<FLASH option byte write protection 3, Address offset: 0x12 */
421 } OB_TypeDef;
422
423 /**
424 * @brief General Purpose I/O
425 */
426
427 typedef struct
428 {
429 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
430 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
431 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
432 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
433 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
434 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
435 __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
436 __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
437 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
438 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
439 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
440 }GPIO_TypeDef;
441
442 /**
443 * @brief Operational Amplifier (OPAMP)
444 */
445
446 typedef struct
447 {
448 __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */
449 } OPAMP_TypeDef;
450
451 /**
452 * @brief System configuration controller
453 */
454
455 typedef struct
456 {
457 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
458 __IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */
459 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
460 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
461 } SYSCFG_TypeDef;
462
463 /**
464 * @brief Inter-integrated Circuit Interface
465 */
466
467 typedef struct
468 {
469 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
470 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
471 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
472 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
473 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
474 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
475 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
476 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
477 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
478 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
479 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
480 }I2C_TypeDef;
481
482 /**
483 * @brief Independent WATCHDOG
484 */
485
486 typedef struct
487 {
488 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
489 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
490 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
491 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
492 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
493 } IWDG_TypeDef;
494
495 /**
496 * @brief Power Control
497 */
498
499 typedef struct
500 {
501 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
502 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
503 } PWR_TypeDef;
504
505 /**
506 * @brief Reset and Clock Control
507 */
508 typedef struct
509 {
510 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
511 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
512 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
513 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
514 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
515 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
516 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
517 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
518 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
519 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
520 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
521 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
522 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
523 } RCC_TypeDef;
524
525 /**
526 * @brief Real-Time Clock
527 */
528
529 typedef struct
530 {
531 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
532 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
533 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
534 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
535 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
536 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
537 uint32_t RESERVED0; /*!< Reserved, 0x18 */
538 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
539 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
540 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
541 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
542 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
543 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
544 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
545 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
546 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
547 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
548 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
549 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
550 uint32_t RESERVED7; /*!< Reserved, 0x4C */
551 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
552 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
553 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
554 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
555 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
556 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
557 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
558 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
559 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
560 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
561 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
562 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
563 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
564 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
565 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
566 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
567 } RTC_TypeDef;
568
569
570 /**
571 * @brief Serial Peripheral Interface
572 */
573
574 typedef struct
575 {
576 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
577 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
578 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
579 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
580 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
581 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
582 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
583 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
584 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
585 } SPI_TypeDef;
586
587 /**
588 * @brief TIM
589 */
590 typedef struct
591 {
592 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
593 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
594 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
595 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
596 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
597 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
598 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
599 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
600 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
601 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
602 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
603 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
604 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
605 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
606 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
607 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
608 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
609 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
610 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
611 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
612 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
613 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
614 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
615 __IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */
616 } TIM_TypeDef;
617
618 /**
619 * @brief Touch Sensing Controller (TSC)
620 */
621 typedef struct
622 {
623 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
624 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
625 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
626 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
627 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
628 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
629 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
630 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
631 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
632 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
633 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
634 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
635 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
636 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
637 } TSC_TypeDef;
638
639 /**
640 * @brief Universal Synchronous Asynchronous Receiver Transmitter
641 */
642
643 typedef struct
644 {
645 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
646 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
647 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
648 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
649 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
650 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
651 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
652 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
653 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
654 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
655 uint16_t RESERVED1; /*!< Reserved, 0x26 */
656 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
657 uint16_t RESERVED2; /*!< Reserved, 0x2A */
658 } USART_TypeDef;
659
660 /**
661 * @brief Universal Serial Bus Full Speed Device
662 */
663
664 typedef struct
665 {
666 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
667 __IO uint16_t RESERVED0; /*!< Reserved */
668 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
669 __IO uint16_t RESERVED1; /*!< Reserved */
670 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
671 __IO uint16_t RESERVED2; /*!< Reserved */
672 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
673 __IO uint16_t RESERVED3; /*!< Reserved */
674 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
675 __IO uint16_t RESERVED4; /*!< Reserved */
676 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
677 __IO uint16_t RESERVED5; /*!< Reserved */
678 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
679 __IO uint16_t RESERVED6; /*!< Reserved */
680 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
681 __IO uint16_t RESERVED7[17]; /*!< Reserved */
682 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
683 __IO uint16_t RESERVED8; /*!< Reserved */
684 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
685 __IO uint16_t RESERVED9; /*!< Reserved */
686 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
687 __IO uint16_t RESERVEDA; /*!< Reserved */
688 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
689 __IO uint16_t RESERVEDB; /*!< Reserved */
690 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
691 __IO uint16_t RESERVEDC; /*!< Reserved */
692 } USB_TypeDef;
693
694 /**
695 * @brief Window WATCHDOG
696 */
697 typedef struct
698 {
699 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
700 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
701 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
702 } WWDG_TypeDef;
703
704 /** @addtogroup Peripheral_memory_map
705 * @{
706 */
707
708 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 256KB) base address in the alias region */
709 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(8 KB) base address in the alias region */
710 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM(up to 40KB) base address in the alias region */
711 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
712
713 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(8 KB) base address in the bit-band region */
714 #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM(up to 40KB) base address in the bit-band region */
715 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
716
717
718 /*!< Peripheral memory map */
719 #define APB1PERIPH_BASE PERIPH_BASE
720 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
721 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
722 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
723 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000)
724
725 /*!< APB1 peripherals */
726 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000)
727 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400)
728 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800)
729 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000)
730 #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400)
731 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800)
732 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00)
733 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000)
734 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x00003400)
735 #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800)
736 #define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00)
737 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x00004000)
738 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400)
739 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800)
740 #define UART4_BASE (APB1PERIPH_BASE + 0x00004C00)
741 #define UART5_BASE (APB1PERIPH_BASE + 0x00005000)
742 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400)
743 #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800)
744 #define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
745 #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
746 #define CAN_BASE (APB1PERIPH_BASE + 0x00006400)
747 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000)
748 #define DAC1_BASE (APB1PERIPH_BASE + 0x00007400)
749 #define DAC_BASE DAC1_BASE
750
751 /*!< APB2 peripherals */
752 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000)
753 #define COMP1_BASE (APB2PERIPH_BASE + 0x0000001C)
754 #define COMP2_BASE (APB2PERIPH_BASE + 0x00000020)
755 #define COMP3_BASE (APB2PERIPH_BASE + 0x00000024)
756 #define COMP4_BASE (APB2PERIPH_BASE + 0x00000028)
757 #define COMP5_BASE (APB2PERIPH_BASE + 0x0000002C)
758 #define COMP6_BASE (APB2PERIPH_BASE + 0x00000030)
759 #define COMP7_BASE (APB2PERIPH_BASE + 0x00000034)
760 #define COMP_BASE COMP1_BASE
761 #define OPAMP1_BASE (APB2PERIPH_BASE + 0x00000038)
762 #define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003C)
763 #define OPAMP3_BASE (APB2PERIPH_BASE + 0x00000040)
764 #define OPAMP4_BASE (APB2PERIPH_BASE + 0x00000044)
765 #define OPAMP_BASE OPAMP1_BASE
766 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400)
767 #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00)
768 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000)
769 #define TIM8_BASE (APB2PERIPH_BASE + 0x00003400)
770 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800)
771 #define TIM15_BASE (APB2PERIPH_BASE + 0x00004000)
772 #define TIM16_BASE (APB2PERIPH_BASE + 0x00004400)
773 #define TIM17_BASE (APB2PERIPH_BASE + 0x00004800)
774
775 /*!< AHB1 peripherals */
776 #define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000)
777 #define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008)
778 #define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001C)
779 #define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030)
780 #define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044)
781 #define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058)
782 #define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006C)
783 #define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080)
784 #define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400)
785 #define DMA2_Channel1_BASE (AHB1PERIPH_BASE + 0x00000408)
786 #define DMA2_Channel2_BASE (AHB1PERIPH_BASE + 0x0000041C)
787 #define DMA2_Channel3_BASE (AHB1PERIPH_BASE + 0x00000430)
788 #define DMA2_Channel4_BASE (AHB1PERIPH_BASE + 0x00000444)
789 #define DMA2_Channel5_BASE (AHB1PERIPH_BASE + 0x00000458)
790 #define RCC_BASE (AHB1PERIPH_BASE + 0x00001000)
791 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000) /*!< Flash registers base address */
792 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
793 #define CRC_BASE (AHB1PERIPH_BASE + 0x00003000)
794 #define TSC_BASE (AHB1PERIPH_BASE + 0x00004000)
795
796 /*!< AHB2 peripherals */
797 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
798 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
799 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
800 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
801 #define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000)
802 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
803
804 /*!< AHB3 peripherals */
805 #define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000)
806 #define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100)
807 #define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300)
808 #define ADC3_BASE (AHB3PERIPH_BASE + 0x00000400)
809 #define ADC4_BASE (AHB3PERIPH_BASE + 0x00000500)
810 #define ADC3_4_COMMON_BASE (AHB3PERIPH_BASE + 0x00000700)
811
812 #define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
813 /**
814 * @}
815 */
816
817 /** @addtogroup Peripheral_declaration
818 * @{
819 */
820 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
821 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
822 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
823 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
824 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
825 #define RTC ((RTC_TypeDef *) RTC_BASE)
826 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
827 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
828 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
829 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
830 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
831 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
832 #define USART2 ((USART_TypeDef *) USART2_BASE)
833 #define USART3 ((USART_TypeDef *) USART3_BASE)
834 #define UART4 ((USART_TypeDef *) UART4_BASE)
835 #define UART5 ((USART_TypeDef *) UART5_BASE)
836 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
837 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
838 #define CAN ((CAN_TypeDef *) CAN_BASE)
839 #define PWR ((PWR_TypeDef *) PWR_BASE)
840 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
841 #define DAC ((DAC_TypeDef *) DAC_BASE)
842 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
843 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
844 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
845 #define COMP3 ((COMP_TypeDef *) COMP3_BASE)
846 #define COMP4 ((COMP_TypeDef *) COMP4_BASE)
847 #define COMP5 ((COMP_TypeDef *) COMP5_BASE)
848 #define COMP6 ((COMP_TypeDef *) COMP6_BASE)
849 #define COMP7 ((COMP_TypeDef *) COMP7_BASE)
850 #define COMP ((COMP_TypeDef *) COMP_BASE)
851 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
852 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
853 #define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)
854 #define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE)
855 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
856 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
857 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
858 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
859 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
860 #define USART1 ((USART_TypeDef *) USART1_BASE)
861 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
862 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
863 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
864 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
865 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
866 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
867 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
868 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
869 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
870 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
871 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
872 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
873 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
874 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
875 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
876 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
877 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
878 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
879 #define RCC ((RCC_TypeDef *) RCC_BASE)
880 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
881 #define OB ((OB_TypeDef *) OB_BASE)
882 #define CRC ((CRC_TypeDef *) CRC_BASE)
883 #define TSC ((TSC_TypeDef *) TSC_BASE)
884 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
885 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
886 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
887 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
888 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
889 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
890 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
891 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
892 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
893 #define ADC4 ((ADC_TypeDef *) ADC4_BASE)
894 #define ADC1_2_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)
895 #define ADC3_4_COMMON ((ADC_Common_TypeDef *) ADC3_4_COMMON_BASE)
896 #define USB ((USB_TypeDef *) USB_BASE)
897 /**
898 * @}
899 */
900
901 /** @addtogroup Exported_constants
902 * @{
903 */
904
905 /** @addtogroup Peripheral_Registers_Bits_Definition
906 * @{
907 */
908
909 /******************************************************************************/
910 /* Peripheral Registers_Bits_Definition */
911 /******************************************************************************/
912
913 /******************************************************************************/
914 /* */
915 /* Analog to Digital Converter SAR (ADC) */
916 /* */
917 /******************************************************************************/
918 /******************** Bit definition for ADC_ISR register ********************/
919 #define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
920 #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
921 #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion flag */
922 #define ADC_ISR_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions flag */
923 #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< ADC overrun flag */
924 #define ADC_ISR_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion flag */
925 #define ADC_ISR_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions flag */
926 #define ADC_ISR_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 flag */
927 #define ADC_ISR_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 flag */
928 #define ADC_ISR_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 flag */
929 #define ADC_ISR_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow flag */
930
931 /******************** Bit definition for ADC_IER register ********************/
932 #define ADC_IER_RDY ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) interrupt source */
933 #define ADC_IER_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling interrupt source */
934 #define ADC_IER_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion interrupt source */
935 #define ADC_IER_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions interrupt source */
936 #define ADC_IER_OVR ((uint32_t)0x00000010) /*!< ADC overrun interrupt source */
937 #define ADC_IER_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion interrupt source */
938 #define ADC_IER_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions interrupt source */
939 #define ADC_IER_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 interrupt source */
940 #define ADC_IER_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 interrupt source */
941 #define ADC_IER_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 interrupt source */
942 #define ADC_IER_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow interrupt source */
943
944 /******************** Bit definition for ADC_CR register ********************/
945 #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC Enable control */
946 #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC Disable command */
947 #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC Start of Regular conversion */
948 #define ADC_CR_JADSTART ((uint32_t)0x00000008) /*!< ADC Start of injected conversion */
949 #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC Stop of Regular conversion */
950 #define ADC_CR_JADSTP ((uint32_t)0x00000020) /*!< ADC Stop of injected conversion */
951 #define ADC_CR_ADVREGEN ((uint32_t)0x30000000) /*!< ADC Voltage regulator Enable */
952 #define ADC_CR_ADVREGEN_0 ((uint32_t)0x10000000) /*!< ADC ADVREGEN bit 0 */
953 #define ADC_CR_ADVREGEN_1 ((uint32_t)0x20000000) /*!< ADC ADVREGEN bit 1 */
954 #define ADC_CR_ADCALDIF ((uint32_t)0x40000000) /*!< ADC Differential Mode for calibration */
955 #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC Calibration */
956
957 /******************** Bit definition for ADC_CFGR register ********************/
958 #define ADC_CFGR_DMAEN ((uint32_t)0x00000001) /*!< ADC DMA Enable */
959 #define ADC_CFGR_DMACFG ((uint32_t)0x00000002) /*!< ADC DMA configuration */
960
961 #define ADC_CFGR_RES ((uint32_t)0x00000018) /*!< ADC Data resolution */
962 #define ADC_CFGR_RES_0 ((uint32_t)0x00000008) /*!< ADC RES bit 0 */
963 #define ADC_CFGR_RES_1 ((uint32_t)0x00000010) /*!< ADC RES bit 1 */
964
965 #define ADC_CFGR_ALIGN ((uint32_t)0x00000020) /*!< ADC Data Alignement */
966
967 #define ADC_CFGR_EXTSEL ((uint32_t)0x000003C0) /*!< ADC External trigger selection for regular group */
968 #define ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040) /*!< ADC EXTSEL bit 0 */
969 #define ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080) /*!< ADC EXTSEL bit 1 */
970 #define ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100) /*!< ADC EXTSEL bit 2 */
971 #define ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200) /*!< ADC EXTSEL bit 3 */
972
973 #define ADC_CFGR_EXTEN ((uint32_t)0x00000C00) /*!< ADC External trigger enable and polarity selection for regular channels */
974 #define ADC_CFGR_EXTEN_0 ((uint32_t)0x00000400) /*!< ADC EXTEN bit 0 */
975 #define ADC_CFGR_EXTEN_1 ((uint32_t)0x00000800) /*!< ADC EXTEN bit 1 */
976
977 #define ADC_CFGR_OVRMOD ((uint32_t)0x00001000) /*!< ADC overrun mode */
978 #define ADC_CFGR_CONT ((uint32_t)0x00002000) /*!< ADC Single/continuous conversion mode for regular conversion */
979 #define ADC_CFGR_AUTDLY ((uint32_t)0x00004000) /*!< ADC Delayed conversion mode */
980 #define ADC_CFGR_AUTOFF ((uint32_t)0x00008000) /*!< ADC Auto power OFF */
981 #define ADC_CFGR_DISCEN ((uint32_t)0x00010000) /*!< ADC Discontinuous mode for regular channels */
982
983 #define ADC_CFGR_DISCNUM ((uint32_t)0x000E0000) /*!< ADC Discontinuous mode channel count */
984 #define ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000) /*!< ADC DISCNUM bit 0 */
985 #define ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000) /*!< ADC DISCNUM bit 1 */
986 #define ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000) /*!< ADC DISCNUM bit 2 */
987
988 #define ADC_CFGR_JDISCEN ((uint32_t)0x00100000) /*!< ADC Discontinous mode on injected channels */
989 #define ADC_CFGR_JQM ((uint32_t)0x00200000) /*!< ADC JSQR Queue mode */
990 #define ADC_CFGR_AWD1SGL ((uint32_t)0x00400000) /*!< Eanble the watchdog 1 on a single channel or on all channels */
991 #define ADC_CFGR_AWD1EN ((uint32_t)0x00800000) /*!< ADC Analog watchdog 1 enable on regular Channels */
992 #define ADC_CFGR_JAWD1EN ((uint32_t)0x01000000) /*!< ADC Analog watchdog 1 enable on injected Channels */
993 #define ADC_CFGR_JAUTO ((uint32_t)0x02000000) /*!< ADC Automatic injected group conversion */
994
995 #define ADC_CFGR_AWD1CH ((uint32_t)0x7C000000) /*!< ADC Analog watchdog 1 Channel selection */
996 #define ADC_CFGR_AWD1CH_0 ((uint32_t)0x04000000) /*!< ADC AWD1CH bit 0 */
997 #define ADC_CFGR_AWD1CH_1 ((uint32_t)0x08000000) /*!< ADC AWD1CH bit 1 */
998 #define ADC_CFGR_AWD1CH_2 ((uint32_t)0x10000000) /*!< ADC AWD1CH bit 2 */
999 #define ADC_CFGR_AWD1CH_3 ((uint32_t)0x20000000) /*!< ADC AWD1CH bit 3 */
1000 #define ADC_CFGR_AWD1CH_4 ((uint32_t)0x40000000) /*!< ADC AWD1CH bit 4 */
1001
1002 /******************** Bit definition for ADC_SMPR1 register ********************/
1003 #define ADC_SMPR1_SMP0 ((uint32_t)0x00000007) /*!< ADC Channel 0 Sampling time selection */
1004 #define ADC_SMPR1_SMP0_0 ((uint32_t)0x00000001) /*!< ADC SMP0 bit 0 */
1005 #define ADC_SMPR1_SMP0_1 ((uint32_t)0x00000002) /*!< ADC SMP0 bit 1 */
1006 #define ADC_SMPR1_SMP0_2 ((uint32_t)0x00000004) /*!< ADC SMP0 bit 2 */
1007
1008 #define ADC_SMPR1_SMP1 ((uint32_t)0x00000038) /*!< ADC Channel 1 Sampling time selection */
1009 #define ADC_SMPR1_SMP1_0 ((uint32_t)0x00000008) /*!< ADC SMP1 bit 0 */
1010 #define ADC_SMPR1_SMP1_1 ((uint32_t)0x00000010) /*!< ADC SMP1 bit 1 */
1011 #define ADC_SMPR1_SMP1_2 ((uint32_t)0x00000020) /*!< ADC SMP1 bit 2 */
1012
1013 #define ADC_SMPR1_SMP2 ((uint32_t)0x000001C0) /*!< ADC Channel 2 Sampling time selection */
1014 #define ADC_SMPR1_SMP2_0 ((uint32_t)0x00000040) /*!< ADC SMP2 bit 0 */
1015 #define ADC_SMPR1_SMP2_1 ((uint32_t)0x00000080) /*!< ADC SMP2 bit 1 */
1016 #define ADC_SMPR1_SMP2_2 ((uint32_t)0x00000100) /*!< ADC SMP2 bit 2 */
1017
1018 #define ADC_SMPR1_SMP3 ((uint32_t)0x00000E00) /*!< ADC Channel 3 Sampling time selection */
1019 #define ADC_SMPR1_SMP3_0 ((uint32_t)0x00000200) /*!< ADC SMP3 bit 0 */
1020 #define ADC_SMPR1_SMP3_1 ((uint32_t)0x00000400) /*!< ADC SMP3 bit 1 */
1021 #define ADC_SMPR1_SMP3_2 ((uint32_t)0x00000800) /*!< ADC SMP3 bit 2 */
1022
1023 #define ADC_SMPR1_SMP4 ((uint32_t)0x00007000) /*!< ADC Channel 4 Sampling time selection */
1024 #define ADC_SMPR1_SMP4_0 ((uint32_t)0x00001000) /*!< ADC SMP4 bit 0 */
1025 #define ADC_SMPR1_SMP4_1 ((uint32_t)0x00002000) /*!< ADC SMP4 bit 1 */
1026 #define ADC_SMPR1_SMP4_2 ((uint32_t)0x00004000) /*!< ADC SMP4 bit 2 */
1027
1028 #define ADC_SMPR1_SMP5 ((uint32_t)0x00038000) /*!< ADC Channel 5 Sampling time selection */
1029 #define ADC_SMPR1_SMP5_0 ((uint32_t)0x00008000) /*!< ADC SMP5 bit 0 */
1030 #define ADC_SMPR1_SMP5_1 ((uint32_t)0x00010000) /*!< ADC SMP5 bit 1 */
1031 #define ADC_SMPR1_SMP5_2 ((uint32_t)0x00020000) /*!< ADC SMP5 bit 2 */
1032
1033 #define ADC_SMPR1_SMP6 ((uint32_t)0x001C0000) /*!< ADC Channel 6 Sampling time selection */
1034 #define ADC_SMPR1_SMP6_0 ((uint32_t)0x00040000) /*!< ADC SMP6 bit 0 */
1035 #define ADC_SMPR1_SMP6_1 ((uint32_t)0x00080000) /*!< ADC SMP6 bit 1 */
1036 #define ADC_SMPR1_SMP6_2 ((uint32_t)0x00100000) /*!< ADC SMP6 bit 2 */
1037
1038 #define ADC_SMPR1_SMP7 ((uint32_t)0x00E00000) /*!< ADC Channel 7 Sampling time selection */
1039 #define ADC_SMPR1_SMP7_0 ((uint32_t)0x00200000) /*!< ADC SMP7 bit 0 */
1040 #define ADC_SMPR1_SMP7_1 ((uint32_t)0x00400000) /*!< ADC SMP7 bit 1 */
1041 #define ADC_SMPR1_SMP7_2 ((uint32_t)0x00800000) /*!< ADC SMP7 bit 2 */
1042
1043 #define ADC_SMPR1_SMP8 ((uint32_t)0x07000000) /*!< ADC Channel 8 Sampling time selection */
1044 #define ADC_SMPR1_SMP8_0 ((uint32_t)0x01000000) /*!< ADC SMP8 bit 0 */
1045 #define ADC_SMPR1_SMP8_1 ((uint32_t)0x02000000) /*!< ADC SMP8 bit 1 */
1046 #define ADC_SMPR1_SMP8_2 ((uint32_t)0x04000000) /*!< ADC SMP8 bit 2 */
1047
1048 #define ADC_SMPR1_SMP9 ((uint32_t)0x38000000) /*!< ADC Channel 9 Sampling time selection */
1049 #define ADC_SMPR1_SMP9_0 ((uint32_t)0x08000000) /*!< ADC SMP9 bit 0 */
1050 #define ADC_SMPR1_SMP9_1 ((uint32_t)0x10000000) /*!< ADC SMP9 bit 1 */
1051 #define ADC_SMPR1_SMP9_2 ((uint32_t)0x20000000) /*!< ADC SMP9 bit 2 */
1052
1053 /******************** Bit definition for ADC_SMPR2 register ********************/
1054 #define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< ADC Channel 10 Sampling time selection */
1055 #define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< ADC SMP10 bit 0 */
1056 #define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< ADC SMP10 bit 1 */
1057 #define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< ADC SMP10 bit 2 */
1058
1059 #define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< ADC Channel 11 Sampling time selection */
1060 #define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< ADC SMP11 bit 0 */
1061 #define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< ADC SMP11 bit 1 */
1062 #define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< ADC SMP11 bit 2 */
1063
1064 #define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< ADC Channel 12 Sampling time selection */
1065 #define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< ADC SMP12 bit 0 */
1066 #define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< ADC SMP12 bit 1 */
1067 #define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< ADC SMP12 bit 2 */
1068
1069 #define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< ADC Channel 13 Sampling time selection */
1070 #define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< ADC SMP13 bit 0 */
1071 #define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< ADC SMP13 bit 1 */
1072 #define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< ADC SMP13 bit 2 */
1073
1074 #define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< ADC Channel 14 Sampling time selection */
1075 #define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< ADC SMP14 bit 0 */
1076 #define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< ADC SMP14 bit 1 */
1077 #define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< ADC SMP14 bit 2 */
1078
1079 #define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< ADC Channel 15 Sampling time selection */
1080 #define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< ADC SMP15 bit 0 */
1081 #define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< ADC SMP15 bit 1 */
1082 #define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< ADC SMP15 bit 2 */
1083
1084 #define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< ADC Channel 16 Sampling time selection */
1085 #define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< ADC SMP16 bit 0 */
1086 #define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< ADC SMP16 bit 1 */
1087 #define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< ADC SMP16 bit 2 */
1088
1089 #define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< ADC Channel 17 Sampling time selection */
1090 #define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< ADC SMP17 bit 0 */
1091 #define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< ADC SMP17 bit 1 */
1092 #define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< ADC SMP17 bit 2 */
1093
1094 #define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< ADC Channel 18 Sampling time selection */
1095 #define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< ADC SMP18 bit 0 */
1096 #define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< ADC SMP18 bit 1 */
1097 #define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< ADC SMP18 bit 2 */
1098
1099 /******************** Bit definition for ADC_TR1 register ********************/
1100 #define ADC_TR1_LT1 ((uint32_t)0x00000FFF) /*!< ADC Analog watchdog 1 lower threshold */
1101 #define ADC_TR1_LT1_0 ((uint32_t)0x00000001) /*!< ADC LT1 bit 0 */
1102 #define ADC_TR1_LT1_1 ((uint32_t)0x00000002) /*!< ADC LT1 bit 1 */
1103 #define ADC_TR1_LT1_2 ((uint32_t)0x00000004) /*!< ADC LT1 bit 2 */
1104 #define ADC_TR1_LT1_3 ((uint32_t)0x00000008) /*!< ADC LT1 bit 3 */
1105 #define ADC_TR1_LT1_4 ((uint32_t)0x00000010) /*!< ADC LT1 bit 4 */
1106 #define ADC_TR1_LT1_5 ((uint32_t)0x00000020) /*!< ADC LT1 bit 5 */
1107 #define ADC_TR1_LT1_6 ((uint32_t)0x00000040) /*!< ADC LT1 bit 6 */
1108 #define ADC_TR1_LT1_7 ((uint32_t)0x00000080) /*!< ADC LT1 bit 7 */
1109 #define ADC_TR1_LT1_8 ((uint32_t)0x00000100) /*!< ADC LT1 bit 8 */
1110 #define ADC_TR1_LT1_9 ((uint32_t)0x00000200) /*!< ADC LT1 bit 9 */
1111 #define ADC_TR1_LT1_10 ((uint32_t)0x00000400) /*!< ADC LT1 bit 10 */
1112 #define ADC_TR1_LT1_11 ((uint32_t)0x00000800) /*!< ADC LT1 bit 11 */
1113
1114 #define ADC_TR1_HT1 ((uint32_t)0x0FFF0000) /*!< ADC Analog watchdog 1 higher threshold */
1115 #define ADC_TR1_HT1_0 ((uint32_t)0x00010000) /*!< ADC HT1 bit 0 */
1116 #define ADC_TR1_HT1_1 ((uint32_t)0x00020000) /*!< ADC HT1 bit 1 */
1117 #define ADC_TR1_HT1_2 ((uint32_t)0x00040000) /*!< ADC HT1 bit 2 */
1118 #define ADC_TR1_HT1_3 ((uint32_t)0x00080000) /*!< ADC HT1 bit 3 */
1119 #define ADC_TR1_HT1_4 ((uint32_t)0x00100000) /*!< ADC HT1 bit 4 */
1120 #define ADC_TR1_HT1_5 ((uint32_t)0x00200000) /*!< ADC HT1 bit 5 */
1121 #define ADC_TR1_HT1_6 ((uint32_t)0x00400000) /*!< ADC HT1 bit 6 */
1122 #define ADC_TR1_HT1_7 ((uint32_t)0x00800000) /*!< ADC HT1 bit 7 */
1123 #define ADC_TR1_HT1_8 ((uint32_t)0x01000000) /*!< ADC HT1 bit 8 */
1124 #define ADC_TR1_HT1_9 ((uint32_t)0x02000000) /*!< ADC HT1 bit 9 */
1125 #define ADC_TR1_HT1_10 ((uint32_t)0x04000000) /*!< ADC HT1 bit 10 */
1126 #define ADC_TR1_HT1_11 ((uint32_t)0x08000000) /*!< ADC HT1 bit 11 */
1127
1128 /******************** Bit definition for ADC_TR2 register ********************/
1129 #define ADC_TR2_LT2 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 2 lower threshold */
1130 #define ADC_TR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */
1131 #define ADC_TR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */
1132 #define ADC_TR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */
1133 #define ADC_TR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */
1134 #define ADC_TR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */
1135 #define ADC_TR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */
1136 #define ADC_TR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */
1137 #define ADC_TR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */
1138
1139 #define ADC_TR2_HT2 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 2 higher threshold */
1140 #define ADC_TR2_HT2_0 ((uint32_t)0x00010000) /*!< ADC HT2 bit 0 */
1141 #define ADC_TR2_HT2_1 ((uint32_t)0x00020000) /*!< ADC HT2 bit 1 */
1142 #define ADC_TR2_HT2_2 ((uint32_t)0x00040000) /*!< ADC HT2 bit 2 */
1143 #define ADC_TR2_HT2_3 ((uint32_t)0x00080000) /*!< ADC HT2 bit 3 */
1144 #define ADC_TR2_HT2_4 ((uint32_t)0x00100000) /*!< ADC HT2 bit 4 */
1145 #define ADC_TR2_HT2_5 ((uint32_t)0x00200000) /*!< ADC HT2 bit 5 */
1146 #define ADC_TR2_HT2_6 ((uint32_t)0x00400000) /*!< ADC HT2 bit 6 */
1147 #define ADC_TR2_HT2_7 ((uint32_t)0x00800000) /*!< ADC HT2 bit 7 */
1148
1149 /******************** Bit definition for ADC_TR3 register ********************/
1150 #define ADC_TR3_LT3 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 3 lower threshold */
1151 #define ADC_TR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */
1152 #define ADC_TR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */
1153 #define ADC_TR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */
1154 #define ADC_TR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */
1155 #define ADC_TR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */
1156 #define ADC_TR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */
1157 #define ADC_TR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */
1158 #define ADC_TR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */
1159
1160 #define ADC_TR3_HT3 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 3 higher threshold */
1161 #define ADC_TR3_HT3_0 ((uint32_t)0x00010000) /*!< ADC HT3 bit 0 */
1162 #define ADC_TR3_HT3_1 ((uint32_t)0x00020000) /*!< ADC HT3 bit 1 */
1163 #define ADC_TR3_HT3_2 ((uint32_t)0x00040000) /*!< ADC HT3 bit 2 */
1164 #define ADC_TR3_HT3_3 ((uint32_t)0x00080000) /*!< ADC HT3 bit 3 */
1165 #define ADC_TR3_HT3_4 ((uint32_t)0x00100000) /*!< ADC HT3 bit 4 */
1166 #define ADC_TR3_HT3_5 ((uint32_t)0x00200000) /*!< ADC HT3 bit 5 */
1167 #define ADC_TR3_HT3_6 ((uint32_t)0x00400000) /*!< ADC HT3 bit 6 */
1168 #define ADC_TR3_HT3_7 ((uint32_t)0x00800000) /*!< ADC HT3 bit 7 */
1169
1170 /******************** Bit definition for ADC_SQR1 register ********************/
1171 #define ADC_SQR1_L ((uint32_t)0x0000000F) /*!< ADC regular channel sequence lenght */
1172 #define ADC_SQR1_L_0 ((uint32_t)0x00000001) /*!< ADC L bit 0 */
1173 #define ADC_SQR1_L_1 ((uint32_t)0x00000002) /*!< ADC L bit 1 */
1174 #define ADC_SQR1_L_2 ((uint32_t)0x00000004) /*!< ADC L bit 2 */
1175 #define ADC_SQR1_L_3 ((uint32_t)0x00000008) /*!< ADC L bit 3 */
1176
1177 #define ADC_SQR1_SQ1 ((uint32_t)0x000007C0) /*!< ADC 1st conversion in regular sequence */
1178 #define ADC_SQR1_SQ1_0 ((uint32_t)0x00000040) /*!< ADC SQ1 bit 0 */
1179 #define ADC_SQR1_SQ1_1 ((uint32_t)0x00000080) /*!< ADC SQ1 bit 1 */
1180 #define ADC_SQR1_SQ1_2 ((uint32_t)0x00000100) /*!< ADC SQ1 bit 2 */
1181 #define ADC_SQR1_SQ1_3 ((uint32_t)0x00000200) /*!< ADC SQ1 bit 3 */
1182 #define ADC_SQR1_SQ1_4 ((uint32_t)0x00000400) /*!< ADC SQ1 bit 4 */
1183
1184 #define ADC_SQR1_SQ2 ((uint32_t)0x0001F000) /*!< ADC 2nd conversion in regular sequence */
1185 #define ADC_SQR1_SQ2_0 ((uint32_t)0x00001000) /*!< ADC SQ2 bit 0 */
1186 #define ADC_SQR1_SQ2_1 ((uint32_t)0x00002000) /*!< ADC SQ2 bit 1 */
1187 #define ADC_SQR1_SQ2_2 ((uint32_t)0x00004000) /*!< ADC SQ2 bit 2 */
1188 #define ADC_SQR1_SQ2_3 ((uint32_t)0x00008000) /*!< ADC SQ2 bit 3 */
1189 #define ADC_SQR1_SQ2_4 ((uint32_t)0x00010000) /*!< ADC SQ2 bit 4 */
1190
1191 #define ADC_SQR1_SQ3 ((uint32_t)0x007C0000) /*!< ADC 3rd conversion in regular sequence */
1192 #define ADC_SQR1_SQ3_0 ((uint32_t)0x00040000) /*!< ADC SQ3 bit 0 */
1193 #define ADC_SQR1_SQ3_1 ((uint32_t)0x00080000) /*!< ADC SQ3 bit 1 */
1194 #define ADC_SQR1_SQ3_2 ((uint32_t)0x00100000) /*!< ADC SQ3 bit 2 */
1195 #define ADC_SQR1_SQ3_3 ((uint32_t)0x00200000) /*!< ADC SQ3 bit 3 */
1196 #define ADC_SQR1_SQ3_4 ((uint32_t)0x00400000) /*!< ADC SQ3 bit 4 */
1197
1198 #define ADC_SQR1_SQ4 ((uint32_t)0x1F000000) /*!< ADC 4th conversion in regular sequence */
1199 #define ADC_SQR1_SQ4_0 ((uint32_t)0x01000000) /*!< ADC SQ4 bit 0 */
1200 #define ADC_SQR1_SQ4_1 ((uint32_t)0x02000000) /*!< ADC SQ4 bit 1 */
1201 #define ADC_SQR1_SQ4_2 ((uint32_t)0x04000000) /*!< ADC SQ4 bit 2 */
1202 #define ADC_SQR1_SQ4_3 ((uint32_t)0x08000000) /*!< ADC SQ4 bit 3 */
1203 #define ADC_SQR1_SQ4_4 ((uint32_t)0x10000000) /*!< ADC SQ4 bit 4 */
1204
1205 /******************** Bit definition for ADC_SQR2 register ********************/
1206 #define ADC_SQR2_SQ5 ((uint32_t)0x0000001F) /*!< ADC 5th conversion in regular sequence */
1207 #define ADC_SQR2_SQ5_0 ((uint32_t)0x00000001) /*!< ADC SQ5 bit 0 */
1208 #define ADC_SQR2_SQ5_1 ((uint32_t)0x00000002) /*!< ADC SQ5 bit 1 */
1209 #define ADC_SQR2_SQ5_2 ((uint32_t)0x00000004) /*!< ADC SQ5 bit 2 */
1210 #define ADC_SQR2_SQ5_3 ((uint32_t)0x00000008) /*!< ADC SQ5 bit 3 */
1211 #define ADC_SQR2_SQ5_4 ((uint32_t)0x00000010) /*!< ADC SQ5 bit 4 */
1212
1213 #define ADC_SQR2_SQ6 ((uint32_t)0x000007C0) /*!< ADC 6th conversion in regular sequence */
1214 #define ADC_SQR2_SQ6_0 ((uint32_t)0x00000040) /*!< ADC SQ6 bit 0 */
1215 #define ADC_SQR2_SQ6_1 ((uint32_t)0x00000080) /*!< ADC SQ6 bit 1 */
1216 #define ADC_SQR2_SQ6_2 ((uint32_t)0x00000100) /*!< ADC SQ6 bit 2 */
1217 #define ADC_SQR2_SQ6_3 ((uint32_t)0x00000200) /*!< ADC SQ6 bit 3 */
1218 #define ADC_SQR2_SQ6_4 ((uint32_t)0x00000400) /*!< ADC SQ6 bit 4 */
1219
1220 #define ADC_SQR2_SQ7 ((uint32_t)0x0001F000) /*!< ADC 7th conversion in regular sequence */
1221 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00001000) /*!< ADC SQ7 bit 0 */
1222 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00002000) /*!< ADC SQ7 bit 1 */
1223 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00004000) /*!< ADC SQ7 bit 2 */
1224 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00008000) /*!< ADC SQ7 bit 3 */
1225 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00010000) /*!< ADC SQ7 bit 4 */
1226
1227 #define ADC_SQR2_SQ8 ((uint32_t)0x007C0000) /*!< ADC 8th conversion in regular sequence */
1228 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00040000) /*!< ADC SQ8 bit 0 */
1229 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00080000) /*!< ADC SQ8 bit 1 */
1230 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00100000) /*!< ADC SQ8 bit 2 */
1231 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00200000) /*!< ADC SQ8 bit 3 */
1232 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00400000) /*!< ADC SQ8 bit 4 */
1233
1234 #define ADC_SQR2_SQ9 ((uint32_t)0x1F000000) /*!< ADC 9th conversion in regular sequence */
1235 #define ADC_SQR2_SQ9_0 ((uint32_t)0x01000000) /*!< ADC SQ9 bit 0 */
1236 #define ADC_SQR2_SQ9_1 ((uint32_t)0x02000000) /*!< ADC SQ9 bit 1 */
1237 #define ADC_SQR2_SQ9_2 ((uint32_t)0x04000000) /*!< ADC SQ9 bit 2 */
1238 #define ADC_SQR2_SQ9_3 ((uint32_t)0x08000000) /*!< ADC SQ9 bit 3 */
1239 #define ADC_SQR2_SQ9_4 ((uint32_t)0x10000000) /*!< ADC SQ9 bit 4 */
1240
1241 /******************** Bit definition for ADC_SQR3 register ********************/
1242 #define ADC_SQR3_SQ10 ((uint32_t)0x0000001F) /*!< ADC 10th conversion in regular sequence */
1243 #define ADC_SQR3_SQ10_0 ((uint32_t)0x00000001) /*!< ADC SQ10 bit 0 */
1244 #define ADC_SQR3_SQ10_1 ((uint32_t)0x00000002) /*!< ADC SQ10 bit 1 */
1245 #define ADC_SQR3_SQ10_2 ((uint32_t)0x00000004) /*!< ADC SQ10 bit 2 */
1246 #define ADC_SQR3_SQ10_3 ((uint32_t)0x00000008) /*!< ADC SQ10 bit 3 */
1247 #define ADC_SQR3_SQ10_4 ((uint32_t)0x00000010) /*!< ADC SQ10 bit 4 */
1248
1249 #define ADC_SQR3_SQ11 ((uint32_t)0x000007C0) /*!< ADC 11th conversion in regular sequence */
1250 #define ADC_SQR3_SQ11_0 ((uint32_t)0x00000040) /*!< ADC SQ11 bit 0 */
1251 #define ADC_SQR3_SQ11_1 ((uint32_t)0x00000080) /*!< ADC SQ11 bit 1 */
1252 #define ADC_SQR3_SQ11_2 ((uint32_t)0x00000100) /*!< ADC SQ11 bit 2 */
1253 #define ADC_SQR3_SQ11_3 ((uint32_t)0x00000200) /*!< ADC SQ11 bit 3 */
1254 #define ADC_SQR3_SQ11_4 ((uint32_t)0x00000400) /*!< ADC SQ11 bit 4 */
1255
1256 #define ADC_SQR3_SQ12 ((uint32_t)0x0001F000) /*!< ADC 12th conversion in regular sequence */
1257 #define ADC_SQR3_SQ12_0 ((uint32_t)0x00001000) /*!< ADC SQ12 bit 0 */
1258 #define ADC_SQR3_SQ12_1 ((uint32_t)0x00002000) /*!< ADC SQ12 bit 1 */
1259 #define ADC_SQR3_SQ12_2 ((uint32_t)0x00004000) /*!< ADC SQ12 bit 2 */
1260 #define ADC_SQR3_SQ12_3 ((uint32_t)0x00008000) /*!< ADC SQ12 bit 3 */
1261 #define ADC_SQR3_SQ12_4 ((uint32_t)0x00010000) /*!< ADC SQ12 bit 4 */
1262
1263 #define ADC_SQR3_SQ13 ((uint32_t)0x007C0000) /*!< ADC 13th conversion in regular sequence */
1264 #define ADC_SQR3_SQ13_0 ((uint32_t)0x00040000) /*!< ADC SQ13 bit 0 */
1265 #define ADC_SQR3_SQ13_1 ((uint32_t)0x00080000) /*!< ADC SQ13 bit 1 */
1266 #define ADC_SQR3_SQ13_2 ((uint32_t)0x00100000) /*!< ADC SQ13 bit 2 */
1267 #define ADC_SQR3_SQ13_3 ((uint32_t)0x00200000) /*!< ADC SQ13 bit 3 */
1268 #define ADC_SQR3_SQ13_4 ((uint32_t)0x00400000) /*!< ADC SQ13 bit 4 */
1269
1270 #define ADC_SQR3_SQ14 ((uint32_t)0x1F000000) /*!< ADC 14th conversion in regular sequence */
1271 #define ADC_SQR3_SQ14_0 ((uint32_t)0x01000000) /*!< ADC SQ14 bit 0 */
1272 #define ADC_SQR3_SQ14_1 ((uint32_t)0x02000000) /*!< ADC SQ14 bit 1 */
1273 #define ADC_SQR3_SQ14_2 ((uint32_t)0x04000000) /*!< ADC SQ14 bit 2 */
1274 #define ADC_SQR3_SQ14_3 ((uint32_t)0x08000000) /*!< ADC SQ14 bit 3 */
1275 #define ADC_SQR3_SQ14_4 ((uint32_t)0x10000000) /*!< ADC SQ14 bit 4 */
1276
1277 /******************** Bit definition for ADC_SQR4 register ********************/
1278 #define ADC_SQR4_SQ15 ((uint32_t)0x0000001F) /*!< ADC 15th conversion in regular sequence */
1279 #define ADC_SQR4_SQ15_0 ((uint32_t)0x00000001) /*!< ADC SQ15 bit 0 */
1280 #define ADC_SQR4_SQ15_1 ((uint32_t)0x00000002) /*!< ADC SQ15 bit 1 */
1281 #define ADC_SQR4_SQ15_2 ((uint32_t)0x00000004) /*!< ADC SQ15 bit 2 */
1282 #define ADC_SQR4_SQ15_3 ((uint32_t)0x00000008) /*!< ADC SQ15 bit 3 */
1283 #define ADC_SQR4_SQ15_4 ((uint32_t)0x00000010) /*!< ADC SQ105 bit 4 */
1284
1285 #define ADC_SQR4_SQ16 ((uint32_t)0x000007C0) /*!< ADC 16th conversion in regular sequence */
1286 #define ADC_SQR4_SQ16_0 ((uint32_t)0x00000040) /*!< ADC SQ16 bit 0 */
1287 #define ADC_SQR4_SQ16_1 ((uint32_t)0x00000080) /*!< ADC SQ16 bit 1 */
1288 #define ADC_SQR4_SQ16_2 ((uint32_t)0x00000100) /*!< ADC SQ16 bit 2 */
1289 #define ADC_SQR4_SQ16_3 ((uint32_t)0x00000200) /*!< ADC SQ16 bit 3 */
1290 #define ADC_SQR4_SQ16_4 ((uint32_t)0x00000400) /*!< ADC SQ16 bit 4 */
1291 /******************** Bit definition for ADC_DR register ********************/
1292 #define ADC_DR_RDATA ((uint32_t)0x0000FFFF) /*!< ADC regular Data converted */
1293 #define ADC_DR_RDATA_0 ((uint32_t)0x00000001) /*!< ADC RDATA bit 0 */
1294 #define ADC_DR_RDATA_1 ((uint32_t)0x00000002) /*!< ADC RDATA bit 1 */
1295 #define ADC_DR_RDATA_2 ((uint32_t)0x00000004) /*!< ADC RDATA bit 2 */
1296 #define ADC_DR_RDATA_3 ((uint32_t)0x00000008) /*!< ADC RDATA bit 3 */
1297 #define ADC_DR_RDATA_4 ((uint32_t)0x00000010) /*!< ADC RDATA bit 4 */
1298 #define ADC_DR_RDATA_5 ((uint32_t)0x00000020) /*!< ADC RDATA bit 5 */
1299 #define ADC_DR_RDATA_6 ((uint32_t)0x00000040) /*!< ADC RDATA bit 6 */
1300 #define ADC_DR_RDATA_7 ((uint32_t)0x00000080) /*!< ADC RDATA bit 7 */
1301 #define ADC_DR_RDATA_8 ((uint32_t)0x00000100) /*!< ADC RDATA bit 8 */
1302 #define ADC_DR_RDATA_9 ((uint32_t)0x00000200) /*!< ADC RDATA bit 9 */
1303 #define ADC_DR_RDATA_10 ((uint32_t)0x00000400) /*!< ADC RDATA bit 10 */
1304 #define ADC_DR_RDATA_11 ((uint32_t)0x00000800) /*!< ADC RDATA bit 11 */
1305 #define ADC_DR_RDATA_12 ((uint32_t)0x00001000) /*!< ADC RDATA bit 12 */
1306 #define ADC_DR_RDATA_13 ((uint32_t)0x00002000) /*!< ADC RDATA bit 13 */
1307 #define ADC_DR_RDATA_14 ((uint32_t)0x00004000) /*!< ADC RDATA bit 14 */
1308 #define ADC_DR_RDATA_15 ((uint32_t)0x00008000) /*!< ADC RDATA bit 15 */
1309
1310 /******************** Bit definition for ADC_JSQR register ********************/
1311 #define ADC_JSQR_JL ((uint32_t)0x00000003) /*!< ADC injected channel sequence length */
1312 #define ADC_JSQR_JL_0 ((uint32_t)0x00000001) /*!< ADC JL bit 0 */
1313 #define ADC_JSQR_JL_1 ((uint32_t)0x00000002) /*!< ADC JL bit 1 */
1314
1315 #define ADC_JSQR_JEXTSEL ((uint32_t)0x0000003C) /*!< ADC external trigger selection for injected group */
1316 #define ADC_JSQR_JEXTSEL_0 ((uint32_t)0x00000004) /*!< ADC JEXTSEL bit 0 */
1317 #define ADC_JSQR_JEXTSEL_1 ((uint32_t)0x00000008) /*!< ADC JEXTSEL bit 1 */
1318 #define ADC_JSQR_JEXTSEL_2 ((uint32_t)0x00000010) /*!< ADC JEXTSEL bit 2 */
1319 #define ADC_JSQR_JEXTSEL_3 ((uint32_t)0x00000020) /*!< ADC JEXTSEL bit 3 */
1320
1321 #define ADC_JSQR_JEXTEN ((uint32_t)0x000000C0) /*!< ADC external trigger enable and polarity selection for injected channels */
1322 #define ADC_JSQR_JEXTEN_0 ((uint32_t)0x00000040) /*!< ADC JEXTEN bit 0 */
1323 #define ADC_JSQR_JEXTEN_1 ((uint32_t)0x00000080) /*!< ADC JEXTEN bit 1 */
1324
1325 #define ADC_JSQR_JSQ1 ((uint32_t)0x00001F00) /*!< ADC 1st conversion in injected sequence */
1326 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000100) /*!< ADC JSQ1 bit 0 */
1327 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000200) /*!< ADC JSQ1 bit 1 */
1328 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000400) /*!< ADC JSQ1 bit 2 */
1329 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000800) /*!< ADC JSQ1 bit 3 */
1330 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00001000) /*!< ADC JSQ1 bit 4 */
1331
1332 #define ADC_JSQR_JSQ2 ((uint32_t)0x0007C000) /*!< ADC 2nd conversion in injected sequence */
1333 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00004000) /*!< ADC JSQ2 bit 0 */
1334 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00008000) /*!< ADC JSQ2 bit 1 */
1335 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00010000) /*!< ADC JSQ2 bit 2 */
1336 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00020000) /*!< ADC JSQ2 bit 3 */
1337 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00040000) /*!< ADC JSQ2 bit 4 */
1338
1339 #define ADC_JSQR_JSQ3 ((uint32_t)0x01F00000) /*!< ADC 3rd conversion in injected sequence */
1340 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00100000) /*!< ADC JSQ3 bit 0 */
1341 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00200000) /*!< ADC JSQ3 bit 1 */
1342 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00400000) /*!< ADC JSQ3 bit 2 */
1343 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00800000) /*!< ADC JSQ3 bit 3 */
1344 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x01000000) /*!< ADC JSQ3 bit 4 */
1345
1346 #define ADC_JSQR_JSQ4 ((uint32_t)0x7C000000) /*!< ADC 4th conversion in injected sequence */
1347 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x04000000) /*!< ADC JSQ4 bit 0 */
1348 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x08000000) /*!< ADC JSQ4 bit 1 */
1349 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x10000000) /*!< ADC JSQ4 bit 2 */
1350 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x20000000) /*!< ADC JSQ4 bit 3 */
1351 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x40000000) /*!< ADC JSQ4 bit 4 */
1352
1353 /******************** Bit definition for ADC_OFR1 register ********************/
1354 #define ADC_OFR1_OFFSET1 ((uint32_t)0x00000FFF) /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
1355 #define ADC_OFR1_OFFSET1_0 ((uint32_t)0x00000001) /*!< ADC OFFSET1 bit 0 */
1356 #define ADC_OFR1_OFFSET1_1 ((uint32_t)0x00000002) /*!< ADC OFFSET1 bit 1 */
1357 #define ADC_OFR1_OFFSET1_2 ((uint32_t)0x00000004) /*!< ADC OFFSET1 bit 2 */
1358 #define ADC_OFR1_OFFSET1_3 ((uint32_t)0x00000008) /*!< ADC OFFSET1 bit 3 */
1359 #define ADC_OFR1_OFFSET1_4 ((uint32_t)0x00000010) /*!< ADC OFFSET1 bit 4 */
1360 #define ADC_OFR1_OFFSET1_5 ((uint32_t)0x00000020) /*!< ADC OFFSET1 bit 5 */
1361 #define ADC_OFR1_OFFSET1_6 ((uint32_t)0x00000040) /*!< ADC OFFSET1 bit 6 */
1362 #define ADC_OFR1_OFFSET1_7 ((uint32_t)0x00000080) /*!< ADC OFFSET1 bit 7 */
1363 #define ADC_OFR1_OFFSET1_8 ((uint32_t)0x00000100) /*!< ADC OFFSET1 bit 8 */
1364 #define ADC_OFR1_OFFSET1_9 ((uint32_t)0x00000200) /*!< ADC OFFSET1 bit 9 */
1365 #define ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400) /*!< ADC OFFSET1 bit 10 */
1366 #define ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800) /*!< ADC OFFSET1 bit 11 */
1367
1368 #define ADC_OFR1_OFFSET1_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 1 */
1369 #define ADC_OFR1_OFFSET1_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET1_CH bit 0 */
1370 #define ADC_OFR1_OFFSET1_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET1_CH bit 1 */
1371 #define ADC_OFR1_OFFSET1_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET1_CH bit 2 */
1372 #define ADC_OFR1_OFFSET1_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET1_CH bit 3 */
1373 #define ADC_OFR1_OFFSET1_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET1_CH bit 4 */
1374
1375 #define ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000) /*!< ADC offset 1 enable */
1376
1377 /******************** Bit definition for ADC_OFR2 register ********************/
1378 #define ADC_OFR2_OFFSET2 ((uint32_t)0x00000FFF) /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
1379 #define ADC_OFR2_OFFSET2_0 ((uint32_t)0x00000001) /*!< ADC OFFSET2 bit 0 */
1380 #define ADC_OFR2_OFFSET2_1 ((uint32_t)0x00000002) /*!< ADC OFFSET2 bit 1 */
1381 #define ADC_OFR2_OFFSET2_2 ((uint32_t)0x00000004) /*!< ADC OFFSET2 bit 2 */
1382 #define ADC_OFR2_OFFSET2_3 ((uint32_t)0x00000008) /*!< ADC OFFSET2 bit 3 */
1383 #define ADC_OFR2_OFFSET2_4 ((uint32_t)0x00000010) /*!< ADC OFFSET2 bit 4 */
1384 #define ADC_OFR2_OFFSET2_5 ((uint32_t)0x00000020) /*!< ADC OFFSET2 bit 5 */
1385 #define ADC_OFR2_OFFSET2_6 ((uint32_t)0x00000040) /*!< ADC OFFSET2 bit 6 */
1386 #define ADC_OFR2_OFFSET2_7 ((uint32_t)0x00000080) /*!< ADC OFFSET2 bit 7 */
1387 #define ADC_OFR2_OFFSET2_8 ((uint32_t)0x00000100) /*!< ADC OFFSET2 bit 8 */
1388 #define ADC_OFR2_OFFSET2_9 ((uint32_t)0x00000200) /*!< ADC OFFSET2 bit 9 */
1389 #define ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400) /*!< ADC OFFSET2 bit 10 */
1390 #define ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800) /*!< ADC OFFSET2 bit 11 */
1391
1392 #define ADC_OFR2_OFFSET2_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 2 */
1393 #define ADC_OFR2_OFFSET2_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET2_CH bit 0 */
1394 #define ADC_OFR2_OFFSET2_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET2_CH bit 1 */
1395 #define ADC_OFR2_OFFSET2_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET2_CH bit 2 */
1396 #define ADC_OFR2_OFFSET2_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET2_CH bit 3 */
1397 #define ADC_OFR2_OFFSET2_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET2_CH bit 4 */
1398
1399 #define ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000) /*!< ADC offset 2 enable */
1400
1401 /******************** Bit definition for ADC_OFR3 register ********************/
1402 #define ADC_OFR3_OFFSET3 ((uint32_t)0x00000FFF) /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
1403 #define ADC_OFR3_OFFSET3_0 ((uint32_t)0x00000001) /*!< ADC OFFSET3 bit 0 */
1404 #define ADC_OFR3_OFFSET3_1 ((uint32_t)0x00000002) /*!< ADC OFFSET3 bit 1 */
1405 #define ADC_OFR3_OFFSET3_2 ((uint32_t)0x00000004) /*!< ADC OFFSET3 bit 2 */
1406 #define ADC_OFR3_OFFSET3_3 ((uint32_t)0x00000008) /*!< ADC OFFSET3 bit 3 */
1407 #define ADC_OFR3_OFFSET3_4 ((uint32_t)0x00000010) /*!< ADC OFFSET3 bit 4 */
1408 #define ADC_OFR3_OFFSET3_5 ((uint32_t)0x00000020) /*!< ADC OFFSET3 bit 5 */
1409 #define ADC_OFR3_OFFSET3_6 ((uint32_t)0x00000040) /*!< ADC OFFSET3 bit 6 */
1410 #define ADC_OFR3_OFFSET3_7 ((uint32_t)0x00000080) /*!< ADC OFFSET3 bit 7 */
1411 #define ADC_OFR3_OFFSET3_8 ((uint32_t)0x00000100) /*!< ADC OFFSET3 bit 8 */
1412 #define ADC_OFR3_OFFSET3_9 ((uint32_t)0x00000200) /*!< ADC OFFSET3 bit 9 */
1413 #define ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400) /*!< ADC OFFSET3 bit 10 */
1414 #define ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800) /*!< ADC OFFSET3 bit 11 */
1415
1416 #define ADC_OFR3_OFFSET3_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 3 */
1417 #define ADC_OFR3_OFFSET3_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET3_CH bit 0 */
1418 #define ADC_OFR3_OFFSET3_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET3_CH bit 1 */
1419 #define ADC_OFR3_OFFSET3_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET3_CH bit 2 */
1420 #define ADC_OFR3_OFFSET3_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET3_CH bit 3 */
1421 #define ADC_OFR3_OFFSET3_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET3_CH bit 4 */
1422
1423 #define ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000) /*!< ADC offset 3 enable */
1424
1425 /******************** Bit definition for ADC_OFR4 register ********************/
1426 #define ADC_OFR4_OFFSET4 ((uint32_t)0x00000FFF) /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
1427 #define ADC_OFR4_OFFSET4_0 ((uint32_t)0x00000001) /*!< ADC OFFSET4 bit 0 */
1428 #define ADC_OFR4_OFFSET4_1 ((uint32_t)0x00000002) /*!< ADC OFFSET4 bit 1 */
1429 #define ADC_OFR4_OFFSET4_2 ((uint32_t)0x00000004) /*!< ADC OFFSET4 bit 2 */
1430 #define ADC_OFR4_OFFSET4_3 ((uint32_t)0x00000008) /*!< ADC OFFSET4 bit 3 */
1431 #define ADC_OFR4_OFFSET4_4 ((uint32_t)0x00000010) /*!< ADC OFFSET4 bit 4 */
1432 #define ADC_OFR4_OFFSET4_5 ((uint32_t)0x00000020) /*!< ADC OFFSET4 bit 5 */
1433 #define ADC_OFR4_OFFSET4_6 ((uint32_t)0x00000040) /*!< ADC OFFSET4 bit 6 */
1434 #define ADC_OFR4_OFFSET4_7 ((uint32_t)0x00000080) /*!< ADC OFFSET4 bit 7 */
1435 #define ADC_OFR4_OFFSET4_8 ((uint32_t)0x00000100) /*!< ADC OFFSET4 bit 8 */
1436 #define ADC_OFR4_OFFSET4_9 ((uint32_t)0x00000200) /*!< ADC OFFSET4 bit 9 */
1437 #define ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400) /*!< ADC OFFSET4 bit 10 */
1438 #define ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800) /*!< ADC OFFSET4 bit 11 */
1439
1440 #define ADC_OFR4_OFFSET4_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 4 */
1441 #define ADC_OFR4_OFFSET4_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET4_CH bit 0 */
1442 #define ADC_OFR4_OFFSET4_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET4_CH bit 1 */
1443 #define ADC_OFR4_OFFSET4_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET4_CH bit 2 */
1444 #define ADC_OFR4_OFFSET4_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET4_CH bit 3 */
1445 #define ADC_OFR4_OFFSET4_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET4_CH bit 4 */
1446
1447 #define ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000) /*!< ADC offset 4 enable */
1448
1449 /******************** Bit definition for ADC_JDR1 register ********************/
1450 #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
1451 #define ADC_JDR1_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
1452 #define ADC_JDR1_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
1453 #define ADC_JDR1_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
1454 #define ADC_JDR1_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
1455 #define ADC_JDR1_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
1456 #define ADC_JDR1_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
1457 #define ADC_JDR1_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
1458 #define ADC_JDR1_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
1459 #define ADC_JDR1_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
1460 #define ADC_JDR1_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
1461 #define ADC_JDR1_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
1462 #define ADC_JDR1_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
1463 #define ADC_JDR1_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
1464 #define ADC_JDR1_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
1465 #define ADC_JDR1_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
1466 #define ADC_JDR1_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
1467
1468 /******************** Bit definition for ADC_JDR2 register ********************/
1469 #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
1470 #define ADC_JDR2_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
1471 #define ADC_JDR2_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
1472 #define ADC_JDR2_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
1473 #define ADC_JDR2_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
1474 #define ADC_JDR2_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
1475 #define ADC_JDR2_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
1476 #define ADC_JDR2_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
1477 #define ADC_JDR2_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
1478 #define ADC_JDR2_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
1479 #define ADC_JDR2_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
1480 #define ADC_JDR2_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
1481 #define ADC_JDR2_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
1482 #define ADC_JDR2_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
1483 #define ADC_JDR2_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
1484 #define ADC_JDR2_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
1485 #define ADC_JDR2_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
1486
1487 /******************** Bit definition for ADC_JDR3 register ********************/
1488 #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
1489 #define ADC_JDR3_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
1490 #define ADC_JDR3_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
1491 #define ADC_JDR3_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
1492 #define ADC_JDR3_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
1493 #define ADC_JDR3_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
1494 #define ADC_JDR3_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
1495 #define ADC_JDR3_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
1496 #define ADC_JDR3_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
1497 #define ADC_JDR3_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
1498 #define ADC_JDR3_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
1499 #define ADC_JDR3_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
1500 #define ADC_JDR3_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
1501 #define ADC_JDR3_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
1502 #define ADC_JDR3_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
1503 #define ADC_JDR3_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
1504 #define ADC_JDR3_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
1505
1506 /******************** Bit definition for ADC_JDR4 register ********************/
1507 #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
1508 #define ADC_JDR4_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
1509 #define ADC_JDR4_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
1510 #define ADC_JDR4_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
1511 #define ADC_JDR4_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
1512 #define ADC_JDR4_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
1513 #define ADC_JDR4_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
1514 #define ADC_JDR4_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
1515 #define ADC_JDR4_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
1516 #define ADC_JDR4_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
1517 #define ADC_JDR4_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
1518 #define ADC_JDR4_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
1519 #define ADC_JDR4_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
1520 #define ADC_JDR4_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
1521 #define ADC_JDR4_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
1522 #define ADC_JDR4_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
1523 #define ADC_JDR4_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
1524
1525 /******************** Bit definition for ADC_AWD2CR register ********************/
1526 #define ADC_AWD2CR_AWD2CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
1527 #define ADC_AWD2CR_AWD2CH_0 ((uint32_t)0x00000002) /*!< ADC AWD2CH bit 0 */
1528 #define ADC_AWD2CR_AWD2CH_1 ((uint32_t)0x00000004) /*!< ADC AWD2CH bit 1 */
1529 #define ADC_AWD2CR_AWD2CH_2 ((uint32_t)0x00000008) /*!< ADC AWD2CH bit 2 */
1530 #define ADC_AWD2CR_AWD2CH_3 ((uint32_t)0x00000010) /*!< ADC AWD2CH bit 3 */
1531 #define ADC_AWD2CR_AWD2CH_4 ((uint32_t)0x00000020) /*!< ADC AWD2CH bit 4 */
1532 #define ADC_AWD2CR_AWD2CH_5 ((uint32_t)0x00000040) /*!< ADC AWD2CH bit 5 */
1533 #define ADC_AWD2CR_AWD2CH_6 ((uint32_t)0x00000080) /*!< ADC AWD2CH bit 6 */
1534 #define ADC_AWD2CR_AWD2CH_7 ((uint32_t)0x00000100) /*!< ADC AWD2CH bit 7 */
1535 #define ADC_AWD2CR_AWD2CH_8 ((uint32_t)0x00000200) /*!< ADC AWD2CH bit 8 */
1536 #define ADC_AWD2CR_AWD2CH_9 ((uint32_t)0x00000400) /*!< ADC AWD2CH bit 9 */
1537 #define ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000800) /*!< ADC AWD2CH bit 10 */
1538 #define ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00001000) /*!< ADC AWD2CH bit 11 */
1539 #define ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00002000) /*!< ADC AWD2CH bit 12 */
1540 #define ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00004000) /*!< ADC AWD2CH bit 13 */
1541 #define ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00008000) /*!< ADC AWD2CH bit 14 */
1542 #define ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00010000) /*!< ADC AWD2CH bit 15 */
1543 #define ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00020000) /*!< ADC AWD2CH bit 16 */
1544 #define ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00030000) /*!< ADC AWD2CH bit 17 */
1545
1546 /******************** Bit definition for ADC_AWD3CR register ********************/
1547 #define ADC_AWD3CR_AWD3CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
1548 #define ADC_AWD3CR_AWD3CH_0 ((uint32_t)0x00000002) /*!< ADC AWD3CH bit 0 */
1549 #define ADC_AWD3CR_AWD3CH_1 ((uint32_t)0x00000004) /*!< ADC AWD3CH bit 1 */
1550 #define ADC_AWD3CR_AWD3CH_2 ((uint32_t)0x00000008) /*!< ADC AWD3CH bit 2 */
1551 #define ADC_AWD3CR_AWD3CH_3 ((uint32_t)0x00000010) /*!< ADC AWD3CH bit 3 */
1552 #define ADC_AWD3CR_AWD3CH_4 ((uint32_t)0x00000020) /*!< ADC AWD3CH bit 4 */
1553 #define ADC_AWD3CR_AWD3CH_5 ((uint32_t)0x00000040) /*!< ADC AWD3CH bit 5 */
1554 #define ADC_AWD3CR_AWD3CH_6 ((uint32_t)0x00000080) /*!< ADC AWD3CH bit 6 */
1555 #define ADC_AWD3CR_AWD3CH_7 ((uint32_t)0x00000100) /*!< ADC AWD3CH bit 7 */
1556 #define ADC_AWD3CR_AWD3CH_8 ((uint32_t)0x00000200) /*!< ADC AWD3CH bit 8 */
1557 #define ADC_AWD3CR_AWD3CH_9 ((uint32_t)0x00000400) /*!< ADC AWD3CH bit 9 */
1558 #define ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000800) /*!< ADC AWD3CH bit 10 */
1559 #define ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00001000) /*!< ADC AWD3CH bit 11 */
1560 #define ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00002000) /*!< ADC AWD3CH bit 12 */
1561 #define ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00004000) /*!< ADC AWD3CH bit 13 */
1562 #define ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00008000) /*!< ADC AWD3CH bit 14 */
1563 #define ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00010000) /*!< ADC AWD3CH bit 15 */
1564 #define ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00020000) /*!< ADC AWD3CH bit 16 */
1565 #define ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00030000) /*!< ADC AWD3CH bit 17 */
1566
1567 /******************** Bit definition for ADC_DIFSEL register ********************/
1568 #define ADC_DIFSEL_DIFSEL ((uint32_t)0x0007FFFE) /*!< ADC differential modes for channels 1 to 18 */
1569 #define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000002) /*!< ADC DIFSEL bit 0 */
1570 #define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000004) /*!< ADC DIFSEL bit 1 */
1571 #define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000008) /*!< ADC DIFSEL bit 2 */
1572 #define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000010) /*!< ADC DIFSEL bit 3 */
1573 #define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000020) /*!< ADC DIFSEL bit 4 */
1574 #define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000040) /*!< ADC DIFSEL bit 5 */
1575 #define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000080) /*!< ADC DIFSEL bit 6 */
1576 #define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000100) /*!< ADC DIFSEL bit 7 */
1577 #define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000200) /*!< ADC DIFSEL bit 8 */
1578 #define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000400) /*!< ADC DIFSEL bit 9 */
1579 #define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000800) /*!< ADC DIFSEL bit 10 */
1580 #define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00001000) /*!< ADC DIFSEL bit 11 */
1581 #define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00002000) /*!< ADC DIFSEL bit 12 */
1582 #define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00004000) /*!< ADC DIFSEL bit 13 */
1583 #define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00008000) /*!< ADC DIFSEL bit 14 */
1584 #define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00010000) /*!< ADC DIFSEL bit 15 */
1585 #define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00020000) /*!< ADC DIFSEL bit 16 */
1586 #define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00030000) /*!< ADC DIFSEL bit 17 */
1587
1588 /******************** Bit definition for ADC_CALFACT register ********************/
1589 #define ADC_CALFACT_CALFACT_S ((uint32_t)0x0000007F) /*!< ADC calibration factors in single-ended mode */
1590 #define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001) /*!< ADC CALFACT_S bit 0 */
1591 #define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002) /*!< ADC CALFACT_S bit 1 */
1592 #define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004) /*!< ADC CALFACT_S bit 2 */
1593 #define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008) /*!< ADC CALFACT_S bit 3 */
1594 #define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010) /*!< ADC CALFACT_S bit 4 */
1595 #define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020) /*!< ADC CALFACT_S bit 5 */
1596 #define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040) /*!< ADC CALFACT_S bit 6 */
1597 #define ADC_CALFACT_CALFACT_D ((uint32_t)0x007F0000) /*!< ADC calibration factors in differential mode */
1598 #define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000) /*!< ADC CALFACT_D bit 0 */
1599 #define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000) /*!< ADC CALFACT_D bit 1 */
1600 #define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000) /*!< ADC CALFACT_D bit 2 */
1601 #define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000) /*!< ADC CALFACT_D bit 3 */
1602 #define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000) /*!< ADC CALFACT_D bit 4 */
1603 #define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000) /*!< ADC CALFACT_D bit 5 */
1604 #define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000) /*!< ADC CALFACT_D bit 6 */
1605
1606 /************************* ADC Common registers *****************************/
1607 /******************** Bit definition for ADC12_CSR register ********************/
1608 #define ADC12_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */
1609 #define ADC12_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */
1610 #define ADC12_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */
1611 #define ADC12_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */
1612 #define ADC12_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */
1613 #define ADC12_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */
1614 #define ADC12_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */
1615 #define ADC12_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */
1616 #define ADC12_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */
1617 #define ADC12_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */
1618 #define ADC12_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */
1619 #define ADC12_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */
1620 #define ADC12_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */
1621 #define ADC12_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */
1622 #define ADC12_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */
1623 #define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */
1624 #define ADC12_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */
1625 #define ADC12_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */
1626 #define ADC12_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */
1627 #define ADC12_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */
1628 #define ADC12_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */
1629 #define ADC12_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */
1630
1631 /******************** Bit definition for ADC34_CSR register ********************/
1632 #define ADC34_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */
1633 #define ADC34_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */
1634 #define ADC34_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */
1635 #define ADC34_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */
1636 #define ADC34_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */
1637 #define ADC34_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */
1638 #define ADC34_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */
1639 #define ADC34_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */
1640 #define ADC34_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */
1641 #define ADC34_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */
1642 #define ADC34_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */
1643 #define ADC34_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */
1644 #define ADC34_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */
1645 #define ADC34_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */
1646 #define ADC34_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */
1647 #define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */
1648 #define ADC34_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */
1649 #define ADC34_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */
1650 #define ADC34_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */
1651 #define ADC34_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */
1652 #define ADC34_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */
1653 #define ADC34_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */
1654
1655 /******************** Bit definition for ADC_CCR register ********************/
1656 #define ADC12_CCR_MULTI ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */
1657 #define ADC12_CCR_MULTI_0 ((uint32_t)0x00000001) /*!< MULTI bit 0 */
1658 #define ADC12_CCR_MULTI_1 ((uint32_t)0x00000002) /*!< MULTI bit 1 */
1659 #define ADC12_CCR_MULTI_2 ((uint32_t)0x00000004) /*!< MULTI bit 2 */
1660 #define ADC12_CCR_MULTI_3 ((uint32_t)0x00000008) /*!< MULTI bit 3 */
1661 #define ADC12_CCR_MULTI_4 ((uint32_t)0x00000010) /*!< MULTI bit 4 */
1662 #define ADC12_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */
1663 #define ADC12_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */
1664 #define ADC12_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */
1665 #define ADC12_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */
1666 #define ADC12_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */
1667 #define ADC12_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */
1668 #define ADC12_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */
1669 #define ADC12_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */
1670 #define ADC12_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */
1671 #define ADC12_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */
1672 #define ADC12_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */
1673 #define ADC12_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */
1674 #define ADC12_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */
1675 #define ADC12_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensor enable */
1676 #define ADC12_CCR_VBATEN ((uint32_t)0x01000000) /*!< VBAT enable */
1677
1678 /******************** Bit definition for ADC_CCR register ********************/
1679 #define ADC34_CCR_MULTI ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */
1680 #define ADC34_CCR_MULTI_0 ((uint32_t)0x00000001) /*!< MULTI bit 0 */
1681 #define ADC34_CCR_MULTI_1 ((uint32_t)0x00000002) /*!< MULTI bit 1 */
1682 #define ADC34_CCR_MULTI_2 ((uint32_t)0x00000004) /*!< MULTI bit 2 */
1683 #define ADC34_CCR_MULTI_3 ((uint32_t)0x00000008) /*!< MULTI bit 3 */
1684 #define ADC34_CCR_MULTI_4 ((uint32_t)0x00000010) /*!< MULTI bit 4 */
1685
1686 #define ADC34_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */
1687 #define ADC34_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */
1688 #define ADC34_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */
1689 #define ADC34_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */
1690 #define ADC34_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */
1691
1692 #define ADC34_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */
1693 #define ADC34_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */
1694 #define ADC34_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */
1695 #define ADC34_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */
1696
1697 #define ADC34_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */
1698 #define ADC34_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */
1699 #define ADC34_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */
1700
1701 #define ADC34_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */
1702 #define ADC34_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensor enable */
1703 #define ADC34_CCR_VBATEN ((uint32_t)0x01000000) /*!< VBAT enable */
1704
1705 /******************** Bit definition for ADC_CDR register ********************/
1706 #define ADC12_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */
1707 #define ADC12_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */
1708 #define ADC12_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */
1709 #define ADC12_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */
1710 #define ADC12_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */
1711 #define ADC12_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */
1712 #define ADC12_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */
1713 #define ADC12_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */
1714 #define ADC12_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */
1715 #define ADC12_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */
1716 #define ADC12_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */
1717 #define ADC12_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */
1718 #define ADC12_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */
1719 #define ADC12_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */
1720 #define ADC12_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */
1721 #define ADC12_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */
1722 #define ADC12_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */
1723
1724 #define ADC12_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */
1725 #define ADC12_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */
1726 #define ADC12_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */
1727 #define ADC12_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */
1728 #define ADC12_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */
1729 #define ADC12_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */
1730 #define ADC12_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */
1731 #define ADC12_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */
1732 #define ADC12_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */
1733 #define ADC12_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */
1734 #define ADC12_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */
1735 #define ADC12_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */
1736 #define ADC12_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */
1737 #define ADC12_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */
1738 #define ADC12_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */
1739 #define ADC12_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */
1740 #define ADC12_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */
1741
1742 /******************** Bit definition for ADC_CDR register ********************/
1743 #define ADC34_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */
1744 #define ADC34_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */
1745 #define ADC34_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */
1746 #define ADC34_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */
1747 #define ADC34_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */
1748 #define ADC34_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */
1749 #define ADC34_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */
1750 #define ADC34_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */
1751 #define ADC34_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */
1752 #define ADC34_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */
1753 #define ADC34_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */
1754 #define ADC34_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */
1755 #define ADC34_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */
1756 #define ADC34_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */
1757 #define ADC34_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */
1758 #define ADC34_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */
1759 #define ADC34_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */
1760
1761 #define ADC34_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */
1762 #define ADC34_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */
1763 #define ADC34_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */
1764 #define ADC34_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */
1765 #define ADC34_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */
1766 #define ADC34_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */
1767 #define ADC34_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */
1768 #define ADC34_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */
1769 #define ADC34_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */
1770 #define ADC34_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */
1771 #define ADC34_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */
1772 #define ADC34_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */
1773 #define ADC34_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */
1774 #define ADC34_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */
1775 #define ADC34_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */
1776 #define ADC34_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */
1777 #define ADC34_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */
1778
1779 /******************************************************************************/
1780 /* */
1781 /* Analog Comparators (COMP) */
1782 /* */
1783 /******************************************************************************/
1784 /********************** Bit definition for COMP1_CSR register ***************/
1785 #define COMP1_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
1786 #define COMP1_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */
1787 #define COMP1_CSR_COMP1MODE ((uint32_t)0x0000000C) /*!< COMP1 power mode */
1788 #define COMP1_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */
1789 #define COMP1_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */
1790 #define COMP1_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
1791 #define COMP1_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
1792 #define COMP1_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
1793 #define COMP1_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
1794 #define COMP1_CSR_COMP1NONINSEL ((uint32_t)0x00000080) /*!< COMP1 non inverting input select */
1795 #define COMP1_CSR_COMP1OUTSEL ((uint32_t)0x00003C00) /*!< COMP1 output select */
1796 #define COMP1_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP1 output select bit 0 */
1797 #define COMP1_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP1 output select bit 1 */
1798 #define COMP1_CSR_COMP1OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP1 output select bit 2 */
1799 #define COMP1_CSR_COMP1OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP1 output select bit 3 */
1800 #define COMP1_CSR_COMP1POL ((uint32_t)0x00008000) /*!< COMP1 output polarity */
1801 #define COMP1_CSR_COMP1HYST ((uint32_t)0x00030000) /*!< COMP1 hysteresis */
1802 #define COMP1_CSR_COMP1HYST_0 ((uint32_t)0x00010000) /*!< COMP1 hysteresis bit 0 */
1803 #define COMP1_CSR_COMP1HYST_1 ((uint32_t)0x00020000) /*!< COMP1 hysteresis bit 1 */
1804 #define COMP1_CSR_COMP1BLANKING ((uint32_t)0x000C0000) /*!< COMP1 blanking */
1805 #define COMP1_CSR_COMP1BLANKING_0 ((uint32_t)0x00040000) /*!< COMP1 blanking bit 0 */
1806 #define COMP1_CSR_COMP1BLANKING_1 ((uint32_t)0x00080000) /*!< COMP1 blanking bit 1 */
1807 #define COMP1_CSR_COMP1BLANKING_2 ((uint32_t)0x00100000) /*!< COMP1 blanking bit 2 */
1808 #define COMP1_CSR_COMP1OUT ((uint32_t)0x40000000) /*!< COMP1 output level */
1809 #define COMP1_CSR_COMP1LOCK ((uint32_t)0x80000000) /*!< COMP1 lock */
1810
1811 /********************** Bit definition for COMP2_CSR register ***************/
1812 #define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
1813 #define COMP2_CSR_COMP2MODE ((uint32_t)0x0000000C) /*!< COMP2 power mode */
1814 #define COMP2_CSR_COMP2MODE_0 ((uint32_t)0x00000004) /*!< COMP2 power mode bit 0 */
1815 #define COMP2_CSR_COMP2MODE_1 ((uint32_t)0x00000008) /*!< COMP2 power mode bit 1 */
1816 #define COMP2_CSR_COMP2INSEL ((uint32_t)0x00400070) /*!< COMP2 inverting input select */
1817 #define COMP2_CSR_COMP2INSEL_0 ((uint32_t)0x00000010) /*!< COMP2 inverting input select bit 0 */
1818 #define COMP2_CSR_COMP2INSEL_1 ((uint32_t)0x00000020) /*!< COMP2 inverting input select bit 1 */
1819 #define COMP2_CSR_COMP2INSEL_2 ((uint32_t)0x00000040) /*!< COMP2 inverting input select bit 2 */
1820 #define COMP2_CSR_COMP2INSEL_3 ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 3 */
1821 #define COMP2_CSR_COMP2NONINSEL ((uint32_t)0x00000080) /*!< COMP2 non inverting input select */
1822 #define COMP2_CSR_COMP2WNDWEN ((uint32_t)0x00000200) /*!< COMP2 window mode enable */
1823 #define COMP2_CSR_COMP2OUTSEL ((uint32_t)0x00003C00) /*!< COMP2 output select */
1824 #define COMP2_CSR_COMP2OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP2 output select bit 0 */
1825 #define COMP2_CSR_COMP2OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP2 output select bit 1 */
1826 #define COMP2_CSR_COMP2OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP2 output select bit 2 */
1827 #define COMP2_CSR_COMP2OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP2 output select bit 3 */
1828 #define COMP2_CSR_COMP2POL ((uint32_t)0x00008000) /*!< COMP2 output polarity */
1829 #define COMP2_CSR_COMP2HYST ((uint32_t)0x00030000) /*!< COMP2 hysteresis */
1830 #define COMP2_CSR_COMP2HYST_0 ((uint32_t)0x00010000) /*!< COMP2 hysteresis bit 0 */
1831 #define COMP2_CSR_COMP2HYST_1 ((uint32_t)0x00020000) /*!< COMP2 hysteresis bit 1 */
1832 #define COMP2_CSR_COMP2BLANKING ((uint32_t)0x000C0000) /*!< COMP2 blanking */
1833 #define COMP2_CSR_COMP2BLANKING_0 ((uint32_t)0x00040000) /*!< COMP2 blanking bit 0 */
1834 #define COMP2_CSR_COMP2BLANKING_1 ((uint32_t)0x00080000) /*!< COMP2 blanking bit 1 */
1835 #define COMP2_CSR_COMP2BLANKING_2 ((uint32_t)0x00100000) /*!< COMP2 blanking bit 2 */
1836 #define COMP2_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
1837 #define COMP2_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
1838
1839 /********************** Bit definition for COMP3_CSR register ***************/
1840 #define COMP3_CSR_COMP3EN ((uint32_t)0x00000001) /*!< COMP3 enable */
1841 #define COMP3_CSR_COMP3MODE ((uint32_t)0x0000000C) /*!< COMP3 power mode */
1842 #define COMP3_CSR_COMP3MODE_0 ((uint32_t)0x00000004) /*!< COMP3 power mode bit 0 */
1843 #define COMP3_CSR_COMP3MODE_1 ((uint32_t)0x00000008) /*!< COMP3 power mode bit 1 */
1844 #define COMP3_CSR_COMP3INSEL ((uint32_t)0x00000070) /*!< COMP3 inverting input select */
1845 #define COMP3_CSR_COMP3INSEL_0 ((uint32_t)0x00000010) /*!< COMP3 inverting input select bit 0 */
1846 #define COMP3_CSR_COMP3INSEL_1 ((uint32_t)0x00000020) /*!< COMP3 inverting input select bit 1 */
1847 #define COMP3_CSR_COMP3INSEL_2 ((uint32_t)0x00000040) /*!< COMP3 inverting input select bit 2 */
1848 #define COMP3_CSR_COMP3NONINSEL ((uint32_t)0x00000080) /*!< COMP3 non inverting input select */
1849 #define COMP3_CSR_COMP3OUTSEL ((uint32_t)0x00003C00) /*!< COMP3 output select */
1850 #define COMP3_CSR_COMP3OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP3 output select bit 0 */
1851 #define COMP3_CSR_COMP3OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP3 output select bit 1 */
1852 #define COMP3_CSR_COMP3OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP3 output select bit 2 */
1853 #define COMP3_CSR_COMP3OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP3 output select bit 3 */
1854 #define COMP3_CSR_COMP3POL ((uint32_t)0x00008000) /*!< COMP3 output polarity */
1855 #define COMP3_CSR_COMP3HYST ((uint32_t)0x00030000) /*!< COMP3 hysteresis */
1856 #define COMP3_CSR_COMP3HYST_0 ((uint32_t)0x00010000) /*!< COMP3 hysteresis bit 0 */
1857 #define COMP3_CSR_COMP3HYST_1 ((uint32_t)0x00020000) /*!< COMP3 hysteresis bit 1 */
1858 #define COMP3_CSR_COMP3BLANKING ((uint32_t)0x000C0000) /*!< COMP3 blanking */
1859 #define COMP3_CSR_COMP3BLANKING_0 ((uint32_t)0x00040000) /*!< COMP3 blanking bit 0 */
1860 #define COMP3_CSR_COMP3BLANKING_1 ((uint32_t)0x00080000) /*!< COMP3 blanking bit 1 */
1861 #define COMP3_CSR_COMP3BLANKING_2 ((uint32_t)0x00100000) /*!< COMP3 blanking bit 2 */
1862 #define COMP3_CSR_COMP3OUT ((uint32_t)0x40000000) /*!< COMP3 output level */
1863 #define COMP3_CSR_COMP3LOCK ((uint32_t)0x80000000) /*!< COMP3 lock */
1864
1865 /********************** Bit definition for COMP4_CSR register ***************/
1866 #define COMP4_CSR_COMP4EN ((uint32_t)0x00000001) /*!< COMP4 enable */
1867 #define COMP4_CSR_COMP4MODE ((uint32_t)0x0000000C) /*!< COMP4 power mode */
1868 #define COMP4_CSR_COMP4MODE_0 ((uint32_t)0x00000004) /*!< COMP4 power mode bit 0 */
1869 #define COMP4_CSR_COMP4MODE_1 ((uint32_t)0x00000008) /*!< COMP4 power mode bit 1 */
1870 #define COMP4_CSR_COMP4INSEL ((uint32_t)0x00400070) /*!< COMP4 inverting input select */
1871 #define COMP4_CSR_COMP4INSEL_0 ((uint32_t)0x00000010) /*!< COMP4 inverting input select bit 0 */
1872 #define COMP4_CSR_COMP4INSEL_1 ((uint32_t)0x00000020) /*!< COMP4 inverting input select bit 1 */
1873 #define COMP4_CSR_COMP4INSEL_2 ((uint32_t)0x00000040) /*!< COMP4 inverting input select bit 2 */
1874 #define COMP4_CSR_COMP4INSEL_3 ((uint32_t)0x00400000) /*!< COMP4 inverting input select bit 3 */
1875 #define COMP4_CSR_COMP4NONINSEL ((uint32_t)0x00000080) /*!< COMP4 non inverting input select */
1876 #define COMP4_CSR_COMP4WNDWEN ((uint32_t)0x00000200) /*!< COMP4 window mode enable */
1877 #define COMP4_CSR_COMP4OUTSEL ((uint32_t)0x00003C00) /*!< COMP4 output select */
1878 #define COMP4_CSR_COMP4OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP4 output select bit 0 */
1879 #define COMP4_CSR_COMP4OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP4 output select bit 1 */
1880 #define COMP4_CSR_COMP4OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP4 output select bit 2 */
1881 #define COMP4_CSR_COMP4OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP4 output select bit 3 */
1882 #define COMP4_CSR_COMP4POL ((uint32_t)0x00008000) /*!< COMP4 output polarity */
1883 #define COMP4_CSR_COMP4HYST ((uint32_t)0x00030000) /*!< COMP4 hysteresis */
1884 #define COMP4_CSR_COMP4HYST_0 ((uint32_t)0x00010000) /*!< COMP4 hysteresis bit 0 */
1885 #define COMP4_CSR_COMP4HYST_1 ((uint32_t)0x00020000) /*!< COMP4 hysteresis bit 1 */
1886 #define COMP4_CSR_COMP4BLANKING ((uint32_t)0x000C0000) /*!< COMP4 blanking */
1887 #define COMP4_CSR_COMP4BLANKING_0 ((uint32_t)0x00040000) /*!< COMP4 blanking bit 0 */
1888 #define COMP4_CSR_COMP4BLANKING_1 ((uint32_t)0x00080000) /*!< COMP4 blanking bit 1 */
1889 #define COMP4_CSR_COMP4BLANKING_2 ((uint32_t)0x00100000) /*!< COMP4 blanking bit 2 */
1890 #define COMP4_CSR_COMP4OUT ((uint32_t)0x40000000) /*!< COMP4 output level */
1891 #define COMP4_CSR_COMP4LOCK ((uint32_t)0x80000000) /*!< COMP4 lock */
1892
1893 /********************** Bit definition for COMP5_CSR register ***************/
1894 #define COMP5_CSR_COMP5EN ((uint32_t)0x00000001) /*!< COMP5 enable */
1895 #define COMP5_CSR_COMP5MODE ((uint32_t)0x0000000C) /*!< COMP5 power mode */
1896 #define COMP5_CSR_COMP5MODE_0 ((uint32_t)0x00000004) /*!< COMP5 power mode bit 0 */
1897 #define COMP5_CSR_COMP5MODE_1 ((uint32_t)0x00000008) /*!< COMP5 power mode bit 1 */
1898 #define COMP5_CSR_COMP5INSEL ((uint32_t)0x00000070) /*!< COMP5 inverting input select */
1899 #define COMP5_CSR_COMP5INSEL_0 ((uint32_t)0x00000010) /*!< COMP5 inverting input select bit 0 */
1900 #define COMP5_CSR_COMP5INSEL_1 ((uint32_t)0x00000020) /*!< COMP5 inverting input select bit 1 */
1901 #define COMP5_CSR_COMP5INSEL_2 ((uint32_t)0x00000040) /*!< COMP5 inverting input select bit 2 */
1902 #define COMP5_CSR_COMP5NONINSEL ((uint32_t)0x00000080) /*!< COMP5 non inverting input select */
1903 #define COMP5_CSR_COMP5OUTSEL ((uint32_t)0x00003C00) /*!< COMP5 output select */
1904 #define COMP5_CSR_COMP5OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP5 output select bit 0 */
1905 #define COMP5_CSR_COMP5OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP5 output select bit 1 */
1906 #define COMP5_CSR_COMP5OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP5 output select bit 2 */
1907 #define COMP5_CSR_COMP5OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP5 output select bit 3 */
1908 #define COMP5_CSR_COMP5POL ((uint32_t)0x00008000) /*!< COMP5 output polarity */
1909 #define COMP5_CSR_COMP5HYST ((uint32_t)0x00030000) /*!< COMP5 hysteresis */
1910 #define COMP5_CSR_COMP5HYST_0 ((uint32_t)0x00010000) /*!< COMP5 hysteresis bit 0 */
1911 #define COMP5_CSR_COMP5HYST_1 ((uint32_t)0x00020000) /*!< COMP5 hysteresis bit 1 */
1912 #define COMP5_CSR_COMP5BLANKING ((uint32_t)0x000C0000) /*!< COMP5 blanking */
1913 #define COMP5_CSR_COMP5BLANKING_0 ((uint32_t)0x00040000) /*!< COMP5 blanking bit 0 */
1914 #define COMP5_CSR_COMP5BLANKING_1 ((uint32_t)0x00080000) /*!< COMP5 blanking bit 1 */
1915 #define COMP5_CSR_COMP5BLANKING_2 ((uint32_t)0x00100000) /*!< COMP5 blanking bit 2 */
1916 #define COMP5_CSR_COMP5OUT ((uint32_t)0x40000000) /*!< COMP5 output level */
1917 #define COMP5_CSR_COMP5LOCK ((uint32_t)0x80000000) /*!< COMP5 lock */
1918
1919 /********************** Bit definition for COMP6_CSR register ***************/
1920 #define COMP6_CSR_COMP6EN ((uint32_t)0x00000001) /*!< COMP6 enable */
1921 #define COMP6_CSR_COMP6MODE ((uint32_t)0x0000000C) /*!< COMP6 power mode */
1922 #define COMP6_CSR_COMP6MODE_0 ((uint32_t)0x00000004) /*!< COMP6 power mode bit 0 */
1923 #define COMP6_CSR_COMP6MODE_1 ((uint32_t)0x00000008) /*!< COMP6 power mode bit 1 */
1924 #define COMP6_CSR_COMP6INSEL ((uint32_t)0x00400070) /*!< COMP6 inverting input select */
1925 #define COMP6_CSR_COMP6INSEL_0 ((uint32_t)0x00000010) /*!< COMP6 inverting input select bit 0 */
1926 #define COMP6_CSR_COMP6INSEL_1 ((uint32_t)0x00000020) /*!< COMP6 inverting input select bit 1 */
1927 #define COMP6_CSR_COMP6INSEL_2 ((uint32_t)0x00000040) /*!< COMP6 inverting input select bit 2 */
1928 #define COMP6_CSR_COMP6INSEL_3 ((uint32_t)0x00400000) /*!< COMP6 inverting input select bit 3 */
1929 #define COMP6_CSR_COMP6NONINSEL ((uint32_t)0x00000080) /*!< COMP6 non inverting input select */
1930 #define COMP6_CSR_COMP6WNDWEN ((uint32_t)0x00000200) /*!< COMP6 window mode enable */
1931 #define COMP6_CSR_COMP6OUTSEL ((uint32_t)0x00003C00) /*!< COMP6 output select */
1932 #define COMP6_CSR_COMP6OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP6 output select bit 0 */
1933 #define COMP6_CSR_COMP6OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP6 output select bit 1 */
1934 #define COMP6_CSR_COMP6OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP6 output select bit 2 */
1935 #define COMP6_CSR_COMP6OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP6 output select bit 3 */
1936 #define COMP6_CSR_COMP6POL ((uint32_t)0x00008000) /*!< COMP6 output polarity */
1937 #define COMP6_CSR_COMP6HYST ((uint32_t)0x00030000) /*!< COMP6 hysteresis */
1938 #define COMP6_CSR_COMP6HYST_0 ((uint32_t)0x00010000) /*!< COMP6 hysteresis bit 0 */
1939 #define COMP6_CSR_COMP6HYST_1 ((uint32_t)0x00020000) /*!< COMP6 hysteresis bit 1 */
1940 #define COMP6_CSR_COMP6BLANKING ((uint32_t)0x000C0000) /*!< COMP6 blanking */
1941 #define COMP6_CSR_COMP6BLANKING_0 ((uint32_t)0x00040000) /*!< COMP6 blanking bit 0 */
1942 #define COMP6_CSR_COMP6BLANKING_1 ((uint32_t)0x00080000) /*!< COMP6 blanking bit 1 */
1943 #define COMP6_CSR_COMP6BLANKING_2 ((uint32_t)0x00100000) /*!< COMP6 blanking bit 2 */
1944 #define COMP6_CSR_COMP6OUT ((uint32_t)0x40000000) /*!< COMP6 output level */
1945 #define COMP6_CSR_COMP6LOCK ((uint32_t)0x80000000) /*!< COMP6 lock */
1946
1947 /********************** Bit definition for COMP7_CSR register ***************/
1948 #define COMP7_CSR_COMP7EN ((uint32_t)0x00000001) /*!< COMP7 enable */
1949 #define COMP7_CSR_COMP7MODE ((uint32_t)0x0000000C) /*!< COMP7 power mode */
1950 #define COMP7_CSR_COMP7MODE_0 ((uint32_t)0x00000004) /*!< COMP7 power mode bit 0 */
1951 #define COMP7_CSR_COMP7MODE_1 ((uint32_t)0x00000008) /*!< COMP7 power mode bit 1 */
1952 #define COMP7_CSR_COMP7INSEL ((uint32_t)0x00000070) /*!< COMP7 inverting input select */
1953 #define COMP7_CSR_COMP7INSEL_0 ((uint32_t)0x00000010) /*!< COMP7 inverting input select bit 0 */
1954 #define COMP7_CSR_COMP7INSEL_1 ((uint32_t)0x00000020) /*!< COMP7 inverting input select bit 1 */
1955 #define COMP7_CSR_COMP7INSEL_2 ((uint32_t)0x00000040) /*!< COMP7 inverting input select bit 2 */
1956 #define COMP7_CSR_COMP7NONINSEL ((uint32_t)0x00000080) /*!< COMP7 non inverting input select */
1957 #define COMP7_CSR_COMP7OUTSEL ((uint32_t)0x00003C00) /*!< COMP7 output select */
1958 #define COMP7_CSR_COMP7OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP7 output select bit 0 */
1959 #define COMP7_CSR_COMP7OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP7 output select bit 1 */
1960 #define COMP7_CSR_COMP7OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP7 output select bit 2 */
1961 #define COMP7_CSR_COMP7OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP7 output select bit 3 */
1962 #define COMP7_CSR_COMP7POL ((uint32_t)0x00008000) /*!< COMP7 output polarity */
1963 #define COMP7_CSR_COMP7HYST ((uint32_t)0x00030000) /*!< COMP7 hysteresis */
1964 #define COMP7_CSR_COMP7HYST_0 ((uint32_t)0x00010000) /*!< COMP7 hysteresis bit 0 */
1965 #define COMP7_CSR_COMP7HYST_1 ((uint32_t)0x00020000) /*!< COMP7 hysteresis bit 1 */
1966 #define COMP7_CSR_COMP7BLANKING ((uint32_t)0x000C0000) /*!< COMP7 blanking */
1967 #define COMP7_CSR_COMP7BLANKING_0 ((uint32_t)0x00040000) /*!< COMP7 blanking bit 0 */
1968 #define COMP7_CSR_COMP7BLANKING_1 ((uint32_t)0x00080000) /*!< COMP7 blanking bit 1 */
1969 #define COMP7_CSR_COMP7BLANKING_2 ((uint32_t)0x00100000) /*!< COMP7 blanking bit 2 */
1970 #define COMP7_CSR_COMP7OUT ((uint32_t)0x40000000) /*!< COMP7 output level */
1971 #define COMP7_CSR_COMP7LOCK ((uint32_t)0x80000000) /*!< COMP7 lock */
1972
1973 /********************** Bit definition for COMP_CSR register ****************/
1974 #define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
1975 #define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */
1976 #define COMP_CSR_COMPxMODE ((uint32_t)0x0000000C) /*!< COMPx power mode */
1977 #define COMP_CSR_COMPxMODE_0 ((uint32_t)0x00000004) /*!< COMPx power mode bit 0 */
1978 #define COMP_CSR_COMPxMODE_1 ((uint32_t)0x00000008) /*!< COMPx power mode bit 1 */
1979 #define COMP_CSR_COMPxINSEL ((uint32_t)0x00400070) /*!< COMPx inverting input select */
1980 #define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */
1981 #define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */
1982 #define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */
1983 #define COMP_CSR_COMPxINSEL_3 ((uint32_t)0x00400000) /*!< COMPx inverting input select bit 3 */
1984 #define COMP_CSR_COMPxNONINSEL ((uint32_t)0x00000080) /*!< COMPx non inverting input select */
1985 #define COMP_CSR_COMPxWNDWEN ((uint32_t)0x00000200) /*!< COMPx window mode enable */
1986 #define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00003C00) /*!< COMPx output select */
1987 #define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000400) /*!< COMPx output select bit 0 */
1988 #define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000800) /*!< COMPx output select bit 1 */
1989 #define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00001000) /*!< COMPx output select bit 2 */
1990 #define COMP_CSR_COMPxOUTSEL_3 ((uint32_t)0x00002000) /*!< COMPx output select bit 3 */
1991 #define COMP_CSR_COMPxPOL ((uint32_t)0x00008000) /*!< COMPx output polarity */
1992 #define COMP_CSR_COMPxHYST ((uint32_t)0x00030000) /*!< COMPx hysteresis */
1993 #define COMP_CSR_COMPxHYST_0 ((uint32_t)0x00010000) /*!< COMPx hysteresis bit 0 */
1994 #define COMP_CSR_COMPxHYST_1 ((uint32_t)0x00020000) /*!< COMPx hysteresis bit 1 */
1995 #define COMP_CSR_COMPxBLANKING ((uint32_t)0x000C0000) /*!< COMPx blanking */
1996 #define COMP_CSR_COMPxBLANKING_0 ((uint32_t)0x00040000) /*!< COMPx blanking bit 0 */
1997 #define COMP_CSR_COMPxBLANKING_1 ((uint32_t)0x00080000) /*!< COMPx blanking bit 1 */
1998 #define COMP_CSR_COMPxBLANKING_2 ((uint32_t)0x00100000) /*!< COMPx blanking bit 2 */
1999 #define COMP_CSR_COMPxINSEL_3 ((uint32_t)0x00400000) /*!< COMPx inverting input select bit 3 */
2000 #define COMP_CSR_COMPxOUT ((uint32_t)0x40000000) /*!< COMPx output level */
2001 #define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /*!< COMPx lock */
2002
2003 /******************************************************************************/
2004 /* */
2005 /* Operational Amplifier (OPAMP) */
2006 /* */
2007 /******************************************************************************/
2008 /********************* Bit definition for OPAMP1_CSR register ***************/
2009 #define OPAMP1_CSR_OPAMP1EN ((uint32_t)0x00000001) /*!< OPAMP1 enable */
2010 #define OPAMP1_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
2011 #define OPAMP1_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
2012 #define OPAMP1_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
2013 #define OPAMP1_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
2014 #define OPAMP1_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
2015 #define OPAMP1_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
2016 #define OPAMP1_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
2017 #define OPAMP1_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
2018 #define OPAMP1_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
2019 #define OPAMP1_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
2020 #define OPAMP1_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
2021 #define OPAMP1_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
2022 #define OPAMP1_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
2023 #define OPAMP1_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
2024 #define OPAMP1_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
2025 #define OPAMP1_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
2026 #define OPAMP1_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
2027 #define OPAMP1_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
2028 #define OPAMP1_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
2029 #define OPAMP1_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
2030 #define OPAMP1_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
2031 #define OPAMP1_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
2032 #define OPAMP1_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
2033 #define OPAMP1_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
2034 #define OPAMP1_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
2035 #define OPAMP1_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
2036 #define OPAMP1_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
2037
2038 /********************* Bit definition for OPAMP2_CSR register ***************/
2039 #define OPAMP2_CSR_OPAMP2EN ((uint32_t)0x00000001) /*!< OPAMP2 enable */
2040 #define OPAMP2_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
2041 #define OPAMP2_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
2042 #define OPAMP2_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
2043 #define OPAMP2_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
2044 #define OPAMP2_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
2045 #define OPAMP2_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
2046 #define OPAMP2_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
2047 #define OPAMP2_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
2048 #define OPAMP2_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
2049 #define OPAMP2_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
2050 #define OPAMP2_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
2051 #define OPAMP2_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
2052 #define OPAMP2_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
2053 #define OPAMP2_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
2054 #define OPAMP2_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
2055 #define OPAMP2_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
2056 #define OPAMP2_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
2057 #define OPAMP2_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
2058 #define OPAMP2_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
2059 #define OPAMP2_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
2060 #define OPAMP2_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
2061 #define OPAMP2_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
2062 #define OPAMP2_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
2063 #define OPAMP2_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
2064 #define OPAMP2_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
2065 #define OPAMP2_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
2066 #define OPAMP2_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
2067
2068 /********************* Bit definition for OPAMP3_CSR register ***************/
2069 #define OPAMP3_CSR_OPAMP3EN ((uint32_t)0x00000001) /*!< OPAMP3 enable */
2070 #define OPAMP3_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
2071 #define OPAMP3_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
2072 #define OPAMP3_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
2073 #define OPAMP3_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
2074 #define OPAMP3_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
2075 #define OPAMP3_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
2076 #define OPAMP3_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
2077 #define OPAMP3_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
2078 #define OPAMP3_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
2079 #define OPAMP3_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
2080 #define OPAMP3_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
2081 #define OPAMP3_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
2082 #define OPAMP3_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
2083 #define OPAMP3_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
2084 #define OPAMP3_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
2085 #define OPAMP3_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
2086 #define OPAMP3_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
2087 #define OPAMP3_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
2088 #define OPAMP3_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
2089 #define OPAMP3_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
2090 #define OPAMP3_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
2091 #define OPAMP3_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
2092 #define OPAMP3_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
2093 #define OPAMP3_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
2094 #define OPAMP3_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
2095 #define OPAMP3_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
2096 #define OPAMP3_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
2097
2098 /********************* Bit definition for OPAMP4_CSR register ***************/
2099 #define OPAMP4_CSR_OPAMP4EN ((uint32_t)0x00000001) /*!< OPAMP4 enable */
2100 #define OPAMP4_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
2101 #define OPAMP4_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
2102 #define OPAMP4_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
2103 #define OPAMP4_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
2104 #define OPAMP4_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
2105 #define OPAMP4_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
2106 #define OPAMP4_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
2107 #define OPAMP4_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
2108 #define OPAMP4_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
2109 #define OPAMP4_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
2110 #define OPAMP4_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
2111 #define OPAMP4_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
2112 #define OPAMP4_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
2113 #define OPAMP4_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
2114 #define OPAMP4_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
2115 #define OPAMP4_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
2116 #define OPAMP4_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
2117 #define OPAMP4_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
2118 #define OPAMP4_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
2119 #define OPAMP4_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
2120 #define OPAMP4_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
2121 #define OPAMP4_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
2122 #define OPAMP4_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
2123 #define OPAMP4_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
2124 #define OPAMP4_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
2125 #define OPAMP4_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
2126 #define OPAMP4_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
2127
2128 /********************* Bit definition for OPAMPx_CSR register ***************/
2129 #define OPAMP_CSR_OPAMPxEN ((uint32_t)0x00000001) /*!< OPAMP enable */
2130 #define OPAMP_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
2131 #define OPAMP_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
2132 #define OPAMP_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
2133 #define OPAMP_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
2134 #define OPAMP_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
2135 #define OPAMP_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
2136 #define OPAMP_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
2137 #define OPAMP_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
2138 #define OPAMP_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
2139 #define OPAMP_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
2140 #define OPAMP_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
2141 #define OPAMP_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
2142 #define OPAMP_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
2143 #define OPAMP_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
2144 #define OPAMP_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
2145 #define OPAMP_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
2146 #define OPAMP_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
2147 #define OPAMP_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
2148 #define OPAMP_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
2149 #define OPAMP_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
2150 #define OPAMP_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
2151 #define OPAMP_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
2152 #define OPAMP_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
2153 #define OPAMP_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
2154 #define OPAMP_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
2155 #define OPAMP_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
2156 #define OPAMP_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
2157
2158 /******************************************************************************/
2159 /* */
2160 /* Controller Area Network (CAN ) */
2161 /* */
2162 /******************************************************************************/
2163 /******************* Bit definition for CAN_MCR register ********************/
2164 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
2165 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
2166 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
2167 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
2168 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
2169 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
2170 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
2171 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
2172 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
2173
2174 /******************* Bit definition for CAN_MSR register ********************/
2175 #define CAN_MSR_INAK ((uint32_t)0x00000001) /*!<Initialization Acknowledge */
2176 #define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!<Sleep Acknowledge */
2177 #define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!<Error Interrupt */
2178 #define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!<Wakeup Interrupt */
2179 #define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!<Sleep Acknowledge Interrupt */
2180 #define CAN_MSR_TXM ((uint32_t)0x00000100) /*!<Transmit Mode */
2181 #define CAN_MSR_RXM ((uint32_t)0x00000200) /*!<Receive Mode */
2182 #define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!<Last Sample Point */
2183 #define CAN_MSR_RX ((uint32_t)0x00000800) /*!<CAN Rx Signal */
2184
2185 /******************* Bit definition for CAN_TSR register ********************/
2186 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
2187 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
2188 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
2189 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
2190 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
2191 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
2192 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
2193 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
2194 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
2195 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
2196 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
2197 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
2198 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
2199 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
2200 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
2201 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
2202
2203 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
2204 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
2205 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
2206 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
2207
2208 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
2209 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
2210 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
2211 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
2212
2213 /******************* Bit definition for CAN_RF0R register *******************/
2214 #define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!<FIFO 0 Message Pending */
2215 #define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!<FIFO 0 Full */
2216 #define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!<FIFO 0 Overrun */
2217 #define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!<Release FIFO 0 Output Mailbox */
2218
2219 /******************* Bit definition for CAN_RF1R register *******************/
2220 #define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!<FIFO 1 Message Pending */
2221 #define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!<FIFO 1 Full */
2222 #define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!<FIFO 1 Overrun */
2223 #define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!<Release FIFO 1 Output Mailbox */
2224
2225 /******************** Bit definition for CAN_IER register *******************/
2226 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
2227 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
2228 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
2229 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
2230 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
2231 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
2232 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
2233 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
2234 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
2235 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
2236 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
2237 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
2238 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
2239 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
2240
2241 /******************** Bit definition for CAN_ESR register *******************/
2242 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
2243 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
2244 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
2245
2246 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
2247 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
2248 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
2249 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
2250
2251 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
2252 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
2253
2254 /******************* Bit definition for CAN_BTR register ********************/
2255 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
2256 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
2257 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Time Segment 1 (Bit 0) */
2258 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Time Segment 1 (Bit 1) */
2259 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Time Segment 1 (Bit 2) */
2260 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Time Segment 1 (Bit 3) */
2261 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
2262 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Time Segment 2 (Bit 0) */
2263 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Time Segment 2 (Bit 1) */
2264 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Time Segment 2 (Bit 2) */
2265 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
2266 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Resynchronization Jump Width (Bit 0) */
2267 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Resynchronization Jump Width (Bit 1) */
2268 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
2269 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
2270
2271 /*!<Mailbox registers */
2272 /****************** Bit definition for CAN_TI0R register ********************/
2273 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
2274 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
2275 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
2276 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
2277 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
2278
2279 /****************** Bit definition for CAN_TDT0R register *******************/
2280 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
2281 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
2282 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
2283
2284 /****************** Bit definition for CAN_TDL0R register *******************/
2285 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
2286 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
2287 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
2288 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
2289
2290 /****************** Bit definition for CAN_TDH0R register *******************/
2291 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
2292 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
2293 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
2294 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
2295
2296 /******************* Bit definition for CAN_TI1R register *******************/
2297 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
2298 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
2299 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
2300 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
2301 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
2302
2303 /******************* Bit definition for CAN_TDT1R register ******************/
2304 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
2305 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
2306 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
2307
2308 /******************* Bit definition for CAN_TDL1R register ******************/
2309 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
2310 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
2311 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
2312 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
2313
2314 /******************* Bit definition for CAN_TDH1R register ******************/
2315 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
2316 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
2317 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
2318 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
2319
2320 /******************* Bit definition for CAN_TI2R register *******************/
2321 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
2322 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
2323 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
2324 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
2325 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
2326
2327 /******************* Bit definition for CAN_TDT2R register ******************/
2328 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
2329 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
2330 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
2331
2332 /******************* Bit definition for CAN_TDL2R register ******************/
2333 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
2334 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
2335 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
2336 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
2337
2338 /******************* Bit definition for CAN_TDH2R register ******************/
2339 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
2340 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
2341 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
2342 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
2343
2344 /******************* Bit definition for CAN_RI0R register *******************/
2345 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
2346 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
2347 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
2348 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
2349
2350 /******************* Bit definition for CAN_RDT0R register ******************/
2351 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
2352 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
2353 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
2354
2355 /******************* Bit definition for CAN_RDL0R register ******************/
2356 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
2357 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
2358 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
2359 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
2360
2361 /******************* Bit definition for CAN_RDH0R register ******************/
2362 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
2363 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
2364 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
2365 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
2366
2367 /******************* Bit definition for CAN_RI1R register *******************/
2368 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
2369 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
2370 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
2371 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
2372
2373 /******************* Bit definition for CAN_RDT1R register ******************/
2374 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
2375 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
2376 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
2377
2378 /******************* Bit definition for CAN_RDL1R register ******************/
2379 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
2380 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
2381 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
2382 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
2383
2384 /******************* Bit definition for CAN_RDH1R register ******************/
2385 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
2386 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
2387 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
2388 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
2389
2390 /*!<CAN filter registers */
2391 /******************* Bit definition for CAN_FMR register ********************/
2392 #define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!<Filter Init Mode */
2393
2394 /******************* Bit definition for CAN_FM1R register *******************/
2395 #define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /*!<Filter Mode */
2396 #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
2397 #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
2398 #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
2399 #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
2400 #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
2401 #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
2402 #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
2403 #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
2404 #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
2405 #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
2406 #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
2407 #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
2408 #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
2409 #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
2410
2411 /******************* Bit definition for CAN_FS1R register *******************/
2412 #define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */
2413 #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
2414 #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
2415 #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
2416 #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
2417 #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
2418 #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
2419 #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
2420 #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
2421 #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
2422 #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
2423 #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
2424 #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
2425 #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
2426 #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
2427
2428 /****************** Bit definition for CAN_FFA1R register *******************/
2429 #define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */
2430 #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */
2431 #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */
2432 #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */
2433 #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */
2434 #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */
2435 #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */
2436 #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */
2437 #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */
2438 #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */
2439 #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */
2440 #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */
2441 #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */
2442 #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */
2443 #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */
2444
2445 /******************* Bit definition for CAN_FA1R register *******************/
2446 #define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */
2447 #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */
2448 #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */
2449 #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */
2450 #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */
2451 #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */
2452 #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */
2453 #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */
2454 #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */
2455 #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */
2456 #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */
2457 #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */
2458 #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */
2459 #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */
2460 #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */
2461
2462 /******************* Bit definition for CAN_F0R1 register *******************/
2463 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2464 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2465 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2466 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2467 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2468 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2469 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2470 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2471 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2472 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2473 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2474 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2475 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2476 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2477 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2478 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2479 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2480 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2481 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2482 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2483 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2484 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2485 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2486 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2487 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2488 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2489 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2490 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2491 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2492 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2493 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2494 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2495
2496 /******************* Bit definition for CAN_F1R1 register *******************/
2497 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2498 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2499 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2500 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2501 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2502 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2503 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2504 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2505 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2506 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2507 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2508 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2509 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2510 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2511 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2512 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2513 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2514 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2515 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2516 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2517 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2518 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2519 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2520 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2521 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2522 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2523 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2524 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2525 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2526 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2527 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2528 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2529
2530 /******************* Bit definition for CAN_F2R1 register *******************/
2531 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2532 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2533 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2534 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2535 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2536 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2537 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2538 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2539 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2540 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2541 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2542 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2543 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2544 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2545 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2546 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2547 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2548 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2549 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2550 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2551 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2552 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2553 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2554 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2555 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2556 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2557 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2558 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2559 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2560 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2561 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2562 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2563
2564 /******************* Bit definition for CAN_F3R1 register *******************/
2565 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2566 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2567 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2568 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2569 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2570 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2571 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2572 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2573 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2574 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2575 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2576 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2577 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2578 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2579 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2580 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2581 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2582 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2583 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2584 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2585 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2586 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2587 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2588 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2589 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2590 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2591 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2592 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2593 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2594 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2595 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2596 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2597
2598 /******************* Bit definition for CAN_F4R1 register *******************/
2599 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2600 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2601 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2602 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2603 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2604 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2605 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2606 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2607 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2608 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2609 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2610 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2611 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2612 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2613 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2614 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2615 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2616 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2617 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2618 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2619 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2620 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2621 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2622 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2623 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2624 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2625 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2626 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2627 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2628 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2629 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2630 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2631
2632 /******************* Bit definition for CAN_F5R1 register *******************/
2633 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2634 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2635 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2636 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2637 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2638 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2639 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2640 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2641 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2642 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2643 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2644 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2645 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2646 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2647 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2648 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2649 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2650 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2651 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2652 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2653 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2654 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2655 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2656 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2657 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2658 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2659 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2660 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2661 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2662 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2663 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2664 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2665
2666 /******************* Bit definition for CAN_F6R1 register *******************/
2667 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2668 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2669 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2670 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2671 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2672 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2673 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2674 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2675 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2676 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2677 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2678 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2679 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2680 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2681 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2682 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2683 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2684 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2685 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2686 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2687 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2688 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2689 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2690 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2691 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2692 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2693 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2694 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2695 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2696 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2697 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2698 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2699
2700 /******************* Bit definition for CAN_F7R1 register *******************/
2701 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2702 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2703 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2704 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2705 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2706 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2707 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2708 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2709 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2710 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2711 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2712 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2713 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2714 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2715 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2716 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2717 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2718 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2719 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2720 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2721 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2722 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2723 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2724 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2725 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2726 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2727 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2728 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2729 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2730 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2731 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2732 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2733
2734 /******************* Bit definition for CAN_F8R1 register *******************/
2735 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2736 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2737 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2738 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2739 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2740 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2741 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2742 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2743 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2744 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2745 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2746 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2747 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2748 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2749 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2750 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2751 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2752 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2753 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2754 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2755 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2756 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2757 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2758 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2759 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2760 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2761 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2762 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2763 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2764 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2765 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2766 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2767
2768 /******************* Bit definition for CAN_F9R1 register *******************/
2769 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2770 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2771 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2772 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2773 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2774 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2775 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2776 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2777 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2778 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2779 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2780 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2781 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2782 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2783 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2784 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2785 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2786 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2787 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2788 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2789 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2790 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2791 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2792 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2793 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2794 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2795 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2796 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2797 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2798 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2799 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2800 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2801
2802 /******************* Bit definition for CAN_F10R1 register ******************/
2803 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2804 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2805 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2806 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2807 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2808 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2809 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2810 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2811 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2812 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2813 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2814 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2815 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2816 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2817 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2818 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2819 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2820 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2821 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2822 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2823 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2824 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2825 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2826 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2827 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2828 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2829 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2830 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2831 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2832 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2833 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2834 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2835
2836 /******************* Bit definition for CAN_F11R1 register ******************/
2837 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2838 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2839 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2840 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2841 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2842 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2843 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2844 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2845 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2846 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2847 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2848 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2849 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2850 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2851 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2852 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2853 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2854 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2855 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2856 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2857 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2858 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2859 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2860 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2861 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2862 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2863 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2864 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2865 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2866 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2867 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2868 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2869
2870 /******************* Bit definition for CAN_F12R1 register ******************/
2871 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2872 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2873 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2874 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2875 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2876 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2877 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2878 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2879 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2880 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2881 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2882 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2883 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2884 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2885 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2886 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2887 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2888 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2889 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2890 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2891 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2892 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2893 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2894 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2895 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2896 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2897 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2898 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2899 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2900 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2901 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2902 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2903
2904 /******************* Bit definition for CAN_F13R1 register ******************/
2905 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2906 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2907 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2908 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2909 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2910 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2911 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2912 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2913 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2914 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2915 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2916 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2917 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2918 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2919 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2920 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2921 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2922 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2923 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2924 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2925 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2926 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2927 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2928 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2929 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2930 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2931 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2932 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2933 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2934 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2935 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2936 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2937
2938 /******************* Bit definition for CAN_F0R2 register *******************/
2939 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2940 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2941 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2942 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2943 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2944 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2945 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2946 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2947 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2948 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2949 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2950 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2951 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2952 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2953 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2954 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2955 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2956 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2957 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2958 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2959 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2960 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2961 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2962 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2963 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2964 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2965 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
2966 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
2967 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
2968 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
2969 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
2970 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
2971
2972 /******************* Bit definition for CAN_F1R2 register *******************/
2973 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
2974 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
2975 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
2976 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
2977 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
2978 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
2979 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
2980 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
2981 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
2982 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
2983 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
2984 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
2985 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
2986 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
2987 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
2988 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
2989 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
2990 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
2991 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
2992 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
2993 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
2994 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
2995 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
2996 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
2997 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
2998 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
2999 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
3000 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
3001 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
3002 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
3003 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
3004 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
3005
3006 /******************* Bit definition for CAN_F2R2 register *******************/
3007 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
3008 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
3009 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
3010 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
3011 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
3012 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
3013 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
3014 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
3015 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
3016 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
3017 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
3018 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
3019 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
3020 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
3021 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
3022 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
3023 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
3024 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
3025 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
3026 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
3027 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
3028 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
3029 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
3030 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
3031 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
3032 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
3033 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
3034 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
3035 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
3036 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
3037 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
3038 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
3039
3040 /******************* Bit definition for CAN_F3R2 register *******************/
3041 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
3042 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
3043 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
3044 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
3045 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
3046 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
3047 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
3048 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
3049 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
3050 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
3051 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
3052 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
3053 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
3054 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
3055 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
3056 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
3057 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
3058 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
3059 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
3060 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
3061 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
3062 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
3063 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
3064 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
3065 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
3066 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
3067 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
3068 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
3069 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
3070 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
3071 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
3072 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
3073
3074 /******************* Bit definition for CAN_F4R2 register *******************/
3075 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
3076 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
3077 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
3078 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
3079 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
3080 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
3081 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
3082 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
3083 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
3084 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
3085 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
3086 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
3087 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
3088 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
3089 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
3090 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
3091 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
3092 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
3093 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
3094 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
3095 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
3096 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
3097 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
3098 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
3099 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
3100 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
3101 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
3102 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
3103 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
3104 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
3105 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
3106 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
3107
3108 /******************* Bit definition for CAN_F5R2 register *******************/
3109 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
3110 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
3111 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
3112 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
3113 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
3114 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
3115 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
3116 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
3117 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
3118 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
3119 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
3120 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
3121 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
3122 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
3123 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
3124 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
3125 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
3126 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
3127 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
3128 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
3129 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
3130 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
3131 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
3132 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
3133 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
3134 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
3135 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
3136 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
3137 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
3138 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
3139 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
3140 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
3141
3142 /******************* Bit definition for CAN_F6R2 register *******************/
3143 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
3144 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
3145 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
3146 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
3147 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
3148 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
3149 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
3150 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
3151 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
3152 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
3153 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
3154 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
3155 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
3156 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
3157 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
3158 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
3159 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
3160 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
3161 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
3162 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
3163 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
3164 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
3165 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
3166 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
3167 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
3168 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
3169 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
3170 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
3171 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
3172 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
3173 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
3174 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
3175
3176 /******************* Bit definition for CAN_F7R2 register *******************/
3177 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
3178 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
3179 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
3180 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
3181 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
3182 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
3183 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
3184 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
3185 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
3186 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
3187 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
3188 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
3189 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
3190 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
3191 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
3192 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
3193 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
3194 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
3195 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
3196 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
3197 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
3198 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
3199 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
3200 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
3201 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
3202 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
3203 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
3204 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
3205 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
3206 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
3207 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
3208 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
3209
3210 /******************* Bit definition for CAN_F8R2 register *******************/
3211 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
3212 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
3213 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
3214 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
3215 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
3216 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
3217 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
3218 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
3219 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
3220 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
3221 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
3222 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
3223 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
3224 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
3225 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
3226 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
3227 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
3228 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
3229 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
3230 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
3231 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
3232 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
3233 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
3234 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
3235 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
3236 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
3237 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
3238 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
3239 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
3240 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
3241 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
3242 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
3243
3244 /******************* Bit definition for CAN_F9R2 register *******************/
3245 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
3246 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
3247 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
3248 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
3249 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
3250 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
3251 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
3252 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
3253 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
3254 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
3255 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
3256 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
3257 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
3258 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
3259 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
3260 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
3261 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
3262 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
3263 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
3264 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
3265 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
3266 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
3267 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
3268 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
3269 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
3270 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
3271 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
3272 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
3273 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
3274 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
3275 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
3276 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
3277
3278 /******************* Bit definition for CAN_F10R2 register ******************/
3279 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
3280 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
3281 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
3282 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
3283 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
3284 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
3285 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
3286 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
3287 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
3288 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
3289 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
3290 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
3291 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
3292 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
3293 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
3294 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
3295 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
3296 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
3297 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
3298 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
3299 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
3300 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
3301 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
3302 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
3303 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
3304 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
3305 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
3306 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
3307 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
3308 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
3309 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
3310 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
3311
3312 /******************* Bit definition for CAN_F11R2 register ******************/
3313 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
3314 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
3315 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
3316 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
3317 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
3318 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
3319 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
3320 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
3321 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
3322 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
3323 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
3324 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
3325 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
3326 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
3327 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
3328 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
3329 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
3330 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
3331 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
3332 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
3333 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
3334 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
3335 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
3336 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
3337 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
3338 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
3339 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
3340 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
3341 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
3342 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
3343 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
3344 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
3345
3346 /******************* Bit definition for CAN_F12R2 register ******************/
3347 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
3348 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
3349 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
3350 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
3351 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
3352 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
3353 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
3354 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
3355 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
3356 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
3357 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
3358 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
3359 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
3360 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
3361 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
3362 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
3363 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
3364 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
3365 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
3366 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
3367 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
3368 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
3369 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
3370 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
3371 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
3372 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
3373 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
3374 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
3375 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
3376 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
3377 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
3378 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
3379
3380 /******************* Bit definition for CAN_F13R2 register ******************/
3381 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
3382 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
3383 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
3384 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
3385 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
3386 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
3387 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
3388 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
3389 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
3390 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
3391 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
3392 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
3393 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
3394 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
3395 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
3396 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
3397 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
3398 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
3399 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
3400 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
3401 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
3402 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
3403 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
3404 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
3405 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
3406 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
3407 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
3408 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
3409 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
3410 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
3411 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
3412 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
3413
3414 /******************************************************************************/
3415 /* */
3416 /* CRC calculation unit (CRC) */
3417 /* */
3418 /******************************************************************************/
3419 /******************* Bit definition for CRC_DR register *********************/
3420 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
3421
3422 /******************* Bit definition for CRC_IDR register ********************/
3423 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
3424
3425 /******************** Bit definition for CRC_CR register ********************/
3426 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
3427 #define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
3428 #define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
3429 #define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
3430 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
3431 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */
3432 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */
3433 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
3434
3435 /******************* Bit definition for CRC_INIT register *******************/
3436 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
3437
3438 /******************* Bit definition for CRC_POL register ********************/
3439 #define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
3440
3441 /******************************************************************************/
3442 /* */
3443 /* Digital to Analog Converter (DAC) */
3444 /* */
3445 /******************************************************************************/
3446 /******************** Bit definition for DAC_CR register ********************/
3447 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
3448 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
3449 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
3450
3451 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
3452 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
3453 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
3454 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
3455
3456 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
3457 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
3458 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
3459
3460 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
3461 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
3462 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
3463 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
3464 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
3465
3466 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
3467 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun IT enable */
3468 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
3469 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
3470 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
3471
3472 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
3473 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
3474 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
3475 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
3476
3477 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
3478 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
3479 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
3480
3481 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
3482 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
3483 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
3484 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
3485 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
3486
3487 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
3488 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun IT enable */
3489
3490 /***************** Bit definition for DAC_SWTRIGR register ******************/
3491 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
3492 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!< DAC channel2 software trigger */
3493
3494 /***************** Bit definition for DAC_DHR12R1 register ******************/
3495 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
3496
3497 /***************** Bit definition for DAC_DHR12L1 register ******************/
3498 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
3499
3500 /****************** Bit definition for DAC_DHR8R1 register ******************/
3501 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
3502
3503 /***************** Bit definition for DAC_DHR12R2 register ******************/
3504 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!< DAC channel2 12-bit Right aligned data */
3505
3506 /***************** Bit definition for DAC_DHR12L2 register ******************/
3507 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!< DAC channel2 12-bit Left aligned data */
3508
3509 /****************** Bit definition for DAC_DHR8R2 register ******************/
3510 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!< DAC channel2 8-bit Right aligned data */
3511
3512 /***************** Bit definition for DAC_DHR12RD register ******************/
3513 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
3514 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
3515
3516 /***************** Bit definition for DAC_DHR12LD register ******************/
3517 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
3518 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
3519
3520 /****************** Bit definition for DAC_DHR8RD register ******************/
3521 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
3522 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!< DAC channel2 8-bit Right aligned data */
3523
3524 /******************* Bit definition for DAC_DOR1 register *******************/
3525 #define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */
3526
3527 /******************* Bit definition for DAC_DOR2 register *******************/
3528 #define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /*!< DAC channel2 data output */
3529
3530 /******************** Bit definition for DAC_SR register ********************/
3531 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
3532 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
3533
3534 /******************************************************************************/
3535 /* */
3536 /* Debug MCU (DBGMCU) */
3537 /* */
3538 /******************************************************************************/
3539 /******************** Bit definition for DBGMCU_IDCODE register *************/
3540 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
3541 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
3542
3543 /******************** Bit definition for DBGMCU_CR register *****************/
3544 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
3545 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
3546 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
3547 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
3548
3549 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
3550 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
3551 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
3552
3553 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
3554 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
3555 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
3556 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
3557 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
3558 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
3559 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
3560 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
3561 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
3562 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
3563 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
3564 #define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000)
3565
3566 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
3567 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
3568 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
3569 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00000004)
3570 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00000008)
3571 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00000010)
3572
3573 /******************************************************************************/
3574 /* */
3575 /* DMA Controller (DMA) */
3576 /* */
3577 /******************************************************************************/
3578 /******************* Bit definition for DMA_ISR register ********************/
3579 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
3580 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
3581 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
3582 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
3583 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
3584 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
3585 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
3586 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
3587 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
3588 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
3589 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
3590 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
3591 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
3592 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
3593 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
3594 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
3595 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
3596 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
3597 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
3598 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
3599 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
3600 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
3601 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
3602 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
3603 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
3604 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
3605 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
3606 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
3607
3608 /******************* Bit definition for DMA_IFCR register *******************/
3609 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
3610 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
3611 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
3612 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
3613 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
3614 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
3615 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
3616 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
3617 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
3618 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
3619 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
3620 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
3621 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
3622 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
3623 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
3624 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
3625 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
3626 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
3627 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
3628 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
3629 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
3630 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
3631 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
3632 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
3633 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
3634 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
3635 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
3636 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
3637
3638 /******************* Bit definition for DMA_CCR register ********************/
3639 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
3640 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
3641 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
3642 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
3643 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
3644 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
3645 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
3646 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
3647
3648 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
3649 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
3650 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
3651
3652 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
3653 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
3654 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
3655
3656 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
3657 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
3658 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
3659
3660 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
3661
3662 /****************** Bit definition for DMA_CNDTR register *******************/
3663 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
3664
3665 /****************** Bit definition for DMA_CPAR register ********************/
3666 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
3667
3668 /****************** Bit definition for DMA_CMAR register ********************/
3669 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
3670
3671 /******************************************************************************/
3672 /* */
3673 /* External Interrupt/Event Controller (EXTI) */
3674 /* */
3675 /******************************************************************************/
3676 /******************* Bit definition for EXTI_IMR1/EXTI_IMR2 register ********/
3677 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
3678 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
3679 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
3680 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
3681 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
3682 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
3683 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
3684 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
3685 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
3686 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
3687 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
3688 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
3689 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
3690 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
3691 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
3692 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
3693 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
3694 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
3695 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
3696 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
3697 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
3698 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
3699 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
3700 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
3701 #define EXTI_IMR_MR24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */
3702 #define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
3703 #define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
3704 #define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
3705 #define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
3706
3707 /******************* Bit definition for EXTI_EMR1/EXTI_EMR2 register ********/
3708 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
3709 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
3710 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
3711 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
3712 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
3713 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
3714 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
3715 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
3716 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
3717 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
3718 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
3719 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
3720 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
3721 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
3722 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
3723 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
3724 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
3725 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
3726 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
3727 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
3728 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
3729 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
3730 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
3731 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
3732 #define EXTI_EMR_MR24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */
3733 #define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
3734 #define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
3735 #define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
3736 #define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
3737
3738 /****************** Bit definition for EXTI_RTSR1/EXTI_RTSR2 register *******/
3739 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
3740 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
3741 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
3742 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
3743 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
3744 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
3745 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
3746 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
3747 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
3748 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
3749 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
3750 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
3751 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
3752 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
3753 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
3754 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
3755 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
3756 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
3757 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
3758 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
3759 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
3760 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
3761 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
3762 #define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
3763 #define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
3764 #define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
3765 #define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
3766 #define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
3767 #define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
3768
3769 /****************** Bit definition for EXTI_FTSR1/EXTI_FTSR2 register *******/
3770 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
3771 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
3772 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
3773 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
3774 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
3775 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
3776 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
3777 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
3778 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
3779 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
3780 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
3781 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
3782 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
3783 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
3784 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
3785 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
3786 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
3787 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
3788 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
3789 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
3790 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
3791 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
3792 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
3793 #define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
3794 #define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
3795 #define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
3796 #define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
3797 #define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
3798 #define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
3799
3800 /****************** Bit definition for EXTI_SWIER1/EXTI_SWIER2 register *****/
3801 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
3802 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
3803 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
3804 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
3805 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
3806 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
3807 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
3808 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
3809 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
3810 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
3811 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
3812 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
3813 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
3814 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
3815 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
3816 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
3817 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
3818 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
3819 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
3820 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
3821 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
3822 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
3823 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
3824 #define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
3825 #define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
3826 #define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
3827 #define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
3828 #define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
3829 #define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
3830
3831 /******************* Bit definition for EXTI_PR1/EXTI_PR2 register **********/
3832 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
3833 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
3834 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
3835 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
3836 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
3837 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
3838 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
3839 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
3840 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
3841 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
3842 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
3843 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
3844 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
3845 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
3846 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
3847 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
3848 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
3849 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
3850 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
3851 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
3852 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
3853 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
3854 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
3855 #define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
3856 #define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
3857 #define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
3858 #define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
3859 #define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
3860 #define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
3861
3862 /******************************************************************************/
3863 /* */
3864 /* FLASH */
3865 /* */
3866 /******************************************************************************/
3867 /******************* Bit definition for FLASH_ACR register ******************/
3868 #define FLASH_ACR_LATENCY ((uint32_t)0x00000007) /*!< LATENCY[2:0] bits (Latency) */
3869 #define FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) /*!< Bit 0 */
3870 #define FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) /*!< Bit 1 */
3871 #define FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) /*!< Bit 2 */
3872
3873 #define FLASH_ACR_HLFCYA ((uint32_t)0x00000008) /*!< Flash Half Cycle Access Enable */
3874 #define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
3875 #define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
3876
3877 /****************** Bit definition for FLASH_KEYR register ******************/
3878 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
3879
3880 #define RDP_KEY ((uint32_t)0x000000A5) /*!< RDP Key */
3881 #define FLASH_KEY1 ((uint32_t)0x45670123) /*!< FPEC Key1 */
3882 #define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< FPEC Key2 */
3883
3884 /***************** Bit definition for FLASH_OPTKEYR register ****************/
3885 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
3886
3887 #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
3888 #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
3889
3890 /****************** Bit definition for FLASH_SR register *******************/
3891 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
3892 #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
3893 #define FLASH_SR_WRPERR ((uint32_t)0x00000010) /*!< Write Protection Error */
3894 #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
3895
3896 /******************* Bit definition for FLASH_CR register *******************/
3897 #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
3898 #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
3899 #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
3900 #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
3901 #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
3902 #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
3903 #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
3904 #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
3905 #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
3906 #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
3907 #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< OptionBytes Loader Launch */
3908
3909 /******************* Bit definition for FLASH_AR register *******************/
3910 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
3911
3912 /****************** Bit definition for FLASH_OBR register *******************/
3913 #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
3914 #define FLASH_OBR_RDPRT ((uint32_t)0x00000006) /*!< Read protection */
3915 #define FLASH_OBR_RDPRT_1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
3916 #define FLASH_OBR_RDPRT_2 ((uint32_t)0x00000006) /*!< Read protection Level 2 */
3917
3918 #define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */
3919 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
3920 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
3921 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
3922 #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
3923 #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
3924 #define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
3925
3926 /****************** Bit definition for FLASH_WRPR register ******************/
3927 #define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
3928
3929 /*----------------------------------------------------------------------------*/
3930
3931 /****************** Bit definition for OB_RDP register **********************/
3932 #define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
3933 #define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
3934
3935 /****************** Bit definition for OB_USER register *********************/
3936 #define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
3937 #define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
3938
3939 /****************** Bit definition for FLASH_WRP0 register ******************/
3940 #define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
3941 #define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
3942
3943 /****************** Bit definition for FLASH_WRP1 register ******************/
3944 #define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
3945 #define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
3946
3947 /****************** Bit definition for FLASH_WRP2 register ******************/
3948 #define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
3949 #define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
3950
3951 /****************** Bit definition for FLASH_WRP3 register ******************/
3952 #define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
3953 #define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
3954 /******************************************************************************/
3955 /* */
3956 /* General Purpose I/O (GPIO) */
3957 /* */
3958 /******************************************************************************/
3959 /******************* Bit definition for GPIO_MODER register *****************/
3960 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
3961 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
3962 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
3963 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
3964 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
3965 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
3966 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
3967 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
3968 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
3969 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
3970 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
3971 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
3972 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
3973 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
3974 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
3975 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
3976 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
3977 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
3978 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
3979 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
3980 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
3981 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
3982 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
3983 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
3984 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
3985 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
3986 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
3987 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
3988 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
3989 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
3990 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
3991 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
3992 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
3993 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
3994 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
3995 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
3996 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
3997 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
3998 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
3999 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
4000 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
4001 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
4002 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
4003 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
4004 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
4005 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
4006 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
4007 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
4008
4009 /****************** Bit definition for GPIO_OTYPER register *****************/
4010 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
4011 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
4012 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
4013 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
4014 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
4015 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
4016 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
4017 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
4018 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
4019 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
4020 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
4021 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
4022 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
4023 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
4024 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
4025 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
4026
4027 /**************** Bit definition for GPIO_OSPEEDR register ******************/
4028 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
4029 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
4030 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
4031 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
4032 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
4033 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
4034 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
4035 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
4036 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
4037 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
4038 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
4039 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
4040 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
4041 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
4042 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
4043 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
4044 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
4045 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
4046 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
4047 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
4048 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
4049 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
4050 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
4051 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
4052 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
4053 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
4054 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
4055 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
4056 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
4057 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
4058 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
4059 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
4060 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
4061 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
4062 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
4063 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
4064 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
4065 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
4066 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
4067 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
4068 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
4069 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
4070 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
4071 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
4072 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
4073 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
4074 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
4075 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
4076
4077 /******************* Bit definition for GPIO_PUPDR register ******************/
4078 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
4079 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
4080 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
4081 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
4082 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
4083 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
4084 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
4085 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
4086 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
4087 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
4088 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
4089 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
4090 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
4091 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
4092 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
4093 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
4094 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
4095 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
4096 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
4097 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
4098 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
4099 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
4100 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
4101 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
4102 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
4103 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
4104 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
4105 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
4106 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
4107 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
4108 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
4109 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
4110 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
4111 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
4112 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
4113 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
4114 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
4115 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
4116 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
4117 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
4118 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
4119 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
4120 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
4121 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
4122 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
4123 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
4124 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
4125 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
4126
4127 /******************* Bit definition for GPIO_IDR register *******************/
4128 #define GPIO_IDR_0 ((uint32_t)0x00000001)
4129 #define GPIO_IDR_1 ((uint32_t)0x00000002)
4130 #define GPIO_IDR_2 ((uint32_t)0x00000004)
4131 #define GPIO_IDR_3 ((uint32_t)0x00000008)
4132 #define GPIO_IDR_4 ((uint32_t)0x00000010)
4133 #define GPIO_IDR_5 ((uint32_t)0x00000020)
4134 #define GPIO_IDR_6 ((uint32_t)0x00000040)
4135 #define GPIO_IDR_7 ((uint32_t)0x00000080)
4136 #define GPIO_IDR_8 ((uint32_t)0x00000100)
4137 #define GPIO_IDR_9 ((uint32_t)0x00000200)
4138 #define GPIO_IDR_10 ((uint32_t)0x00000400)
4139 #define GPIO_IDR_11 ((uint32_t)0x00000800)
4140 #define GPIO_IDR_12 ((uint32_t)0x00001000)
4141 #define GPIO_IDR_13 ((uint32_t)0x00002000)
4142 #define GPIO_IDR_14 ((uint32_t)0x00004000)
4143 #define GPIO_IDR_15 ((uint32_t)0x00008000)
4144
4145 /****************** Bit definition for GPIO_ODR register ********************/
4146 #define GPIO_ODR_0 ((uint32_t)0x00000001)
4147 #define GPIO_ODR_1 ((uint32_t)0x00000002)
4148 #define GPIO_ODR_2 ((uint32_t)0x00000004)
4149 #define GPIO_ODR_3 ((uint32_t)0x00000008)
4150 #define GPIO_ODR_4 ((uint32_t)0x00000010)
4151 #define GPIO_ODR_5 ((uint32_t)0x00000020)
4152 #define GPIO_ODR_6 ((uint32_t)0x00000040)
4153 #define GPIO_ODR_7 ((uint32_t)0x00000080)
4154 #define GPIO_ODR_8 ((uint32_t)0x00000100)
4155 #define GPIO_ODR_9 ((uint32_t)0x00000200)
4156 #define GPIO_ODR_10 ((uint32_t)0x00000400)
4157 #define GPIO_ODR_11 ((uint32_t)0x00000800)
4158 #define GPIO_ODR_12 ((uint32_t)0x00001000)
4159 #define GPIO_ODR_13 ((uint32_t)0x00002000)
4160 #define GPIO_ODR_14 ((uint32_t)0x00004000)
4161 #define GPIO_ODR_15 ((uint32_t)0x00008000)
4162
4163 /****************** Bit definition for GPIO_BSRR register ********************/
4164 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
4165 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
4166 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
4167 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
4168 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
4169 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
4170 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
4171 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
4172 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
4173 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
4174 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
4175 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
4176 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
4177 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
4178 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
4179 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
4180 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
4181 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
4182 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
4183 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
4184 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
4185 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
4186 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
4187 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
4188 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
4189 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
4190 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
4191 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
4192 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
4193 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
4194 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
4195 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
4196
4197 /****************** Bit definition for GPIO_LCKR register ********************/
4198 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
4199 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
4200 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
4201 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
4202 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
4203 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
4204 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
4205 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
4206 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
4207 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
4208 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
4209 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
4210 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
4211 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
4212 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
4213 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
4214 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
4215
4216 /****************** Bit definition for GPIO_AFRL register ********************/
4217 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
4218 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
4219 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
4220 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
4221 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
4222 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
4223 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
4224 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
4225
4226 /****************** Bit definition for GPIO_AFRH register ********************/
4227 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
4228 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
4229 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
4230 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
4231 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
4232 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
4233 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
4234 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
4235
4236 /****************** Bit definition for GPIO_BRR register *********************/
4237 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
4238 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
4239 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
4240 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
4241 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
4242 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
4243 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
4244 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
4245 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
4246 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
4247 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
4248 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
4249 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
4250 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
4251 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
4252 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
4253
4254 /******************************************************************************/
4255 /* */
4256 /* Inter-integrated Circuit Interface (I2C) */
4257 /* */
4258 /******************************************************************************/
4259 /******************* Bit definition for I2C_CR1 register *******************/
4260 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
4261 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
4262 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
4263 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
4264 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
4265 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
4266 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
4267 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
4268 #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
4269 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
4270 #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
4271 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
4272 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
4273 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
4274 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
4275 #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
4276 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
4277 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
4278 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
4279 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
4280 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
4281
4282 /****************** Bit definition for I2C_CR2 register ********************/
4283 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
4284 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
4285 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
4286 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
4287 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
4288 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
4289 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
4290 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
4291 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
4292 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
4293 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
4294
4295 /******************* Bit definition for I2C_OAR1 register ******************/
4296 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
4297 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
4298 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
4299
4300 /******************* Bit definition for I2C_OAR2 register *******************/
4301 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
4302 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
4303 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
4304
4305 /******************* Bit definition for I2C_TIMINGR register *****************/
4306 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
4307 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
4308 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
4309 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
4310 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
4311
4312 /******************* Bit definition for I2C_TIMEOUTR register *****************/
4313 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
4314 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
4315 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
4316 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
4317 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
4318
4319 /****************** Bit definition for I2C_ISR register *********************/
4320 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
4321 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
4322 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
4323 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
4324 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
4325 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
4326 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
4327 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
4328 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
4329 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
4330 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
4331 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
4332 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
4333 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
4334 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
4335 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
4336 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
4337
4338 /****************** Bit definition for I2C_ICR register *********************/
4339 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
4340 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
4341 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
4342 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
4343 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
4344 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
4345 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
4346 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
4347 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
4348
4349 /****************** Bit definition for I2C_PECR register ********************/
4350 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
4351
4352 /****************** Bit definition for I2C_RXDR register *********************/
4353 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
4354
4355 /****************** Bit definition for I2C_TXDR register *********************/
4356 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
4357
4358
4359 /******************************************************************************/
4360 /* */
4361 /* Independent WATCHDOG (IWDG) */
4362 /* */
4363 /******************************************************************************/
4364 /******************* Bit definition for IWDG_KR register ********************/
4365 #define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /*!< Key value (write only, read 0000h) */
4366
4367 /******************* Bit definition for IWDG_PR register ********************/
4368 #define IWDG_PR_PR ((uint32_t)0x00000007) /*!< PR[2:0] (Prescaler divider) */
4369 #define IWDG_PR_PR_0 ((uint32_t)0x00000001) /*!< Bit 0 */
4370 #define IWDG_PR_PR_1 ((uint32_t)0x00000002) /*!< Bit 1 */
4371 #define IWDG_PR_PR_2 ((uint32_t)0x00000004) /*!< Bit 2 */
4372
4373 /******************* Bit definition for IWDG_RLR register *******************/
4374 #define IWDG_RLR_RL ((uint32_t)0x00000FFF) /*!< Watchdog counter reload value */
4375
4376 /******************* Bit definition for IWDG_SR register ********************/
4377 #define IWDG_SR_PVU ((uint32_t)0x00000001) /*!< Watchdog prescaler value update */
4378 #define IWDG_SR_RVU ((uint32_t)0x00000002) /*!< Watchdog counter reload value update */
4379 #define IWDG_SR_WVU ((uint32_t)0x00000004) /*!< Watchdog counter window value update */
4380
4381 /******************* Bit definition for IWDG_KR register ********************/
4382 #define IWDG_WINR_WIN ((uint32_t)0x00000FFF) /*!< Watchdog counter window value */
4383
4384 /******************************************************************************/
4385 /* */
4386 /* Power Control */
4387 /* */
4388 /******************************************************************************/
4389 /******************** Bit definition for PWR_CR register ********************/
4390 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
4391 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
4392 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
4393 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
4394 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
4395
4396 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
4397 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
4398 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
4399 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
4400
4401 /*!< PVD level configuration */
4402 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
4403 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
4404 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
4405 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
4406 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
4407 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
4408 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
4409 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
4410
4411 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
4412
4413 /******************* Bit definition for PWR_CSR register ********************/
4414 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
4415 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
4416 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
4417 #define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
4418
4419 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
4420 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
4421 #define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /*!< Enable WKUP pin 3 */
4422
4423 /******************************************************************************/
4424 /* */
4425 /* Reset and Clock Control */
4426 /* */
4427 /******************************************************************************/
4428 /******************** Bit definition for RCC_CR register ********************/
4429 #define RCC_CR_HSION ((uint32_t)0x00000001)
4430 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
4431
4432 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
4433 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
4434 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
4435 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
4436 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
4437 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
4438
4439 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
4440 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
4441 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
4442 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
4443 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
4444 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
4445 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
4446 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
4447 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
4448
4449 #define RCC_CR_HSEON ((uint32_t)0x00010000)
4450 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
4451 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
4452 #define RCC_CR_CSSON ((uint32_t)0x00080000)
4453 #define RCC_CR_PLLON ((uint32_t)0x01000000)
4454 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
4455
4456 /******************** Bit definition for RCC_CFGR register ******************/
4457 /*!< SW configuration */
4458 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
4459 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
4460 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
4461
4462 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
4463 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
4464 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
4465
4466 /*!< SWS configuration */
4467 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
4468 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
4469 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
4470
4471 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
4472 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
4473 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
4474
4475 /*!< HPRE configuration */
4476 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
4477 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
4478 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
4479 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
4480 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
4481
4482 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
4483 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
4484 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
4485 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
4486 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
4487 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
4488 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
4489 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
4490 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
4491
4492 /*!< PPRE1 configuration */
4493 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
4494 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
4495 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
4496 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
4497
4498 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
4499 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
4500 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
4501 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
4502 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
4503
4504 /*!< PPRE2 configuration */
4505 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
4506 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
4507 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
4508 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
4509
4510 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
4511 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
4512 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
4513 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
4514 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
4515
4516 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
4517 #define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
4518 #define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
4519
4520 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
4521 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
4522 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
4523
4524 /*!< PLLMUL configuration */
4525 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
4526 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
4527 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
4528 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
4529 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
4530
4531 #define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
4532 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
4533 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
4534 #define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
4535 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
4536 #define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
4537 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
4538 #define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
4539 #define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
4540 #define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
4541 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
4542 #define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
4543 #define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
4544 #define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
4545 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
4546
4547 /*!< USB configuration */
4548 #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB prescaler */
4549
4550 #define RCC_CFGR_USBPRE_DIV1_5 ((uint32_t)0x00000000) /*!< USB prescaler is PLL clock divided by 1.5 */
4551 #define RCC_CFGR_USBPRE_DIV1 ((uint32_t)0x00400000) /*!< USB prescaler is PLL clock divided by 1 */
4552
4553 /*!< I2S configuration */
4554 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000) /*!< I2S external clock source selection */
4555
4556 #define RCC_CFGR_I2SSRC_SYSCLK ((uint32_t)0x00000000) /*!< System clock selected as I2S clock source */
4557 #define RCC_CFGR_I2SSRC_EXT ((uint32_t)0x00800000) /*!< External clock selected as I2S clock source */
4558
4559 /*!< MCO configuration */
4560 #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
4561 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
4562 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
4563 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
4564
4565 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
4566 #define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
4567 #define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
4568 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
4569 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
4570 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
4571 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
4572
4573 #define RCC_CFGR_MCOF ((uint32_t)0x10000000) /*!< Microcontroller Clock Output Flag */
4574 #define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
4575
4576 /********************* Bit definition for RCC_CIR register ********************/
4577 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
4578 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
4579 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
4580 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
4581 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
4582 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
4583 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
4584 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
4585 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
4586 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
4587 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
4588 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
4589 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
4590 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
4591 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
4592 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
4593 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
4594
4595 /****************** Bit definition for RCC_APB2RSTR register *****************/
4596 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG reset */
4597 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 reset */
4598 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 reset */
4599 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 reset */
4600 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
4601 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 reset */
4602 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 reset */
4603 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 reset */
4604
4605 /****************** Bit definition for RCC_APB1RSTR register ******************/
4606 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
4607 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
4608 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
4609 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
4610 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
4611 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
4612 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 reset */
4613 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI3 reset */
4614 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
4615 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
4616 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
4617 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
4618 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
4619 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
4620 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB reset */
4621 #define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN reset */
4622 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR reset */
4623 #define RCC_APB1RSTR_DAC1RST ((uint32_t)0x20000000) /*!< DAC 1 reset */
4624
4625 /****************** Bit definition for RCC_AHBENR register ******************/
4626 #define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
4627 #define RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) /*!< DMA2 clock enable */
4628 #define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
4629 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
4630 #define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
4631 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
4632 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
4633 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
4634 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
4635 #define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */
4636 #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
4637 #define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
4638 #define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /*!< ADC1/ ADC2 clock enable */
4639 #define RCC_AHBENR_ADC34EN ((uint32_t)0x20000000) /*!< ADC3/ ADC4 clock enable */
4640
4641 /***************** Bit definition for RCC_APB2ENR register ******************/
4642 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< SYSCFG clock enable */
4643 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
4644 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
4645 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 clock enable */
4646 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
4647 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
4648 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
4649 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
4650
4651 /****************** Bit definition for RCC_APB1ENR register ******************/
4652 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
4653 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
4654 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
4655 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
4656 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
4657 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
4658 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
4659 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI3 clock enable */
4660 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
4661 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
4662 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
4663 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
4664 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
4665 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
4666 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
4667 #define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
4668 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
4669 #define RCC_APB1ENR_DAC1EN ((uint32_t)0x20000000) /*!< DAC 1 clock enable */
4670
4671 /******************** Bit definition for RCC_BDCR register ******************/
4672 #define RCC_BDCR_LSE ((uint32_t)0x00000007) /*!< External Low Speed oscillator [2:0] bits */
4673 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
4674 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
4675 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
4676
4677 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
4678 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
4679 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
4680
4681 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
4682 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
4683 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
4684
4685 /*!< RTC configuration */
4686 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
4687 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
4688 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
4689 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 32 used as RTC clock */
4690
4691 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
4692 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
4693
4694 /******************** Bit definition for RCC_CSR register *******************/
4695 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
4696 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
4697 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
4698 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
4699 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
4700 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
4701 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
4702 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
4703 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
4704 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
4705
4706 /******************* Bit definition for RCC_AHBRSTR register ****************/
4707 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA reset */
4708 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB reset */
4709 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC reset */
4710 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD reset */
4711 #define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00200000) /*!< GPIOE reset */
4712 #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF reset */
4713 #define RCC_AHBRSTR_TSCRST ((uint32_t)0x01000000) /*!< TSC reset */
4714 #define RCC_AHBRSTR_ADC12RST ((uint32_t)0x10000000) /*!< ADC1 & ADC2 reset */
4715 #define RCC_AHBRSTR_ADC34RST ((uint32_t)0x20000000) /*!< ADC3 & ADC4 reset */
4716
4717 /******************* Bit definition for RCC_CFGR2 register ******************/
4718 /*!< PREDIV configuration */
4719 #define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
4720 #define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
4721 #define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
4722 #define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
4723 #define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
4724
4725 #define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
4726 #define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
4727 #define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
4728 #define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
4729 #define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
4730 #define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
4731 #define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
4732 #define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
4733 #define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
4734 #define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
4735 #define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
4736 #define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
4737 #define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
4738 #define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
4739 #define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
4740 #define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
4741
4742 /*!< ADCPRE12 configuration */
4743 #define RCC_CFGR2_ADCPRE12 ((uint32_t)0x000001F0) /*!< ADCPRE12[8:4] bits */
4744 #define RCC_CFGR2_ADCPRE12_0 ((uint32_t)0x00000010) /*!< Bit 0 */
4745 #define RCC_CFGR2_ADCPRE12_1 ((uint32_t)0x00000020) /*!< Bit 1 */
4746 #define RCC_CFGR2_ADCPRE12_2 ((uint32_t)0x00000040) /*!< Bit 2 */
4747 #define RCC_CFGR2_ADCPRE12_3 ((uint32_t)0x00000080) /*!< Bit 3 */
4748 #define RCC_CFGR2_ADCPRE12_4 ((uint32_t)0x00000100) /*!< Bit 4 */
4749
4750 #define RCC_CFGR2_ADCPRE12_NO ((uint32_t)0x00000000) /*!< ADC12 clock disabled, ADC12 can use AHB clock */
4751 #define RCC_CFGR2_ADCPRE12_DIV1 ((uint32_t)0x00000100) /*!< ADC12 PLL clock divided by 1 */
4752 #define RCC_CFGR2_ADCPRE12_DIV2 ((uint32_t)0x00000110) /*!< ADC12 PLL clock divided by 2 */
4753 #define RCC_CFGR2_ADCPRE12_DIV4 ((uint32_t)0x00000120) /*!< ADC12 PLL clock divided by 4 */
4754 #define RCC_CFGR2_ADCPRE12_DIV6 ((uint32_t)0x00000130) /*!< ADC12 PLL clock divided by 6 */
4755 #define RCC_CFGR2_ADCPRE12_DIV8 ((uint32_t)0x00000140) /*!< ADC12 PLL clock divided by 8 */
4756 #define RCC_CFGR2_ADCPRE12_DIV10 ((uint32_t)0x00000150) /*!< ADC12 PLL clock divided by 10 */
4757 #define RCC_CFGR2_ADCPRE12_DIV12 ((uint32_t)0x00000160) /*!< ADC12 PLL clock divided by 12 */
4758 #define RCC_CFGR2_ADCPRE12_DIV16 ((uint32_t)0x00000170) /*!< ADC12 PLL clock divided by 16 */
4759 #define RCC_CFGR2_ADCPRE12_DIV32 ((uint32_t)0x00000180) /*!< ADC12 PLL clock divided by 32 */
4760 #define RCC_CFGR2_ADCPRE12_DIV64 ((uint32_t)0x00000190) /*!< ADC12 PLL clock divided by 64 */
4761 #define RCC_CFGR2_ADCPRE12_DIV128 ((uint32_t)0x000001A0) /*!< ADC12 PLL clock divided by 128 */
4762 #define RCC_CFGR2_ADCPRE12_DIV256 ((uint32_t)0x000001B0) /*!< ADC12 PLL clock divided by 256 */
4763
4764 /*!< ADCPRE34 configuration */
4765 #define RCC_CFGR2_ADCPRE34 ((uint32_t)0x00003E00) /*!< ADCPRE34[13:5] bits */
4766 #define RCC_CFGR2_ADCPRE34_0 ((uint32_t)0x00000200) /*!< Bit 0 */
4767 #define RCC_CFGR2_ADCPRE34_1 ((uint32_t)0x00000400) /*!< Bit 1 */
4768 #define RCC_CFGR2_ADCPRE34_2 ((uint32_t)0x00000800) /*!< Bit 2 */
4769 #define RCC_CFGR2_ADCPRE34_3 ((uint32_t)0x00001000) /*!< Bit 3 */
4770 #define RCC_CFGR2_ADCPRE34_4 ((uint32_t)0x00002000) /*!< Bit 4 */
4771
4772 #define RCC_CFGR2_ADCPRE34_NO ((uint32_t)0x00000000) /*!< ADC34 clock disabled, ADC34 can use AHB clock */
4773 #define RCC_CFGR2_ADCPRE34_DIV1 ((uint32_t)0x00002000) /*!< ADC34 PLL clock divided by 1 */
4774 #define RCC_CFGR2_ADCPRE34_DIV2 ((uint32_t)0x00002200) /*!< ADC34 PLL clock divided by 2 */
4775 #define RCC_CFGR2_ADCPRE34_DIV4 ((uint32_t)0x00002400) /*!< ADC34 PLL clock divided by 4 */
4776 #define RCC_CFGR2_ADCPRE34_DIV6 ((uint32_t)0x00002600) /*!< ADC34 PLL clock divided by 6 */
4777 #define RCC_CFGR2_ADCPRE34_DIV8 ((uint32_t)0x00002800) /*!< ADC34 PLL clock divided by 8 */
4778 #define RCC_CFGR2_ADCPRE34_DIV10 ((uint32_t)0x00002A00) /*!< ADC34 PLL clock divided by 10 */
4779 #define RCC_CFGR2_ADCPRE34_DIV12 ((uint32_t)0x00002C00) /*!< ADC34 PLL clock divided by 12 */
4780 #define RCC_CFGR2_ADCPRE34_DIV16 ((uint32_t)0x00002E00) /*!< ADC34 PLL clock divided by 16 */
4781 #define RCC_CFGR2_ADCPRE34_DIV32 ((uint32_t)0x00003000) /*!< ADC34 PLL clock divided by 32 */
4782 #define RCC_CFGR2_ADCPRE34_DIV64 ((uint32_t)0x00003200) /*!< ADC34 PLL clock divided by 64 */
4783 #define RCC_CFGR2_ADCPRE34_DIV128 ((uint32_t)0x00003400) /*!< ADC34 PLL clock divided by 128 */
4784 #define RCC_CFGR2_ADCPRE34_DIV256 ((uint32_t)0x00003600) /*!< ADC34 PLL clock divided by 256 */
4785
4786 /******************* Bit definition for RCC_CFGR3 register ******************/
4787 #define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
4788 #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
4789 #define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
4790
4791 #define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
4792 #define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
4793 #define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
4794 #define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
4795
4796 #define RCC_CFGR3_I2CSW ((uint32_t)0x00000030) /*!< I2CSW bits */
4797 #define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
4798 #define RCC_CFGR3_I2C2SW ((uint32_t)0x00000020) /*!< I2C2SW bits */
4799
4800 #define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
4801 #define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
4802 #define RCC_CFGR3_I2C2SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C2 clock source */
4803 #define RCC_CFGR3_I2C2SW_SYSCLK ((uint32_t)0x00000020) /*!< System clock selected as I2C2 clock source */
4804
4805 #define RCC_CFGR3_TIMSW ((uint32_t)0x00000300) /*!< TIMSW bits */
4806 #define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /*!< TIM1SW bits */
4807 #define RCC_CFGR3_TIM8SW ((uint32_t)0x00000200) /*!< TIM8SW bits */
4808
4809 #define RCC_CFGR3_TIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
4810 #define RCC_CFGR3_TIM1SW_PLL ((uint32_t)0x00000100) /*!< PLL clock used as TIM1 clock source */
4811
4812 #define RCC_CFGR3_TIM8SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM8 clock source */
4813 #define RCC_CFGR3_TIM8SW_PLL ((uint32_t)0x00000200) /*!< PLL clock used as TIM8 clock source */
4814
4815 #define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
4816 #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
4817 #define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
4818
4819 #define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */
4820 #define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
4821 #define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
4822 #define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
4823
4824 #define RCC_CFGR3_USART3SW ((uint32_t)0x000C0000) /*!< USART3SW[1:0] bits */
4825 #define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
4826 #define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
4827
4828 #define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */
4829 #define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
4830 #define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
4831 #define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
4832
4833 #define RCC_CFGR3_UART4SW ((uint32_t)0x00300000) /*!< UART4SW[1:0] bits */
4834 #define RCC_CFGR3_UART4SW_0 ((uint32_t)0x00100000) /*!< Bit 0 */
4835 #define RCC_CFGR3_UART4SW_1 ((uint32_t)0x00200000) /*!< Bit 1 */
4836
4837 #define RCC_CFGR3_UART4SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as UART4 clock source */
4838 #define RCC_CFGR3_UART4SW_SYSCLK ((uint32_t)0x00100000) /*!< System clock selected as UART4 clock source */
4839 #define RCC_CFGR3_UART4SW_LSE ((uint32_t)0x00200000) /*!< LSE oscillator clock used as UART4 clock source */
4840 #define RCC_CFGR3_UART4SW_HSI ((uint32_t)0x00300000) /*!< HSI oscillator clock used as UART4 clock source */
4841
4842 #define RCC_CFGR3_UART5SW ((uint32_t)0x00C00000) /*!< UART5SW[1:0] bits */
4843 #define RCC_CFGR3_UART5SW_0 ((uint32_t)0x00400000) /*!< Bit 0 */
4844 #define RCC_CFGR3_UART5SW_1 ((uint32_t)0x00800000) /*!< Bit 1 */
4845
4846 #define RCC_CFGR3_UART5SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as UART5 clock source */
4847 #define RCC_CFGR3_UART5SW_SYSCLK ((uint32_t)0x00400000) /*!< System clock selected as UART5 clock source */
4848 #define RCC_CFGR3_UART5SW_LSE ((uint32_t)0x00800000) /*!< LSE oscillator clock used as UART5 clock source */
4849 #define RCC_CFGR3_UART5SW_HSI ((uint32_t)0x00C00000) /*!< HSI oscillator clock used as UART5 clock source */
4850
4851 /******************************************************************************/
4852 /* */
4853 /* Real-Time Clock (RTC) */
4854 /* */
4855 /******************************************************************************/
4856 /******************** Bits definition for RTC_TR register *******************/
4857 #define RTC_TR_PM ((uint32_t)0x00400000)
4858 #define RTC_TR_HT ((uint32_t)0x00300000)
4859 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
4860 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
4861 #define RTC_TR_HU ((uint32_t)0x000F0000)
4862 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
4863 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
4864 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
4865 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
4866 #define RTC_TR_MNT ((uint32_t)0x00007000)
4867 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
4868 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
4869 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
4870 #define RTC_TR_MNU ((uint32_t)0x00000F00)
4871 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
4872 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
4873 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
4874 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
4875 #define RTC_TR_ST ((uint32_t)0x00000070)
4876 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
4877 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
4878 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
4879 #define RTC_TR_SU ((uint32_t)0x0000000F)
4880 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
4881 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
4882 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
4883 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
4884
4885 /******************** Bits definition for RTC_DR register *******************/
4886 #define RTC_DR_YT ((uint32_t)0x00F00000)
4887 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
4888 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
4889 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
4890 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
4891 #define RTC_DR_YU ((uint32_t)0x000F0000)
4892 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
4893 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
4894 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
4895 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
4896 #define RTC_DR_WDU ((uint32_t)0x0000E000)
4897 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
4898 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
4899 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
4900 #define RTC_DR_MT ((uint32_t)0x00001000)
4901 #define RTC_DR_MU ((uint32_t)0x00000F00)
4902 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
4903 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
4904 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
4905 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
4906 #define RTC_DR_DT ((uint32_t)0x00000030)
4907 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
4908 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
4909 #define RTC_DR_DU ((uint32_t)0x0000000F)
4910 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
4911 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
4912 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
4913 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
4914
4915 /******************** Bits definition for RTC_CR register *******************/
4916 #define RTC_CR_COE ((uint32_t)0x00800000)
4917 #define RTC_CR_OSEL ((uint32_t)0x00600000)
4918 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
4919 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
4920 #define RTC_CR_POL ((uint32_t)0x00100000)
4921 #define RTC_CR_COSEL ((uint32_t)0x00080000)
4922 #define RTC_CR_BCK ((uint32_t)0x00040000)
4923 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
4924 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
4925 #define RTC_CR_TSIE ((uint32_t)0x00008000)
4926 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
4927 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
4928 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
4929 #define RTC_CR_TSE ((uint32_t)0x00000800)
4930 #define RTC_CR_WUTE ((uint32_t)0x00000400)
4931 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
4932 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
4933 #define RTC_CR_FMT ((uint32_t)0x00000040)
4934 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
4935 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
4936 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
4937 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
4938 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
4939 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
4940 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
4941
4942 /******************** Bits definition for RTC_ISR register ******************/
4943 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
4944 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
4945 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
4946 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
4947 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
4948 #define RTC_ISR_TSF ((uint32_t)0x00000800)
4949 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
4950 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
4951 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
4952 #define RTC_ISR_INIT ((uint32_t)0x00000080)
4953 #define RTC_ISR_INITF ((uint32_t)0x00000040)
4954 #define RTC_ISR_RSF ((uint32_t)0x00000020)
4955 #define RTC_ISR_INITS ((uint32_t)0x00000010)
4956 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
4957 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
4958 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
4959 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
4960
4961 /******************** Bits definition for RTC_PRER register *****************/
4962 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
4963 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
4964
4965 /******************** Bits definition for RTC_WUTR register *****************/
4966 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
4967
4968 /******************** Bits definition for RTC_ALRMAR register ***************/
4969 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
4970 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
4971 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
4972 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
4973 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
4974 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
4975 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
4976 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
4977 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
4978 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
4979 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
4980 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
4981 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
4982 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
4983 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
4984 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
4985 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
4986 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
4987 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
4988 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
4989 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
4990 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
4991 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
4992 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
4993 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
4994 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
4995 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
4996 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
4997 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
4998 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
4999 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
5000 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
5001 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
5002 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
5003 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
5004 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
5005 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
5006 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
5007 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
5008 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
5009
5010 /******************** Bits definition for RTC_ALRMBR register ***************/
5011 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
5012 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
5013 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
5014 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
5015 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
5016 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
5017 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
5018 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
5019 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
5020 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
5021 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
5022 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
5023 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
5024 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
5025 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
5026 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
5027 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
5028 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
5029 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
5030 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
5031 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
5032 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
5033 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
5034 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
5035 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
5036 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
5037 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
5038 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
5039 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
5040 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
5041 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
5042 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
5043 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
5044 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
5045 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
5046 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
5047 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
5048 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
5049 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
5050 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
5051
5052 /******************** Bits definition for RTC_WPR register ******************/
5053 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
5054
5055 /******************** Bits definition for RTC_SSR register ******************/
5056 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
5057
5058 /******************** Bits definition for RTC_SHIFTR register ***************/
5059 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
5060 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
5061
5062 /******************** Bits definition for RTC_TSTR register *****************/
5063 #define RTC_TSTR_PM ((uint32_t)0x00400000)
5064 #define RTC_TSTR_HT ((uint32_t)0x00300000)
5065 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
5066 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
5067 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
5068 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
5069 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
5070 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
5071 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
5072 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
5073 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
5074 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
5075 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
5076 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
5077 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
5078 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
5079 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
5080 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
5081 #define RTC_TSTR_ST ((uint32_t)0x00000070)
5082 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
5083 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
5084 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
5085 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
5086 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
5087 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
5088 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
5089 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
5090
5091 /******************** Bits definition for RTC_TSDR register *****************/
5092 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
5093 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
5094 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
5095 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
5096 #define RTC_TSDR_MT ((uint32_t)0x00001000)
5097 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
5098 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
5099 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
5100 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
5101 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
5102 #define RTC_TSDR_DT ((uint32_t)0x00000030)
5103 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
5104 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
5105 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
5106 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
5107 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
5108 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
5109 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
5110
5111 /******************** Bits definition for RTC_TSSSR register ****************/
5112 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
5113
5114 /******************** Bits definition for RTC_CAL register *****************/
5115 #define RTC_CALR_CALP ((uint32_t)0x00008000)
5116 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
5117 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
5118 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
5119 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
5120 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
5121 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
5122 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
5123 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
5124 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
5125 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
5126 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
5127 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
5128
5129 /******************** Bits definition for RTC_TAFCR register ****************/
5130 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
5131 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
5132 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
5133 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
5134 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
5135 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
5136 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
5137 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
5138 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
5139 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
5140 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
5141 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
5142 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
5143 #define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
5144 #define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
5145 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
5146 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
5147 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
5148 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
5149 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
5150
5151 /******************** Bits definition for RTC_ALRMASSR register *************/
5152 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
5153 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
5154 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
5155 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
5156 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
5157 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
5158
5159 /******************** Bits definition for RTC_ALRMBSSR register *************/
5160 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
5161 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
5162 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
5163 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
5164 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
5165 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
5166
5167 /******************** Bits definition for RTC_BKP0R register ****************/
5168 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
5169
5170 /******************** Bits definition for RTC_BKP1R register ****************/
5171 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
5172
5173 /******************** Bits definition for RTC_BKP2R register ****************/
5174 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
5175
5176 /******************** Bits definition for RTC_BKP3R register ****************/
5177 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
5178
5179 /******************** Bits definition for RTC_BKP4R register ****************/
5180 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
5181
5182 /******************** Bits definition for RTC_BKP5R register ****************/
5183 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
5184
5185 /******************** Bits definition for RTC_BKP6R register ****************/
5186 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
5187
5188 /******************** Bits definition for RTC_BKP7R register ****************/
5189 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
5190
5191 /******************** Bits definition for RTC_BKP8R register ****************/
5192 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
5193
5194 /******************** Bits definition for RTC_BKP9R register ****************/
5195 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
5196
5197 /******************** Bits definition for RTC_BKP10R register ***************/
5198 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
5199
5200 /******************** Bits definition for RTC_BKP11R register ***************/
5201 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
5202
5203 /******************** Bits definition for RTC_BKP12R register ***************/
5204 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
5205
5206 /******************** Bits definition for RTC_BKP13R register ***************/
5207 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
5208
5209 /******************** Bits definition for RTC_BKP14R register ***************/
5210 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
5211
5212 /******************** Bits definition for RTC_BKP15R register ***************/
5213 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
5214
5215 /******************** Number of backup registers ******************************/
5216 #define RTC_BKP_NUMBER ((uint32_t)0x00000010)
5217
5218 /******************************************************************************/
5219 /* */
5220 /* Serial Peripheral Interface (SPI) */
5221 /* */
5222 /******************************************************************************/
5223 /******************* Bit definition for SPI_CR1 register ********************/
5224 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
5225 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
5226 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
5227 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
5228 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
5229 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
5230 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
5231 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
5232 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
5233 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
5234 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
5235 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
5236 #define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
5237 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
5238 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
5239 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
5240 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
5241
5242 /******************* Bit definition for SPI_CR2 register ********************/
5243 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
5244 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
5245 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
5246 #define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
5247 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
5248 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
5249 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
5250 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
5251 #define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
5252 #define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
5253 #define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
5254 #define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
5255 #define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
5256 #define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
5257 #define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
5258 #define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
5259
5260 /******************** Bit definition for SPI_SR register ********************/
5261 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
5262 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
5263 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
5264 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
5265 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
5266 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
5267 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
5268 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
5269 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
5270 #define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
5271 #define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
5272 #define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
5273 #define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
5274 #define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
5275 #define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
5276
5277 /******************** Bit definition for SPI_DR register ********************/
5278 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!< Data Register */
5279
5280 /******************* Bit definition for SPI_CRCPR register ******************/
5281 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!< CRC polynomial register */
5282
5283 /****************** Bit definition for SPI_RXCRCR register ******************/
5284 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!< Rx CRC Register */
5285
5286 /****************** Bit definition for SPI_TXCRCR register ******************/
5287 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!< Tx CRC Register */
5288
5289 /****************** Bit definition for SPI_I2SCFGR register *****************/
5290 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
5291 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
5292 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
5293 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
5294 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
5295 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
5296 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5297 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5298 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
5299 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
5300 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5301 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5302 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
5303 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
5304
5305 /****************** Bit definition for SPI_I2SPR register *******************/
5306 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
5307 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
5308 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
5309
5310 /******************************************************************************/
5311 /* */
5312 /* System Configuration(SYSCFG) */
5313 /* */
5314 /******************************************************************************/
5315 /***************** Bit definition for SYSCFG_CFGR1 register *****************/
5316 #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
5317 #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
5318 #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
5319 #define SYSCFG_CFGR1_USB_IT_RMP ((uint32_t)0x00000020) /*!< USB interrupt remap */
5320 #define SYSCFG_CFGR1_TIM1_ITR3_RMP ((uint32_t)0x00000040) /*!< Timer 1 ITR3 selection */
5321 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP ((uint32_t)0x00000080) /*!< DAC1 Trigger1 remap */
5322 #define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00007900) /*!< DMA remap mask */
5323 #define SYSCFG_CFGR1_ADC24_DMA_RMP ((uint32_t)0x00000100) /*!< ADC2 and ADC4 DMA remap */
5324 #define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
5325 #define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
5326 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */
5327 #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 CH2 DMA remap */
5328 #define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
5329 #define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
5330 #define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
5331 #define SYSCFG_CFGR1_I2C_PB9_FMP ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
5332 #define SYSCFG_CFGR1_I2C1_FMP ((uint32_t)0x00100000) /*!< I2C1 Fast mode plus */
5333 #define SYSCFG_CFGR1_I2C2_FMP ((uint32_t)0x00200000) /*!< I2C2 Fast mode plus */
5334 #define SYSCFG_CFGR1_ENCODER_MODE ((uint32_t)0x00C00000) /*!< Encoder Mode */
5335 #define SYSCFG_CFGR1_ENCODER_MODE_0 ((uint32_t)0x00400000) /*!< Encoder Mode 0 */
5336 #define SYSCFG_CFGR1_ENCODER_MODE_1 ((uint32_t)0x00800000) /*!< Encoder Mode 1 */
5337 #define SYSCFG_CFGR1_FPU_IE ((uint32_t)0xFC000000) /*!< Floating Point Unit Interrupt Enable */
5338 #define SYSCFG_CFGR1_FPU_IE_0 ((uint32_t)0x04000000) /*!< Floating Point Unit Interrupt Enable 0 */
5339 #define SYSCFG_CFGR1_FPU_IE_1 ((uint32_t)0x08000000) /*!< Floating Point Unit Interrupt Enable 1 */
5340 #define SYSCFG_CFGR1_FPU_IE_2 ((uint32_t)0x10000000) /*!< Floating Point Unit Interrupt Enable 2 */
5341 #define SYSCFG_CFGR1_FPU_IE_3 ((uint32_t)0x20000000) /*!< Floating Point Unit Interrupt Enable 3 */
5342 #define SYSCFG_CFGR1_FPU_IE_4 ((uint32_t)0x40000000) /*!< Floating Point Unit Interrupt Enable 4 */
5343 #define SYSCFG_CFGR1_FPU_IE_5 ((uint32_t)0x80000000) /*!< Floating Point Unit Interrupt Enable 5 */
5344
5345 /***************** Bit definition for SYSCFG_RCR register *******************/
5346 #define SYSCFG_RCR_PAGE0 ((uint32_t)0x00000001) /*!< ICODE SRAM Write protection page 0 */
5347 #define SYSCFG_RCR_PAGE1 ((uint32_t)0x00000002) /*!< ICODE SRAM Write protection page 1 */
5348 #define SYSCFG_RCR_PAGE2 ((uint32_t)0x00000004) /*!< ICODE SRAM Write protection page 2 */
5349 #define SYSCFG_RCR_PAGE3 ((uint32_t)0x00000008) /*!< ICODE SRAM Write protection page 3 */
5350 #define SYSCFG_RCR_PAGE4 ((uint32_t)0x00000010) /*!< ICODE SRAM Write protection page 4 */
5351 #define SYSCFG_RCR_PAGE5 ((uint32_t)0x00000020) /*!< ICODE SRAM Write protection page 5 */
5352 #define SYSCFG_RCR_PAGE6 ((uint32_t)0x00000040) /*!< ICODE SRAM Write protection page 6 */
5353 #define SYSCFG_RCR_PAGE7 ((uint32_t)0x00000080) /*!< ICODE SRAM Write protection page 7 */
5354
5355 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
5356 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
5357 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
5358 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
5359 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
5360
5361 /*!<*
5362 * @brief EXTI0 configuration
5363 */
5364 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
5365 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
5366 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
5367 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
5368 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */
5369 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
5370
5371 /*!<*
5372 * @brief EXTI1 configuration
5373 */
5374 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
5375 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
5376 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
5377 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
5378 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */
5379 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
5380
5381 /*!<*
5382 * @brief EXTI2 configuration
5383 */
5384 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
5385 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
5386 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
5387 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
5388 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */
5389 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
5390
5391 /*!<*
5392 * @brief EXTI3 configuration
5393 */
5394 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
5395 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
5396 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
5397 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
5398 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */
5399
5400 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
5401 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
5402 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
5403 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
5404 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
5405
5406 /*!<*
5407 * @brief EXTI4 configuration
5408 */
5409 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
5410 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
5411 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
5412 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
5413 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */
5414 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
5415
5416 /*!<*
5417 * @brief EXTI5 configuration
5418 */
5419 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
5420 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
5421 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
5422 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
5423 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */
5424 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
5425
5426 /*!<*
5427 * @brief EXTI6 configuration
5428 */
5429 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
5430 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
5431 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
5432 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
5433 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */
5434 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
5435
5436 /*!<*
5437 * @brief EXTI7 configuration
5438 */
5439 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
5440 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
5441 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
5442 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
5443 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
5444
5445 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
5446 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
5447 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
5448 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
5449 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
5450
5451 /*!<*
5452 * @brief EXTI8 configuration
5453 */
5454 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
5455 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
5456 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
5457 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
5458 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */
5459
5460 /*!<*
5461 * @brief EXTI9 configuration
5462 */
5463 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
5464 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
5465 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
5466 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
5467 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */
5468 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
5469
5470 /*!<*
5471 * @brief EXTI10 configuration
5472 */
5473 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
5474 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
5475 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
5476 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
5477 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PE[10] pin */
5478 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
5479
5480 /*!<*
5481 * @brief EXTI11 configuration
5482 */
5483 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
5484 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
5485 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
5486 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
5487 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */
5488
5489 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
5490 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
5491 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
5492 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
5493 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
5494
5495 /*!<*
5496 * @brief EXTI12 configuration
5497 */
5498 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
5499 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
5500 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
5501 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
5502 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */
5503
5504 /*!<*
5505 * @brief EXTI13 configuration
5506 */
5507 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
5508 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
5509 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
5510 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
5511 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */
5512
5513 /*!<*
5514 * @brief EXTI14 configuration
5515 */
5516 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
5517 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
5518 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
5519 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
5520 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */
5521
5522 /*!<*
5523 * @brief EXTI15 configuration
5524 */
5525 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
5526 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
5527 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
5528 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
5529 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
5530
5531 /***************** Bit definition for SYSCFG_CFGR2 register *****************/
5532 #define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM1/8/15/16/17 */
5533 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */
5534 #define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
5535 #define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /*!< Disables the adddress parity check on RAM */
5536 #define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
5537
5538 /******************************************************************************/
5539 /* */
5540 /* TIM */
5541 /* */
5542 /******************************************************************************/
5543 /******************* Bit definition for TIM_CR1 register ********************/
5544 #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
5545 #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
5546 #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
5547 #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
5548 #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
5549
5550 #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
5551 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
5552 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
5553
5554 #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
5555
5556 #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
5557 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5558 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5559
5560 #define TIM_CR1_UIFREMAP ((uint32_t)0x00000800) /*!<Update interrupt flag remap */
5561
5562 /******************* Bit definition for TIM_CR2 register ********************/
5563 #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
5564 #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
5565 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
5566
5567 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
5568 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5569 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5570 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
5571
5572 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
5573 #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
5574 #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
5575 #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
5576 #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
5577 #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
5578 #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
5579 #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
5580 #define TIM_CR2_OIS5 ((uint32_t)0x00010000) /*!<Output Idle state 4 (OC4 output) */
5581 #define TIM_CR2_OIS6 ((uint32_t)0x00040000) /*!<Output Idle state 4 (OC4 output) */
5582
5583 #define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /*!<MMS[2:0] bits (Master Mode Selection) */
5584 #define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
5585 #define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
5586 #define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
5587 #define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /*!<Bit 2 */
5588
5589 /******************* Bit definition for TIM_SMCR register *******************/
5590 #define TIM_SMCR_SMS ((uint32_t)0x00010007) /*!<SMS[2:0] bits (Slave mode selection) */
5591 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5592 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5593 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5594 #define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /*!<Bit 3 */
5595
5596 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
5597
5598 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
5599 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5600 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5601 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
5602
5603 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
5604
5605 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
5606 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5607 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5608 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5609 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5610
5611 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
5612 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
5613 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
5614
5615 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
5616 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
5617
5618 /******************* Bit definition for TIM_DIER register *******************/
5619 #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
5620 #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
5621 #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
5622 #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
5623 #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
5624 #define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
5625 #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
5626 #define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
5627 #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
5628 #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
5629 #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
5630 #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
5631 #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
5632 #define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
5633 #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
5634
5635 /******************** Bit definition for TIM_SR register ********************/
5636 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
5637 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
5638 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
5639 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
5640 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
5641 #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
5642 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
5643 #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
5644 #define TIM_SR_B2IF ((uint32_t)0x00000100) /*!<Break2 interrupt Flag */
5645 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
5646 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
5647 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
5648 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
5649 #define TIM_SR_CC5IF ((uint32_t)0x00010000) /*!<Capture/Compare 5 interrupt Flag */
5650 #define TIM_SR_CC6IF ((uint32_t)0x00020000) /*!<Capture/Compare 6 interrupt Flag */
5651
5652 /******************* Bit definition for TIM_EGR register ********************/
5653 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
5654 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
5655 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
5656 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
5657 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
5658 #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
5659 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
5660 #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
5661 #define TIM_EGR_B2G ((uint32_t)0x00000100) /*!<Break Generation */
5662
5663 /****************** Bit definition for TIM_CCMR1 register *******************/
5664 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
5665 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5666 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5667
5668 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
5669 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
5670
5671 #define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
5672 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5673 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5674 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
5675 #define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
5676
5677 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
5678
5679 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
5680 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5681 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5682
5683 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
5684 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
5685
5686 #define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
5687 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
5688 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
5689 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
5690 #define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
5691
5692 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
5693
5694 /*----------------------------------------------------------------------------*/
5695
5696 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
5697 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
5698 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
5699
5700 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
5701 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5702 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5703 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
5704 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
5705
5706 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
5707 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
5708 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
5709
5710 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
5711 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
5712 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
5713 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
5714 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
5715
5716 /****************** Bit definition for TIM_CCMR2 register *******************/
5717 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
5718 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5719 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5720
5721 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
5722 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
5723
5724 #define TIM_CCMR2_OC3M ((uint32_t)0x00010070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
5725 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5726 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5727 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
5728 #define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
5729
5730 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
5731
5732 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
5733 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5734 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5735
5736 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
5737 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
5738
5739 #define TIM_CCMR2_OC4M ((uint32_t)0x01007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
5740 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
5741 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
5742 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
5743 #define TIM_CCMR2_OC4M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
5744
5745 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
5746
5747 /*----------------------------------------------------------------------------*/
5748
5749 #define TIM_CCMR2_IC3PSC ((uint32_t)0x00000000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
5750 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x000000000004) /*!<Bit 0 */
5751 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x000000000008) /*!<Bit 1 */
5752
5753 #define TIM_CCMR2_IC3F ((uint32_t)0x0000000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
5754 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x000000000010) /*!<Bit 0 */
5755 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x000000000020) /*!<Bit 1 */
5756 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x000000000040) /*!<Bit 2 */
5757 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x000000000080) /*!<Bit 3 */
5758
5759 #define TIM_CCMR2_IC4PSC ((uint32_t)0x000000000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
5760 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x000000000400) /*!<Bit 0 */
5761 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x000000000800) /*!<Bit 1 */
5762
5763 #define TIM_CCMR2_IC4F ((uint32_t)0x00000000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
5764 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x000000001000) /*!<Bit 0 */
5765 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x000000002000) /*!<Bit 1 */
5766 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x000000004000) /*!<Bit 2 */
5767 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x000000008000) /*!<Bit 3 */
5768
5769 /******************* Bit definition for TIM_CCER register *******************/
5770 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
5771 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
5772 #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
5773 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
5774 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
5775 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
5776 #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
5777 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
5778 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
5779 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
5780 #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
5781 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
5782 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
5783 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
5784 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
5785 #define TIM_CCER_CC5E ((uint32_t)0x00010000) /*!<Capture/Compare 5 output enable */
5786 #define TIM_CCER_CC5P ((uint32_t)0x00020000) /*!<Capture/Compare 5 output Polarity */
5787 #define TIM_CCER_CC6E ((uint32_t)0x00100000) /*!<Capture/Compare 6 output enable */
5788 #define TIM_CCER_CC6P ((uint32_t)0x00200000) /*!<Capture/Compare 6 output Polarity */
5789
5790 /******************* Bit definition for TIM_CNT register ********************/
5791 #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
5792 #define TIM_CNT_UIFCPY ((uint32_t)0x80000000) /*!<Update interrupt flag copy */
5793
5794 /******************* Bit definition for TIM_PSC register ********************/
5795 #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
5796
5797 /******************* Bit definition for TIM_ARR register ********************/
5798 #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
5799
5800 /******************* Bit definition for TIM_RCR register ********************/
5801 #define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
5802
5803 /******************* Bit definition for TIM_CCR1 register *******************/
5804 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
5805
5806 /******************* Bit definition for TIM_CCR2 register *******************/
5807 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
5808
5809 /******************* Bit definition for TIM_CCR3 register *******************/
5810 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
5811
5812 /******************* Bit definition for TIM_CCR4 register *******************/
5813 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
5814
5815 /******************* Bit definition for TIM_CCR5 register *******************/
5816 #define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /*!<Capture/Compare 5 Value */
5817 #define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /*!<Group Channel 5 and Channel 1 */
5818 #define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /*!<Group Channel 5 and Channel 2 */
5819 #define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /*!<Group Channel 5 and Channel 3 */
5820
5821 /******************* Bit definition for TIM_CCR6 register *******************/
5822 #define TIM_CCR6_CCR6 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 6 Value */
5823
5824 /******************* Bit definition for TIM_BDTR register *******************/
5825 #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
5826 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5827 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5828 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5829 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5830 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
5831 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
5832 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
5833 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
5834
5835 #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
5836 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5837 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5838
5839 #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
5840 #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
5841 #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable for Break1 */
5842 #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity for Break1 */
5843 #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
5844 #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
5845
5846 #define TIM_BDTR_BKF ((uint32_t)0x000F0000) /*!<Break Filter for Break1 */
5847 #define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /*!<Break Filter for Break2 */
5848
5849 #define TIM_BDTR_BK2E ((uint32_t)0x01000000) /*!<Break enable for Break2 */
5850 #define TIM_BDTR_BK2P ((uint32_t)0x02000000) /*!<Break Polarity for Break2 */
5851
5852 /******************* Bit definition for TIM_DCR register ********************/
5853 #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
5854 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5855 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5856 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5857 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5858 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
5859
5860 #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
5861 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5862 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5863 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5864 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5865 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
5866
5867 /******************* Bit definition for TIM_DMAR register *******************/
5868 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
5869
5870 /******************* Bit definition for TIM16_OR register *********************/
5871 #define TIM16_OR_TI1_RMP ((uint32_t)0x000000C0) /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */
5872 #define TIM16_OR_TI1_RMP_0 ((uint32_t)0x00000040) /*!<Bit 0 */
5873 #define TIM16_OR_TI1_RMP_1 ((uint32_t)0x00000080) /*!<Bit 1 */
5874
5875 /******************* Bit definition for TIM1_OR register *********************/
5876 #define TIM1_OR_ETR_RMP ((uint32_t)0x0000000F) /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */
5877 #define TIM1_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5878 #define TIM1_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5879 #define TIM1_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5880 #define TIM1_OR_ETR_RMP_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5881
5882 /******************* Bit definition for TIM8_OR register *********************/
5883 #define TIM8_OR_ETR_RMP ((uint32_t)0x0000000F) /*!<ETR_RMP[3:0] bits (TIM8 ETR remap) */
5884 #define TIM8_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5885 #define TIM8_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5886 #define TIM8_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5887 #define TIM8_OR_ETR_RMP_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5888
5889 /****************** Bit definition for TIM_CCMR3 register *******************/
5890 #define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /*!<Output Compare 5 Fast enable */
5891 #define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /*!<Output Compare 5 Preload enable */
5892
5893 #define TIM_CCMR3_OC5M ((uint32_t)0x00010070) /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
5894 #define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5895 #define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5896 #define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
5897 #define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
5898
5899 #define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /*!<Output Compare 5 Clear Enable */
5900
5901 #define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /*!<Output Compare 6 Fast enable */
5902 #define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /*!<Output Compare 6 Preload enable */
5903
5904 #define TIM_CCMR3_OC6M ((uint32_t)0x01007000) /*!<OC6M[2:0] bits (Output Compare 6 Mode) */
5905 #define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
5906 #define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
5907 #define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
5908 #define TIM_CCMR3_OC6M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
5909
5910 #define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /*!<Output Compare 6 Clear Enable */
5911
5912 /******************************************************************************/
5913 /* */
5914 /* Touch Sensing Controller (TSC) */
5915 /* */
5916 /******************************************************************************/
5917 /******************* Bit definition for TSC_CR register *********************/
5918 #define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */
5919 #define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */
5920 #define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */
5921 #define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */
5922 #define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */
5923
5924 #define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */
5925 #define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */
5926 #define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */
5927 #define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */
5928
5929 #define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
5930 #define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
5931 #define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
5932 #define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
5933
5934 #define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */
5935 #define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */
5936
5937 #define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
5938 #define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
5939 #define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
5940 #define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */
5941 #define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */
5942 #define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */
5943 #define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */
5944 #define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */
5945
5946 #define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
5947 #define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5948 #define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5949 #define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
5950 #define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
5951
5952 #define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
5953 #define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */
5954 #define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */
5955 #define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */
5956 #define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */
5957
5958 /******************* Bit definition for TSC_IER register ********************/
5959 #define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */
5960 #define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */
5961
5962 /******************* Bit definition for TSC_ICR register ********************/
5963 #define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */
5964 #define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */
5965
5966 /******************* Bit definition for TSC_ISR register ********************/
5967 #define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */
5968 #define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */
5969
5970 /******************* Bit definition for TSC_IOHCR register ******************/
5971 #define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
5972 #define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
5973 #define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
5974 #define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
5975 #define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
5976 #define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
5977 #define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
5978 #define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
5979 #define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
5980 #define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
5981 #define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
5982 #define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
5983 #define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
5984 #define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
5985 #define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
5986 #define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
5987 #define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
5988 #define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
5989 #define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
5990 #define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
5991 #define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
5992 #define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
5993 #define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
5994 #define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
5995 #define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
5996 #define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
5997 #define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
5998 #define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
5999 #define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
6000 #define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
6001 #define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
6002 #define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
6003
6004 /******************* Bit definition for TSC_IOASCR register *****************/
6005 #define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */
6006 #define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */
6007 #define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */
6008 #define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */
6009 #define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */
6010 #define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */
6011 #define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */
6012 #define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */
6013 #define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */
6014 #define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */
6015 #define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */
6016 #define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */
6017 #define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */
6018 #define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */
6019 #define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */
6020 #define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */
6021 #define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */
6022 #define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */
6023 #define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */
6024 #define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */
6025 #define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */
6026 #define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */
6027 #define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */
6028 #define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */
6029 #define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */
6030 #define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */
6031 #define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */
6032 #define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */
6033 #define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */
6034 #define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */
6035 #define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */
6036 #define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */
6037
6038 /******************* Bit definition for TSC_IOSCR register ******************/
6039 #define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */
6040 #define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */
6041 #define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */
6042 #define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */
6043 #define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */
6044 #define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */
6045 #define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */
6046 #define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */
6047 #define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */
6048 #define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */
6049 #define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */
6050 #define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */
6051 #define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */
6052 #define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */
6053 #define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */
6054 #define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */
6055 #define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */
6056 #define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */
6057 #define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */
6058 #define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */
6059 #define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */
6060 #define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */
6061 #define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */
6062 #define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */
6063 #define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */
6064 #define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */
6065 #define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */
6066 #define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */
6067 #define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */
6068 #define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */
6069 #define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */
6070 #define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */
6071
6072 /******************* Bit definition for TSC_IOCCR register ******************/
6073 #define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */
6074 #define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */
6075 #define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */
6076 #define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */
6077 #define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */
6078 #define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */
6079 #define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */
6080 #define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */
6081 #define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */
6082 #define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */
6083 #define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */
6084 #define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */
6085 #define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */
6086 #define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */
6087 #define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */
6088 #define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */
6089 #define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */
6090 #define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */
6091 #define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */
6092 #define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */
6093 #define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */
6094 #define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */
6095 #define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */
6096 #define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */
6097 #define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */
6098 #define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */
6099 #define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */
6100 #define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */
6101 #define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */
6102 #define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */
6103 #define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */
6104 #define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */
6105
6106 /******************* Bit definition for TSC_IOGCSR register *****************/
6107 #define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */
6108 #define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */
6109 #define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */
6110 #define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */
6111 #define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */
6112 #define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */
6113 #define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */
6114 #define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */
6115 #define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */
6116 #define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */
6117 #define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */
6118 #define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */
6119 #define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */
6120 #define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */
6121 #define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */
6122 #define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */
6123
6124 /******************* Bit definition for TSC_IOGXCR register *****************/
6125 #define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */
6126
6127 /******************************************************************************/
6128 /* */
6129 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
6130 /* */
6131 /******************************************************************************/
6132 /****************** Bit definition for USART_CR1 register *******************/
6133 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
6134 #define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
6135 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
6136 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
6137 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
6138 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
6139 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
6140 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
6141 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
6142 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
6143 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
6144 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
6145 #define USART_CR1_M ((uint32_t)0x00001000) /*!< Word length */
6146 #define USART_CR1_M0 ((uint32_t)0x00001000) /*!< SmartCard Word length */
6147 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
6148 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
6149 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
6150 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
6151 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
6152 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
6153 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
6154 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
6155 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
6156 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
6157 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
6158 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
6159 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
6160 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
6161 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
6162 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
6163 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
6164
6165 /****************** Bit definition for USART_CR2 register *******************/
6166 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
6167 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
6168 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
6169 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
6170 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
6171 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
6172 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
6173 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
6174 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
6175 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
6176 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
6177 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
6178 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
6179 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
6180 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
6181 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
6182 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
6183 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
6184 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
6185 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
6186 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
6187 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
6188
6189 /****************** Bit definition for USART_CR3 register *******************/
6190 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
6191 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
6192 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
6193 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
6194 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
6195 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
6196 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
6197 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
6198 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
6199 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
6200 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
6201 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
6202 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
6203 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
6204 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
6205 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
6206 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
6207 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
6208 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
6209 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
6210 #define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
6211 #define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
6212 #define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
6213 #define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
6214
6215 /****************** Bit definition for USART_BRR register *******************/
6216 #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
6217 #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
6218
6219 /****************** Bit definition for USART_GTPR register ******************/
6220 #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
6221 #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
6222
6223
6224 /******************* Bit definition for USART_RTOR register *****************/
6225 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
6226 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
6227
6228 /******************* Bit definition for USART_RQR register ******************/
6229 #define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
6230 #define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
6231 #define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
6232 #define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
6233 #define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
6234
6235 /******************* Bit definition for USART_ISR register ******************/
6236 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
6237 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
6238 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
6239 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
6240 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
6241 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
6242 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
6243 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
6244 #define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
6245 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
6246 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
6247 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
6248 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
6249 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
6250 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
6251 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
6252 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
6253 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
6254 #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
6255 #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
6256 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
6257 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
6258
6259 /******************* Bit definition for USART_ICR register ******************/
6260 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
6261 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
6262 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
6263 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
6264 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
6265 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
6266 #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
6267 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
6268 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
6269 #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
6270 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
6271 #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
6272
6273 /******************* Bit definition for USART_RDR register ******************/
6274 #define USART_RDR_RDR ((uint32_t)0x000001FF) /*!< RDR[8:0] bits (Receive Data value) */
6275
6276 /******************* Bit definition for USART_TDR register ******************/
6277 #define USART_TDR_TDR ((uint32_t)0x000001FF) /*!< TDR[8:0] bits (Transmit Data value) */
6278
6279 /******************************************************************************/
6280 /* */
6281 /* USB Device General registers */
6282 /* */
6283 /******************************************************************************/
6284 #define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
6285 #define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
6286 #define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
6287 #define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
6288 #define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
6289
6290 /**************************** ISTR interrupt events *************************/
6291 #define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
6292 #define USB_ISTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
6293 #define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
6294 #define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
6295 #define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
6296 #define USB_ISTR_RESET ((uint16_t)0x0400) /*!< RESET (clear-only bit) */
6297 #define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame (clear-only bit) */
6298 #define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame (clear-only bit) */
6299 #define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
6300 #define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
6301
6302 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
6303 #define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
6304 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
6305 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
6306 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
6307 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
6308 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
6309 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
6310
6311 /************************* CNTR control register bits definitions ***********/
6312 #define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
6313 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
6314 #define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
6315 #define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
6316 #define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
6317 #define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Mask */
6318 #define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Mask */
6319 #define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Mask */
6320 #define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
6321 #define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
6322 #define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power MODE */
6323 #define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
6324 #define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
6325
6326 /******************** FNR Frame Number Register bit definitions ************/
6327 #define USB_FNR_RXDP ((uint16_t)0x8000) /*!< status of D+ data line */
6328 #define USB_FNR_RXDM ((uint16_t)0x4000) /*!< status of D- data line */
6329 #define USB_FNR_LCK ((uint16_t)0x2000) /*!< LoCKed */
6330 #define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */
6331 #define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */
6332
6333 /******************** DADDR Device ADDRess bit definitions ****************/
6334 #define USB_DADDR_EF ((uint8_t)0x80) /*!< USB device address Enable Function */
6335 #define USB_DADDR_ADD ((uint8_t)0x7F) /*!< USB device address */
6336
6337 /****************************** Endpoint register *************************/
6338 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
6339 #define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
6340 #define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
6341 #define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
6342 #define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
6343 #define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
6344 #define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
6345 #define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
6346 /* bit positions */
6347 #define USB_EP_CTR_RX ((uint16_t)0x8000) /*!< EndPoint Correct TRansfer RX */
6348 #define USB_EP_DTOG_RX ((uint16_t)0x4000) /*!< EndPoint Data TOGGLE RX */
6349 #define USB_EPRX_STAT ((uint16_t)0x3000) /*!< EndPoint RX STATus bit field */
6350 #define USB_EP_SETUP ((uint16_t)0x0800) /*!< EndPoint SETUP */
6351 #define USB_EP_T_FIELD ((uint16_t)0x0600) /*!< EndPoint TYPE */
6352 #define USB_EP_KIND ((uint16_t)0x0100) /*!< EndPoint KIND */
6353 #define USB_EP_CTR_TX ((uint16_t)0x0080) /*!< EndPoint Correct TRansfer TX */
6354 #define USB_EP_DTOG_TX ((uint16_t)0x0040) /*!< EndPoint Data TOGGLE TX */
6355 #define USB_EPTX_STAT ((uint16_t)0x0030) /*!< EndPoint TX STATus bit field */
6356 #define USB_EPADDR_FIELD ((uint16_t)0x000F) /*!< EndPoint ADDRess FIELD */
6357
6358 /* EndPoint REGister MASK (no toggle fields) */
6359 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
6360 /*!< EP_TYPE[1:0] EndPoint TYPE */
6361 #define USB_EP_TYPE_MASK ((uint16_t)0x0600) /*!< EndPoint TYPE Mask */
6362 #define USB_EP_BULK ((uint16_t)0x0000) /*!< EndPoint BULK */
6363 #define USB_EP_CONTROL ((uint16_t)0x0200) /*!< EndPoint CONTROL */
6364 #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400) /*!< EndPoint ISOCHRONOUS */
6365 #define USB_EP_INTERRUPT ((uint16_t)0x0600) /*!< EndPoint INTERRUPT */
6366 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
6367
6368 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
6369 /*!< STAT_TX[1:0] STATus for TX transfer */
6370 #define USB_EP_TX_DIS ((uint16_t)0x0000) /*!< EndPoint TX DISabled */
6371 #define USB_EP_TX_STALL ((uint16_t)0x0010) /*!< EndPoint TX STALLed */
6372 #define USB_EP_TX_NAK ((uint16_t)0x0020) /*!< EndPoint TX NAKed */
6373 #define USB_EP_TX_VALID ((uint16_t)0x0030) /*!< EndPoint TX VALID */
6374 #define USB_EPTX_DTOG1 ((uint16_t)0x0010) /*!< EndPoint TX Data TOGgle bit1 */
6375 #define USB_EPTX_DTOG2 ((uint16_t)0x0020) /*!< EndPoint TX Data TOGgle bit2 */
6376 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
6377 /*!< STAT_RX[1:0] STATus for RX transfer */
6378 #define USB_EP_RX_DIS ((uint16_t)0x0000) /*!< EndPoint RX DISabled */
6379 #define USB_EP_RX_STALL ((uint16_t)0x1000) /*!< EndPoint RX STALLed */
6380 #define USB_EP_RX_NAK ((uint16_t)0x2000) /*!< EndPoint RX NAKed */
6381 #define USB_EP_RX_VALID ((uint16_t)0x3000) /*!< EndPoint RX VALID */
6382 #define USB_EPRX_DTOG1 ((uint16_t)0x1000) /*!< EndPoint RX Data TOGgle bit1 */
6383 #define USB_EPRX_DTOG2 ((uint16_t)0x2000) /*!< EndPoint RX Data TOGgle bit1 */
6384 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
6385
6386 /******************************************************************************/
6387 /* */
6388 /* Window WATCHDOG */
6389 /* */
6390 /******************************************************************************/
6391 /******************* Bit definition for WWDG_CR register ********************/
6392 #define WWDG_CR_T ((uint32_t)0x0000007F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
6393 #define WWDG_CR_T0 ((uint32_t)0x00000001) /*!<Bit 0 */
6394 #define WWDG_CR_T1 ((uint32_t)0x00000002) /*!<Bit 1 */
6395 #define WWDG_CR_T2 ((uint32_t)0x00000004) /*!<Bit 2 */
6396 #define WWDG_CR_T3 ((uint32_t)0x00000008) /*!<Bit 3 */
6397 #define WWDG_CR_T4 ((uint32_t)0x00000010) /*!<Bit 4 */
6398 #define WWDG_CR_T5 ((uint32_t)0x00000020) /*!<Bit 5 */
6399 #define WWDG_CR_T6 ((uint32_t)0x00000040) /*!<Bit 6 */
6400
6401 #define WWDG_CR_WDGA ((uint32_t)0x00000080) /*!<Activation bit */
6402
6403 /******************* Bit definition for WWDG_CFR register *******************/
6404 #define WWDG_CFR_W ((uint32_t)0x0000007F) /*!<W[6:0] bits (7-bit window value) */
6405 #define WWDG_CFR_W0 ((uint32_t)0x00000001) /*!<Bit 0 */
6406 #define WWDG_CFR_W1 ((uint32_t)0x00000002) /*!<Bit 1 */
6407 #define WWDG_CFR_W2 ((uint32_t)0x00000004) /*!<Bit 2 */
6408 #define WWDG_CFR_W3 ((uint32_t)0x00000008) /*!<Bit 3 */
6409 #define WWDG_CFR_W4 ((uint32_t)0x00000010) /*!<Bit 4 */
6410 #define WWDG_CFR_W5 ((uint32_t)0x00000020) /*!<Bit 5 */
6411 #define WWDG_CFR_W6 ((uint32_t)0x00000040) /*!<Bit 6 */
6412
6413 #define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /*!<WDGTB[1:0] bits (Timer Base) */
6414 #define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /*!<Bit 0 */
6415 #define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /*!<Bit 1 */
6416
6417 #define WWDG_CFR_EWI ((uint32_t)0x00000200) /*!<Early Wakeup Interrupt */
6418
6419 /******************* Bit definition for WWDG_SR register ********************/
6420 #define WWDG_SR_EWIF ((uint32_t)0x00000001) /*!<Early Wakeup Interrupt Flag */
6421
6422 /**
6423 * @}
6424 */
6425
6426 /**
6427 * @}
6428 */
6429
6430 /** @addtogroup Exported_macros
6431 * @{
6432 */
6433
6434 /****************************** ADC Instances *********************************/
6435 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
6436 ((INSTANCE) == ADC2) || \
6437 ((INSTANCE) == ADC3) || \
6438 ((INSTANCE) == ADC4))
6439
6440 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
6441 ((INSTANCE) == ADC3))
6442
6443 #define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_2_COMMON) || \
6444 ((INSTANCE) == ADC3_4_COMMON))
6445
6446 /****************************** CAN Instances *********************************/
6447 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
6448
6449 /****************************** COMP Instances ********************************/
6450 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
6451 ((INSTANCE) == COMP2) || \
6452 ((INSTANCE) == COMP3) || \
6453 ((INSTANCE) == COMP4) || \
6454 ((INSTANCE) == COMP5) || \
6455 ((INSTANCE) == COMP6) || \
6456 ((INSTANCE) == COMP7))
6457
6458 /******************** COMP Instances with switch on DAC1 Channel1 output ******/
6459 #define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) ((INSTANCE) == COMP1)
6460
6461 /******************** COMP Instances with window mode capability **************/
6462 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP2) || \
6463 ((INSTANCE) == COMP4) || \
6464 ((INSTANCE) == COMP6))
6465
6466 /****************************** CRC Instances *********************************/
6467 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
6468
6469 /****************************** DAC Instances *********************************/
6470 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
6471
6472 #define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \
6473 (((INSTANCE) == DAC1) && \
6474 (((CHANNEL) == DAC_CHANNEL_1) || \
6475 ((CHANNEL) == DAC_CHANNEL_2)))
6476
6477 /****************************** DMA Instances *********************************/
6478 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
6479 ((INSTANCE) == DMA1_Channel2) || \
6480 ((INSTANCE) == DMA1_Channel3) || \
6481 ((INSTANCE) == DMA1_Channel4) || \
6482 ((INSTANCE) == DMA1_Channel5) || \
6483 ((INSTANCE) == DMA1_Channel6) || \
6484 ((INSTANCE) == DMA1_Channel7) || \
6485 ((INSTANCE) == DMA2_Channel1) || \
6486 ((INSTANCE) == DMA2_Channel2) || \
6487 ((INSTANCE) == DMA2_Channel3) || \
6488 ((INSTANCE) == DMA2_Channel4) || \
6489 ((INSTANCE) == DMA2_Channel5))
6490
6491 /****************************** GPIO Instances ********************************/
6492 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
6493 ((INSTANCE) == GPIOB) || \
6494 ((INSTANCE) == GPIOC) || \
6495 ((INSTANCE) == GPIOD) || \
6496 ((INSTANCE) == GPIOE) || \
6497 ((INSTANCE) == GPIOF))
6498
6499 /****************************** I2C Instances *********************************/
6500 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
6501 ((INSTANCE) == I2C2))
6502
6503 /****************************** I2S Instances *********************************/
6504 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
6505 ((INSTANCE) == SPI3))
6506
6507 /****************************** IWDG Instances ********************************/
6508 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
6509
6510 /****************************** OPAMP Instances *******************************/
6511 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
6512 ((INSTANCE) == OPAMP2) || \
6513 ((INSTANCE) == OPAMP3) || \
6514 ((INSTANCE) == OPAMP4))
6515
6516 /****************************** RTC Instances *********************************/
6517 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
6518
6519 /****************************** SMBUS Instances *******************************/
6520 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
6521 ((INSTANCE) == I2C2))
6522
6523 /****************************** SPI Instances *********************************/
6524 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
6525 ((INSTANCE) == SPI2) || \
6526 ((INSTANCE) == SPI3))
6527
6528 /******************* TIM Instances : All supported instances ******************/
6529 #define IS_TIM_INSTANCE(INSTANCE)\
6530 (((INSTANCE) == TIM1) || \
6531 ((INSTANCE) == TIM2) || \
6532 ((INSTANCE) == TIM3) || \
6533 ((INSTANCE) == TIM4) || \
6534 ((INSTANCE) == TIM6) || \
6535 ((INSTANCE) == TIM7) || \
6536 ((INSTANCE) == TIM8) || \
6537 ((INSTANCE) == TIM15) || \
6538 ((INSTANCE) == TIM16) || \
6539 ((INSTANCE) == TIM17))
6540
6541 /******************* TIM Instances : at least 1 capture/compare channel *******/
6542 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
6543 (((INSTANCE) == TIM1) || \
6544 ((INSTANCE) == TIM2) || \
6545 ((INSTANCE) == TIM3) || \
6546 ((INSTANCE) == TIM4) || \
6547 ((INSTANCE) == TIM8) || \
6548 ((INSTANCE) == TIM15) || \
6549 ((INSTANCE) == TIM16) || \
6550 ((INSTANCE) == TIM17))
6551
6552 /****************** TIM Instances : at least 2 capture/compare channels *******/
6553 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
6554 (((INSTANCE) == TIM1) || \
6555 ((INSTANCE) == TIM2) || \
6556 ((INSTANCE) == TIM3) || \
6557 ((INSTANCE) == TIM4) || \
6558 ((INSTANCE) == TIM8) || \
6559 ((INSTANCE) == TIM15))
6560
6561 /****************** TIM Instances : at least 3 capture/compare channels *******/
6562 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
6563 (((INSTANCE) == TIM1) || \
6564 ((INSTANCE) == TIM2) || \
6565 ((INSTANCE) == TIM3) || \
6566 ((INSTANCE) == TIM4) || \
6567 ((INSTANCE) == TIM8))
6568
6569 /****************** TIM Instances : at least 4 capture/compare channels *******/
6570 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
6571 (((INSTANCE) == TIM1) || \
6572 ((INSTANCE) == TIM2) || \
6573 ((INSTANCE) == TIM3) || \
6574 ((INSTANCE) == TIM4) || \
6575 ((INSTANCE) == TIM8))
6576
6577 /****************** TIM Instances : at least 5 capture/compare channels *******/
6578 #define IS_TIM_CC5_INSTANCE(INSTANCE)\
6579 (((INSTANCE) == TIM1) || \
6580 ((INSTANCE) == TIM8))
6581
6582 /****************** TIM Instances : at least 6 capture/compare channels *******/
6583 #define IS_TIM_CC6_INSTANCE(INSTANCE)\
6584 (((INSTANCE) == TIM1) || \
6585 ((INSTANCE) == TIM8))
6586
6587 /************************** TIM Instances : Advanced-control timers ***********/
6588
6589 /****************** TIM Instances : supporting clock selection ****************/
6590 #define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
6591 (((INSTANCE) == TIM1) || \
6592 ((INSTANCE) == TIM2) || \
6593 ((INSTANCE) == TIM3) || \
6594 ((INSTANCE) == TIM4) || \
6595 ((INSTANCE) == TIM8) || \
6596 ((INSTANCE) == TIM15))
6597
6598 /****************** TIM Instances : supporting external clock mode 1 for ETRF input */
6599 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
6600 (((INSTANCE) == TIM1) || \
6601 ((INSTANCE) == TIM2) || \
6602 ((INSTANCE) == TIM3) || \
6603 ((INSTANCE) == TIM4) || \
6604 ((INSTANCE) == TIM8))
6605
6606 /****************** TIM Instances : supporting external clock mode 2 **********/
6607 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
6608 (((INSTANCE) == TIM1) || \
6609 ((INSTANCE) == TIM2) || \
6610 ((INSTANCE) == TIM3) || \
6611 ((INSTANCE) == TIM4) || \
6612 ((INSTANCE) == TIM8))
6613
6614 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
6615 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
6616 (((INSTANCE) == TIM1) || \
6617 ((INSTANCE) == TIM2) || \
6618 ((INSTANCE) == TIM3) || \
6619 ((INSTANCE) == TIM4) || \
6620 ((INSTANCE) == TIM8) || \
6621 ((INSTANCE) == TIM15))
6622
6623 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
6624 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
6625 (((INSTANCE) == TIM1) || \
6626 ((INSTANCE) == TIM2) || \
6627 ((INSTANCE) == TIM3) || \
6628 ((INSTANCE) == TIM4) || \
6629 ((INSTANCE) == TIM8) || \
6630 ((INSTANCE) == TIM15))
6631
6632 /****************** TIM Instances : supporting OCxREF clear *******************/
6633 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
6634 (((INSTANCE) == TIM1) || \
6635 ((INSTANCE) == TIM2) || \
6636 ((INSTANCE) == TIM3) || \
6637 ((INSTANCE) == TIM4) || \
6638 ((INSTANCE) == TIM8))
6639
6640 /****************** TIM Instances : supporting encoder interface **************/
6641 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
6642 (((INSTANCE) == TIM1) || \
6643 ((INSTANCE) == TIM2) || \
6644 ((INSTANCE) == TIM3) || \
6645 ((INSTANCE) == TIM4) || \
6646 ((INSTANCE) == TIM8))
6647
6648 /****************** TIM Instances : supporting Hall interface *****************/
6649 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
6650 (((INSTANCE) == TIM1) || \
6651 ((INSTANCE) == TIM8))
6652
6653 /****************** TIM Instances : supporting input XOR function *************/
6654 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
6655 (((INSTANCE) == TIM1) || \
6656 ((INSTANCE) == TIM2) || \
6657 ((INSTANCE) == TIM3) || \
6658 ((INSTANCE) == TIM4) || \
6659 ((INSTANCE) == TIM8) || \
6660 ((INSTANCE) == TIM15))
6661
6662 /****************** TIM Instances : supporting master mode ********************/
6663 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
6664 (((INSTANCE) == TIM1) || \
6665 ((INSTANCE) == TIM2) || \
6666 ((INSTANCE) == TIM3) || \
6667 ((INSTANCE) == TIM4) || \
6668 ((INSTANCE) == TIM6) || \
6669 ((INSTANCE) == TIM7) || \
6670 ((INSTANCE) == TIM8) || \
6671 ((INSTANCE) == TIM15))
6672
6673 /****************** TIM Instances : supporting slave mode *********************/
6674 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
6675 (((INSTANCE) == TIM1) || \
6676 ((INSTANCE) == TIM2) || \
6677 ((INSTANCE) == TIM3) || \
6678 ((INSTANCE) == TIM4) || \
6679 ((INSTANCE) == TIM8) || \
6680 ((INSTANCE) == TIM15))
6681
6682 /****************** TIM Instances : supporting synchronization ****************/
6683 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\
6684 (((INSTANCE) == TIM1) || \
6685 ((INSTANCE) == TIM2) || \
6686 ((INSTANCE) == TIM3) || \
6687 ((INSTANCE) == TIM4) || \
6688 ((INSTANCE) == TIM6) || \
6689 ((INSTANCE) == TIM7) || \
6690 ((INSTANCE) == TIM8) || \
6691 ((INSTANCE) == TIM15))
6692
6693 /****************** TIM Instances : supporting 32 bits counter ****************/
6694 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
6695 ((INSTANCE) == TIM2)
6696
6697 /****************** TIM Instances : supporting DMA burst **********************/
6698 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
6699 (((INSTANCE) == TIM1) || \
6700 ((INSTANCE) == TIM2) || \
6701 ((INSTANCE) == TIM3) || \
6702 ((INSTANCE) == TIM4) || \
6703 ((INSTANCE) == TIM8) || \
6704 ((INSTANCE) == TIM15) || \
6705 ((INSTANCE) == TIM16) || \
6706 ((INSTANCE) == TIM17))
6707
6708 /****************** TIM Instances : supporting the break function *************/
6709 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
6710 (((INSTANCE) == TIM1) || \
6711 ((INSTANCE) == TIM8) || \
6712 ((INSTANCE) == TIM15) || \
6713 ((INSTANCE) == TIM16) || \
6714 ((INSTANCE) == TIM17))
6715
6716 /****************** TIM Instances : supporting input/output channel(s) ********/
6717 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
6718 ((((INSTANCE) == TIM1) && \
6719 (((CHANNEL) == TIM_CHANNEL_1) || \
6720 ((CHANNEL) == TIM_CHANNEL_2) || \
6721 ((CHANNEL) == TIM_CHANNEL_3) || \
6722 ((CHANNEL) == TIM_CHANNEL_4) || \
6723 ((CHANNEL) == TIM_CHANNEL_5) || \
6724 ((CHANNEL) == TIM_CHANNEL_6))) \
6725 || \
6726 (((INSTANCE) == TIM2) && \
6727 (((CHANNEL) == TIM_CHANNEL_1) || \
6728 ((CHANNEL) == TIM_CHANNEL_2) || \
6729 ((CHANNEL) == TIM_CHANNEL_3) || \
6730 ((CHANNEL) == TIM_CHANNEL_4))) \
6731 || \
6732 (((INSTANCE) == TIM3) && \
6733 (((CHANNEL) == TIM_CHANNEL_1) || \
6734 ((CHANNEL) == TIM_CHANNEL_2) || \
6735 ((CHANNEL) == TIM_CHANNEL_3) || \
6736 ((CHANNEL) == TIM_CHANNEL_4))) \
6737 || \
6738 (((INSTANCE) == TIM4) && \
6739 (((CHANNEL) == TIM_CHANNEL_1) || \
6740 ((CHANNEL) == TIM_CHANNEL_2) || \
6741 ((CHANNEL) == TIM_CHANNEL_3) || \
6742 ((CHANNEL) == TIM_CHANNEL_4))) \
6743 || \
6744 (((INSTANCE) == TIM8) && \
6745 (((CHANNEL) == TIM_CHANNEL_1) || \
6746 ((CHANNEL) == TIM_CHANNEL_2) || \
6747 ((CHANNEL) == TIM_CHANNEL_3) || \
6748 ((CHANNEL) == TIM_CHANNEL_4) || \
6749 ((CHANNEL) == TIM_CHANNEL_5) || \
6750 ((CHANNEL) == TIM_CHANNEL_6))) \
6751 || \
6752 (((INSTANCE) == TIM15) && \
6753 (((CHANNEL) == TIM_CHANNEL_1) || \
6754 ((CHANNEL) == TIM_CHANNEL_2))) \
6755 || \
6756 (((INSTANCE) == TIM16) && \
6757 (((CHANNEL) == TIM_CHANNEL_1))) \
6758 || \
6759 (((INSTANCE) == TIM17) && \
6760 (((CHANNEL) == TIM_CHANNEL_1))))
6761
6762 /****************** TIM Instances : supporting complementary output(s) ********/
6763 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
6764 ((((INSTANCE) == TIM1) && \
6765 (((CHANNEL) == TIM_CHANNEL_1) || \
6766 ((CHANNEL) == TIM_CHANNEL_2) || \
6767 ((CHANNEL) == TIM_CHANNEL_3))) \
6768 || \
6769 (((INSTANCE) == TIM8) && \
6770 (((CHANNEL) == TIM_CHANNEL_1) || \
6771 ((CHANNEL) == TIM_CHANNEL_2) || \
6772 ((CHANNEL) == TIM_CHANNEL_3))) \
6773 || \
6774 (((INSTANCE) == TIM15) && \
6775 ((CHANNEL) == TIM_CHANNEL_1)) \
6776 || \
6777 (((INSTANCE) == TIM16) && \
6778 ((CHANNEL) == TIM_CHANNEL_1)) \
6779 || \
6780 (((INSTANCE) == TIM17) && \
6781 ((CHANNEL) == TIM_CHANNEL_1)))
6782
6783 /****************** TIM Instances : supporting counting mode selection ********/
6784 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
6785 (((INSTANCE) == TIM1) || \
6786 ((INSTANCE) == TIM2) || \
6787 ((INSTANCE) == TIM3) || \
6788 ((INSTANCE) == TIM4) || \
6789 ((INSTANCE) == TIM8))
6790
6791 /****************** TIM Instances : supporting repetition counter *************/
6792 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
6793 (((INSTANCE) == TIM1) || \
6794 ((INSTANCE) == TIM8) || \
6795 ((INSTANCE) == TIM15) || \
6796 ((INSTANCE) == TIM16) || \
6797 ((INSTANCE) == TIM17))
6798
6799 /****************** TIM Instances : supporting clock division *****************/
6800 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
6801 (((INSTANCE) == TIM1) || \
6802 ((INSTANCE) == TIM2) || \
6803 ((INSTANCE) == TIM3) || \
6804 ((INSTANCE) == TIM4) || \
6805 ((INSTANCE) == TIM8) || \
6806 ((INSTANCE) == TIM15) || \
6807 ((INSTANCE) == TIM16) || \
6808 ((INSTANCE) == TIM17))
6809
6810 /****************** TIM Instances : supporting 2 break inputs *****************/
6811 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
6812 (((INSTANCE) == TIM1) || \
6813 ((INSTANCE) == TIM8))
6814
6815 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
6816 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)\
6817 (((INSTANCE) == TIM1) || \
6818 ((INSTANCE) == TIM8))
6819
6820 /****************** TIM Instances : supporting DMA generation on Update events*/
6821 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
6822 (((INSTANCE) == TIM1) || \
6823 ((INSTANCE) == TIM2) || \
6824 ((INSTANCE) == TIM3) || \
6825 ((INSTANCE) == TIM4) || \
6826 ((INSTANCE) == TIM6) || \
6827 ((INSTANCE) == TIM7) || \
6828 ((INSTANCE) == TIM8) || \
6829 ((INSTANCE) == TIM15) || \
6830 ((INSTANCE) == TIM16) || \
6831 ((INSTANCE) == TIM17))
6832
6833 /****************** TIM Instances : supporting DMA generation on Capture/Compare events */
6834 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
6835 (((INSTANCE) == TIM1) || \
6836 ((INSTANCE) == TIM2) || \
6837 ((INSTANCE) == TIM3) || \
6838 ((INSTANCE) == TIM4) || \
6839 ((INSTANCE) == TIM8) || \
6840 ((INSTANCE) == TIM15) || \
6841 ((INSTANCE) == TIM16) || \
6842 ((INSTANCE) == TIM17))
6843
6844 /****************** TIM Instances : supporting commutation event generation ***/
6845 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
6846 (((INSTANCE) == TIM1) || \
6847 ((INSTANCE) == TIM8) || \
6848 ((INSTANCE) == TIM15) || \
6849 ((INSTANCE) == TIM16) || \
6850 ((INSTANCE) == TIM17))
6851
6852 /****************** TIM Instances : supporting remapping capability ***********/
6853 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
6854 (((INSTANCE) == TIM1) || \
6855 ((INSTANCE) == TIM8) || \
6856 ((INSTANCE) == TIM16))
6857
6858 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
6859 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) \
6860 (((INSTANCE) == TIM1) || \
6861 ((INSTANCE) == TIM8))
6862
6863 /****************************** TSC Instances *********************************/
6864 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
6865
6866 /******************** USART Instances : Synchronous mode **********************/
6867 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
6868 ((INSTANCE) == USART2) || \
6869 ((INSTANCE) == USART3))
6870
6871 /****************** USART Instances : Auto Baud Rate detection ****************/
6872 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
6873 ((INSTANCE) == USART2) || \
6874 ((INSTANCE) == USART3))
6875
6876 /******************** UART Instances : Asynchronous mode **********************/
6877 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
6878 ((INSTANCE) == USART2) || \
6879 ((INSTANCE) == USART3) || \
6880 ((INSTANCE) == UART4) || \
6881 ((INSTANCE) == UART5))
6882
6883 /******************** UART Instances : Half-Duplex mode **********************/
6884 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
6885 ((INSTANCE) == USART2) || \
6886 ((INSTANCE) == USART3) || \
6887 ((INSTANCE) == UART4) || \
6888 ((INSTANCE) == UART5))
6889
6890 /******************** UART Instances : LIN mode **********************/
6891 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
6892 ((INSTANCE) == USART2) || \
6893 ((INSTANCE) == USART3) || \
6894 ((INSTANCE) == UART4) || \
6895 ((INSTANCE) == UART5))
6896
6897 /******************** UART Instances : Wake-up from Stop mode **********************/
6898 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
6899 ((INSTANCE) == USART2) || \
6900 ((INSTANCE) == USART3) || \
6901 ((INSTANCE) == UART4) || \
6902 ((INSTANCE) == UART5))
6903
6904 /****************** UART Instances : Hardware Flow control ********************/
6905 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
6906 ((INSTANCE) == USART2) || \
6907 ((INSTANCE) == USART3))
6908
6909 /****************** UART Instances : Auto Baud Rate detection *****************/
6910 #define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
6911 ((INSTANCE) == USART2) || \
6912 ((INSTANCE) == USART3))
6913
6914 /****************** UART Instances : Driver Enable ****************************/
6915 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
6916 ((INSTANCE) == USART2) || \
6917 ((INSTANCE) == USART3))
6918
6919 /********************* UART Instances : Smard card mode ***********************/
6920 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
6921 ((INSTANCE) == USART2) || \
6922 ((INSTANCE) == USART3))
6923
6924 /*********************** UART Instances : IRDA mode ***************************/
6925 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
6926 ((INSTANCE) == USART2) || \
6927 ((INSTANCE) == USART3) || \
6928 ((INSTANCE) == UART4) || \
6929 ((INSTANCE) == UART5))
6930
6931 /****************************** USB Instances *********************************/
6932 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
6933
6934 /****************************** WWDG Instances ********************************/
6935 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
6936
6937 /**
6938 * @}
6939 */
6940
6941
6942 /******************************************************************************/
6943 /* For a painless codes migration between the STM32F3xx device product */
6944 /* lines, the aliases defined below are put in place to overcome the */
6945 /* differences in the interrupt handlers and IRQn definitions. */
6946 /* No need to update developed interrupt code when moving across */
6947 /* product lines within the same STM32F3 Family */
6948 /******************************************************************************/
6949
6950 /* Aliases for __IRQn */
6951
6952 #define ADC1_IRQn ADC1_2_IRQn
6953 #define CAN_TX_IRQn USB_HP_CAN_TX_IRQn
6954 #define CAN_RX0_IRQn USB_LP_CAN_RX0_IRQn
6955 #define TIM15_IRQn TIM1_BRK_TIM15_IRQn
6956 #define TIM16_IRQn TIM1_UP_TIM16_IRQn
6957 #define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
6958 #define COMP_IRQn COMP1_2_3_IRQn
6959 #define COMP2_IRQn COMP1_2_3_IRQn
6960 #define COMP1_2_IRQn COMP1_2_3_IRQn
6961 #define COMP4_6_IRQn COMP4_5_6_IRQn
6962 #define TIM6_DAC1_IRQn TIM6_DAC_IRQn
6963
6964 /* Aliases for __IRQHandler */
6965 #define ADC1_IRQHandler ADC1_2_IRQHandler
6966 #define CAN_TX_IRQHandler USB_HP_CAN_TX_IRQHandler
6967 #define CAN_RX0_IRQHandler USB_LP_CAN_RX0_IRQHandler
6968 #define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
6969 #define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
6970 #define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
6971 #define COMP_IRQHandler COMP1_2_3_IRQHandler
6972 #define COMP2_IRQHandler COMP1_2_3_IRQHandler
6973 #define COMP1_2_IRQHandler COMP1_2_3_IRQHandler
6974 #define COMP4_6_IRQHandler COMP4_5_6_IRQHandler
6975 #define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
6976
6977 #ifdef __cplusplus
6978 }
6979 #endif /* __cplusplus */
6980
6981 #endif /* __STM32F303xC_H */
6982
6983 /**
6984 * @}
6985 */
6986
6987 /**
6988 * @}
6989 */
6990
6991 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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