tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F302R8/system_stm32f3xx.c

   1 /**
   2   ******************************************************************************
   3   * @file    system_stm32f3xx.c
   4   * @author  MCD Application Team
   5   * @version V2.1.0
   6   * @date    12-Sept-2014
   7   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
   8   *
   9   * 1. This file provides two functions and one global variable to be called from
  10   *    user application:
  11   *      - SystemInit(): This function is called at startup just after reset and
  12   *                      before branch to main program. This call is made inside
  13   *                      the "startup_stm32f3xx.s" file.
  14   *
  15   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
  16   *                                  by the user application to setup the SysTick
  17   *                                  timer or configure other parameters.
  18   *
  19   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
  20   *                                 be called whenever the core clock is changed
  21   *                                 during program execution.
  22   *
  23   * 2. After each device reset the HSI (8 MHz) is used as system clock source.
  24   *    Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to
  25   *    configure the system clock before to branch to main program.
  26   *
  27   * 3. This file configures the system clock as follows:
  28   *-----------------------------------------------------------------------------
  29   * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
  30   *                                    | (external 8 MHz clock) | (internal 8 MHz)
  31   *                                    | 2- PLL_HSE_XTAL        |
  32   *                                    | (external 8 MHz xtal)  |
  33   *-----------------------------------------------------------------------------
  34   * SYSCLK(MHz)                        | 72                     | 64
  35   *-----------------------------------------------------------------------------
  36   * AHBCLK (MHz)                       | 72                     | 64
  37   *-----------------------------------------------------------------------------
  38   * APB1CLK (MHz)                      | 36                     | 32
  39   *-----------------------------------------------------------------------------
  40   * APB2CLK (MHz)                      | 72                     | 64
  41   *-----------------------------------------------------------------------------
  42   * USB capable (48 MHz precise clock) | NO                     | NO
  43   *-----------------------------------------------------------------------------
  44   ******************************************************************************
  45   * @attention
  46   *
  47   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  48   *
  49   * Redistribution and use in source and binary forms, with or without modification,
  50   * are permitted provided that the following conditions are met:
  51   *   1. Redistributions of source code must retain the above copyright notice,
  52   *      this list of conditions and the following disclaimer.
  53   *   2. Redistributions in binary form must reproduce the above copyright notice,
  54   *      this list of conditions and the following disclaimer in the documentation
  55   *      and/or other materials provided with the distribution.
  56   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  57   *      may be used to endorse or promote products derived from this software
  58   *      without specific prior written permission.
  59   *
  60   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  61   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  62   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  63   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  64   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  65   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  66   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  67   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  68   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  69   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  70   *
  71   ******************************************************************************
  72   */
  73
  74 /** @addtogroup CMSIS
  75   * @{
  76   */
  77
  78 /** @addtogroup stm32f3xx_system
  79   * @{
  80   */
  81
  82 /** @addtogroup STM32F3xx_System_Private_Includes
  83   * @{
  84   */
  85
  86 #include "stm32f3xx.h"
  87 #include "hal_tick.h"
  88
  89 /**
  90   * @}
  91   */
  92
  93 /** @addtogroup STM32F3xx_System_Private_TypesDefinitions
  94   * @{
  95   */
  96
  97 /**
  98   * @}
  99   */
 100
 101 /** @addtogroup STM32F3xx_System_Private_Defines
 102   * @{
 103   */
 104 #if !defined  (HSE_VALUE)
 105   #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
 106                                                 This value can be provided and adapted by the user application. */
 107 #endif /* HSE_VALUE */
 108
 109 #if !defined  (HSI_VALUE)
 110   #define HSI_VALUE    ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
 111                                                 This value can be provided and adapted by the user application. */
 112 #endif /* HSI_VALUE */
 113
 114 /*!< Uncomment the following line if you need to relocate your vector Table in
 115      Internal SRAM. */
 116 /* #define VECT_TAB_SRAM */
 117 #define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
 118                                   This value must be a multiple of 0x200. */
 119 /**
 120   * @}
 121   */
 122
 123 /** @addtogroup STM32F3xx_System_Private_Macros
 124   * @{
 125   */
 126
 127 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
 128 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
 129 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
 130
 131 /**
 132   * @}
 133   */
 134
 135 /** @addtogroup STM32F3xx_System_Private_Variables
 136   * @{
 137   */
 138   /* This variable is updated in three ways:
 139       1) by calling CMSIS function SystemCoreClockUpdate()
 140       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
 141       3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
 142          Note: If you use this function to configure the system clock there is no need to
 143                call the 2 first functions listed above, since SystemCoreClock variable is
 144                updated automatically.
 145   */
 146 uint32_t SystemCoreClock = 72000000;
 147 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 148
 149 /**
 150   * @}
 151   */
 152
 153 /** @addtogroup STM32F3xx_System_Private_FunctionPrototypes
 154   * @{
 155   */
 156
 157 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
 158 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
 159 #endif
 160
 161 uint8_t SetSysClock_PLL_HSI(void);
 162
 163 /**
 164   * @}
 165   */
 166
 167 /** @addtogroup STM32F3xx_System_Private_Functions
 168   * @{
 169   */
 170
 171 /**
 172   * @brief  Setup the microcontroller system
 173   *         Initialize the FPU setting, vector table location and the PLL configuration is reset.
 174   * @param  None
 175   * @retval None
 176   */
 177 void SystemInit(void)
 178 {
 179   /* FPU settings ------------------------------------------------------------*/
 180   #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
 181     SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
 182   #endif
 183
 184   /* Reset the RCC clock configuration to the default reset state ------------*/
 185   /* Set HSION bit */
 186   RCC->CR |= (uint32_t)0x00000001;
 187
 188   /* Reset CFGR register */
 189   RCC->CFGR &= 0xF87FC00C;
 190
 191   /* Reset HSEON, CSSON and PLLON bits */
 192   RCC->CR &= (uint32_t)0xFEF6FFFF;
 193
 194   /* Reset HSEBYP bit */
 195   RCC->CR &= (uint32_t)0xFFFBFFFF;
 196
 197   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
 198   RCC->CFGR &= (uint32_t)0xFF80FFFF;
 199
 200   /* Reset PREDIV1[3:0] bits */
 201   RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
 202
 203   /* Reset USARTSW[1:0], I2CSW and TIMs bits */
 204   RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
 205
 206   /* Disable all interrupts */
 207   RCC->CIR = 0x00000000;
 208
 209 #ifdef VECT_TAB_SRAM
 210   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
 211 #else
 212   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
 213 #endif
 214
 215   /* Configure the Cube driver */
 216   SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
 217   HAL_Init();
 218
 219   /* Configure the System clock source, PLL Multiplier and Divider factors,
 220      AHB/APBx prescalers and Flash settings */
 221   SetSysClock();
 222
 223   /* Reset the timer to avoid issues after the RAM initialization */
 224   TIM_MST_RESET_ON;
 225   TIM_MST_RESET_OFF;
 226 }
 227
 228 /**
 229    * @brief  Update SystemCoreClock variable according to Clock Register Values.
 230   *         The SystemCoreClock variable contains the core clock (HCLK), it can
 231   *         be used by the user application to setup the SysTick timer or configure
 232   *         other parameters.
 233   *
 234   * @note   Each time the core clock (HCLK) changes, this function must be called
 235   *         to update SystemCoreClock variable value. Otherwise, any configuration
 236   *         based on this variable will be incorrect.
 237   *
 238   * @note   - The system frequency computed by this function is not the real
 239   *           frequency in the chip. It is calculated based on the predefined
 240   *           constant and the selected clock source:
 241   *
 242   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
 243   *
 244   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
 245   *
 246   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
 247   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
 248   *
 249   *         (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value
 250   *             8 MHz) but the real value may vary depending on the variations
 251   *             in voltage and temperature.
 252   *
 253   *         (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value
 254   *              8 MHz), user has to ensure that HSE_VALUE is same as the real
 255   *              frequency of the crystal used. Otherwise, this function may
 256   *              have wrong result.
 257   *
 258   *         - The result of this function could be not correct when using fractional
 259   *           value for HSE crystal.
 260   *
 261   * @param  None
 262   * @retval None
 263   */
 264 void SystemCoreClockUpdate (void)
 265 {
 266   uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
 267
 268   /* Get SYSCLK source -------------------------------------------------------*/
 269   tmp = RCC->CFGR & RCC_CFGR_SWS;
 270
 271   switch (tmp)
 272   {
 273     case RCC_CFGR_SWS_HSI:  /* HSI used as system clock */
 274       SystemCoreClock = HSI_VALUE;
 275       break;
 276     case RCC_CFGR_SWS_HSE:  /* HSE used as system clock */
 277       SystemCoreClock = HSE_VALUE;
 278       break;
 279     case RCC_CFGR_SWS_PLL:  /* PLL used as system clock */
 280       /* Get PLL clock source and multiplication factor ----------------------*/
 281       pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
 282       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
 283       pllmull = ( pllmull >> 18) + 2;
 284
 285 #if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
 286         predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
 287       if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
 288       {
 289         /* HSE oscillator clock selected as PREDIV1 clock entry */
 290         SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
 291       }
 292       else
 293       {
 294         /* HSI oscillator clock selected as PREDIV1 clock entry */
 295         SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull;
 296       }
 297 #else
 298       if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2)
 299       {
 300         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
 301         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
 302       }
 303       else
 304       {
 305         predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
 306         /* HSE oscillator clock selected as PREDIV1 clock entry */
 307         SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
 308       }
 309 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
 310       break;
 311     default: /* HSI used as system clock */
 312       SystemCoreClock = HSI_VALUE;
 313       break;
 314   }
 315   /* Compute HCLK clock frequency ----------------*/
 316   /* Get HCLK prescaler */
 317   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
 318   /* HCLK clock frequency */
 319   SystemCoreClock >>= tmp;
 320 }
 321
 322 /**
 323   * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
 324   *               AHB/APBx prescalers and Flash settings
 325   * @note   This function should be called only once the RCC clock configuration
 326   *         is reset to the default reset state (done in SystemInit() function).
 327   * @param  None
 328   * @retval None
 329   */
 330 void SetSysClock(void)
 331 {
 332   /* 1- Try to start with HSE and external clock */
 333 #if USE_PLL_HSE_EXTC != 0
 334   if (SetSysClock_PLL_HSE(1) == 0)
 335 #endif
 336   {
 337     /* 2- If fail try to start with HSE and external xtal */
 338     #if USE_PLL_HSE_XTAL != 0
 339     if (SetSysClock_PLL_HSE(0) == 0)
 340     #endif
 341     {
 342       /* 3- If fail start with HSI clock */
 343       if (SetSysClock_PLL_HSI() == 0)
 344       {
 345         while(1)
 346         {
 347           // [TODO] Put something here to tell the user that a problem occured...
 348         }
 349       }
 350     }
 351   }
 352
 353   /* Output clock on MCO1 pin(PA8) for debugging purpose */
 354   //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 72 MHz or 64 MHz
 355 }
 356
 357 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
 358 /******************************************************************************/
 359 /*            PLL (clocked by HSE) used as System clock source                */
 360 /******************************************************************************/
 361 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
 362 {
 363   RCC_ClkInitTypeDef RCC_ClkInitStruct;
 364   RCC_OscInitTypeDef RCC_OscInitStruct;
 365
 366   /* Enable HSE oscillator and activate PLL with HSE as source */
 367   RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
 368   if (bypass == 0)
 369   {
 370     RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
 371   }
 372   else
 373   {
 374     RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
 375   }
 376   RCC_OscInitStruct.HSEPredivValue      = RCC_HSE_PREDIV_DIV1;
 377   RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
 378   RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
 379   RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
 380   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 381   {
 382     return 0; // FAIL
 383   }
 384
 385   /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
 386   RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
 387   RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
 388   RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 72 MHz
 389   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 36 MHz
 390   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 72 MHz
 391   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
 392   {
 393     return 0; // FAIL
 394   }
 395
 396   /* Output clock on MCO1 pin(PA8) for debugging purpose */
 397   //if (bypass == 0)
 398   //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
 399   //else
 400   //  HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock
 401
 402   return 1; // OK
 403 }
 404 #endif
 405
 406 /******************************************************************************/
 407 /*            PLL (clocked by HSI) used as System clock source                */
 408 /******************************************************************************/
 409 uint8_t SetSysClock_PLL_HSI(void)
 410 {
 411   RCC_ClkInitTypeDef RCC_ClkInitStruct;
 412   RCC_OscInitTypeDef RCC_OscInitStruct;
 413
 414   /* Enable HSI oscillator and activate PLL with HSI as source */
 415   RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
 416   RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
 417   RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
 418   RCC_OscInitStruct.HSICalibrationValue = 16;
 419   RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
 420   RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
 421   RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)
 422   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 423   {
 424     return 0; // FAIL
 425   }
 426
 427   /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
 428   RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
 429   RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
 430   RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 64 MHz
 431   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 32 MHz
 432   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 64 MHz
 433   if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
 434   {
 435     return 0; // FAIL
 436   }
 437
 438   /* Output clock on MCO1 pin(PA8) for debugging purpose */
 439   //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz
 440
 441   return 1; // OK
 442 }
 443
 444 /**
 445   * @}
 446   */
 447
 448 /**
 449   * @}
 450   */
 451
 452 /**
 453   * @}
 454   */
 455
 456 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 457