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1 /**
2 ******************************************************************************
3 * @file stm32f3xx_hal_adc_ex.c
4 * @author MCD Application Team
5 * @version V1.1.0
6 * @date 12-Sept-2014
7 * @brief This file provides firmware functions to manage the following
8 * functionalities of the Analog to Digital Convertor (ADC)
9 * peripheral:
10 * + Initialization and de-initialization functions
11 * ++ Initialization and Configuration of ADC
12 * + Operation functions
13 * ++ Start, stop, get result of conversions of regular and injected
14 * groups, using 3 possible modes: polling, interruption or DMA.
15 * ++ Multimode feature (available on devices with 2 ADCs or more)
16 * ++ Calibration (ADC automatic self-calibration)
17 * + Control functions
18 * ++ Configure channels on regular group
19 * ++ Configure channels on injected group
20 * ++ Configure the analog watchdog
21 * + State functions
22 * ++ ADC state machine management
23 * ++ Interrupts and flags management
24 *
25 @verbatim
26 ==============================================================================
27 ##### ADC specific features #####
28 ==============================================================================
29 [..]
30 (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution (available only on
31 STM32F30xxC devices).
32
33 (#) Interrupt generation at the end of regular conversion, end of injected
34 conversion, and in case of analog watchdog or overrun events.
35
36 (#) Single and continuous conversion modes.
37
38 (#) Scan mode for automatic conversion of channel 0 to channel 'n'.
39
40 (#) Data alignment with in-built data coherency.
41
42 (#) Channel-wise programmable sampling time.
43
44 (#) ADC conversion Regular or Injected groups.
45
46 (#) External trigger (timer or EXTI) with configurable polarity for both
47 regular and injected groups.
48
49 (#) DMA request generation for transfer of conversions data of regular group.
50
51 (#) Multimode Dual mode (available on devices with 2 ADCs or more).
52
53 (#) Configurable DMA data storage in Multimode Dual mode (available on devices
54 with 2 DCs or more).
55
56 (#) Configurable delay between conversions in Dual interleaved mode (available
57 on devices with 2 DCs or more).
58
59 (#) ADC calibration
60
61 (#) ADC channels selectable single/differential input (available only on
62 STM32F30xxC devices)
63
64 (#) ADC Injected sequencer&channels configuration context queue (available
65 only on STM32F30xxC devices)
66
67 (#) ADC offset on injected and regular groups (offset on regular group
68 available only on STM32F30xxC devices)
69
70 (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
71 slower speed.
72
73 (#) ADC input range: from Vref\96 (connected to Vssa) to Vref+ (connected to
74 Vdda or to an external voltage reference).
75
76
77 ##### How to use this driver #####
78 ==============================================================================
79 [..]
80
81 (#) Enable the ADC interface
82 As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured
83 at RCC top level: clock source and clock prescaler.
84
85 For STM32F30x/STM32F33x devices:
86 Two possible clock sources: synchronous clock derived from AHB clock
87 or asynchronous clock derived from ADC dedicated PLL 72MHz.
88 - synchronous clock is configured using macro __ADCx_CLK_ENABLE()
89 - asynchronous clock is configured using macro __HAL_RCC_ADCx_CONFIG()
90 or function HAL_RCCEx_PeriphCLKConfig().
91
92 For example, in case of device with a single ADC:
93 __ADC1_CLK_ENABLE() (mandatory)
94 __HAL_RCC_ADC1_CONFIG(RCC_ADC1PLLCLK_DIV1); (optional)
95
96 For example, in case of device with several ADCs:
97 if((hadc->Instance == ADC1) || (hadc->Instance == ADC2))
98 {
99 __ADC12_CLK_ENABLE() (mandatory)
100 __HAL_RCC_ADC12_CONFIG(RCC_ADC12PLLCLK_DIV1); (optional)
101 }
102 else
103 {
104 __ADC34_CLK_ENABLE() (mandatory)
105 __HAL_RCC_ADC34_CONFIG(RCC_ADC34PLLCLK_DIV1); (optional)
106 }
107
108 For STM32F37x devices:
109 Only one clock source: APB2 clock.
110 Example:
111 __HAL_RCC_ADC1_CONFIG(RCC_ADC1PCLK2_DIV2);
112
113 (#) ADC pins configuration
114 (++) Enable the clock for the ADC GPIOs using the following function:
115 __GPIOx_CLK_ENABLE();
116 (++) Configure these ADC pins in analog mode using HAL_GPIO_Init();
117
118 (#) Configure the ADC parameters (conversion resolution, data alignment,
119 continuous mode, ...) using the HAL_ADC_Init() function.
120
121 (#) Activate the ADC peripheral using one of the start functions:
122 HAL_ADC_Start(), HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()
123 HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT() or
124 HAL_ADC_MultiModeStart_DMA().
125
126 *** Channels to regular group configuration ***
127 ============================================
128 [..]
129 (+) To configure the ADC regular group features, use
130 HAL_ADC_Init() and HAL_ADC_ConfigChannel() functions.
131 (+) To activate the continuous mode, use the HAL_ADC_Init() function.
132 (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
133
134 *** Multimode ADCs configuration ***
135 ======================================================
136 [..]
137 (+) Multimode feature is available on devices with 2 ADCs or more.
138 (+) Refer to "Channels to regular group" description to
139 configure the ADC1 and ADC2 regular groups.
140 (+) Select the Multi mode ADC features (dual mode
141 simultaneous, interleaved, ...) and configure the DMA mode using
142 HAL_ADCEx_MultiModeConfigChannel() functions.
143 (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue()
144 function.
145
146 *** DMA for regular configuration ***
147 =============================================================
148 [..]
149 (+) To enable the DMA mode for regular group, use the
150 HAL_ADC_Start_DMA() function.
151 (+) To enable the generation of DMA requests continuously at the end of
152 the last DMA transfer, use the HAL_ADC_Init() function.
153
154 *** Channels to injected group configuration ***
155 =============================================
156 [..]
157 (+) To configure the ADC Injected channels group features, use
158 HAL_ADCEx_InjectedConfigChannel() functions.
159 (+) To activate the continuous mode, use the HAL_ADC_Init() function.
160 (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue()
161 function.
162
163 @endverbatim
164 ******************************************************************************
165 * @attention
166 *
167 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
168 *
169 * Redistribution and use in source and binary forms, with or without modification,
170 * are permitted provided that the following conditions are met:
171 * 1. Redistributions of source code must retain the above copyright notice,
172 * this list of conditions and the following disclaimer.
173 * 2. Redistributions in binary form must reproduce the above copyright notice,
174 * this list of conditions and the following disclaimer in the documentation
175 * and/or other materials provided with the distribution.
176 * 3. Neither the name of STMicroelectronics nor the names of its contributors
177 * may be used to endorse or promote products derived from this software
178 * without specific prior written permission.
179 *
180 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
181 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
182 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
183 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
184 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
185 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
186 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
187 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
188 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
189 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
190 *
191 ******************************************************************************
192 */
193
194 /* Includes ------------------------------------------------------------------*/
195 #include "stm32f3xx_hal.h"
196
197 /** @addtogroup STM32F3xx_HAL_Driver
198 * @{
199 */
200
201 /** @defgroup ADCEx ADC Extended HAL module driver
202 * @brief ADC Extended HAL module driver
203 * @{
204 */
205
206 #ifdef HAL_ADC_MODULE_ENABLED
207
208 /* Private typedef -----------------------------------------------------------*/
209 /* Private define ------------------------------------------------------------*/
210 /** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
211 * @{
212 */
213 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
214 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
215 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
216 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
217 /* Fixed timeout values for ADC calibration, enable settling time, disable */
218 /* settling time. */
219 /* Values defined to be higher than worst cases: low clock frequency, */
220 /* maximum prescalers. */
221 /* Ex of profile low frequency : Clock source at 0.5 MHz, ADC clock */
222 /* prescaler 256 (devices STM32F30xx), sampling time 7.5 ADC clock cycles, */
223 /* resolution 12 bits. */
224 /* Unit: ms */
225 #define ADC_CALIBRATION_TIMEOUT ((uint32_t) 10)
226 #define ADC_ENABLE_TIMEOUT ((uint32_t) 2)
227 #define ADC_DISABLE_TIMEOUT ((uint32_t) 2)
228 #define ADC_STOP_CONVERSION_TIMEOUT ((uint32_t) 11)
229
230 /* Timeout to wait for current conversion on going to be completed. */
231 /* Timeout fixed to worst case, for 1 channel. */
232 /* - maximum sampling time (601.5 adc_clk) */
233 /* - ADC resolution (Tsar 12 bits= 12.5 adc_clk) */
234 /* - ADC clock (from PLL with prescaler 256 (devices STM32F30xx)) */
235 /* Unit: cycles of CPU clock. */
236 #define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 156928)
237
238 /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
239 /* Maximum delay is 10us (refer to device datasheet, param. TADCVREG_STUP). */
240 /* Delay in CPU cycles, fixed to worst case: maximum CPU frequency 72MHz to */
241 /* have the minimum number of CPU cycles to fulfill this delay. */
242 #define ADC_STAB_DELAY_CPU_CYCLES ((uint32_t)720)
243
244 /* Delay for temperature sensor stabilization time. */
245 /* Maximum delay is 10us (refer device datasheet, parameter tSTART). */
246 /* Delay in CPU cycles, fixed to worst case: maximum CPU frequency 72MHz to */
247 /* have the minimum number of CPU cycles to fulfill this delay. */
248 #define ADC_TEMPSENSOR_DELAY_CPU_CYCLES ((uint32_t)720)
249
250 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
251 /* STM32F302xC || STM32F303xC || STM32F358xx || */
252 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
253 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
254
255 #if defined(STM32F373xC) || defined(STM32F378xx)
256 /* Fixed timeout values for ADC calibration, enable settling time. */
257 /* Values defined to be higher than worst cases: low clocks freq, */
258 /* maximum prescalers. */
259 /* ex: On STM32F303C, clock source PLL=1MHz, presc. RCC_ADC12PLLCLK_DIV256 */
260 /* Unit: ms */
261 #define ADC_CALIBRATION_TIMEOUT ((uint32_t) 10)
262 #define ADC_ENABLE_TIMEOUT ((uint32_t) 10)
263
264 /* Delay for ADC stabilization time. */
265 /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
266 /* Delay in CPU cycles, fixed to worst case: maximum CPU frequency 48MHz to */
267 /* have the minimum number of CPU cycles to fulfill this delay. */
268 #define ADC_STAB_DELAY_CPU_CYCLES ((uint32_t)72)
269
270 /* Maximum number of CPU cycles corresponding to 1 ADC cycle */
271 /* Value fixed to worst case: clock prescalers slowing down ADC clock to */
272 /* minimum frequency */
273 /* - AHB prescaler: 16 */
274 /* - ADC prescaler: 8 */
275 /* Unit: cycles of CPU clock. */
276 #define ADC_CYCLE_WORST_CASE_CPU_CYCLES ((uint32_t) 128)
277
278 /* ADC conversion cycles (unit: ADC clock cycles) */
279 /* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */
280 /* resolution 12 bits) */
281 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 ((uint32_t) 14)
282 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 ((uint32_t) 20)
283 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 ((uint32_t) 26)
284 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 ((uint32_t) 41)
285 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 ((uint32_t) 54)
286 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 ((uint32_t) 68)
287 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 ((uint32_t) 84)
288 #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 ((uint32_t)252)
289 #endif /* STM32F373xC || STM32F378xx */
290 /**
291 * @}
292 */
293
294 /* Private macro -------------------------------------------------------------*/
295 /* Private variables ---------------------------------------------------------*/
296 /* Private function prototypes -----------------------------------------------*/
297 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
298 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
299 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
300 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
301 static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
302 static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc);
303 static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup);
304 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
305 /* STM32F302xC || STM32F303xC || STM32F358xx || */
306 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
307 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
308
309 #if defined(STM32F373xC) || defined(STM32F378xx)
310 static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
311 static HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc);
312 #endif /* STM32F373xC || STM32F378xx */
313
314 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
315 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
316 static void ADC_DMAError(DMA_HandleTypeDef *hdma);
317
318 /* Exported functions --------------------------------------------------------*/
319
320 /** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
321 * @{
322 */
323
324 /** @defgroup ADCEx_Exported_Functions_Group1 Extended Initialization and de-initialization functions
325 * @brief Extended Initialization and Configuration functions
326 *
327 @verbatim
328 ===============================================================================
329 ##### Initialization and de-initialization functions #####
330 ===============================================================================
331 [..] This section provides functions allowing to:
332 (+) Initialize and configure the ADC.
333 (+) De-initialize the ADC.
334
335 @endverbatim
336 * @{
337 */
338
339 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
340 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
341 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
342 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
343 /**
344 * @brief Initializes the ADC peripheral and regular group according to
345 * parameters specified in structure "ADC_InitTypeDef".
346 * @note As prerequisite, ADC clock must be configured at RCC top level
347 * depending on both possible clock sources: AHB clock or PLL clock.
348 * See commented example code below that can be copied and uncommented
349 * into HAL_ADC_MspInit().
350 * @note Possibility to update parameters on the fly:
351 * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
352 * coming from ADC state reset. Following calls to this function can
353 * be used to reconfigure some parameters of ADC_InitTypeDef
354 * structure on the fly, without modifying MSP configuration. If ADC
355 * MSP has to be modified again, HAL_ADC_DeInit() must be called
356 * before HAL_ADC_Init().
357 * The setting of these parameters is conditioned to ADC state.
358 * For parameters constraints, see comments of structure
359 * "ADC_InitTypeDef".
360 * @note This function configures the ADC within 2 scopes: scope of entire
361 * ADC and scope of regular group. For parameters details, see comments
362 * of structure "ADC_InitTypeDef".
363 * @note For devices with several ADCs: parameters related to common ADC
364 * registers (ADC clock mode) are set only if all ADCs sharing the
365 * same common group are disabled.
366 * If this is not the case, these common parameters setting are
367 * bypassed without error reporting: it can be the intended behaviour in
368 * case of update of a parameter of ADC_InitTypeDef on the fly,
369 * without disabling the other ADCs sharing the same common group.
370 * @param hadc: ADC handle
371 * @retval HAL status
372 */
373 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
374 {
375 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
376 ADC_Common_TypeDef *tmpADC_Common;
377 ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
378 uint32_t tmpCFGR = 0;
379 uint32_t WaitLoopIndex = 0;
380
381 /* Check ADC handle */
382 if(hadc == HAL_NULL)
383 {
384 return HAL_ERROR;
385 }
386
387 /* Check the parameters */
388 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
389 assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
390 assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
391 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
392 assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
393 assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
394 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
395 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
396 assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
397 assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
398 assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
399 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
400 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
401 assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
402 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
403
404
405 /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */
406 /* at RCC top level depending on both possible clock sources: */
407 /* PLL clock or AHB clock. */
408 /* For example: */
409 /* if((hadc->Instance == ADC1) || (hadc->Instance == ADC2)) */
410 /* { */
411 /* __ADC12_CLK_ENABLE(); */
412 /* __HAL_RCC_ADC12_CONFIG(RCC_ADC12PLLCLK_DIV1); */
413 /* } */
414 /* else */
415 /* { */
416 /* __ADC34_CLK_ENABLE(); */
417 /* __HAL_RCC_ADC34_CONFIG(RCC_ADC34PLLCLK_DIV1); */
418 /* } */
419
420
421 /* Actions performed only if ADC is coming from state reset: */
422 /* - Initialization of ADC MSP */
423 /* - ADC voltage regulator enable */
424 if (hadc->State == HAL_ADC_STATE_RESET)
425 {
426 /* Init the low level hardware */
427 HAL_ADC_MspInit(hadc);
428
429 /* Enable voltage regulator (if disabled at this step) */
430 if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN_0))
431 {
432 /* Note: The software must wait for the startup time of the ADC voltage */
433 /* regulator before launching a calibration or enabling the ADC. */
434 /* This temporization must be implemented by software and is */
435 /* equal to 10 us in the worst case process/temperature/power */
436 /* supply. */
437
438 /* Disable the ADC (if not already disabled) */
439 tmpHALStatus = ADC_Disable(hadc);
440
441 /* Check if ADC is effectively disabled */
442 if (tmpHALStatus != HAL_ERROR)
443 {
444 /* Initialize the ADC state */
445 hadc->State = HAL_ADC_STATE_BUSY;
446
447 /* Set the intermediate state before moving the ADC voltage regulator */
448 /* to state enable. */
449 hadc->Instance->CR &= ~(ADC_CR_ADVREGEN);
450 /* Set ADVREGEN bits to 0x01 */
451 hadc->Instance->CR |= ADC_CR_ADVREGEN_0;
452
453 /* Delay for ADC stabilization time. */
454 /* Delay fixed to worst case: maximum CPU frequency */
455 while(WaitLoopIndex < ADC_STAB_DELAY_CPU_CYCLES)
456 {
457 WaitLoopIndex++;
458 }
459 }
460 }
461 }
462
463 /* Verification that ADC voltage regulator is correctly enabled, whatever */
464 /* ADC coming from state reset or not (if any potential problem of */
465 /* clocking, voltage regulator would not be enabled). */
466 if ((hadc->Instance->CR & ADC_CR_ADVREGEN) != ADC_CR_ADVREGEN_0)
467 {
468 /* Update ADC state machine to error */
469 hadc->State = HAL_ADC_STATE_ERROR;
470
471 /* Set ADC error code to ADC IP internal error */
472 hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
473
474 tmpHALStatus = HAL_ERROR;
475 }
476
477
478 /* Configuration of ADC parameters if previous preliminary actions are */
479 /* correctly completed. */
480 /* and if there is no conversion on going on regular group (ADC can be */
481 /* enabled anyway, in case of call of this function to update a parameter */
482 /* on the fly). */
483 if ((hadc->State != HAL_ADC_STATE_ERROR) &&
484 (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) )
485 {
486 /* Initialize the ADC state */
487 hadc->State = HAL_ADC_STATE_BUSY;
488
489 /* Configuration of common ADC parameters */
490
491 /* Pointer to the common control register to which is belonging hadc */
492 /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
493 /* control registers) */
494 tmpADC_Common = __HAL_ADC_COMMON_REGISTER(hadc);
495
496 /* Set handle of the other ADC sharing the same common register */
497 __HAL_ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
498
499
500 /* Parameters update conditioned to ADC state: */
501 /* Parameters that can be updated only when ADC is disabled: */
502 /* - Multimode clock configuration */
503 if ((__HAL_ADC_IS_ENABLED(hadc) == RESET) &&
504 ( (tmphadcSharingSameCommonRegister.Instance == HAL_NULL) ||
505 (__HAL_ADC_IS_ENABLED(&tmphadcSharingSameCommonRegister) == RESET) ))
506 {
507 /* Reset configuration of ADC common register CCR: */
508 /* - ADC clock mode: CKMODE */
509 /* Some parameters of this register are not reset, since they are set */
510 /* by other functions and must be kept in case of usage of this */
511 /* function on the fly (update of a parameter of ADC_InitTypeDef */
512 /* without needing to reconfigure all other ADC groups/channels */
513 /* parameters): */
514 /* - multimode related parameters: MDMA, DMACFG, DELAY, MULTI (set */
515 /* into HAL_ADCEx_MultiModeConfigChannel() ) */
516 /* - internal measurement paths: Vbat, temperature sensor, Vref */
517 /* (set into HAL_ADC_ConfigChannel() or */
518 /* HAL_ADCEx_InjectedConfigChannel() ) */
519 tmpADC_Common->CCR &= ~(ADC_CCR_CKMODE);
520
521 /* Configuration of common ADC clock: clock source PLL or AHB with */
522 /* selectable prescaler */
523 tmpADC_Common->CCR |= hadc->Init.ClockPrescaler;
524 }
525
526 /* Configuration of ADC: */
527 /* - resolution */
528 /* - data alignment */
529 /* - external trigger to start conversion */
530 /* - external trigger polarity */
531 /* - continuous conversion mode */
532 /* - overrun */
533 /* - discontinuous mode */
534 hadc->Instance->CFGR &= ~( ADC_CFGR_DISCNUM |
535 ADC_CFGR_DISCEN |
536 ADC_CFGR_CONT |
537 ADC_CFGR_OVRMOD |
538 ADC_CFGR_EXTSEL |
539 ADC_CFGR_EXTEN |
540 ADC_CFGR_ALIGN |
541 ADC_CFGR_RES );
542
543 tmpCFGR |= ( __HAL_ADC_CFGR_CONTINUOUS(hadc->Init.ContinuousConvMode) |
544 __HAL_ADC_CFGR_OVERRUN(hadc->Init.Overrun) |
545 hadc->Init.DataAlign |
546 hadc->Init.Resolution );
547
548 /* Enable discontinuous mode only if continuous mode is disabled */
549 if ((hadc->Init.DiscontinuousConvMode == ENABLE) &&
550 (hadc->Init.ContinuousConvMode == DISABLE) )
551 {
552 /* Enable the selected ADC regular discontinuous mode */
553 /* Set the number of channels to be converted in discontinuous mode */
554 tmpCFGR |= ( ADC_CFGR_DISCEN |
555 __HAL_ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) );
556 }
557
558 /* Enable external trigger if trigger selection is different of software */
559 /* start. */
560 /* Note: This configuration keeps the hardware feature of parameter */
561 /* ExternalTrigConvEdge "trigger edge none" equivalent to */
562 /* software start. */
563 if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
564 {
565 tmpCFGR |= ( __HAL_ADC_CFGR_EXTSEL(hadc, hadc->Init.ExternalTrigConv) |
566 hadc->Init.ExternalTrigConvEdge );
567 }
568
569 /* Parameters update conditioned to ADC state: */
570 /* Parameters that can be updated when ADC is disabled or enabled without */
571 /* conversion on going on regular and injected groups: */
572 /* - DMA continuous request */
573 /* - LowPowerAutoWait feature */
574 if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
575 {
576 hadc->Instance->CFGR &= ~( ADC_CFGR_AUTDLY |
577 ADC_CFGR_DMACFG );
578
579 tmpCFGR |= ( __HAL_ADC_CFGR_AUTOWAIT(hadc->Init.LowPowerAutoWait) |
580 __HAL_ADC_CFGR_DMACONTREQ(hadc->Init.DMAContinuousRequests) );
581 }
582
583 /* Update ADC configuration register with previous settings */
584 hadc->Instance->CFGR |= tmpCFGR;
585
586
587 /* Configuration of regular group sequencer: */
588 /* - if scan mode is disabled, regular channels sequence length is set to */
589 /* 0x00: 1 channel converted (channel on regular rank 1) */
590 /* Parameter "NbrOfConversion" is discarded. */
591 /* Note: Scan mode is not present by hardware on this device, but */
592 /* emulated by software for alignment over all STM32 devices. */
593 /* - if scan mode is enabled, regular channels sequence length is set to */
594 /* parameter "NbrOfConversion" */
595 hadc->Instance->SQR1 &= ~(ADC_SQR1_L);
596 if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
597 {
598 /* Set number of ranks in regular group sequencer */
599 hadc->Instance->SQR1 |= (hadc->Init.NbrOfConversion - (uint8_t)1);
600 }
601
602 /* Set ADC error code to none */
603 __HAL_ADC_CLEAR_ERRORCODE(hadc);
604
605 /* Initialize the ADC state */
606 hadc->State = HAL_ADC_STATE_READY;
607
608 }
609 else
610 {
611 /* Update ADC state machine to error */
612 hadc->State = HAL_ADC_STATE_ERROR;
613
614 tmpHALStatus = HAL_ERROR;
615 }
616
617
618 /* Return function status */
619 return tmpHALStatus;
620 }
621 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
622 /* STM32F302xC || STM32F303xC || STM32F358xx || */
623 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
624 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
625
626 #if defined(STM32F373xC) || defined(STM32F378xx)
627 /**
628 * @brief Initializes the ADC peripheral and regular group according to
629 * parameters specified in structure "ADC_InitTypeDef".
630 * @note As prerequisite, ADC clock must be configured at RCC top level
631 * (clock source APB2).
632 * See commented example code below that can be copied and uncommented
633 * into HAL_ADC_MspInit().
634 * @note Possibility to update parameters on the fly:
635 * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
636 * coming from ADC state reset. Following calls to this function can
637 * be used to reconfigure some parameters of ADC_InitTypeDef
638 * structure on the fly, without modifying MSP configuration. If ADC
639 * MSP has to be modified again, HAL_ADC_DeInit() must be called
640 * before HAL_ADC_Init().
641 * The setting of these parameters is conditioned to ADC state.
642 * For parameters constraints, see comments of structure
643 * "ADC_InitTypeDef".
644 * @note This function configures the ADC within 2 scopes: scope of entire
645 * ADC and scope of regular group. For parameters details, see comments
646 * of structure "ADC_InitTypeDef".
647 * @param hadc: ADC handle
648 * @retval HAL status
649 */
650 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
651 {
652 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
653
654 /* Check ADC handle */
655 if(hadc == HAL_NULL)
656 {
657 return HAL_ERROR;
658 }
659
660 /* Check the parameters */
661 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
662 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
663 assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
664 assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
665 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
666 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
667 assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
668 assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
669
670 /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */
671 /* at RCC top level. */
672 /* For example: */
673 /* __ADC1_CLK_ENABLE(); */
674
675
676 /* Actions performed only if ADC is coming from state reset: */
677 /* - Initialization of ADC MSP */
678 if (hadc->State == HAL_ADC_STATE_RESET)
679 {
680 /* Init the low level hardware */
681 HAL_ADC_MspInit(hadc);
682 }
683
684 /* Stop potential conversion on going, on regular and injected groups */
685 /* Disable ADC peripheral */
686 /* Note: In case of ADC already enabled, precaution to not launch an */
687 /* unwanted conversion while modifying register CR2 by writing 1 to */
688 /* bit ADON. */
689 tmpHALStatus = ADC_ConversionStop_Disable(hadc);
690
691
692 /* Configuration of ADC parameters if previous preliminary actions are */
693 /* correctly completed. */
694 if (tmpHALStatus != HAL_ERROR)
695 {
696 /* Initialize the ADC state */
697 hadc->State = HAL_ADC_STATE_BUSY;
698
699 /* Set ADC parameters */
700
701 /* Configuration of ADC: */
702 /* - data alignment */
703 /* - external trigger to start conversion */
704 /* - external trigger polarity (always set to 1, because needed for all */
705 /* triggers: external trigger of SW start) */
706 /* - continuous conversion mode */
707 hadc->Instance->CR2 &= ~( ADC_CR2_ALIGN |
708 ADC_CR2_EXTSEL |
709 ADC_CR2_EXTTRIG |
710 ADC_CR2_CONT );
711
712 hadc->Instance->CR2 |= ( hadc->Init.DataAlign |
713 hadc->Init.ExternalTrigConv |
714 ADC_CR2_EXTTRIG |
715 __HAL_ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode) );
716
717 /* Configuration of ADC: */
718 /* - scan mode */
719 /* - discontinuous mode disable/enable */
720 /* - discontinuous mode number of conversions */
721 hadc->Instance->CR1 &= ~( ADC_CR1_SCAN |
722 ADC_CR1_DISCEN |
723 ADC_CR1_DISCNUM );
724
725 hadc->Instance->CR1 |= ( __HAL_ADC_CR1_SCAN(hadc->Init.ScanConvMode) );
726
727 /* Enable discontinuous mode only if continuous mode is disabled */
728 if ((hadc->Init.DiscontinuousConvMode == ENABLE) &&
729 (hadc->Init.ContinuousConvMode == DISABLE) )
730 {
731 /* Enable the selected ADC regular discontinuous mode */
732 hadc->Instance->CR1 |= (ADC_CR1_DISCEN);
733
734 /* Set the number of channels to be converted in discontinuous mode */
735 hadc->Instance->CR1 |= __HAL_ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
736 }
737
738 /* Configuration of regular group sequencer: */
739 /* - if scan mode is disabled, regular channels sequence length is set to */
740 /* 0x00: 1 channel converted (channel on regular rank 1) */
741 /* Parameter "NbrOfConversion" is discarded. */
742 /* Note: Scan mode is present by hardware on this device and, if */
743 /* disabled, discards automatically nb of conversions. Anyway, nb of */
744 /* conversions is forced to 0x00 for alignment over all STM32 devices. */
745 /* - if scan mode is enabled, regular channels sequence length is set to */
746 /* parameter "NbrOfConversion" */
747 hadc->Instance->SQR1 &= ~(ADC_SQR1_L);
748 if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
749 {
750 /* Set number of ranks in regular group sequencer */
751 hadc->Instance->SQR1 |= __HAL_ADC_SQR1_L(hadc->Init.NbrOfConversion);
752 }
753
754 /* Set ADC error code to none */
755 __HAL_ADC_CLEAR_ERRORCODE(hadc);
756
757 /* Initialize the ADC state */
758 hadc->State = HAL_ADC_STATE_READY;
759 }
760
761 /* Return function status */
762 return tmpHALStatus;
763 }
764 #endif /* STM32F373xC || STM32F378xx */
765
766 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
767 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
768 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
769 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
770 /**
771 * @brief Deinitialize the ADC peripheral registers to their default reset
772 * values, with deinitialization of the ADC MSP.
773 * @note For devices with several ADCs: reset of ADC common registers is done
774 * only if all ADCs sharing the same common group are disabled.
775 * If this is not the case, reset of these common parameters reset is
776 * bypassed without error reporting: it can be the intended behaviour in
777 * case of reset of a single ADC while the other ADCs sharing the same
778 * common group is still running.
779 * @note For devices with several ADCs: Global reset of all ADCs sharing a
780 * common group is possible.
781 * As this function is intended to reset a single ADC, to not impact
782 * other ADCs, instructions for global reset of multiple ADCs have been
783 * let commented below.
784 * If needed, the example code can be copied and uncommented into
785 * function HAL_ADC_MspDeInit().
786 * @param hadc: ADC handle
787 * @retval HAL status
788 */
789 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
790 {
791 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
792 ADC_Common_TypeDef *tmpADC_Common;
793 ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
794
795 /* Check ADC handle */
796 if(hadc == HAL_NULL)
797 {
798 return HAL_ERROR;
799 }
800
801 /* Check the parameters */
802 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
803
804 /* Change ADC state */
805 hadc->State = HAL_ADC_STATE_BUSY;
806
807 /* Stop potential conversion on going, on regular and injected groups */
808 tmpHALStatus = ADC_ConversionStop(hadc, REGULAR_INJECTED_GROUP);
809
810 /* Disable ADC peripheral if conversions are effectively stopped */
811 if (tmpHALStatus != HAL_ERROR)
812 {
813 /* Flush register JSQR: queue sequencer reset when injected queue */
814 /* sequencer is enabled and ADC disabled */
815 /* Enable injected queue sequencer after injected conversion stop */
816 hadc->Instance->CFGR |= ADC_CFGR_JQM;
817
818 /* Disable the ADC peripheral */
819 tmpHALStatus = ADC_Disable(hadc);
820
821 /* Check if ADC is effectively disabled */
822 if (tmpHALStatus != HAL_ERROR)
823 {
824 /* Change ADC state */
825 hadc->State = HAL_ADC_STATE_READY;
826 }
827 else
828 {
829 tmpHALStatus = HAL_ERROR;
830 }
831 }
832
833
834 /* Configuration of ADC parameters if previous preliminary actions are */
835 /* correctly completed. */
836 if (tmpHALStatus != HAL_ERROR)
837 {
838
839 /* ========== Reset ADC registers ========== */
840 /* Reset register IER */
841 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 |
842 ADC_IT_JQOVF | ADC_IT_OVR |
843 ADC_IT_JEOS | ADC_IT_JEOC |
844 ADC_IT_EOS | ADC_IT_EOC |
845 ADC_IT_EOSMP | ADC_IT_RDY ) );
846
847 /* Reset register ISR */
848 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
849 ADC_FLAG_JQOVF | ADC_FLAG_OVR |
850 ADC_FLAG_JEOS | ADC_FLAG_JEOC |
851 ADC_FLAG_EOS | ADC_FLAG_EOC |
852 ADC_FLAG_EOSMP | ADC_FLAG_RDY ) );
853
854 /* Reset register CR */
855 /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART are */
856 /* in access mode "read-set": no direct reset applicable. */
857 /* Reset Calibration mode to default setting (single ended): */
858 /* Disable voltage regulator: */
859 /* Note: Voltage regulator disable is conditioned to ADC state disabled: */
860 /* already done above. */
861 /* Note: Voltage regulator disable is intended for power saving. */
862 /* Sequence to disable voltage regulator: */
863 /* 1. Set the intermediate state before moving the ADC voltage regulator */
864 /* to disable state. */
865 hadc->Instance->CR &= ~(ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
866 /* 2. Set ADVREGEN bits to 0x10 */
867 hadc->Instance->CR |= ADC_CR_ADVREGEN_1;
868
869 /* Reset register CFGR */
870 hadc->Instance->CFGR &= ~(ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |
871 ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |
872 ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |
873 ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |
874 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |
875 ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN );
876
877 /* Reset register SMPR1 */
878 hadc->Instance->SMPR1 &= ~(ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |
879 ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |
880 ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 );
881
882 /* Reset register SMPR2 */
883 hadc->Instance->SMPR2 &= ~(ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
884 ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
885 ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10 );
886
887 /* Reset register TR1 */
888 hadc->Instance->TR1 &= ~(ADC_TR1_HT1 | ADC_TR1_LT1);
889
890 /* Reset register TR2 */
891 hadc->Instance->TR2 &= ~(ADC_TR2_HT2 | ADC_TR2_LT2);
892
893 /* Reset register TR3 */
894 hadc->Instance->TR3 &= ~(ADC_TR3_HT3 | ADC_TR3_LT3);
895
896 /* Reset register SQR1 */
897 hadc->Instance->SQR1 &= ~(ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
898 ADC_SQR1_SQ1 | ADC_SQR1_L);
899
900 /* Reset register SQR2 */
901 hadc->Instance->SQR2 &= ~(ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 |
902 ADC_SQR2_SQ6 | ADC_SQR2_SQ5);
903
904 /* Reset register SQR3 */
905 hadc->Instance->SQR3 &= ~(ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 |
906 ADC_SQR3_SQ11 | ADC_SQR3_SQ10);
907
908 /* Reset register SQR4 */
909 hadc->Instance->SQR4 &= ~(ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
910
911 /* Reset register DR */
912 /* bits in access mode read only, no direct reset applicable*/
913
914 /* Reset register OFR1 */
915 hadc->Instance->OFR1 &= ~(ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
916 /* Reset register OFR2 */
917 hadc->Instance->OFR2 &= ~(ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
918 /* Reset register OFR3 */
919 hadc->Instance->OFR3 &= ~(ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
920 /* Reset register OFR4 */
921 hadc->Instance->OFR4 &= ~(ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
922
923 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
924 /* bits in access mode read only, no direct reset applicable*/
925
926 /* Reset register AWD2CR */
927 hadc->Instance->AWD2CR &= ~(ADC_AWD2CR_AWD2CH);
928
929 /* Reset register AWD3CR */
930 hadc->Instance->AWD3CR &= ~(ADC_AWD3CR_AWD3CH);
931
932 /* Reset register DIFSEL */
933 hadc->Instance->DIFSEL &= ~(ADC_DIFSEL_DIFSEL);
934
935 /* Reset register CALFACT */
936 hadc->Instance->CALFACT &= ~(ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
937
938
939
940
941
942
943 /* ========== Reset common ADC registers ========== */
944
945 /* Pointer to the common control register to which is belonging hadc */
946 /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
947 /* control registers) */
948 tmpADC_Common = __HAL_ADC_COMMON_REGISTER(hadc);
949
950 /* Set handle of the other ADC sharing the same common register */
951 __HAL_ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
952
953 /* Software is allowed to change common parameters only when all ADCs of */
954 /* the common group are disabled. */
955 if ((__HAL_ADC_IS_ENABLED(hadc) == RESET) &&
956 ( (tmphadcSharingSameCommonRegister.Instance == HAL_NULL) ||
957 (__HAL_ADC_IS_ENABLED(&tmphadcSharingSameCommonRegister) == RESET) ))
958 {
959 /* Reset configuration of ADC common register CCR:
960 - clock mode: CKMODE
961 - multimode related parameters: MDMA, DMACFG, DELAY, MULTI (set into
962 HAL_ADCEx_MultiModeConfigChannel() )
963 - internal measurement paths: Vbat, temperature sensor, Vref (set into
964 HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
965 */
966 tmpADC_Common->CCR &= ~( ADC_CCR_CKMODE |
967 ADC_CCR_VBATEN |
968 ADC_CCR_TSEN |
969 ADC_CCR_VREFEN |
970 ADC_CCR_DMACFG |
971 ADC_CCR_DMACFG |
972 ADC_CCR_DELAY |
973 ADC_CCR_MULTI );
974
975 /* Other ADC common registers (CSR, CDR) are in access mode read only,
976 no direct reset applicable */
977 }
978
979
980 /* ========== Hard reset of ADC peripheral ========== */
981 /* Performs a global reset of the entire ADC peripheral: ADC state is */
982 /* forced to a similar state after device power-on. */
983 /* Caution: */
984 /* These settings impact both ADC of common group: ADC1&ADC2, ADC3&ADC4 */
985 /* if available (ADC2, ADC3, ADC4 availability depends on STM32 product) */
986 /* As this function is intended to reset a single ADC, instructions for */
987 /* global reset of multiple ADC have been let commented below. */
988 /* */
989 /* If global reset of common ADC is corresponding to the current */
990 /* application, copy-paste and uncomment the following reset code into */
991 /* function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)": */
992 /* */
993 /* ADC clock reset */
994 /* if((hadc->Instance == ADC1) || (hadc->Instance == ADC2)) */
995 /* { */
996 /* __ADC12_FORCE_RESET(); */
997 /* __ADC12_RELEASE_RESET(); */
998 /* } */
999 /* else */
1000 /* { */
1001 /* __ADC34_FORCE_RESET(); */
1002 /* __ADC34_RELEASE_RESET(); */
1003 /* } */
1004 /* */
1005 /* ADC clock disable of both possible clock sources: AHB clock and */
1006 /* PLL clock. */
1007 /* if((hadc->Instance == ADC1) || (hadc->Instance == ADC2)) */
1008 /* { */
1009 /* __HAL_RCC_ADC12_CONFIG(RCC_ADC12PLLCLK_OFF); */
1010 /* __ADC12_CLK_DISABLE(); */
1011 /* } */
1012 /* else */
1013 /* { */
1014 /* __HAL_RCC_ADC34_CONFIG(RCC_ADC12PLLCLK_OFF); */
1015 /* __ADC34_CLK_DISABLE(); */
1016 /* } */
1017
1018 /* DeInit the low level hardware */
1019 HAL_ADC_MspDeInit(hadc);
1020
1021 /* Set ADC error code to none */
1022 __HAL_ADC_CLEAR_ERRORCODE(hadc);
1023
1024 /* Change ADC state */
1025 hadc->State = HAL_ADC_STATE_RESET;
1026 }
1027
1028 /* Process unlocked */
1029 __HAL_UNLOCK(hadc);
1030
1031 /* Return function status */
1032 return tmpHALStatus;
1033 }
1034 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
1035 /* STM32F302xC || STM32F303xC || STM32F358xx || */
1036 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
1037 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
1038
1039 #if defined(STM32F373xC) || defined(STM32F378xx)
1040 /**
1041 * @brief Deinitialize the ADC peripheral registers to its default reset values.
1042 * @note To not impact other ADCs, reset of common ADC registers have been
1043 * left commented below.
1044 * If needed, the example code can be copied and uncommented into
1045 * function HAL_ADC_MspDeInit().
1046 * @param hadc: ADC handle
1047 * @retval HAL status
1048 */
1049 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
1050 {
1051 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
1052
1053 /* Check ADC handle */
1054 if(hadc == HAL_NULL)
1055 {
1056 return HAL_ERROR;
1057 }
1058
1059 /* Check the parameters */
1060 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1061
1062 /* Change ADC state */
1063 hadc->State = HAL_ADC_STATE_BUSY;
1064
1065 /* Stop potential conversion on going, on regular and injected groups */
1066 /* Disable ADC peripheral */
1067 tmpHALStatus = ADC_ConversionStop_Disable(hadc);
1068
1069
1070 /* Configuration of ADC parameters if previous preliminary actions are */
1071 /* correctly completed. */
1072 if (tmpHALStatus != HAL_ERROR)
1073 {
1074 /* ========== Reset ADC registers ========== */
1075 /* Reset register SR */
1076 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC |
1077 ADC_FLAG_JSTRT | ADC_FLAG_STRT));
1078
1079 /* Reset register CR1 */
1080 hadc->Instance->CR1 &= ~(ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM |
1081 ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO |
1082 ADC_CR1_AWDSGL | ADC_CR1_SCAN | ADC_CR1_JEOCIE |
1083 ADC_CR1_AWDIE | ADC_CR1_EOCIE | ADC_CR1_AWDCH);
1084
1085 /* Reset register CR2 */
1086 hadc->Instance->CR2 &= ~(ADC_CR2_TSVREFE | ADC_CR2_SWSTART | ADC_CR2_JSWSTART |
1087 ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL | ADC_CR2_JEXTTRIG |
1088 ADC_CR2_JEXTSEL | ADC_CR2_ALIGN | ADC_CR2_DMA |
1089 ADC_CR2_RSTCAL | ADC_CR2_CAL | ADC_CR2_CONT |
1090 ADC_CR2_ADON );
1091
1092 /* Reset register SMPR1 */
1093 hadc->Instance->SMPR1 &= ~(ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 | ADC_SMPR1_SMP15 |
1094 ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 | ADC_SMPR1_SMP12 |
1095 ADC_SMPR1_SMP11 |ADC_SMPR1_SMP10);
1096
1097 /* Reset register SMPR2 */
1098 hadc->Instance->SMPR2 &= ~(ADC_SMPR2_SMP9 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 |
1099 ADC_SMPR2_SMP6 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 |
1100 ADC_SMPR2_SMP3 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 |
1101 ADC_SMPR2_SMP0);
1102
1103 /* Reset register JOFR1 */
1104 hadc->Instance->JOFR1 &= ~(ADC_JOFR1_JOFFSET1);
1105 /* Reset register JOFR2 */
1106 hadc->Instance->JOFR2 &= ~(ADC_JOFR2_JOFFSET2);
1107 /* Reset register JOFR3 */
1108 hadc->Instance->JOFR3 &= ~(ADC_JOFR3_JOFFSET3);
1109 /* Reset register JOFR4 */
1110 hadc->Instance->JOFR4 &= ~(ADC_JOFR4_JOFFSET4);
1111
1112 /* Reset register HTR */
1113 hadc->Instance->HTR &= ~(ADC_HTR_HT);
1114 /* Reset register LTR */
1115 hadc->Instance->LTR &= ~(ADC_LTR_LT);
1116
1117 /* Reset register SQR1 */
1118 hadc->Instance->SQR1 &= ~(ADC_SQR1_L |
1119 ADC_SQR1_SQ16 | ADC_SQR1_SQ15 |
1120 ADC_SQR1_SQ14 | ADC_SQR1_SQ13 );
1121
1122 /* Reset register SQR1 */
1123 hadc->Instance->SQR1 &= ~(ADC_SQR1_L |
1124 ADC_SQR1_SQ16 | ADC_SQR1_SQ15 |
1125 ADC_SQR1_SQ14 | ADC_SQR1_SQ13 );
1126
1127 /* Reset register SQR2 */
1128 hadc->Instance->SQR2 &= ~(ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 |
1129 ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 );
1130
1131 /* Reset register SQR3 */
1132 hadc->Instance->SQR3 &= ~(ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 |
1133 ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1 );
1134
1135 /* Reset register JSQR */
1136 hadc->Instance->JSQR &= ~(ADC_JSQR_JL |
1137 ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
1138 ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 );
1139
1140 /* Reset register JSQR */
1141 hadc->Instance->JSQR &= ~(ADC_JSQR_JL |
1142 ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
1143 ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 );
1144
1145 /* Reset register DR */
1146 /* bits in access mode read only, no direct reset applicable*/
1147
1148 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
1149 /* bits in access mode read only, no direct reset applicable*/
1150
1151 /* Reset VBAT measurement path, in case of enabled before by selecting */
1152 /* channel ADC_CHANNEL_VBAT. */
1153 SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_VBAT);
1154
1155
1156 /* ========== Hard reset ADC peripheral ========== */
1157 /* Performs a global reset of the entire ADC peripheral: ADC state is */
1158 /* forced to a similar state after device power-on. */
1159 /* If needed, copy-paste and uncomment the following reset code into */
1160 /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)": */
1161 /* */
1162 /* __ADC1_FORCE_RESET(); */
1163 /* __ADC1_RELEASE_RESET(); */
1164
1165 /* DeInit the low level hardware */
1166 HAL_ADC_MspDeInit(hadc);
1167
1168 /* Set ADC error code to none */
1169 __HAL_ADC_CLEAR_ERRORCODE(hadc);
1170
1171 /* Change ADC state */
1172 hadc->State = HAL_ADC_STATE_RESET;
1173
1174 }
1175
1176 /* Process unlocked */
1177 __HAL_UNLOCK(hadc);
1178
1179 /* Return function status */
1180 return tmpHALStatus;
1181 }
1182 #endif /* STM32F373xC || STM32F378xx */
1183
1184 /**
1185 * @}
1186 */
1187
1188 /** @defgroup ADCEx_Exported_Functions_Group2 Extended Input and Output operation functions
1189 * @brief Extended IO operation functions
1190 *
1191 @verbatim
1192 ===============================================================================
1193 ##### IO operation functions #####
1194 ===============================================================================
1195 [..] This section provides functions allowing to:
1196 (+) Start conversion of regular group.
1197 (+) Stop conversion of regular group.
1198 (+) Poll for conversion complete on regular group.
1199 (+) Poll for conversion event.
1200 (+) Get result of regular channel conversion.
1201 (+) Start conversion of regular group and enable interruptions.
1202 (+) Stop conversion of regular group and disable interruptions.
1203 (+) Handle ADC interrupt request
1204 (+) Start conversion of regular group and enable DMA transfer.
1205 (+) Stop conversion of regular group and disable ADC DMA transfer.
1206
1207 (+) Start conversion of injected group.
1208 (+) Stop conversion of injected group.
1209 (+) Poll for conversion complete on injected group.
1210 (+) Get result of injected channel conversion.
1211 (+) Start conversion of injected group and enable interruptions.
1212 (+) Stop conversion of injected group and disable interruptions.
1213
1214 (+) Start multimode and enable DMA transfer.
1215 (+) Stop multimode and disable ADC DMA transfer.
1216 (+) Get result of multimode conversion.
1217
1218 (+) Perform the ADC self-calibration for single or differential ending.
1219 (+) Get calibration factors for single or differential ending.
1220 (+) Set calibration factors for single or differential ending.
1221
1222 @endverbatim
1223 * @{
1224 */
1225
1226 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
1227 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
1228 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
1229 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
1230 /**
1231 * @brief Enables ADC, starts conversion of regular group.
1232 * Interruptions enabled in this function: None.
1233 * @note: Case of multimode enabled (for devices with several ADCs): if ADC
1234 * is slave, ADC is enabled only (conversion is not started). If ADC
1235 * is master, ADC is enabled and multimode conversion is started.
1236 * @param hadc: ADC handle
1237 * @retval HAL status
1238 */
1239 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
1240 {
1241 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
1242
1243 /* Check the parameters */
1244 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1245
1246 /* Process locked */
1247 __HAL_LOCK(hadc);
1248
1249 /* Enable the ADC peripheral */
1250 tmpHALStatus = ADC_Enable(hadc);
1251
1252 /* Start conversion if ADC is effectively enabled */
1253 if (tmpHALStatus != HAL_ERROR)
1254 {
1255 /* State machine update: Check if an injected conversion is ongoing */
1256 if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
1257 {
1258 /* Change ADC state */
1259 hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
1260 }
1261 else
1262 {
1263 /* Change ADC state */
1264 hadc->State = HAL_ADC_STATE_BUSY_REG;
1265 }
1266
1267 /* Set ADC error code to none */
1268 __HAL_ADC_CLEAR_ERRORCODE(hadc);
1269
1270 /* Clear regular group conversion flag and overrun flag */
1271 /* (To ensure of no unknown state from potential previous ADC operations) */
1272 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
1273
1274 /* Enable conversion of regular group. */
1275 /* If software start has been selected, conversion starts immediately. */
1276 /* If external trigger has been selected, conversion will start at next */
1277 /* trigger event. */
1278 /* Case of multimode enabled (for devices with several ADCs): if ADC is */
1279 /* slave, ADC is enabled only (conversion is not started). If ADC is */
1280 /* master, ADC is enabled and conversion is started. */
1281 if (__HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) )
1282 {
1283 hadc->Instance->CR |= ADC_CR_ADSTART;
1284 }
1285 }
1286
1287 /* Process unlocked */
1288 __HAL_UNLOCK(hadc);
1289
1290 /* Return function status */
1291 return tmpHALStatus;
1292 }
1293 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
1294 /* STM32F302xC || STM32F303xC || STM32F358xx || */
1295 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
1296 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
1297
1298 #if defined(STM32F373xC) || defined(STM32F378xx)
1299 /**
1300 * @brief Enables ADC, starts conversion of regular group.
1301 * Interruptions enabled in this function: None.
1302 * @param hadc: ADC handle
1303 * @retval HAL status
1304 */
1305 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
1306 {
1307 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
1308
1309 /* Check the parameters */
1310 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1311
1312 /* Process locked */
1313 __HAL_LOCK(hadc);
1314
1315 /* Enable the ADC peripheral */
1316 tmpHALStatus = ADC_Enable(hadc);
1317
1318 /* Start conversion if ADC is effectively enabled */
1319 if (tmpHALStatus != HAL_ERROR)
1320 {
1321 /* State machine update: Check if an injected conversion is ongoing */
1322 if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
1323 {
1324 /* Change ADC state */
1325 hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
1326 }
1327 else
1328 {
1329 /* Change ADC state */
1330 hadc->State = HAL_ADC_STATE_BUSY_REG;
1331 }
1332
1333 /* Set ADC error code to none */
1334 __HAL_ADC_CLEAR_ERRORCODE(hadc);
1335
1336 /* Clear regular group conversion flag and overrun flag */
1337 /* (To ensure of no unknown state from potential previous ADC operations) */
1338 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
1339
1340 /* Start conversion of regular group if software start has been selected. */
1341 /* If external trigger has been selected, conversion will start at next */
1342 /* trigger event. */
1343 /* Note: Alternate trigger for single conversion could be to force an */
1344 /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
1345 if (__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc))
1346 {
1347 /* Start ADC conversion on regular group */
1348 hadc->Instance->CR2 |= ADC_CR2_SWSTART;
1349 }
1350 }
1351
1352 /* Process unlocked */
1353 __HAL_UNLOCK(hadc);
1354
1355 /* Return function status */
1356 return tmpHALStatus;
1357 }
1358 #endif /* STM32F373xC || STM32F378xx */
1359
1360 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
1361 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
1362 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
1363 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
1364 /**
1365 * @brief Stop ADC conversion of regular group (and injected group in
1366 * case of auto_injection mode), disable ADC peripheral.
1367 * @note: ADC peripheral disable is forcing interruption of potential
1368 * conversion on injected group. If injected group is under use, it
1369 * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
1370 * @param hadc: ADC handle
1371 * @retval HAL status.
1372 */
1373 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
1374 {
1375 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
1376
1377 /* Check the parameters */
1378 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1379
1380 /* Process locked */
1381 __HAL_LOCK(hadc);
1382
1383 /* 1. Stop potential conversion on going, on regular and injected groups */
1384 tmpHALStatus = ADC_ConversionStop(hadc, REGULAR_INJECTED_GROUP);
1385
1386 /* Disable ADC peripheral if conversions are effectively stopped */
1387 if (tmpHALStatus != HAL_ERROR)
1388 {
1389 /* 2. Disable the ADC peripheral */
1390 tmpHALStatus = ADC_Disable(hadc);
1391
1392 /* Check if ADC is effectively disabled */
1393 if (tmpHALStatus != HAL_ERROR)
1394 {
1395 /* Change ADC state */
1396 hadc->State = HAL_ADC_STATE_READY;
1397 }
1398 }
1399
1400 /* Process unlocked */
1401 __HAL_UNLOCK(hadc);
1402
1403 /* Return function status */
1404 return tmpHALStatus;
1405 }
1406 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
1407 /* STM32F302xC || STM32F303xC || STM32F358xx || */
1408 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
1409 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
1410
1411 #if defined(STM32F373xC) || defined(STM32F378xx)
1412 /**
1413 * @brief Stop ADC conversion of regular group (and injected channels in
1414 * case of auto_injection mode), disable ADC peripheral.
1415 * @note: ADC peripheral disable is forcing interruption of potential
1416 * conversion on injected group. If injected group is under use, it
1417 * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
1418 * @param hadc: ADC handle
1419 * @retval HAL status.
1420 */
1421 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
1422 {
1423 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
1424
1425 /* Check the parameters */
1426 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1427
1428 /* Process locked */
1429 __HAL_LOCK(hadc);
1430
1431 /* Stop potential conversion on going, on regular and injected groups */
1432 /* Disable ADC peripheral */
1433 tmpHALStatus = ADC_ConversionStop_Disable(hadc);
1434
1435 /* Check if ADC is effectively disabled */
1436 if (tmpHALStatus != HAL_ERROR)
1437 {
1438 /* Change ADC state */
1439 hadc->State = HAL_ADC_STATE_READY;
1440 }
1441
1442 /* Process unlocked */
1443 __HAL_UNLOCK(hadc);
1444
1445 /* Return function status */
1446 return tmpHALStatus;
1447 }
1448 #endif /* STM32F373xC || STM32F378xx */
1449
1450 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
1451 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
1452 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
1453 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
1454 /**
1455 * @brief Wait for regular group conversion to be completed.
1456 * @param hadc: ADC handle
1457 * @param Timeout: Timeout value in millisecond.
1458 * @retval HAL status
1459 */
1460 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
1461 {
1462 uint32_t tickstart;
1463 uint32_t tmp_Flag_EOC;
1464
1465 /* Check the parameters */
1466 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1467
1468 /* If end of conversion selected to end of sequence */
1469 if (hadc->Init.EOCSelection == EOC_SEQ_CONV)
1470 {
1471 tmp_Flag_EOC = ADC_FLAG_EOS;
1472 }
1473 /* If end of conversion selected to end of each conversion */
1474 else /* EOC_SINGLE_CONV */
1475 {
1476 tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS);
1477 }
1478
1479 /* Get timeout */
1480 tickstart = HAL_GetTick();
1481
1482 /* Wait until End of Conversion flag is raised */
1483 while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
1484 {
1485 /* Check if timeout is disabled (set to infinite wait) */
1486 if(Timeout != HAL_MAX_DELAY)
1487 {
1488 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
1489 {
1490 /* Update ADC state machine to timeout */
1491 hadc->State = HAL_ADC_STATE_TIMEOUT;
1492
1493 /* Process unlocked */
1494 __HAL_UNLOCK(hadc);
1495
1496 return HAL_ERROR;
1497 }
1498 }
1499 }
1500
1501 /* Clear end of conversion flag of regular group if low power feature */
1502 /* "LowPowerAutoWait " is disabled, to not interfere with this feature */
1503 /* until data register is read using function HAL_ADC_GetValue(). */
1504 if (hadc->Init.LowPowerAutoWait == DISABLE)
1505 {
1506 /* Clear regular group conversion flag */
1507 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
1508 }
1509
1510 /* Update state machine on conversion status if not in error state */
1511 if(hadc->State != HAL_ADC_STATE_ERROR)
1512 {
1513 /* Update ADC state machine */
1514 if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG)
1515 {
1516 /* Check if a conversion is ready on injected group */
1517 if(hadc->State == HAL_ADC_STATE_EOC_INJ)
1518 {
1519 /* Change ADC state */
1520 hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
1521 }
1522 else
1523 {
1524 /* Change ADC state */
1525 hadc->State = HAL_ADC_STATE_EOC_REG;
1526 }
1527 }
1528 }
1529
1530 /* Return ADC state */
1531 return HAL_OK;
1532 }
1533 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
1534 /* STM32F302xC || STM32F303xC || STM32F358xx || */
1535 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
1536 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
1537
1538 #if defined(STM32F373xC) || defined(STM32F378xx)
1539 /**
1540 * @brief Wait for regular group conversion to be completed.
1541 * @param hadc: ADC handle
1542 * @param Timeout: Timeout value in millisecond.
1543 * @retval HAL status
1544 */
1545 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
1546 {
1547 uint32_t tickstart;
1548
1549 /* Variables for polling in case of scan mode enabled */
1550 uint32_t Conversion_Timeout_CPU_cycles_max =0;
1551 uint32_t Conversion_Timeout_CPU_cycles =0;
1552
1553 /* Check the parameters */
1554 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1555
1556 /* Get timeout */
1557 tickstart = HAL_GetTick();
1558
1559 /* Polling for end of conversion: differentiation if single/sequence */
1560 /* conversion. */
1561 /* - If single conversion for regular group (Scan mode disabled or enabled */
1562 /* with NbrOfConversion =1), flag EOC is used to determine the */
1563 /* conversion completion. */
1564 /* - If sequence conversion for regular group, flag EOC is set only a the */
1565 /* end of the sequence. To poll for each conversion, the maximum */
1566 /* conversion time is calculated from ADC conversion time (selected */
1567 /* sampling time + conversion time of 12.5 ADC clock cycles) and */
1568 /* APB2/ADC clock prescalers (depending on settings, conversion time */
1569 /* range can be from 28 to 32256 CPU cycles). */
1570 if ((HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_SCAN)) &&
1571 ((hadc->Instance->SQR1 & ADC_SQR1_L) == RESET) )
1572 {
1573 /* Wait until End of Conversion flag is raised */
1574 while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC))
1575 {
1576 /* Check if timeout is disabled (set to infinite wait) */
1577 if(Timeout != HAL_MAX_DELAY)
1578 {
1579 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
1580 {
1581 /* Update ADC state machine to timeout */
1582 hadc->State = HAL_ADC_STATE_TIMEOUT;
1583
1584 /* Process unlocked */
1585 __HAL_UNLOCK(hadc);
1586
1587 return HAL_ERROR;
1588 }
1589 }
1590 }
1591 }
1592 else
1593 {
1594 /* Computation of CPU cycles corresponding to ADC conversion cycles */
1595 /* Retrieve ADC clock prescaler and ADC maximum conversion cycles on all */
1596 /* channels. */
1597 Conversion_Timeout_CPU_cycles_max = __HAL_ADC_CLOCK_PRECSALER_RANGE() ;
1598 Conversion_Timeout_CPU_cycles_max *= __HAL_ADC_CONVCYCLES_MAX_RANGE(hadc);
1599
1600 /* Maximum conversion cycles taking in account offset of 34 CPU cycles: */
1601 /* number of CPU cycles for processing of conversion cycles estimation. */
1602 Conversion_Timeout_CPU_cycles = 34;
1603
1604 /* Poll with maximum conversion time */
1605 while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
1606 {
1607 /* Check if timeout is disabled (set to infinite wait) */
1608 if(Timeout != HAL_MAX_DELAY)
1609 {
1610 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
1611 {
1612 /* Update ADC state machine to timeout */
1613 hadc->State = HAL_ADC_STATE_TIMEOUT;
1614
1615 /* Process unlocked */
1616 __HAL_UNLOCK(hadc);
1617
1618 return HAL_ERROR;
1619 }
1620 }
1621 Conversion_Timeout_CPU_cycles ++;
1622 }
1623 }
1624
1625 /* Clear regular group conversion flag */
1626 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
1627
1628 /* Update state machine on conversion status if not in error state */
1629 if(hadc->State != HAL_ADC_STATE_ERROR)
1630 {
1631 /* Update ADC state machine */
1632 if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG)
1633 {
1634 /* Check if a conversion is ready on injected group */
1635 if(hadc->State == HAL_ADC_STATE_EOC_INJ)
1636 {
1637 /* Change ADC state */
1638 hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
1639 }
1640 else
1641 {
1642 /* Change ADC state */
1643 hadc->State = HAL_ADC_STATE_EOC_REG;
1644 }
1645 }
1646 }
1647
1648 /* Return ADC state */
1649 return HAL_OK;
1650 }
1651 #endif /* STM32F373xC || STM32F378xx */
1652
1653 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
1654 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
1655 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
1656 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
1657 /**
1658 * @brief Poll for conversion event.
1659 * @param hadc: ADC handle
1660 * @param EventType: the ADC event type.
1661 * This parameter can be one of the following values:
1662 * @arg AWD_EVENT: ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
1663 * @arg AWD2_EVENT: ADC Analog watchdog 2 event (additional analog watchdog, present only on STM32F3 devices)
1664 * @arg AWD3_EVENT: ADC Analog watchdog 3 event (additional analog watchdog, present only on STM32F3 devices)
1665 * @arg OVR_EVENT: ADC Overrun event
1666 * @arg JQOVF_EVENT: ADC Injected context queue overflow event
1667 * @param Timeout: Timeout value in millisecond.
1668 * @retval HAL status
1669 */
1670 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
1671 {
1672 uint32_t tickstart;
1673
1674 /* Check the parameters */
1675 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1676 assert_param(IS_ADC_EVENT_TYPE(EventType));
1677
1678 tickstart = HAL_GetTick();
1679
1680 /* Check selected event flag */
1681 while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
1682 {
1683 /* Check if timeout is disabled (set to infinite wait) */
1684 if(Timeout != HAL_MAX_DELAY)
1685 {
1686 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
1687 {
1688 /* Update ADC state machine to timeout */
1689 hadc->State = HAL_ADC_STATE_TIMEOUT;
1690
1691 /* Process unlocked */
1692 __HAL_UNLOCK(hadc);
1693
1694 return HAL_ERROR;
1695 }
1696 }
1697 }
1698
1699
1700 switch(EventType)
1701 {
1702 /* Analog watchdog (level out of window) event */
1703 /* Note: In case of several analog watchdog enabled, if needed to know */
1704 /* which one triggered and on which ADCx, test ADC state of Analog Watchdog */
1705 /* flags HAL_ADC_STATE_AWD/2/3 function. */
1706 /* For example: "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD) " */
1707 /* "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD2)" */
1708 /* "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD3)" */
1709 /* Check analog watchdog 1 flag */
1710 case AWD_EVENT:
1711 /* Change ADC state */
1712 hadc->State = HAL_ADC_STATE_AWD;
1713
1714 /* Clear ADC analog watchdog flag */
1715 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
1716 break;
1717
1718 /* Check analog watchdog 2 flag */
1719 case AWD2_EVENT:
1720 /* Change ADC state */
1721 hadc->State = HAL_ADC_STATE_AWD2;
1722
1723 /* Clear ADC analog watchdog flag */
1724 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
1725 break;
1726
1727 /* Check analog watchdog 3 flag */
1728 case AWD3_EVENT:
1729 /* Change ADC state */
1730 hadc->State = HAL_ADC_STATE_AWD3;
1731
1732 /* Clear ADC analog watchdog flag */
1733 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
1734 break;
1735
1736 /* Injected context queue overflow event */
1737 case JQOVF_EVENT:
1738 /* Change ADC state */
1739 hadc->State = HAL_ADC_STATE_ERROR;
1740
1741 /* Set ADC error code to Injected context queue overflow */
1742 hadc->ErrorCode |= HAL_ADC_ERROR_JQOVF;
1743
1744 /* Clear ADC Injected context queue overflow flag */
1745 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
1746 break;
1747
1748 /* Overrun event */
1749 default: /* Case OVR_EVENT */
1750 /* If overrun is set to overwrite previous data, overrun event is not */
1751 /* considered as an error. */
1752 /* (cf ref manual "Managing conversions without using the DMA and without */
1753 /* overrun ") */
1754 if (hadc->Init.Overrun == OVR_DATA_PRESERVED)
1755 {
1756 /* Change ADC state */
1757 hadc->State = HAL_ADC_STATE_ERROR;
1758
1759 /* Set ADC error code to overrun */
1760 hadc->ErrorCode |= HAL_ADC_ERROR_OVR;
1761 }
1762
1763 /* Clear ADC Overrun flag */
1764 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1765 break;
1766 }
1767
1768 /* Return ADC state */
1769 return HAL_OK;
1770 }
1771 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
1772 /* STM32F302xC || STM32F303xC || STM32F358xx || */
1773 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
1774 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
1775
1776 #if defined(STM32F373xC) || defined(STM32F378xx)
1777 /**
1778 * @brief Poll for conversion event.
1779 * @param hadc: ADC handle
1780 * @param EventType: the ADC event type.
1781 * This parameter can be one of the following values:
1782 * @arg AWD_EVENT: ADC Analog watchdog event.
1783 * @param Timeout: Timeout value in millisecond.
1784 * @retval HAL status
1785 */
1786 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
1787 {
1788 uint32_t tickstart;
1789
1790 /* Check the parameters */
1791 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1792 assert_param(IS_ADC_EVENT_TYPE(EventType));
1793
1794 tickstart = HAL_GetTick();
1795
1796 /* Check selected event flag */
1797 while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
1798 {
1799 /* Check if timeout is disabled (set to infinite wait) */
1800 if(Timeout != HAL_MAX_DELAY)
1801 {
1802 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
1803 {
1804 /* Update ADC state machine to timeout */
1805 hadc->State = HAL_ADC_STATE_TIMEOUT;
1806
1807 /* Process unlocked */
1808 __HAL_UNLOCK(hadc);
1809
1810 return HAL_ERROR;
1811 }
1812 }
1813 }
1814
1815 /* Analog watchdog (level out of window) event */
1816 /* Change ADC state */
1817 hadc->State = HAL_ADC_STATE_AWD;
1818
1819 /* Clear ADC analog watchdog flag */
1820 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
1821
1822 /* Return ADC state */
1823 return HAL_OK;
1824 }
1825 #endif /* STM32F373xC || STM32F378xx */
1826
1827 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
1828 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
1829 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
1830 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
1831 /**
1832 * @brief Enables ADC, starts conversion of regular group with interruption.
1833 * Interruptions enabled in this function: EOC (end of conversion),
1834 * overrun (if available).
1835 * Each of these interruptions has its dedicated callback function.
1836 * @note: Case of multimode enabled (for devices with several ADCs): This
1837 * function must be called for ADC slave first, then ADC master.
1838 * For ADC slave, ADC is enabled only (conversion is not started).
1839 * For ADC master, ADC is enabled and multimode conversion is started.
1840 * @param hadc: ADC handle
1841 * @retval HAL status
1842 */
1843 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
1844 {
1845 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
1846
1847 /* Check the parameters */
1848 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1849
1850 /* Process locked */
1851 __HAL_LOCK(hadc);
1852
1853 /* Enable the ADC peripheral */
1854 tmpHALStatus = ADC_Enable(hadc);
1855
1856 /* Start conversion if ADC is effectively enabled */
1857 if (tmpHALStatus != HAL_ERROR)
1858 {
1859 /* State machine update: Check if an injected conversion is ongoing */
1860 if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
1861 {
1862 /* Change ADC state */
1863 hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
1864 }
1865 else
1866 {
1867 /* Change ADC state */
1868 hadc->State = HAL_ADC_STATE_BUSY_REG;
1869 }
1870
1871 /* Set ADC error code to none */
1872 __HAL_ADC_CLEAR_ERRORCODE(hadc);
1873
1874 /* Clear regular group conversion flag and overrun flag */
1875 /* (To ensure of no unknown state from potential previous ADC operations) */
1876 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
1877
1878 /* Enable ADC end of conversion interrupt */
1879 /* Enable ADC overrun interrupt */
1880 switch(hadc->Init.EOCSelection)
1881 {
1882 case EOC_SEQ_CONV:
1883 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
1884 __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOS | ADC_IT_OVR));
1885 break;
1886 /* case EOC_SINGLE_CONV */
1887 default:
1888 __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
1889 break;
1890 }
1891
1892 /* Enable conversion of regular group. */
1893 /* If software start has been selected, conversion starts immediately. */
1894 /* If external trigger has been selected, conversion will start at next */
1895 /* trigger event. */
1896 /* Case of multimode enabled (for devices with several ADCs): if ADC is */
1897 /* slave, ADC is enabled only (conversion is not started). If ADC is */
1898 /* master, ADC is enabled and conversion is started. */
1899 if (__HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) )
1900 {
1901 hadc->Instance->CR |= ADC_CR_ADSTART;
1902 }
1903 }
1904
1905 /* Process unlocked */
1906 __HAL_UNLOCK(hadc);
1907
1908 /* Return function status */
1909 return tmpHALStatus;
1910 }
1911 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
1912 /* STM32F302xC || STM32F303xC || STM32F358xx || */
1913 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
1914 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
1915
1916 #if defined(STM32F373xC) || defined(STM32F378xx)
1917 /**
1918 * @brief Enables ADC, starts conversion of regular group with interruption.
1919 * Interruptions enabled in this function: EOC (end of conversion),
1920 * overrun (if available).
1921 * Each of these interruptions has its dedicated callback function.
1922 * @param hadc: ADC handle
1923 * @retval HAL status
1924 */
1925 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
1926 {
1927 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
1928
1929 /* Check the parameters */
1930 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1931
1932 /* Process locked */
1933 __HAL_LOCK(hadc);
1934
1935 /* Enable the ADC peripheral */
1936 tmpHALStatus = ADC_Enable(hadc);
1937
1938 /* Start conversion if ADC is effectively enabled */
1939 if (tmpHALStatus != HAL_ERROR)
1940 {
1941 /* State machine update: Check if an injected conversion is ongoing */
1942 if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
1943 {
1944 /* Change ADC state */
1945 hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
1946 }
1947 else
1948 {
1949 /* Change ADC state */
1950 hadc->State = HAL_ADC_STATE_BUSY_REG;
1951 }
1952
1953 /* Set ADC error code to none */
1954 __HAL_ADC_CLEAR_ERRORCODE(hadc);
1955
1956 /* Clear regular group conversion flag and overrun flag */
1957 /* (To ensure of no unknown state from potential previous ADC operations) */
1958 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
1959
1960 /* Enable end of conversion interrupt for regular group */
1961 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
1962
1963 /* Start conversion of regular group if software start has been selected. */
1964 /* If external trigger has been selected, conversion will start at next */
1965 /* trigger event. */
1966 if (__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc))
1967 {
1968 /* Start ADC conversion on regular group */
1969 hadc->Instance->CR2 |= ADC_CR2_SWSTART;
1970 }
1971 }
1972
1973 /* Process unlocked */
1974 __HAL_UNLOCK(hadc);
1975
1976 /* Return function status */
1977 return tmpHALStatus;
1978 }
1979 #endif /* STM32F373xC || STM32F378xx */
1980
1981 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
1982 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
1983 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
1984 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
1985 /**
1986 * @brief Stop ADC conversion of regular group (and injected group in
1987 * case of auto_injection mode), disable interruption of
1988 * end-of-conversion, disable ADC peripheral.
1989 * @note: ADC peripheral disable is forcing interruption of potential
1990 * conversion on injected group. If injected group is under use, it
1991 * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
1992 * @param hadc: ADC handle
1993 * @retval HAL status.
1994 */
1995 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
1996 {
1997 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
1998
1999 /* Check the parameters */
2000 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2001
2002 /* Process locked */
2003 __HAL_LOCK(hadc);
2004
2005 /* 1. Stop potential conversion on going, on regular and injected groups */
2006 tmpHALStatus = ADC_ConversionStop(hadc, REGULAR_INJECTED_GROUP);
2007
2008 /* Disable ADC peripheral if conversions are effectively stopped */
2009 if (tmpHALStatus != HAL_ERROR)
2010 {
2011 /* Disable ADC end of conversion interrupt for regular group */
2012 /* Disable ADC overrun interrupt */
2013 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
2014
2015 /* 2. Disable the ADC peripheral */
2016 tmpHALStatus = ADC_Disable(hadc);
2017
2018 /* Check if ADC is effectively disabled */
2019 if (tmpHALStatus != HAL_ERROR)
2020 {
2021 /* Change ADC state */
2022 hadc->State = HAL_ADC_STATE_READY;
2023 }
2024 }
2025
2026 /* Process unlocked */
2027 __HAL_UNLOCK(hadc);
2028
2029 /* Return function status */
2030 return tmpHALStatus;
2031 }
2032 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2033 /* STM32F302xC || STM32F303xC || STM32F358xx || */
2034 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2035 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2036
2037 #if defined(STM32F373xC) || defined(STM32F378xx)
2038 /**
2039 * @brief Stop ADC conversion of regular group (and injected group in
2040 * case of auto_injection mode), disable interrution of
2041 * end-of-conversion, disable ADC peripheral.
2042 * @param hadc: ADC handle
2043 * @retval None
2044 */
2045 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
2046 {
2047 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
2048
2049 /* Check the parameters */
2050 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2051
2052 /* Process locked */
2053 __HAL_LOCK(hadc);
2054
2055 /* Stop potential conversion on going, on regular and injected groups */
2056 /* Disable ADC peripheral */
2057 tmpHALStatus = ADC_ConversionStop_Disable(hadc);
2058
2059 /* Check if ADC is effectively disabled */
2060 if (tmpHALStatus != HAL_ERROR)
2061 {
2062 /* Disable ADC end of conversion interrupt for regular group */
2063 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
2064
2065 /* Change ADC state */
2066 hadc->State = HAL_ADC_STATE_READY;
2067 }
2068
2069 /* Process unlocked */
2070 __HAL_UNLOCK(hadc);
2071
2072 /* Return function status */
2073 return tmpHALStatus;
2074 }
2075 #endif /* STM32F373xC || STM32F378xx */
2076
2077 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
2078 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
2079 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
2080 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2081 /**
2082 * @brief Enables ADC, starts conversion of regular group and transfers result
2083 * through DMA.
2084 * Interruptions enabled in this function:
2085 * overrun (if available), DMA half transfer, DMA transfer complete.
2086 * Each of these interruptions has its dedicated callback function.
2087 * @note: Case of multimode enabled (for devices with several ADCs): This
2088 * function is for single-ADC mode only. For multimode, use the
2089 * dedicated MultimodeStart function.
2090 * @param hadc: ADC handle
2091 * @param pData: The destination Buffer address.
2092 * @param Length: The length of data to be transferred from ADC peripheral to memory.
2093 * @retval None
2094 */
2095 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
2096 {
2097 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
2098
2099 /* Check the parameters */
2100 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2101
2102 /* Process locked */
2103 __HAL_LOCK(hadc);
2104
2105 /* Verification if multimode is disabled (for devices with several ADC) */
2106 /* If multimode is enabled, dedicated function multimode conversion */
2107 /* start DMA must be used. */
2108 if(__HAL_ADC_COMMON_CCR_MULTI(hadc) == RESET)
2109 {
2110
2111 /* Enable the ADC peripheral */
2112 tmpHALStatus = ADC_Enable(hadc);
2113
2114 /* Start conversion if ADC is effectively enabled */
2115 if (tmpHALStatus != HAL_ERROR)
2116 {
2117 /* State machine update: Check if an injected conversion is ongoing */
2118 if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
2119 {
2120 /* Change ADC state */
2121 hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
2122 }
2123 else
2124 {
2125 /* Change ADC state */
2126 hadc->State = HAL_ADC_STATE_BUSY_REG;
2127 }
2128
2129 /* Set ADC error code to none */
2130 __HAL_ADC_CLEAR_ERRORCODE(hadc);
2131
2132
2133 /* Set the DMA transfer complete callback */
2134 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
2135
2136 /* Set the DMA half transfer complete callback */
2137 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
2138
2139 /* Set the DMA error callback */
2140 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
2141
2142
2143 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
2144 /* start (in case of SW start): */
2145
2146 /* Clear regular group conversion flag and overrun flag */
2147 /* (To ensure of no unknown state from potential previous ADC */
2148 /* operations) */
2149 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
2150
2151 /* Enable ADC overrun interrupt */
2152 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
2153
2154 /* Enable ADC DMA mode */
2155 hadc->Instance->CFGR |= ADC_CFGR_DMAEN;
2156
2157 /* Start the DMA channel */
2158 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
2159
2160 /* Enable conversion of regular group. */
2161 /* If software start has been selected, conversion starts immediately. */
2162 /* If external trigger has been selected, conversion will start at next */
2163 /* trigger event. */
2164 hadc->Instance->CR |= ADC_CR_ADSTART;
2165
2166 }
2167 }
2168 else
2169 {
2170 tmpHALStatus = HAL_ERROR;
2171 }
2172
2173 /* Process unlocked */
2174 __HAL_UNLOCK(hadc);
2175
2176 /* Return function status */
2177 return tmpHALStatus;
2178 }
2179 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2180 /* STM32F302xC || STM32F303xC || STM32F358xx || */
2181 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2182 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2183
2184 #if defined(STM32F373xC) || defined(STM32F378xx)
2185 /**
2186 * @brief Enables ADC, starts conversion of regular group and transfers result
2187 * through DMA.
2188 * Interruptions enabled in this function:
2189 * overrun (if available), DMA half transfer, DMA transfer complete.
2190 * Each of these interruptions has its dedicated callback function.
2191 * @note For devices with several ADCs: This function is for single-ADC mode
2192 * only. For multimode, use the dedicated MultimodeStart function.
2193 * @param hadc: ADC handle
2194 * @param pData: The destination Buffer address.
2195 * @param Length: The length of data to be transferred from ADC peripheral to memory.
2196 * @retval None
2197 */
2198 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
2199 {
2200 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
2201
2202 /* Check the parameters */
2203 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2204
2205 /* Process locked */
2206 __HAL_LOCK(hadc);
2207
2208 /* Enable the ADC peripheral */
2209 tmpHALStatus = ADC_Enable(hadc);
2210
2211 /* Start conversion if ADC is effectively enabled */
2212 if (tmpHALStatus != HAL_ERROR)
2213 {
2214 /* State machine update: Check if an injected conversion is ongoing */
2215 if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
2216 {
2217 /* Change ADC state */
2218 hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
2219 }
2220 else
2221 {
2222 /* Change ADC state */
2223 hadc->State = HAL_ADC_STATE_BUSY_REG;
2224 }
2225
2226 /* Set ADC error code to none */
2227 __HAL_ADC_CLEAR_ERRORCODE(hadc);
2228
2229
2230 /* Set the DMA transfer complete callback */
2231 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
2232
2233 /* Set the DMA half transfer complete callback */
2234 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
2235
2236 /* Set the DMA error callback */
2237 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
2238
2239
2240 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
2241 /* start (in case of SW start): */
2242
2243 /* Clear regular group conversion flag and overrun flag */
2244 /* (To ensure of no unknown state from potential previous ADC operations) */
2245 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
2246
2247 /* Enable ADC DMA mode */
2248 hadc->Instance->CR2 |= ADC_CR2_DMA;
2249
2250 /* Start the DMA channel */
2251 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
2252
2253 /* Start conversion of regular group if software start has been selected. */
2254 /* If external trigger has been selected, conversion will start at next */
2255 /* trigger event. */
2256 /* Note: Alternate trigger for single conversion could be to force an */
2257 /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
2258 if (__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc))
2259 {
2260 /* Start ADC conversion on regular group */
2261 hadc->Instance->CR2 |= ADC_CR2_SWSTART;
2262 }
2263 }
2264
2265 /* Process unlocked */
2266 __HAL_UNLOCK(hadc);
2267
2268 /* Return function status */
2269 return tmpHALStatus;
2270 }
2271 #endif /* STM32F373xC || STM32F378xx */
2272
2273 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
2274 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
2275 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
2276 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2277 /**
2278 * @brief Stop ADC conversion of regular group (and injected channels in
2279 * case of auto_injection mode), disable ADC DMA transfer, disable
2280 * ADC peripheral.
2281 * Each of these interruptions has its dedicated callback function.
2282 * @note: ADC peripheral disable is forcing interruption of potential
2283 * conversion on injected group. If injected group is under use, it
2284 * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
2285 * @note: Case of multimode enabled (for devices with several ADCs): This
2286 * function is for single-ADC mode only. For multimode, use the
2287 * dedicated MultimodeStop function.
2288 * @param hadc: ADC handle
2289 * @retval HAL status.
2290 */
2291 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
2292 {
2293 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
2294
2295 /* Check the parameters */
2296 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2297
2298 /* Process locked */
2299 __HAL_LOCK(hadc);
2300
2301 /* 1. Stop potential conversion on going, on regular and injected groups */
2302 tmpHALStatus = ADC_ConversionStop(hadc, REGULAR_INJECTED_GROUP);
2303
2304 /* Disable ADC peripheral if conversions are effectively stopped */
2305 if (tmpHALStatus == HAL_OK)
2306 {
2307 /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
2308 hadc->Instance->CFGR &= ~ADC_CFGR_DMAEN;
2309
2310 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
2311 /* while DMA transfer is on going) */
2312 tmpHALStatus = HAL_DMA_Abort(hadc->DMA_Handle);
2313
2314 /* Check if DMA channel effectively disabled */
2315 if (tmpHALStatus != HAL_OK)
2316 {
2317 /* Update ADC state machine to error */
2318 hadc->State = HAL_ADC_STATE_ERROR;
2319 }
2320
2321 /* Disable ADC overrun interrupt */
2322 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
2323
2324 /* 2. Disable the ADC peripheral */
2325 /* Update "tmpHALStatus" only if DMA channel disabling passed, to keep in */
2326 /* memory a potential failing status. */
2327 if (tmpHALStatus == HAL_OK)
2328 {
2329 tmpHALStatus = ADC_Disable(hadc);
2330 }
2331 else
2332 {
2333 ADC_Disable(hadc);
2334 }
2335
2336 /* Check if ADC is effectively disabled */
2337 if (tmpHALStatus == HAL_OK)
2338 {
2339 /* Change ADC state */
2340 hadc->State = HAL_ADC_STATE_READY;
2341 }
2342
2343 }
2344
2345 /* Process unlocked */
2346 __HAL_UNLOCK(hadc);
2347
2348 /* Return function status */
2349 return tmpHALStatus;
2350 }
2351 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2352 /* STM32F302xC || STM32F303xC || STM32F358xx || */
2353 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2354 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2355
2356 #if defined(STM32F373xC) || defined(STM32F378xx)
2357 /**
2358 * @brief Stop ADC conversion of regular group (and injected group in
2359 * case of auto_injection mode), disable ADC DMA transfer, disable
2360 * ADC peripheral.
2361 * @note: ADC peripheral disable is forcing interruption of potential
2362 * conversion on injected group. If injected group is under use, it
2363 * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
2364 * @note For devices with several ADCs: This function is for single-ADC mode
2365 * only. For multimode, use the dedicated MultimodeStop function.
2366 * @param hadc: ADC handle
2367 * @retval HAL status.
2368 */
2369 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
2370 {
2371 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
2372
2373 /* Check the parameters */
2374 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2375
2376 /* Process locked */
2377 __HAL_LOCK(hadc);
2378
2379 /* Stop potential conversion on going, on regular and injected groups */
2380 /* Disable ADC peripheral */
2381 tmpHALStatus = ADC_ConversionStop_Disable(hadc);
2382
2383 /* Check if ADC is effectively disabled */
2384 if (tmpHALStatus != HAL_ERROR)
2385 {
2386 /* Disable ADC DMA mode */
2387 hadc->Instance->CR2 &= ~ADC_CR2_DMA;
2388
2389 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
2390 /* while DMA transfer is on going) */
2391 tmpHALStatus = HAL_DMA_Abort(hadc->DMA_Handle);
2392
2393 /* Check if DMA channel effectively disabled */
2394 if (tmpHALStatus == HAL_OK)
2395 {
2396 /* Change ADC state */
2397 hadc->State = HAL_ADC_STATE_READY;
2398 }
2399 else
2400 {
2401 /* Update ADC state machine to error */
2402 hadc->State = HAL_ADC_STATE_ERROR;
2403 }
2404 }
2405
2406 /* Process unlocked */
2407 __HAL_UNLOCK(hadc);
2408
2409 /* Return function status */
2410 return tmpHALStatus;
2411 }
2412 #endif /* STM32F373xC || STM32F378xx */
2413
2414 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
2415 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
2416 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
2417 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2418 /**
2419 * @brief Get ADC regular group conversion result.
2420 * @param hadc: ADC handle
2421 * @retval Converted value
2422 */
2423 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
2424 {
2425 /* Check the parameters */
2426 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2427
2428 /* Note: EOC flag is automatically cleared by hardware when reading */
2429 /* register DR. Additionally, clear flag EOS by software. */
2430
2431 /* Clear regular group conversion flag */
2432 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) );
2433
2434 /* Return ADC converted value */
2435 return hadc->Instance->DR;
2436 }
2437 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2438 /* STM32F302xC || STM32F303xC || STM32F358xx || */
2439 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2440 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2441
2442 #if defined(STM32F373xC) || defined(STM32F378xx)
2443 /**
2444 * @brief Get ADC regular group conversion result.
2445 * @param hadc: ADC handle
2446 * @retval Converted value
2447 */
2448 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
2449 {
2450 /* Check the parameters */
2451 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2452
2453 /* Note: EOC flag is not cleared here by software because automatically */
2454 /* cleared by hardware when reading register DR. */
2455
2456 /* Return ADC converted value */
2457 return hadc->Instance->DR;
2458 }
2459 #endif /* STM32F373xC || STM32F378xx */
2460
2461 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
2462 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
2463 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
2464 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2465 /**
2466 * @brief Handles ADC interrupt request.
2467 * @param hadc: ADC handle
2468 * @retval None
2469 */
2470 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
2471 {
2472 /* Check the parameters */
2473 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2474 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
2475 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
2476
2477 /* ========== Check End of Conversion flag for regular group ========== */
2478 if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) ||
2479 (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOS)) )
2480 {
2481 /* Update state machine on conversion status if not in error state */
2482 if(hadc->State != HAL_ADC_STATE_ERROR)
2483 {
2484 /* Check if an injected conversion is ready */
2485 if(hadc->State == HAL_ADC_STATE_EOC_INJ)
2486 {
2487 /* Change ADC state */
2488 hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
2489 }
2490 else
2491 {
2492 /* Change ADC state */
2493 hadc->State = HAL_ADC_STATE_EOC_REG;
2494 }
2495 }
2496
2497 /* Disable interruption if no further conversion upcoming by regular */
2498 /* external trigger or by continuous mode, */
2499 /* and if scan sequence if completed. */
2500 if(__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
2501 (hadc->Init.ContinuousConvMode == DISABLE) )
2502 {
2503 /* If End of Sequence is reached, disable interrupts */
2504 if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
2505 {
2506 /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
2507 /* ADSTART==0 (no conversion on going) */
2508 if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
2509 {
2510 /* Disable ADC end of sequence conversion interrupt */
2511 /* Note: Overrun interrupt was enabled with EOC interrupt in */
2512 /* HAL_Start_IT(), but is not disabled here because can be used */
2513 /* by overrun IRQ process below. */
2514 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
2515 }
2516 else
2517 {
2518 /* Change ADC state to error state */
2519 hadc->State = HAL_ADC_STATE_ERROR;
2520
2521 /* Set ADC error code to ADC IP internal error */
2522 hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
2523 }
2524 }
2525 }
2526
2527 /* Conversion complete callback */
2528 /* Note: into callback, to determine if conversion has been triggered */
2529 /* from EOC or EOS, possibility to use: */
2530 /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
2531 HAL_ADC_ConvCpltCallback(hadc);
2532
2533
2534 /* Clear regular group conversion flag */
2535 /* Note: in case of overrun set to OVR_DATA_PRESERVED, end of conversion */
2536 /* flags clear induces the release of the preserved data. */
2537 /* Therefore, if the preserved data value is needed, it must be */
2538 /* read preliminarily into HAL_ADC_ConvCpltCallback(). */
2539 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) );
2540 }
2541
2542
2543 /* ========== Check End of Conversion flag for injected group ========== */
2544 if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC)) ||
2545 (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOS)) )
2546 {
2547 /* Update state machine on conversion status if not in error state */
2548 if(hadc->State != HAL_ADC_STATE_ERROR)
2549 {
2550 /* Check if a regular conversion is ready */
2551 if(hadc->State == HAL_ADC_STATE_EOC_REG)
2552 {
2553 /* Change ADC state */
2554 hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
2555 }
2556 else
2557 {
2558 /* Change ADC state */
2559 hadc->State = HAL_ADC_STATE_EOC_INJ;
2560 }
2561 }
2562
2563 /* Disable interruption if no further conversion upcoming by injected */
2564 /* external trigger or by automatic injected conversion with regular */
2565 /* group having no further conversion upcoming (same conditions as */
2566 /* regular group interruption disabling above), */
2567 /* and if injected scan sequence is completed. */
2568 if(__HAL_ADC_IS_SOFTWARE_START_INJECTED(hadc) ||
2569 (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO) &&
2570 (__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
2571 (hadc->Init.ContinuousConvMode == DISABLE) ) ) )
2572 {
2573 /* If End of Sequence is reached, disable interrupts */
2574 if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
2575 {
2576 /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
2577 /* JADSTART==0 (no conversion on going) */
2578 if (__HAL_ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
2579 {
2580 /* Disable ADC end of sequence conversion interrupt */
2581 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
2582 }
2583 else
2584 {
2585 /* Change ADC state to error state */
2586 hadc->State = HAL_ADC_STATE_ERROR;
2587
2588 /* Set ADC error code to ADC IP internal error */
2589 hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
2590 }
2591 }
2592 }
2593
2594 /* Conversion complete callback */
2595 /* Note: into callback, to determine if conversion has been triggered */
2596 /* from JEOC or JEOS, possibility to use: */
2597 /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) " */
2598 HAL_ADCEx_InjectedConvCpltCallback(hadc);
2599
2600 /* Clear injected group conversion flag */
2601 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
2602 }
2603
2604
2605 /* ========== Check Analog watchdog flags ========== */
2606 if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD1) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD1)) ||
2607 (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD2) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD2)) ||
2608 (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD3) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD3)) )
2609 {
2610
2611 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD1) != RESET)
2612 {
2613 /* Change ADC state */
2614 hadc->State = HAL_ADC_STATE_AWD;
2615
2616 /* Clear ADC Analog watchdog flag */
2617 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
2618 }
2619 else if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD2) != RESET)
2620 {
2621 /* Change ADC state */
2622 hadc->State = HAL_ADC_STATE_AWD2;
2623
2624 /* Clear ADC Analog watchdog flag */
2625 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
2626 }
2627 else if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD3) != RESET)
2628 {
2629 /* Change ADC state */
2630 hadc->State = HAL_ADC_STATE_AWD3;
2631
2632 /* Clear ADC Analog watchdog flag */
2633 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
2634 }
2635 else
2636 {
2637 /* Change ADC state to error state */
2638 hadc->State = HAL_ADC_STATE_ERROR;
2639 }
2640
2641 /* Level out of window callback */
2642 /* Note: In case of several analog watchdog enabled, if needed to know */
2643 /* which one triggered and on which ADCx, either: */
2644 /* Test Analog Watchdog flags ADC_FLAG_AWD1/2/3 into function */
2645 /* HAL_ADC_LevelOutOfWindowCallback(). */
2646 /* For example: "if (__HAL_ADC_GET_FLAG(&hadc1, ADC_FLAG_AWD1) != RESET)" */
2647 /* "if (__HAL_ADC_GET_FLAG(&hadc1, ADC_FLAG_AWD2) != RESET)" */
2648 /* "if (__HAL_ADC_GET_FLAG(&hadc1, ADC_FLAG_AWD3) != RESET)" */
2649 /* Test ADC state of Analog Watchdog flags HAL_ADC_STATE_AWD/2/3 into */
2650 /* HAL_ADC_LevelOutOfWindowCallback(). */
2651 /* For example: "if (HAL_ADC_GetState(&hadc1) == HAL_ADC_STATE_AWD) " */
2652 /* "if (HAL_ADC_GetState(&hadc1) == HAL_ADC_STATE_AWD2)" */
2653 /* "if (HAL_ADC_GetState(&hadc1) == HAL_ADC_STATE_AWD3)" */
2654 HAL_ADC_LevelOutOfWindowCallback(hadc);
2655 }
2656
2657
2658 /* ========== Check Overrun flag ========== */
2659 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR))
2660 {
2661 /* If overrun is set to overwrite previous data (default setting), */
2662 /* overrun event is not considered as an error. */
2663 /* (cf ref manual "Managing conversions without using the DMA and without */
2664 /* overrun ") */
2665 /* Exception for usage with DMA overrun event always considered as an */
2666 /* error. */
2667 if ((hadc->Init.Overrun == OVR_DATA_PRESERVED) ||
2668 HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN) )
2669 {
2670 /* Change ADC state to error state */
2671 hadc->State = HAL_ADC_STATE_ERROR;
2672
2673 /* Set ADC error code to overrun */
2674 hadc->ErrorCode |= HAL_ADC_ERROR_OVR;
2675
2676 /* Error callback */
2677 HAL_ADC_ErrorCallback(hadc);
2678 }
2679
2680 /* Clear the Overrun flag */
2681 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
2682
2683 }
2684
2685
2686 /* ========== Check Injected context queue overflow flag ========== */
2687 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JQOVF) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JQOVF))
2688 {
2689 /* Change ADC state to overrun state */
2690 hadc->State = HAL_ADC_STATE_ERROR;
2691
2692 /* Set ADC error code to Injected context queue overflow */
2693 hadc->ErrorCode |= HAL_ADC_ERROR_JQOVF;
2694
2695 /* Clear the Injected context queue overflow flag */
2696 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
2697
2698 /* Error callback */
2699 HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
2700 }
2701
2702 }
2703 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2704 /* STM32F302xC || STM32F303xC || STM32F358xx || */
2705 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2706 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2707
2708 #if defined(STM32F373xC) || defined(STM32F378xx)
2709 /**
2710 * @brief Handles ADC interrupt request
2711 * @param hadc: ADC handle
2712 * @retval None
2713 */
2714 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
2715 {
2716 /* Check the parameters */
2717 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2718 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
2719 assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
2720
2721
2722 /* ========== Check End of Conversion flag for regular group ========== */
2723 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC))
2724 {
2725 /* Check if an injected conversion is ready */
2726 if(hadc->State == HAL_ADC_STATE_EOC_INJ)
2727 {
2728 /* Change ADC state */
2729 hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
2730 }
2731 else
2732 {
2733 /* Change ADC state */
2734 hadc->State = HAL_ADC_STATE_EOC_REG;
2735 }
2736
2737 /* Disable interruption if no further conversion upcoming regular */
2738 /* external trigger or by continuous mode */
2739 if(__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
2740 (hadc->Init.ContinuousConvMode == DISABLE) )
2741 {
2742 /* Disable ADC end of single conversion interrupt */
2743 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
2744 }
2745
2746 /* Conversion complete callback */
2747 HAL_ADC_ConvCpltCallback(hadc);
2748
2749 /* Clear regular group conversion flag */
2750 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
2751 }
2752
2753
2754 /* ========== Check End of Conversion flag for injected group ========== */
2755 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC))
2756 {
2757 /* Check if a regular conversion is ready */
2758 if(hadc->State == HAL_ADC_STATE_EOC_REG)
2759 {
2760 /* Change ADC state */
2761 hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
2762 }
2763 else
2764 {
2765 /* Change ADC state */
2766 hadc->State = HAL_ADC_STATE_EOC_INJ;
2767 }
2768
2769 /* Disable interruption if no further conversion upcoming injected */
2770 /* external trigger or by automatic injected conversion with regular */
2771 /* group having no further conversion upcoming (same conditions as */
2772 /* regular group interruption disabling above). */
2773 if(__HAL_ADC_IS_SOFTWARE_START_INJECTED(hadc) ||
2774 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
2775 (__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
2776 (hadc->Init.ContinuousConvMode == DISABLE) ) ) )
2777 {
2778 /* Disable ADC end of single conversion interrupt */
2779 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
2780 }
2781
2782 /* Conversion complete callback */
2783 HAL_ADCEx_InjectedConvCpltCallback(hadc);
2784
2785 /* Clear injected group conversion flag (and regular conversion flag raised simultaneously) */
2786 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC | ADC_FLAG_EOC));
2787 }
2788
2789
2790 /* ========== Check Analog watchdog flags ========== */
2791 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
2792 {
2793 /* Change ADC state */
2794 hadc->State = HAL_ADC_STATE_AWD;
2795
2796 /* Clear the ADCx's Analog watchdog flag */
2797 __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_AWD);
2798
2799 /* Level out of window callback */
2800 HAL_ADC_LevelOutOfWindowCallback(hadc);
2801 }
2802
2803 }
2804 #endif /* STM32F373xC || STM32F378xx */
2805
2806
2807 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
2808 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
2809 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
2810 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2811 /**
2812 * @brief Perform an ADC automatic self-calibration
2813 * Calibration prerequisite: ADC must be disabled (execute this
2814 * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
2815 * @param hadc: ADC handle
2816 * @param SingleDiff: Selection of single-ended or differential input
2817 * This parameter can be one of the following values:
2818 * @arg ADC_SINGLE_ENDED: Channel in mode input single ended
2819 * @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
2820 * @retval HAL status
2821 */
2822 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
2823 {
2824 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
2825 uint32_t tickstart;
2826
2827 /* Check the parameters */
2828 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2829 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
2830
2831 /* Process locked */
2832 __HAL_LOCK(hadc);
2833
2834 /* Calibration prerequisite: ADC must be disabled. */
2835
2836 /* Disable the ADC (if not already disabled) */
2837 tmpHALStatus = ADC_Disable(hadc);
2838
2839 /* Check if ADC is effectively disabled */
2840 if (tmpHALStatus != HAL_ERROR)
2841 {
2842 /* Change ADC state */
2843 hadc->State = HAL_ADC_STATE_READY;
2844
2845 /* Select calibration mode single ended or differential ended */
2846 hadc->Instance->CR &= (~ADC_CR_ADCALDIF);
2847 if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
2848 {
2849 hadc->Instance->CR |= ADC_CR_ADCALDIF;
2850 }
2851
2852 /* Start ADC calibration */
2853 hadc->Instance->CR |= ADC_CR_ADCAL;
2854
2855 tickstart = HAL_GetTick();
2856
2857 /* Wait for calibration completion */
2858 while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL))
2859 {
2860 if((HAL_GetTick()-tickstart) > ADC_CALIBRATION_TIMEOUT)
2861 {
2862 /* Update ADC state machine to error */
2863 hadc->State = HAL_ADC_STATE_ERROR;
2864
2865 /* Process unlocked */
2866 __HAL_UNLOCK(hadc);
2867
2868 return HAL_ERROR;
2869 }
2870 }
2871 }
2872 else
2873 {
2874 /* Update ADC state machine to error */
2875 tmpHALStatus = HAL_ERROR;
2876 }
2877
2878 /* Process unlocked */
2879 __HAL_UNLOCK(hadc);
2880
2881 /* Return function status */
2882 return tmpHALStatus;
2883 }
2884 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2885 /* STM32F302xC || STM32F303xC || STM32F358xx || */
2886 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2887 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2888
2889 #if defined(STM32F373xC) || defined(STM32F378xx)
2890 /**
2891 * @brief Perform an ADC automatic self-calibration
2892 * Calibration prerequisite: ADC must be disabled (execute this
2893 * function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
2894 * During calibration process, ADC is enabled. ADC is let enabled at
2895 * the completion of this function.
2896 * @param hadc: ADC handle
2897 * @retval HAL status
2898 */
2899 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
2900 {
2901 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
2902 uint32_t WaitLoopIndex = 0;
2903 uint32_t tickstart;
2904
2905 /* Check the parameters */
2906 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2907
2908 /* Process locked */
2909 __HAL_LOCK(hadc);
2910
2911 /* 1. Calibration prerequisite: */
2912 /* - ADC must be disabled for at least two ADC clock cycles in disable */
2913 /* mode before ADC enable */
2914 /* Stop potential conversion on going, on regular and injected groups */
2915 /* Disable ADC peripheral */
2916 tmpHALStatus = ADC_ConversionStop_Disable(hadc);
2917
2918 /* Check if ADC is effectively disabled */
2919 if (tmpHALStatus != HAL_ERROR)
2920 {
2921
2922 /* Wait two ADC clock cycles */
2923 while(WaitLoopIndex < ADC_CYCLE_WORST_CASE_CPU_CYCLES *2)
2924 {
2925 WaitLoopIndex++;
2926 }
2927
2928 /* 2. Enable the ADC peripheral */
2929 ADC_Enable(hadc);
2930
2931
2932 /* 3. Resets ADC calibration registers */
2933 hadc->Instance->CR2 |= ADC_CR2_RSTCAL;
2934
2935 tickstart = HAL_GetTick();
2936
2937 /* Wait for calibration reset completion */
2938 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL))
2939 {
2940 if((HAL_GetTick()-tickstart) > ADC_CALIBRATION_TIMEOUT)
2941 {
2942 /* Update ADC state machine to error */
2943 hadc->State = HAL_ADC_STATE_ERROR;
2944
2945 /* Process unlocked */
2946 __HAL_UNLOCK(hadc);
2947
2948 return HAL_ERROR;
2949 }
2950 }
2951
2952
2953 /* 4. Start ADC calibration */
2954 hadc->Instance->CR2 |= ADC_CR2_CAL;
2955
2956 tickstart = HAL_GetTick();
2957
2958 /* Wait for calibration completion */
2959 while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL))
2960 {
2961 if((HAL_GetTick()-tickstart) > ADC_CALIBRATION_TIMEOUT)
2962 {
2963 /* Update ADC state machine to error */
2964 hadc->State = HAL_ADC_STATE_ERROR;
2965
2966 /* Process unlocked */
2967 __HAL_UNLOCK(hadc);
2968
2969 return HAL_ERROR;
2970 }
2971 }
2972
2973 }
2974
2975 /* Process unlocked */
2976 __HAL_UNLOCK(hadc);
2977
2978 /* Return function status */
2979 return tmpHALStatus;
2980 }
2981
2982 #endif /* STM32F373xC || STM32F378xx */
2983
2984 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
2985 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
2986 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
2987 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2988 /**
2989 * @brief Get the calibration factor from automatic conversion result
2990 * @param hadc: ADC handle
2991 * @param SingleDiff: Selection of single-ended or differential input
2992 * This parameter can be one of the following values:
2993 * @arg ADC_SINGLE_ENDED: Channel in mode input single ended
2994 * @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
2995 * @retval Converted value
2996 */
2997 uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
2998 {
2999 /* Check the parameters */
3000 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3001 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
3002
3003 /* Return the selected ADC calibration value */
3004 if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
3005 {
3006 return __HAL_ADC_CALFACT_DIFF_GET(hadc->Instance->CALFACT);
3007 }
3008 else
3009 {
3010 return ((hadc->Instance->CALFACT) & 0x0000007F);
3011 }
3012 }
3013 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
3014 /* STM32F302xC || STM32F303xC || STM32F358xx || */
3015 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
3016 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
3017
3018 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
3019 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
3020 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
3021 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
3022 /**
3023 * @brief Set the calibration factor to overwrite automatic conversion result. ADC must be enabled and no conversion on going.
3024 * @param hadc: ADC handle
3025 * @param SingleDiff: Selection of single-ended or differential input
3026 * This parameter can be one of the following values:
3027 * @arg ADC_SINGLE_ENDED: Channel in mode input single ended
3028 * @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
3029 * @param CalibrationFactor: Calibration factor (coded on 7 bits maximum)
3030 * @retval HAL state
3031 */
3032 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
3033 {
3034 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
3035
3036 /* Check the parameters */
3037 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3038 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
3039 assert_param(IS_ADC_CALFACT(CalibrationFactor));
3040
3041 /* Process locked */
3042 __HAL_LOCK(hadc);
3043
3044 /* Verification of hardware constraints before modifying the calibration */
3045 /* factors register: ADC must be enabled, no conversion on going. */
3046 if ( (__HAL_ADC_IS_ENABLED(hadc) != RESET) &&
3047 (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) )
3048 {
3049 /* Set the selected ADC calibration value */
3050 if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
3051 {
3052 hadc->Instance->CALFACT &= ~ADC_CALFACT_CALFACT_D;
3053 hadc->Instance->CALFACT |= __HAL_ADC_CALFACT_DIFF_SET(CalibrationFactor);
3054 }
3055 else
3056 {
3057 hadc->Instance->CALFACT &= ~ADC_CALFACT_CALFACT_S;
3058 hadc->Instance->CALFACT |= CalibrationFactor;
3059 }
3060 }
3061 else
3062 {
3063 /* Update ADC state machine to error */
3064 hadc->State = HAL_ADC_STATE_ERROR;
3065
3066 /* Update ADC state machine to error */
3067 tmpHALStatus = HAL_ERROR;
3068 }
3069
3070 /* Process unlocked */
3071 __HAL_UNLOCK(hadc);
3072
3073 /* Return function status */
3074 return tmpHALStatus;
3075 }
3076 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
3077 /* STM32F302xC || STM32F303xC || STM32F358xx || */
3078 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
3079 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
3080
3081 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
3082 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
3083 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
3084 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
3085 /**
3086 * @brief Enables ADC, starts conversion of injected group.
3087 * Interruptions enabled in this function: None.
3088 * @note: Case of multimode enabled (for devices with several ADCs): This
3089 * function must be called for ADC slave first, then ADC master.
3090 * For ADC slave, ADC is enabled only (conversion is not started).
3091 * For ADC master, ADC is enabled and multimode conversion is started.
3092 * @param hadc: ADC handle
3093 * @retval HAL status
3094 */
3095 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
3096 {
3097 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
3098
3099 /* Check the parameters */
3100 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3101
3102 /* Process locked */
3103 __HAL_LOCK(hadc);
3104
3105 /* Enable the ADC peripheral */
3106 tmpHALStatus = ADC_Enable(hadc);
3107
3108 /* Start conversion if ADC is effectively enabled */
3109 if (tmpHALStatus != HAL_ERROR)
3110 {
3111 /* Check if a regular conversion is ongoing */
3112 if(hadc->State == HAL_ADC_STATE_BUSY_REG)
3113 {
3114 /* Change ADC state */
3115 hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
3116 }
3117 else
3118 {
3119 /* Change ADC state */
3120 hadc->State = HAL_ADC_STATE_BUSY_INJ;
3121 }
3122
3123 /* Set ADC error code to none */
3124 __HAL_ADC_CLEAR_ERRORCODE(hadc);
3125
3126 /* Clear injected group conversion flag */
3127 /* (To ensure of no unknown state from potential previous ADC operations) */
3128 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
3129
3130 /* Enable conversion of injected group, if automatic injected conversion */
3131 /* is disabled. */
3132 /* If software start has been selected, conversion starts immediately. */
3133 /* If external trigger has been selected, conversion will start at next */
3134 /* trigger event. */
3135 /* Case of multimode enabled (for devices with several ADCs): if ADC is */
3136 /* slave, ADC is enabled only (conversion is not started). If ADC is */
3137 /* master, ADC is enabled and conversion is started. */
3138 if (
3139 HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO) &&
3140 __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) )
3141 {
3142 hadc->Instance->CR |= ADC_CR_JADSTART;
3143 }
3144 }
3145
3146 /* Process unlocked */
3147 __HAL_UNLOCK(hadc);
3148
3149 /* Return function status */
3150 return tmpHALStatus;
3151 }
3152 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
3153 /* STM32F302xC || STM32F303xC || STM32F358xx || */
3154 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
3155 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
3156
3157 #if defined(STM32F373xC) || defined(STM32F378xx)
3158 /**
3159 * @brief Enables ADC, starts conversion of injected group.
3160 * Interruptions enabled in this function: None.
3161 * @param hadc: ADC handle
3162 * @retval HAL status
3163 */
3164 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
3165 {
3166 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
3167
3168 /* Check the parameters */
3169 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3170
3171 /* Process locked */
3172 __HAL_LOCK(hadc);
3173
3174 /* Enable the ADC peripheral */
3175 tmpHALStatus = ADC_Enable(hadc);
3176
3177 /* Start conversion if ADC is effectively enabled */
3178 if (tmpHALStatus != HAL_ERROR)
3179 {
3180 /* Check if a regular conversion is ongoing */
3181 if(hadc->State == HAL_ADC_STATE_BUSY_REG)
3182 {
3183 /* Change ADC state */
3184 hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
3185 }
3186 else
3187 {
3188 /* Change ADC state */
3189 hadc->State = HAL_ADC_STATE_BUSY_INJ;
3190 }
3191
3192 /* Set ADC error code to none */
3193 __HAL_ADC_CLEAR_ERRORCODE(hadc);
3194
3195 /* Clear injected group conversion flag */
3196 /* (To ensure of no unknown state from potential previous ADC operations) */
3197 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
3198
3199 /* Start conversion of injected group if software start has been selected */
3200 /* and if automatic injected conversion is disabled. */
3201 /* If external trigger has been selected, conversion will start at next */
3202 /* trigger event. */
3203 /* If automatic injected conversion is enabled, conversion will start */
3204 /* after next regular group conversion. */
3205 if (__HAL_ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
3206 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
3207 {
3208 /* Enable ADC software conversion for injected channels */
3209 hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
3210 }
3211 }
3212
3213 /* Process unlocked */
3214 __HAL_UNLOCK(hadc);
3215
3216 /* Return function status */
3217 return tmpHALStatus;
3218 }
3219 #endif /* STM32F373xC || STM32F378xx */
3220
3221 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
3222 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
3223 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
3224 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
3225 /**
3226 * @brief Stop conversion of injected channels. Disable ADC peripheral if
3227 * no regular conversion is on going.
3228 * @note If ADC must be disabled with this function and if regular conversion
3229 * is on going, function HAL_ADC_Stop must be used preliminarily.
3230 * @note In case of auto-injection mode, HAL_ADC_Stop must be used.
3231 * @note: Case of multimode enabled (for devices with several ADCs): This
3232 * function must be called for ADC master first, then ADC slave.
3233 * For ADC master, conversion is stopped and ADC is disabled.
3234 * For ADC slave, ADC is disabled only (conversion stop of ADC master
3235 * has already stopped conversion of ADC slave).
3236 * @param hadc: ADC handle
3237 * @retval None
3238 */
3239 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
3240 {
3241 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
3242
3243 /* Check the parameters */
3244 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3245
3246 /* Process locked */
3247 __HAL_LOCK(hadc);
3248
3249 /* 1. Stop potential conversion on going on injected group only. */
3250 tmpHALStatus = ADC_ConversionStop(hadc, INJECTED_GROUP);
3251
3252 /* Disable ADC peripheral if injected conversions are effectively stopped */
3253 /* and if no conversion on the other group (regular group) is intended to */
3254 /* continue. */
3255 if (tmpHALStatus != HAL_ERROR)
3256 {
3257 if((__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) &&
3258 (hadc->State != HAL_ADC_STATE_BUSY_REG) &&
3259 (hadc->State != HAL_ADC_STATE_BUSY_INJ_REG) )
3260 {
3261 /* 2. Disable the ADC peripheral */
3262 tmpHALStatus = ADC_Disable(hadc);
3263
3264 /* Check if ADC is effectively disabled */
3265 if (tmpHALStatus != HAL_ERROR)
3266 {
3267 /* Change ADC state */
3268 hadc->State = HAL_ADC_STATE_READY;
3269 }
3270 }
3271 /* Conversion on injected group is stopped, but ADC not disabled since */
3272 /* conversion on regular group is still running. */
3273 else
3274 {
3275 hadc->State = HAL_ADC_STATE_BUSY_REG;
3276 }
3277 }
3278
3279 /* Process unlocked */
3280 __HAL_UNLOCK(hadc);
3281
3282 /* Return function status */
3283 return tmpHALStatus;
3284 }
3285 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
3286 /* STM32F302xC || STM32F303xC || STM32F358xx || */
3287 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
3288 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
3289
3290 #if defined(STM32F373xC) || defined(STM32F378xx)
3291 /**
3292 * @brief Stop conversion of injected channels. Disable ADC peripheral if
3293 * no regular conversion is on going.
3294 * @note If ADC must be disabled with this function and if regular conversion
3295 * is on going, function HAL_ADC_Stop must be used preliminarily.
3296 * @note In case of auto-injection mode, HAL_ADC_Stop must be used.
3297 * @param hadc: ADC handle
3298 * @retval None
3299 */
3300 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
3301 {
3302 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
3303
3304 /* Check the parameters */
3305 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3306
3307 /* Process locked */
3308 __HAL_LOCK(hadc);
3309
3310 /* Stop potential conversion and disable ADC peripheral */
3311 /* Conditioned to: */
3312 /* - No conversion on the other group (regular group) is intended to */
3313 /* continue (injected and regular groups stop conversion and ADC disable */
3314 /* are common) */
3315 /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
3316 if((hadc->State != HAL_ADC_STATE_BUSY_REG) &&
3317 (hadc->State != HAL_ADC_STATE_BUSY_INJ_REG) &&
3318 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
3319 {
3320 /* Stop potential conversion on going, on regular and injected groups */
3321 /* Disable ADC peripheral */
3322 tmpHALStatus = ADC_ConversionStop_Disable(hadc);
3323
3324 /* Check if ADC is effectively disabled */
3325 if (tmpHALStatus != HAL_ERROR)
3326 {
3327 /* Change ADC state */
3328 hadc->State = HAL_ADC_STATE_READY;
3329 }
3330 }
3331 else
3332 {
3333 /* Update ADC state machine to error */
3334 hadc->State = HAL_ADC_STATE_ERROR;
3335
3336 tmpHALStatus = HAL_ERROR;
3337 }
3338
3339 /* Process unlocked */
3340 __HAL_UNLOCK(hadc);
3341
3342 /* Return function status */
3343 return tmpHALStatus;
3344 }
3345 #endif /* STM32F373xC || STM32F378xx */
3346
3347 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
3348 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
3349 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
3350 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
3351 /**
3352 * @brief Wait for injected group conversion to be completed.
3353 * @param hadc: ADC handle
3354 * @param Timeout: Timeout value in millisecond.
3355 * @retval HAL status
3356 */
3357 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
3358 {
3359 uint32_t tickstart;
3360 uint32_t tmp_Flag_EOC;
3361
3362 /* Check the parameters */
3363 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3364
3365 /* If end of conversion selected to end of sequence */
3366 if (hadc->Init.EOCSelection == EOC_SEQ_CONV)
3367 {
3368 tmp_Flag_EOC = ADC_FLAG_JEOS;
3369 }
3370 /* If end of conversion selected to end of each conversion */
3371 else /* EOC_SINGLE_CONV */
3372 {
3373 tmp_Flag_EOC = (ADC_FLAG_JEOC | ADC_FLAG_JEOS);
3374 }
3375
3376 /* Get timeout */
3377 tickstart = HAL_GetTick();
3378
3379 /* Wait until End of Conversion flag is raised */
3380 while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
3381 {
3382 /* Check if timeout is disabled (set to infinite wait) */
3383 if(Timeout != HAL_MAX_DELAY)
3384 {
3385 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
3386 {
3387 /* Update ADC state machine to timeout */
3388 hadc->State = HAL_ADC_STATE_TIMEOUT;
3389
3390 /* Process unlocked */
3391 __HAL_UNLOCK(hadc);
3392
3393 return HAL_ERROR;
3394 }
3395 }
3396 }
3397
3398 /* Clear end of conversion flag of injected group if low power feature */
3399 /* "Auto Wait" is disabled, to not interfere with this feature until data */
3400 /* register is read using function HAL_ADC_GetValue(). */
3401 if (hadc->Init.LowPowerAutoWait == DISABLE)
3402 {
3403 /* Clear injected group conversion flag */
3404 __HAL_ADC_CLEAR_FLAG(hadc,(ADC_FLAG_JEOC | ADC_FLAG_JEOS));
3405 }
3406
3407
3408 /* Update ADC state machine */
3409 if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG)
3410 {
3411 /* Check if a conversion is ready on regular group */
3412 if(hadc->State == HAL_ADC_STATE_EOC_REG)
3413 {
3414 /* Change ADC state */
3415 hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
3416 }
3417 else
3418 {
3419 /* Change ADC state */
3420 hadc->State = HAL_ADC_STATE_EOC_INJ;
3421 }
3422 }
3423
3424 /* Return ADC state */
3425 return HAL_OK;
3426 }
3427 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
3428 /* STM32F302xC || STM32F303xC || STM32F358xx || */
3429 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
3430 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
3431
3432 #if defined(STM32F373xC) || defined(STM32F378xx)
3433 /**
3434 * @brief Wait for injected group conversion to be completed.
3435 * @param hadc: ADC handle
3436 * @param Timeout: Timeout value in millisecond.
3437 * @retval HAL status
3438 */
3439 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
3440 {
3441 uint32_t tickstart;
3442
3443 /* Variables for polling in case of scan mode enabled */
3444 uint32_t Conversion_Timeout_CPU_cycles_max =0;
3445 uint32_t Conversion_Timeout_CPU_cycles =0;
3446
3447 /* Check the parameters */
3448 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3449
3450 /* Get timeout */
3451 tickstart = HAL_GetTick();
3452
3453 /* Polling for end of conversion: differentiation if single/sequence */
3454 /* conversion. */
3455 /* For injected group, flag JEOC is set only at the end of the sequence, */
3456 /* not for each conversion within the sequence. */
3457 /* - If single conversion for injected group (scan mode disabled or */
3458 /* InjectedNbrOfConversion ==1), flag jEOC is used to determine the */
3459 /* conversion completion. */
3460 /* - If sequence conversion for injected group (scan mode enabled and */
3461 /* InjectedNbrOfConversion >=2), flag JEOC is set only at the end of the */
3462 /* sequence. */
3463 /* To poll for each conversion, the maximum conversion time is computed */
3464 /* from ADC conversion time (selected sampling time + conversion time of */
3465 /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */
3466 /* settings, conversion time range can be from 28 to 32256 CPU cycles). */
3467 if ((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET)
3468 {
3469 /* Wait until End of Conversion flag is raised */
3470 while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC))
3471 {
3472 /* Check if timeout is disabled (set to infinite wait) */
3473 if(Timeout != HAL_MAX_DELAY)
3474 {
3475 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
3476 {
3477 /* Update ADC state machine to timeout */
3478 hadc->State = HAL_ADC_STATE_TIMEOUT;
3479
3480 /* Process unlocked */
3481 __HAL_UNLOCK(hadc);
3482
3483 return HAL_ERROR;
3484 }
3485 }
3486 }
3487 }
3488 else
3489 {
3490 /* Calculation of CPU cycles corresponding to ADC conversion cycles. */
3491 /* Retrieve ADC clock prescaler and ADC maximum conversion cycles on all */
3492 /* channels. */
3493 Conversion_Timeout_CPU_cycles_max = __HAL_ADC_CLOCK_PRECSALER_RANGE() ;
3494 Conversion_Timeout_CPU_cycles_max *= __HAL_ADC_CONVCYCLES_MAX_RANGE(hadc);
3495
3496 /* Maximum conversion cycles taking in account offset of 34 CPU cycles: */
3497 /* number of CPU cycles for processing of conversion cycles estimation. */
3498 Conversion_Timeout_CPU_cycles = 34;
3499
3500 /* Poll with maximum conversion time */
3501 while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
3502 {
3503 /* Check if timeout is disabled (set to infinite wait) */
3504 if(Timeout != HAL_MAX_DELAY)
3505 {
3506 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
3507 {
3508 /* Update ADC state machine to timeout */
3509 hadc->State = HAL_ADC_STATE_TIMEOUT;
3510
3511 /* Process unlocked */
3512 __HAL_UNLOCK(hadc);
3513
3514 return HAL_ERROR;
3515 }
3516 }
3517 Conversion_Timeout_CPU_cycles ++;
3518 }
3519 }
3520
3521
3522 /* Clear injected group conversion flag (and regular conversion flag raised simultaneously) */
3523 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC | ADC_FLAG_EOC);
3524
3525 /* Check if a regular conversion is ready */
3526 if(hadc->State == HAL_ADC_STATE_EOC_REG)
3527 {
3528 /* Change ADC state */
3529 hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
3530 }
3531 else
3532 {
3533 /* Change ADC state */
3534 hadc->State = HAL_ADC_STATE_EOC_INJ;
3535 }
3536
3537 /* Return ADC state */
3538 return HAL_OK;
3539 }
3540 #endif /* STM32F373xC || STM32F378xx */
3541
3542 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
3543 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
3544 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
3545 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
3546 /**
3547 * @brief Enables ADC, starts conversion of injected group with interruption.
3548 * Interruptions enabled in this function: JEOC (end of conversion).
3549 * Each of these interruptions has its dedicated callback function.
3550 * @note: Case of multimode enabled (for devices with several ADCs): This
3551 * function must be called for ADC slave first, then ADC master.
3552 * For ADC slave, ADC is enabled only (conversion is not started).
3553 * For ADC master, ADC is enabled and multimode conversion is started.
3554 * @param hadc: ADC handle
3555 * @retval HAL status.
3556 */
3557 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
3558 {
3559 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
3560
3561 /* Check the parameters */
3562 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3563
3564 /* Process locked */
3565 __HAL_LOCK(hadc);
3566
3567 /* Enable the ADC peripheral */
3568 tmpHALStatus = ADC_Enable(hadc);
3569
3570 /* Start conversion if ADC is effectively enabled */
3571 if (tmpHALStatus != HAL_ERROR)
3572 {
3573 /* Check if a regular conversion is ongoing */
3574 if(hadc->State == HAL_ADC_STATE_BUSY_REG)
3575 {
3576 /* Change ADC state */
3577 hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
3578 }
3579 else
3580 {
3581 /* Change ADC state */
3582 hadc->State = HAL_ADC_STATE_BUSY_INJ;
3583 }
3584
3585 /* Set ADC error code to none */
3586 __HAL_ADC_CLEAR_ERRORCODE(hadc);
3587
3588 /* Clear injected group conversion flag */
3589 /* (To ensure of no unknown state from potential previous ADC operations) */
3590 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
3591
3592 /* Enable ADC Injected context queue overflow interrupt if this feature */
3593 /* is enabled. */
3594 if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != RESET)
3595 {
3596 __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF);
3597 }
3598
3599 /* Enable ADC end of conversion interrupt */
3600 switch(hadc->Init.EOCSelection)
3601 {
3602 case EOC_SEQ_CONV:
3603 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
3604 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
3605 break;
3606 /* case EOC_SINGLE_CONV */
3607 default:
3608 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
3609 break;
3610 }
3611
3612 /* Enable conversion of injected group, if automatic injected conversion */
3613 /* is disabled. */
3614 /* If software start has been selected, conversion starts immediately. */
3615 /* If external trigger has been selected, conversion will start at next */
3616 /* trigger event. */
3617 /* Case of multimode enabled (for devices with several ADCs): if ADC is */
3618 /* slave, ADC is enabled only (conversion is not started). If ADC is */
3619 /* master, ADC is enabled and conversion is started. */
3620 if (
3621 HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO) &&
3622 __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) )
3623 {
3624 hadc->Instance->CR |= ADC_CR_JADSTART;
3625 }
3626 }
3627
3628 /* Process unlocked */
3629 __HAL_UNLOCK(hadc);
3630
3631 /* Return function status */
3632 return tmpHALStatus;
3633 }
3634 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
3635 /* STM32F302xC || STM32F303xC || STM32F358xx || */
3636 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
3637 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
3638
3639 #if defined(STM32F373xC) || defined(STM32F378xx)
3640 /**
3641 * @brief Enables ADC, starts conversion of injected group with interruption.
3642 * Interruptions enabled in this function: JEOC (end of conversion),
3643 * overrun (if available).
3644 * Each of these interruptions has its dedicated callback function.
3645 * @param hadc: ADC handle
3646 * @retval HAL status.
3647 */
3648 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
3649 {
3650 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
3651
3652 /* Check the parameters */
3653 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3654
3655 /* Process locked */
3656 __HAL_LOCK(hadc);
3657
3658 /* Enable the ADC peripheral */
3659 tmpHALStatus = ADC_Enable(hadc);
3660
3661 /* Start conversion if ADC is effectively enabled */
3662 if (tmpHALStatus != HAL_ERROR)
3663 {
3664 /* Check if a regular conversion is ongoing */
3665 if(hadc->State == HAL_ADC_STATE_BUSY_REG)
3666 {
3667 /* Change ADC state */
3668 hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
3669 }
3670 else
3671 {
3672 /* Change ADC state */
3673 hadc->State = HAL_ADC_STATE_BUSY_INJ;
3674 }
3675
3676 /* Set ADC error code to none */
3677 __HAL_ADC_CLEAR_ERRORCODE(hadc);
3678
3679 /* Clear injected group conversion flag */
3680 /* (To ensure of no unknown state from potential previous ADC operations) */
3681 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
3682
3683 /* Enable end of conversion interrupt for injected channels */
3684 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
3685
3686 /* Start conversion of injected group if software start has been selected */
3687 /* and if automatic injected conversion is disabled. */
3688 /* If external trigger has been selected, conversion will start at next */
3689 /* trigger event. */
3690 /* If automatic injected conversion is enabled, conversion will start */
3691 /* after next regular group conversion. */
3692 if (__HAL_ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
3693 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
3694 {
3695 /* Enable ADC software conversion for injected channels */
3696 hadc->Instance->CR2 |= ADC_CR2_JSWSTART;
3697 }
3698 }
3699
3700 /* Process unlocked */
3701 __HAL_UNLOCK(hadc);
3702
3703 /* Return function status */
3704 return tmpHALStatus;
3705 }
3706 #endif /* STM32F373xC || STM32F378xx */
3707
3708 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
3709 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
3710 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
3711 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
3712 /**
3713 * @brief Stop conversion of injected channels, disable interruption of
3714 * end-of-conversion. Disable ADC peripheral if no regular conversion
3715 * is on going.
3716 * @note If ADC must be disabled with this function and if regular conversion
3717 * is on going, function HAL_ADC_Stop must be used preliminarily.
3718 * @note: Case of multimode enabled (for devices with several ADCs): This
3719 * function must be called for ADC master first, then ADC slave.
3720 * For ADC master, conversion is stopped and ADC is disabled.
3721 * For ADC slave, ADC is disabled only (conversion stop of ADC master
3722 * has already stopped conversion of ADC slave).
3723 * @note In case of auto-injection mode, HAL_ADC_Stop must be used.
3724 * @param hadc: ADC handle
3725 * @retval None
3726 */
3727 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
3728 {
3729 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
3730
3731 /* Check the parameters */
3732 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3733
3734 /* Process locked */
3735 __HAL_LOCK(hadc);
3736
3737 /* 1. Stop potential conversion on going on injected group only. */
3738 tmpHALStatus = ADC_ConversionStop(hadc, INJECTED_GROUP);
3739
3740 /* Disable ADC peripheral if injected conversions are effectively stopped */
3741 /* and if no conversion on the other group (regular group) is intended to */
3742 /* continue. */
3743 if (tmpHALStatus != HAL_ERROR)
3744 {
3745 /* Disable ADC end of conversion interrupt for injected channels */
3746 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS));
3747
3748 if((__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) &&
3749 (hadc->State != HAL_ADC_STATE_BUSY_REG) &&
3750 (hadc->State != HAL_ADC_STATE_BUSY_INJ_REG) )
3751 {
3752 /* 2. Disable the ADC peripheral */
3753 tmpHALStatus = ADC_Disable(hadc);
3754
3755 /* Check if ADC is effectively disabled */
3756 if (tmpHALStatus != HAL_ERROR)
3757 {
3758 /* Change ADC state */
3759 hadc->State = HAL_ADC_STATE_READY;
3760 }
3761 }
3762 /* Conversion on injected group is stopped, but ADC not disabled since */
3763 /* conversion on regular group is still running. */
3764 else
3765 {
3766 hadc->State = HAL_ADC_STATE_BUSY_REG;
3767 }
3768 }
3769
3770 /* Process unlocked */
3771 __HAL_UNLOCK(hadc);
3772
3773 /* Return function status */
3774 return tmpHALStatus;
3775 }
3776 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
3777 /* STM32F302xC || STM32F303xC || STM32F358xx || */
3778 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
3779 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
3780
3781 #if defined(STM32F373xC) || defined(STM32F378xx)
3782 /**
3783 * @brief Stop conversion of injected channels, disable interruption of
3784 * end-of-conversion. Disable ADC peripheral if no regular conversion
3785 * is on going.
3786 * @note If ADC must be disabled with this function and if regular conversion
3787 * is on going, function HAL_ADC_Stop must be used preliminarily.
3788 * @param hadc: ADC handle
3789 * @retval None
3790 */
3791 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
3792 {
3793 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
3794
3795 /* Check the parameters */
3796 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3797
3798 /* Process locked */
3799 __HAL_LOCK(hadc);
3800
3801 /* Stop potential conversion and disable ADC peripheral */
3802 /* Conditioned to: */
3803 /* - No conversion on the other group (regular group) is intended to */
3804 /* continue (injected and regular groups stop conversion and ADC disable */
3805 /* are common) */
3806 /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
3807 if((hadc->State != HAL_ADC_STATE_BUSY_REG) &&
3808 (hadc->State != HAL_ADC_STATE_BUSY_INJ_REG) &&
3809 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
3810 {
3811 /* Stop potential conversion on going, on regular and injected groups */
3812 /* Disable ADC peripheral */
3813 tmpHALStatus = ADC_ConversionStop_Disable(hadc);
3814
3815 /* Check if ADC is effectively disabled */
3816 if (tmpHALStatus != HAL_ERROR)
3817 {
3818 /* Disable ADC end of conversion interrupt for injected channels */
3819 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
3820
3821 /* Change ADC state */
3822 hadc->State = HAL_ADC_STATE_READY;
3823 }
3824 }
3825 else
3826 {
3827 /* Update ADC state machine to error */
3828 hadc->State = HAL_ADC_STATE_ERROR;
3829
3830 tmpHALStatus = HAL_ERROR;
3831 }
3832
3833 /* Process unlocked */
3834 __HAL_UNLOCK(hadc);
3835
3836 /* Return function status */
3837 return tmpHALStatus;
3838 }
3839 #endif /* STM32F373xC || STM32F378xx */
3840
3841 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
3842 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
3843 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
3844 /**
3845 * @brief Enables ADC, starts conversion of regular group and transfers result
3846 * through DMA.
3847 * Multimode must have been previously configured using
3848 * HAL_ADCEx_MultiModeConfigChannel() function.
3849 * Interruptions enabled in this function:
3850 * overrun, DMA half transfer, DMA transfer complete.
3851 * Each of these interruptions has its dedicated callback function.
3852 * @note: ADC slave can be enabled preliminarily using single-mode
3853 * HAL_ADC_Start() function.
3854 * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
3855 * @param pData: The destination Buffer address.
3856 * @param Length: The length of data to be transferred from ADC peripheral to memory.
3857 * @retval None
3858 */
3859 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
3860 {
3861 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
3862 ADC_HandleTypeDef tmphadcSlave;
3863 ADC_Common_TypeDef *tmpADC_Common;
3864
3865 /* Check the parameters */
3866 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
3867 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
3868 assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
3869 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
3870
3871 /* Process locked */
3872 __HAL_LOCK(hadc);
3873
3874 /* Set a temporary handle of the ADC slave associated to the ADC master */
3875 /* (Depending on STM32F3 product, there may be up to 2 ADC slaves) */
3876 __HAL_ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
3877
3878 if (tmphadcSlave.Instance == HAL_NULL)
3879 {
3880 /* Update ADC state machine to error */
3881 hadc->State = HAL_ADC_STATE_ERROR;
3882
3883 /* Process unlocked */
3884 __HAL_UNLOCK(hadc);
3885
3886 return HAL_ERROR;
3887 }
3888
3889
3890 /* Enable the ADC peripherals: master and slave (in case if not already */
3891 /* enabled previously) */
3892 tmpHALStatus = ADC_Enable(hadc);
3893 if (tmpHALStatus != HAL_ERROR)
3894 {
3895 tmpHALStatus = ADC_Enable(&tmphadcSlave);
3896 }
3897
3898 /* Start conversion all ADCs of multimode are effectively enabled */
3899 if (tmpHALStatus != HAL_ERROR)
3900 {
3901 /* State machine update (ADC master): Check if an injected conversion is */
3902 /* ongoing. */
3903 if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
3904 {
3905 /* Change ADC state */
3906 hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
3907 }
3908 else
3909 {
3910 /* Change ADC state */
3911 hadc->State = HAL_ADC_STATE_BUSY_REG;
3912 }
3913
3914 /* Set ADC error code to none */
3915 __HAL_ADC_CLEAR_ERRORCODE(hadc);
3916
3917
3918 /* Set the DMA transfer complete callback */
3919 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
3920
3921 /* Set the DMA half transfer complete callback */
3922 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
3923
3924 /* Set the DMA error callback */
3925 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
3926
3927 /* Pointer to the common control register to which is belonging hadc */
3928 /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
3929 /* control registers) */
3930 tmpADC_Common = __HAL_ADC_COMMON_REGISTER(hadc);
3931
3932
3933 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
3934 /* start (in case of SW start): */
3935
3936 /* Clear regular group conversion flag and overrun flag */
3937 /* (To ensure of no unknown state from potential previous ADC operations) */
3938 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
3939
3940 /* Enable ADC overrun interrupt */
3941 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
3942
3943 /* Start the DMA channel */
3944 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
3945
3946 /* Enable conversion of regular group. */
3947 /* If software start has been selected, conversion starts immediately. */
3948 /* If external trigger has been selected, conversion will start at next */
3949 /* trigger event. */
3950 hadc->Instance->CR |= ADC_CR_ADSTART;
3951
3952 }
3953
3954 /* Process unlocked */
3955 __HAL_UNLOCK(hadc);
3956
3957 /* Return function status */
3958 return tmpHALStatus;
3959 }
3960
3961 /**
3962 * @brief Stop ADC conversion of regular group (and injected channels in
3963 * case of auto_injection mode), disable ADC DMA transfer, disable
3964 * ADC peripheral.
3965 * @note Multimode is kept enabled after this function. To disable multimode
3966 * (set with HAL_ADCEx_MultiModeConfigChannel(), ADC must be
3967 * reinitialized using HAL_ADC_Init() or HAL_ADC_ReInit().
3968 * @note In case of DMA configured in circular mode, function
3969 * HAL_ADC_Stop_DMA must be called after this function with handle of
3970 * ADC slave, to properly disable the DMA channel.
3971 * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
3972 * @retval None
3973 */
3974 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
3975 {
3976 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
3977 uint32_t tickstart;
3978 ADC_HandleTypeDef tmphadcSlave;
3979 ADC_Common_TypeDef *tmpADC_Common;
3980
3981 /* Check the parameters */
3982 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
3983
3984 /* Process locked */
3985 __HAL_LOCK(hadc);
3986
3987
3988 /* 1. Stop potential multimode conversion on going, on regular and injected groups */
3989 tmpHALStatus = ADC_ConversionStop(hadc, REGULAR_INJECTED_GROUP);
3990
3991 /* Disable ADC peripheral if conversions are effectively stopped */
3992 if (tmpHALStatus != HAL_ERROR)
3993 {
3994 /* Set a temporary handle of the ADC slave associated to the ADC master */
3995 /* (Depending on STM32F3 product, there may be up to 2 ADC slaves) */
3996 __HAL_ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
3997
3998 if (tmphadcSlave.Instance == HAL_NULL)
3999 {
4000 /* Update ADC state machine to error */
4001 hadc->State = HAL_ADC_STATE_ERROR;
4002
4003 /* Process unlocked */
4004 __HAL_UNLOCK(hadc);
4005
4006 return HAL_ERROR;
4007 }
4008
4009 /* Procedure to disable the ADC peripheral: wait for conversions */
4010 /* effectively stopped (ADC master and ADC slave), then disable ADC */
4011
4012 /* 1. Wait until ADSTP=0 for ADC master and ADC slave*/
4013 tickstart = HAL_GetTick();
4014
4015 while(__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) ||
4016 __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) )
4017 {
4018 if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
4019 {
4020 /* Update ADC state machine to error */
4021 hadc->State = HAL_ADC_STATE_ERROR;
4022
4023 /* Process unlocked */
4024 __HAL_UNLOCK(hadc);
4025
4026 return HAL_ERROR;
4027 }
4028 }
4029
4030
4031 /* Pointer to the common control register to which is belonging hadc */
4032 /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
4033 /* control registers) */
4034 tmpADC_Common = __HAL_ADC_COMMON_REGISTER(hadc);
4035
4036 /* Reset configuration of ADC DMA continuous request for dual mode */
4037 tmpADC_Common->CCR &= ~ADC_CCR_DMACFG;
4038
4039 /* Disable the DMA channel (in case of DMA in circular mode or stop while */
4040 /* while DMA transfer is on going) */
4041 /* Note: DMA channel of ADC slave should stopped after this function with */
4042 /* function HAL_ADC_Stop_DMA. */
4043 tmpHALStatus = HAL_DMA_Abort(hadc->DMA_Handle);
4044
4045 /* Check if DMA channel effectively disabled */
4046 if (tmpHALStatus != HAL_OK)
4047 {
4048 /* Update ADC state machine to error */
4049 hadc->State = HAL_ADC_STATE_ERROR;
4050 }
4051
4052 /* Disable ADC overrun interrupt */
4053 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
4054
4055
4056
4057 /* 2. Disable the ADC peripherals: master and slave */
4058 /* Update "tmpHALStatus" only if DMA channel disabling passed, to keep in */
4059 /* memory a potential failing status. */
4060 if (tmpHALStatus != HAL_ERROR)
4061 {
4062 /* Check if ADC are effectively disabled */
4063 if ((ADC_Disable(hadc) != HAL_ERROR) &&
4064 (ADC_Disable(&tmphadcSlave) != HAL_ERROR) )
4065 {
4066 tmpHALStatus = HAL_OK;
4067
4068 /* Change ADC state (ADC master) */
4069 hadc->State = HAL_ADC_STATE_READY;
4070 }
4071 }
4072 else
4073 {
4074 ADC_Disable(hadc);
4075 ADC_Disable(&tmphadcSlave);
4076 }
4077
4078 }
4079
4080 /* Process unlocked */
4081 __HAL_UNLOCK(hadc);
4082
4083 /* Return function status */
4084 return tmpHALStatus;
4085 }
4086
4087 /**
4088 * @brief Returns the last ADC Master&Slave regular conversions results data
4089 * in the selected multi mode.
4090 * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
4091 * @retval The converted data value.
4092 */
4093 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
4094 {
4095 ADC_Common_TypeDef *tmpADC_Common;
4096
4097 /* Check the parameters */
4098 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
4099
4100 /* Pointer to the common control register to which is belonging hadc */
4101 /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
4102 /* control registers) */
4103 tmpADC_Common = __HAL_ADC_COMMON_REGISTER(hadc);
4104
4105 /* Return the multi mode conversion value */
4106 return tmpADC_Common->CDR;
4107 }
4108 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
4109 /* STM32F302xC || STM32F303xC || STM32F358xx || */
4110 /* STM32F303x8 || STM32F334x8 || STM32F328xx */
4111
4112 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
4113 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
4114 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
4115 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
4116 /**
4117 * @brief Get ADC injected group conversion result.
4118 * @param hadc: ADC handle
4119 * @param InjectedRank: the converted ADC injected rank.
4120 * This parameter can be one of the following values:
4121 * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
4122 * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
4123 * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
4124 * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
4125 * @retval None
4126 */
4127 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
4128 {
4129 uint32_t tmp_jdr = 0;
4130
4131 /* Check the parameters */
4132 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
4133 assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
4134
4135 /* Clear injected group conversion flag to have similar behaviour as */
4136 /* regular group: reading data register also clears end of conversion flag, */
4137 /* and in case of usage of ADC feature "LowPowerAutoWait". */
4138 __HAL_ADC_CLEAR_FLAG(hadc,(ADC_FLAG_JEOC | ADC_FLAG_JEOS));
4139
4140 /* Get ADC converted value */
4141 switch(InjectedRank)
4142 {
4143 case ADC_INJECTED_RANK_4:
4144 tmp_jdr = hadc->Instance->JDR4;
4145 break;
4146 case ADC_INJECTED_RANK_3:
4147 tmp_jdr = hadc->Instance->JDR3;
4148 break;
4149 case ADC_INJECTED_RANK_2:
4150 tmp_jdr = hadc->Instance->JDR2;
4151 break;
4152 case ADC_INJECTED_RANK_1:
4153 default:
4154 tmp_jdr = hadc->Instance->JDR1;
4155 break;
4156 }
4157
4158 /* Return ADC converted value */
4159 return tmp_jdr;
4160 }
4161 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
4162 /* STM32F302xC || STM32F303xC || STM32F358xx || */
4163 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
4164 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
4165
4166 #if defined(STM32F373xC) || defined(STM32F378xx)
4167 /**
4168 * @brief Get ADC injected group conversion result.
4169 * @param hadc: ADC handle
4170 * @param InjectedRank: the converted ADC injected rank.
4171 * This parameter can be one of the following values:
4172 * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
4173 * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
4174 * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
4175 * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
4176 * @retval None
4177 */
4178 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
4179 {
4180 uint32_t tmp_jdr = 0;
4181
4182 /* Check the parameters */
4183 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
4184 assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
4185
4186 /* Clear injected group conversion flag to have similar behaviour as */
4187 /* regular group: reading data register also clears end of conversion flag. */
4188 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
4189
4190 /* Get ADC converted value */
4191 switch(InjectedRank)
4192 {
4193 case ADC_INJECTED_RANK_4:
4194 tmp_jdr = hadc->Instance->JDR4;
4195 break;
4196 case ADC_INJECTED_RANK_3:
4197 tmp_jdr = hadc->Instance->JDR3;
4198 break;
4199 case ADC_INJECTED_RANK_2:
4200 tmp_jdr = hadc->Instance->JDR2;
4201 break;
4202 case ADC_INJECTED_RANK_1:
4203 default:
4204 tmp_jdr = hadc->Instance->JDR1;
4205 break;
4206 }
4207
4208 /* Return ADC converted value */
4209 return tmp_jdr;
4210 }
4211 #endif /* STM32F373xC || STM32F378xx */
4212
4213 /**
4214 * @brief Injected conversion complete callback in non blocking mode
4215 * @param hadc: ADC handle
4216 * @retval None
4217 */
4218 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
4219 {
4220 /* NOTE : This function Should not be modified, when the callback is needed,
4221 the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file
4222 */
4223 }
4224
4225 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
4226 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
4227 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
4228 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
4229 /**
4230 * @brief Injected context queue overflow flag callback.
4231 * @note: This callback is called if injected context queue is enabled
4232 (parameter "QueueInjectedContext" in injected channel configuration)
4233 and if a new injected context is set when queue is full (maximum 2
4234 contexts).
4235 * @param hadc: ADC handle
4236 * @retval None
4237 */
4238 __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc)
4239 {
4240 /* NOTE : This function should not be modified. When the callback is needed,
4241 function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented
4242 in the user file.
4243 */
4244 }
4245 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
4246 /* STM32F302xC || STM32F303xC || STM32F358xx || */
4247 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
4248 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
4249
4250 /**
4251 * @}
4252 */
4253
4254 /** @defgroup ADCEx_Exported_Functions_Group3 Extended Peripheral Control functions
4255 * @brief Extended Peripheral Control functions
4256 *
4257 @verbatim
4258 ===============================================================================
4259 ##### Peripheral Control functions #####
4260 ===============================================================================
4261 [..] This section provides functions allowing to:
4262 (+) Configure channels on regular group
4263 (+) Configure channels on injected group
4264 (+) Configure multimode
4265 (+) Configure the analog watchdog
4266
4267 @endverbatim
4268 * @{
4269 */
4270
4271
4272 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
4273 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
4274 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
4275 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
4276 /**
4277 * @brief Configures the the selected channel to be linked to the regular
4278 * group.
4279 * @note In case of usage of internal measurement channels:
4280 * Vbat/VrefInt/TempSensor.
4281 * The recommended sampling time is at least:
4282 * - For devices STM32F37x: 17.1us for temperature sensor
4283 * - For the other STM32F3 devices: 2.2us for each of channels
4284 * Vbat/VrefInt/TempSensor.
4285 * These internal paths can be be disabled using function
4286 * HAL_ADC_DeInit().
4287 * @note Possibility to update parameters on the fly:
4288 * This function initializes channel into regular group, following
4289 * calls to this function can be used to reconfigure some parameters
4290 * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
4291 * the ADC.
4292 * The setting of these parameters is conditioned to ADC state.
4293 * For parameters constraints, see comments of structure
4294 * "ADC_ChannelConfTypeDef".
4295 * @param hadc: ADC handle
4296 * @param sConfig: Structure ADC channel for regular group.
4297 * @retval HAL status
4298 */
4299 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
4300 {
4301 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
4302 ADC_Common_TypeDef *tmpADC_Common;
4303 ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
4304 uint32_t tmpOffsetShifted;
4305 uint32_t WaitLoopIndex = 0;
4306
4307 /* Check the parameters */
4308 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
4309 assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
4310 assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
4311 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff));
4312 assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber));
4313 assert_param(IS_ADC_RANGE(__HAL_ADC_GET_RESOLUTION(hadc), sConfig->Offset));
4314
4315
4316 /* Verification of channel number: Channels 1 to 14 are available in */
4317 /* differential mode. Channels 15, 16, 17, 18 can be used only in */
4318 /* single-ended mode. */
4319 if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
4320 {
4321 assert_param(IS_ADC_CHANNEL(sConfig->Channel));
4322 }
4323 else
4324 {
4325 assert_param(IS_ADC_DIFF_CHANNEL(sConfig->Channel));
4326 }
4327
4328 /* Process locked */
4329 __HAL_LOCK(hadc);
4330
4331
4332 /* Parameters update conditioned to ADC state: */
4333 /* Parameters that can be updated when ADC is disabled or enabled without */
4334 /* conversion on going on regular group: */
4335 /* - Channel number */
4336 /* - Channel rank */
4337 if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
4338 {
4339 /* Regular sequence configuration */
4340 /* For Rank 1 to 4 */
4341 if (sConfig->Rank < 5)
4342 {
4343 /* Clear the old SQx bits for the selected rank */
4344 hadc->Instance->SQR1 &= ~__HAL_ADC_SQR1_RK(ADC_SQR2_SQ5, sConfig->Rank);
4345
4346 /* Set the SQx bits for the selected rank */
4347 hadc->Instance->SQR1 |= __HAL_ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
4348 }
4349 /* For Rank 5 to 9 */
4350 else if (sConfig->Rank < 10)
4351 {
4352 /* Clear the old SQx bits for the selected rank */
4353 hadc->Instance->SQR2 &= ~__HAL_ADC_SQR2_RK(ADC_SQR2_SQ5, sConfig->Rank);
4354
4355 /* Set the SQx bits for the selected rank */
4356 hadc->Instance->SQR2 |= __HAL_ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
4357 }
4358 /* For Rank 10 to 14 */
4359 else if (sConfig->Rank < 15)
4360 {
4361 /* Clear the old SQx bits for the selected rank */
4362 hadc->Instance->SQR3 &= ~__HAL_ADC_SQR3_RK(ADC_SQR3_SQ10, sConfig->Rank);
4363
4364 /* Set the SQx bits for the selected rank */
4365 hadc->Instance->SQR3 |= __HAL_ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
4366 }
4367 /* For Rank 15 to 16 */
4368 else
4369 {
4370 /* Clear the old SQx bits for the selected rank */
4371 hadc->Instance->SQR4 &= ~__HAL_ADC_SQR4_RK(ADC_SQR4_SQ15, sConfig->Rank);
4372
4373 /* Set the SQx bits for the selected rank */
4374 hadc->Instance->SQR4 |= __HAL_ADC_SQR4_RK(sConfig->Channel, sConfig->Rank);
4375 }
4376
4377
4378 /* Parameters update conditioned to ADC state: */
4379 /* Parameters that can be updated when ADC is disabled or enabled without */
4380 /* conversion on going on regular group: */
4381 /* - Channel sampling time */
4382 /* - Channel offset */
4383 if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
4384 {
4385 /* Channel sampling time configuration */
4386 /* For channels 10 to 18 */
4387 if (sConfig->Channel > ADC_CHANNEL_10)
4388 {
4389 /* Clear the old sample time */
4390 hadc->Instance->SMPR2 &= ~__HAL_ADC_SMPR2(ADC_SMPR1_SMP0, sConfig->Channel);
4391
4392 /* Set the new sample time */
4393 hadc->Instance->SMPR2 |= __HAL_ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
4394 }
4395 else /* For channels 0 to 9 */
4396 {
4397 /* Clear the old sample time */
4398 hadc->Instance->SMPR1 &= ~__HAL_ADC_SMPR1(ADC_SMPR2_SMP10, sConfig->Channel);
4399
4400 /* Set the new sample time */
4401 hadc->Instance->SMPR1 |= __HAL_ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
4402 }
4403
4404
4405 /* Configure the offset: offset enable/disable, channel, offset value */
4406
4407 /* Shift the offset in function of the selected ADC resolution. */
4408 /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
4409 tmpOffsetShifted = __HAL_ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset);
4410
4411 switch (sConfig->OffsetNumber)
4412 {
4413 case ADC_OFFSET_1:
4414 /* Configure offset register 1: */
4415 /* - Enable offset */
4416 /* - Set channel number */
4417 /* - Set offset value */
4418 hadc->Instance->OFR1 &= ~( ADC_OFR1_OFFSET1_CH |
4419 ADC_OFR1_OFFSET1 );
4420 hadc->Instance->OFR1 |= ( ADC_OFR1_OFFSET1_EN |
4421 __HAL_ADC_OFR_CHANNEL(sConfig->Channel) |
4422 tmpOffsetShifted );
4423 break;
4424
4425 case ADC_OFFSET_2:
4426 /* Configure offset register 2: */
4427 /* - Enable offset */
4428 /* - Set channel number */
4429 /* - Set offset value */
4430 hadc->Instance->OFR2 &= ~( ADC_OFR2_OFFSET2_CH |
4431 ADC_OFR2_OFFSET2 );
4432 hadc->Instance->OFR2 |= ( ADC_OFR2_OFFSET2_EN |
4433 __HAL_ADC_OFR_CHANNEL(sConfig->Channel) |
4434 tmpOffsetShifted );
4435 break;
4436
4437 case ADC_OFFSET_3:
4438 /* Configure offset register 3: */
4439 /* - Enable offset */
4440 /* - Set channel number */
4441 /* - Set offset value */
4442 hadc->Instance->OFR3 &= ~( ADC_OFR3_OFFSET3_CH |
4443 ADC_OFR3_OFFSET3 );
4444 hadc->Instance->OFR3 |= ( ADC_OFR3_OFFSET3_EN |
4445 __HAL_ADC_OFR_CHANNEL(sConfig->Channel) |
4446 tmpOffsetShifted );
4447 break;
4448
4449 case ADC_OFFSET_4:
4450 /* Configure offset register 1: */
4451 /* - Enable offset */
4452 /* - Set channel number */
4453 /* - Set offset value */
4454 hadc->Instance->OFR4 &= ~( ADC_OFR4_OFFSET4_CH |
4455 ADC_OFR4_OFFSET4 );
4456 hadc->Instance->OFR4 |= ( ADC_OFR4_OFFSET4_EN |
4457 __HAL_ADC_OFR_CHANNEL(sConfig->Channel) |
4458 tmpOffsetShifted );
4459 break;
4460
4461 /* Case ADC_OFFSET_NONE */
4462 default :
4463 /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled. If this is the case, offset OFRx is disabled. */
4464 if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == __HAL_ADC_OFR_CHANNEL(sConfig->Channel))
4465 {
4466 /* Disable offset OFR1*/
4467 hadc->Instance->OFR1 &= ~ADC_OFR1_OFFSET1_EN;
4468 }
4469 if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == __HAL_ADC_OFR_CHANNEL(sConfig->Channel))
4470 {
4471 /* Disable offset OFR2*/
4472 hadc->Instance->OFR2 &= ~ADC_OFR2_OFFSET2_EN;
4473 }
4474 if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == __HAL_ADC_OFR_CHANNEL(sConfig->Channel))
4475 {
4476 /* Disable offset OFR3*/
4477 hadc->Instance->OFR3 &= ~ADC_OFR3_OFFSET3_EN;
4478 }
4479 if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == __HAL_ADC_OFR_CHANNEL(sConfig->Channel))
4480 {
4481 /* Disable offset OFR4*/
4482 hadc->Instance->OFR4 &= ~ADC_OFR4_OFFSET4_EN;
4483 }
4484 break;
4485 }
4486
4487 }
4488
4489
4490 /* Parameters update conditioned to ADC state: */
4491 /* Parameters that can be updated only when ADC is disabled: */
4492 /* - Single or differential mode */
4493 /* - Internal measurement channels: Vbat/VrefInt/TempSensor */
4494 if (__HAL_ADC_IS_ENABLED(hadc) == RESET)
4495 {
4496 /* Configuration of differential mode */
4497 if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
4498 {
4499 /* Disable differential mode (default mode: single-ended) */
4500 hadc->Instance->DIFSEL &= ~(__HAL_ADC_DIFSEL_CHANNEL(sConfig->Channel));
4501 }
4502 else
4503 {
4504 /* Enable differential mode */
4505 hadc->Instance->DIFSEL |= __HAL_ADC_DIFSEL_CHANNEL(sConfig->Channel);
4506
4507 /* Sampling time configuration of channel ADC_IN+1 (negative input) */
4508 /* For channels 10 to 18 */
4509 if (sConfig->Channel > ADC_CHANNEL_10)
4510 {
4511 /* Clear the old sample time */
4512 hadc->Instance->SMPR2 &= ~__HAL_ADC_SMPR2(ADC_SMPR1_SMP0, (sConfig->Channel +1));
4513
4514 /* Set the new sample time */
4515 hadc->Instance->SMPR2 |= __HAL_ADC_SMPR2(sConfig->SamplingTime, (sConfig->Channel +1));
4516 }
4517 else /* For channels 0 to 9 */
4518 {
4519 /* Clear the old sample time */
4520 hadc->Instance->SMPR1 &= ~__HAL_ADC_SMPR1(ADC_SMPR2_SMP10, (sConfig->Channel +1));
4521
4522 /* Set the new sample time */
4523 hadc->Instance->SMPR1 |= __HAL_ADC_SMPR1(sConfig->SamplingTime, (sConfig->Channel +1));
4524 }
4525 }
4526
4527
4528 /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */
4529 /* internal measurement paths enable: If internal channel selected, */
4530 /* enable dedicated internal buffers and path. */
4531 /* Note: these internal measurement paths can be disabled using */
4532 /* HAL_ADC_DeInit(). */
4533
4534 /* Configuration of common ADC parameters */
4535 /* Pointer to the common control register to which is belonging hadc */
4536 /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
4537 /* control registers) */
4538 tmpADC_Common = __HAL_ADC_COMMON_REGISTER(hadc);
4539
4540 /* If the requested internal measurement path has already been enabled, */
4541 /* bypass the configuration processing. */
4542 if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
4543 (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) ||
4544 ( (sConfig->Channel == ADC_CHANNEL_VBAT) &&
4545 (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) ||
4546 ( (sConfig->Channel == ADC_CHANNEL_VREFINT) &&
4547 (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
4548 )
4549 {
4550 /* Configuration of common ADC parameters (continuation) */
4551 /* Set handle of the other ADC sharing the same common register */
4552 __HAL_ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
4553
4554 /* Software is allowed to change common parameters only when all ADCs */
4555 /* of the common group are disabled. */
4556 if ((__HAL_ADC_IS_ENABLED(hadc) == RESET) &&
4557 ( (tmphadcSharingSameCommonRegister.Instance == HAL_NULL) ||
4558 (__HAL_ADC_IS_ENABLED(&tmphadcSharingSameCommonRegister) == RESET) ))
4559 {
4560 /* If Channel_16 is selected, enable Temp. sensor measurement path */
4561 /* Note: Temp. sensor internal channels available on ADC1 only */
4562 if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1))
4563 {
4564 tmpADC_Common->CCR |= ADC_CCR_TSEN;
4565
4566 /* Delay for temperature sensor stabilization time */
4567 while(WaitLoopIndex < ADC_TEMPSENSOR_DELAY_CPU_CYCLES)
4568 {
4569 WaitLoopIndex++;
4570 }
4571 }
4572 /* If Channel_17 is selected, enable VBAT measurement path */
4573 /* Note: VBAT internal channels available on ADC1 only */
4574 else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && (hadc->Instance == ADC1))
4575 {
4576 tmpADC_Common->CCR |= ADC_CCR_VBATEN;
4577 }
4578 /* If Channel_18 is selected, enable VREFINT measurement path */
4579 /* Note: VrefInt internal channels available on all ADCs, but only */
4580 /* one ADC is allowed to be connected to VrefInt at the same */
4581 /* time. */
4582 else if (sConfig->Channel == ADC_CHANNEL_VREFINT)
4583 {
4584 tmpADC_Common->CCR |= ADC_CCR_VREFEN;
4585 }
4586 }
4587 /* If the requested internal measurement path has already been */
4588 /* enabled and other ADC of the common group are enabled, internal */
4589 /* measurement paths cannot be enabled. */
4590 else
4591 {
4592 /* Update ADC state machine to error */
4593 hadc->State = HAL_ADC_STATE_ERROR;
4594
4595 tmpHALStatus = HAL_ERROR;
4596 }
4597 }
4598
4599 }
4600
4601 }
4602 /* If a conversion is on going on regular group, no update on regular */
4603 /* channel could be done on neither of the channel configuration structure */
4604 /* parameters. */
4605 else
4606 {
4607 /* Update ADC state machine to error */
4608 hadc->State = HAL_ADC_STATE_ERROR;
4609
4610 tmpHALStatus = HAL_ERROR;
4611 }
4612
4613 /* Process unlocked */
4614 __HAL_UNLOCK(hadc);
4615
4616 /* Return function status */
4617 return tmpHALStatus;
4618 }
4619 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
4620 /* STM32F302xC || STM32F303xC || STM32F358xx || */
4621 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
4622 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
4623
4624 #if defined(STM32F373xC) || defined(STM32F378xx)
4625 /**
4626 * @brief Configures the the selected channel to be linked to the regular
4627 * group.
4628 * @note In case of usage of internal measurement channels:
4629 * Vbat/VrefInt/TempSensor.
4630 * The recommended sampling time is at least:
4631 * - For devices STM32F37x: 17.1us for temperature sensor
4632 * - For the other STM32F3 devices: 2.2us for each of channels
4633 * Vbat/VrefInt/TempSensor.
4634 * These internal paths can be be disabled using function
4635 * HAL_ADC_DeInit().
4636 * @note Possibility to update parameters on the fly:
4637 * This function initializes channel into regular group, following
4638 * calls to this function can be used to reconfigure some parameters
4639 * of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
4640 * the ADC.
4641 * The setting of these parameters is conditioned to ADC state.
4642 * For parameters constraints, see comments of structure
4643 * "ADC_ChannelConfTypeDef".
4644 * @param hadc: ADC handle
4645 * @param sConfig: Structure of ADC channel for regular group.
4646 * @retval HAL status
4647 */
4648 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
4649 {
4650 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
4651
4652 /* Check the parameters */
4653 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
4654 assert_param(IS_ADC_CHANNEL(sConfig->Channel));
4655 assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
4656 assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
4657
4658 /* Process locked */
4659 __HAL_LOCK(hadc);
4660
4661
4662 /* Regular sequence configuration */
4663 /* For Rank 1 to 6 */
4664 if (sConfig->Rank < 7)
4665 {
4666 /* Clear the old SQx bits for the selected rank */
4667 hadc->Instance->SQR3 &= ~__HAL_ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
4668
4669 /* Set the SQx bits for the selected rank */
4670 hadc->Instance->SQR3 |= __HAL_ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
4671 }
4672 /* For Rank 7 to 12 */
4673 else if (sConfig->Rank < 13)
4674 {
4675 /* Clear the old SQx bits for the selected rank */
4676 hadc->Instance->SQR2 &= ~__HAL_ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
4677
4678 /* Set the SQx bits for the selected rank */
4679 hadc->Instance->SQR2 |= __HAL_ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
4680 }
4681 /* For Rank 13 to 16 */
4682 else
4683 {
4684 /* Clear the old SQx bits for the selected rank */
4685 hadc->Instance->SQR1 &= ~__HAL_ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
4686
4687 /* Set the SQx bits for the selected rank */
4688 hadc->Instance->SQR1 |= __HAL_ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
4689 }
4690
4691 /* Channel sampling time configuration */
4692 /* For channels 10 to 18 */
4693 if (sConfig->Channel > ADC_CHANNEL_10)
4694 {
4695 /* Clear the old sample time */
4696 hadc->Instance->SMPR1 &= ~__HAL_ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
4697
4698 /* Set the new sample time */
4699 hadc->Instance->SMPR1 |= __HAL_ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
4700 }
4701 else /* For channels 0 to 9 */
4702 {
4703 /* Clear the old sample time */
4704 hadc->Instance->SMPR2 &= ~__HAL_ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
4705
4706 /* Set the new sample time */
4707 hadc->Instance->SMPR2 |= __HAL_ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
4708 }
4709
4710 /* if ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor / VREFINT measurement path */
4711 if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT))
4712 {
4713 hadc->Instance->CR2 |= ADC_CR2_TSVREFE;
4714 }
4715
4716 /* if ADC1 Channel_17 is selected, enable VBAT measurement path */
4717 else if (sConfig->Channel == ADC_CHANNEL_VBAT)
4718 {
4719 SYSCFG->CFGR1 |= SYSCFG_CFGR1_VBAT;
4720 }
4721
4722
4723 /* Process unlocked */
4724 __HAL_UNLOCK(hadc);
4725
4726 /* Return function status */
4727 return tmpHALStatus;
4728 }
4729 #endif /* STM32F373xC || STM32F378xx */
4730
4731 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
4732 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
4733 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
4734 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
4735 /**
4736 * @brief Configures the ADC injected group and the selected channel to be
4737 * linked to the injected group.
4738 * @note Possibility to update parameters on the fly:
4739 * This function initializes injected group, following calls to this
4740 * function can be used to reconfigure some parameters of structure
4741 * "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC.
4742 * The setting of these parameters is conditioned to ADC state.
4743 * For parameters constraints, see comments of structure
4744 * "ADC_InjectionConfTypeDef".
4745 * @note In case of usage of internal measurement channels:
4746 * Vbat/VrefInt/TempSensor.
4747 * The recommended sampling time is at least:
4748 * - For devices STM32F37x: 17.1us for temperature sensor
4749 * - For the other STM32F3 devices: 2.2us for each of channels
4750 * Vbat/VrefInt/TempSensor.
4751 * These internal paths can be be disabled using function
4752 * HAL_ADC_DeInit().
4753 * @note To reset injected sequencer, function HAL_ADCEx_InjectedStop() can
4754 * be used.
4755 * @note Caution: For Injected Context Queue use: a context must be fully
4756 * defined before start of injected conversion: all channels configured
4757 * consecutively for the same ADC instance. Therefore, Number of calls of
4758 * HAL_ADCEx_InjectedConfigChannel() must correspond to value of parameter
4759 * InjectedNbrOfConversion for each context.
4760 * - Example 1: If 1 context intended to be used (or not use of this feature:
4761 * QueueInjectedContext=DISABLE) and usage of the 3 first injected ranks
4762 * (InjectedNbrOfConversion=3), HAL_ADCEx_InjectedConfigChannel() must be
4763 * called once for each channel (3 times) before launching a conversion.
4764 * This function must not be called to configure the 4th injected channel:
4765 * it would start a new context into context queue.
4766 * - Example 2: If 2 contexts intended to be used and usage of the 3 first
4767 * injected ranks (InjectedNbrOfConversion=3),
4768 * HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and
4769 * for each context (3 channels x 2 contexts = 6 calls). Conversion can
4770 * start once the 1st context is set. The 2nd context can be set on the fly.
4771 * @param hadc: ADC handle
4772 * @param sConfigInjected: Structure of ADC injected group and ADC channel for
4773 * injected group.
4774 * @retval None
4775 */
4776 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
4777 {
4778 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
4779 ADC_Common_TypeDef *tmpADC_Common;
4780 ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
4781 uint32_t tmpOffsetShifted;
4782 uint32_t WaitLoopIndex = 0;
4783
4784 /* Injected context queue feature: temporary JSQR variables defined in */
4785 /* static to be passed over calls of this function */
4786 static uint32_t tmp_JSQR_ContextQueueBeingBuilt_ADCInstance = 0;
4787 static uint32_t tmp_JSQR_ContextQueueBeingBuilt_Channel_Count = 0;
4788 static uint32_t tmp_JSQR_ContextQueueBeingBuilt;
4789
4790 /* Check the parameters */
4791 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
4792 assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
4793 assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
4794 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff));
4795 assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
4796 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
4797 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
4798 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext));
4799 assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
4800 assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
4801 assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber));
4802 assert_param(IS_ADC_RANGE(__HAL_ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
4803
4804 /* Verification of channel number: Channels 1 to 14 are available in */
4805 /* differential mode. Channels 15, 16, 17, 18 can be used only in */
4806 /* single-ended mode. */
4807 if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
4808 {
4809 assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
4810 }
4811 else
4812 {
4813 assert_param(IS_ADC_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
4814 }
4815
4816 /* Process locked */
4817 __HAL_LOCK(hadc);
4818
4819
4820 /* Configuration of Injected group sequencer. */
4821 /* Hardware constraint: Must fully define injected context register JSQR */
4822 /* before make it entering into injected sequencer queue. */
4823 /* */
4824 /* - if scan mode is disabled: */
4825 /* * Injected channels sequence length is set to 0x00: 1 channel */
4826 /* converted (channel on injected rank 1) */
4827 /* Parameter "InjectedNbrOfConversion" is discarded. */
4828 /* * Injected context register JSQR setting is simple: register is fully */
4829 /* defined on one call of this function (for injected rank 1) and can */
4830 /* be entered into queue directly. */
4831 /* - if scan mode is enabled: */
4832 /* * Injected channels sequence length is set to parameter */
4833 /* "InjectedNbrOfConversion". */
4834 /* * Injected context register JSQR setting more complex: register is */
4835 /* fully defined over successive calls of this function, for each */
4836 /* injected channel rank. It is entered into queue only when all */
4837 /* injected ranks have been set. */
4838 /* Note: Scan mode is not present by hardware on this device, but used */
4839 /* by software for alignment over all STM32 devices. */
4840
4841 if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) ||
4842 (sConfigInjected->InjectedNbrOfConversion == 1) )
4843 {
4844 /* Configuration of context register JSQR: */
4845 /* - number of ranks in injected group sequencer: fixed to 1st rank */
4846 /* (scan mode disabled, only rank 1 used) */
4847 /* - external trigger to start conversion */
4848 /* - external trigger polarity */
4849 /* - channel set to rank 1 (scan mode disabled, only rank 1 used) */
4850
4851 if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
4852 {
4853 tmp_JSQR_ContextQueueBeingBuilt = 0;
4854
4855 /* Enable external trigger if trigger selection is different of */
4856 /* software start. */
4857 /* Note: This configuration keeps the hardware feature of parameter */
4858 /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
4859 /* software start. */
4860 if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
4861 {
4862 tmp_JSQR_ContextQueueBeingBuilt |= ( __HAL_ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) |
4863 __HAL_ADC_JSQR_JEXTSEL(hadc, sConfigInjected->ExternalTrigInjecConv) |
4864 sConfigInjected->ExternalTrigInjecConvEdge );
4865 }
4866 else
4867 {
4868 tmp_JSQR_ContextQueueBeingBuilt |= ( __HAL_ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) );
4869 }
4870
4871 hadc->Instance->JSQR = tmp_JSQR_ContextQueueBeingBuilt;
4872
4873 }
4874 /* If another injected rank than rank1 was intended to be set, and could */
4875 /* not due to ScanConvMode disabled, error is reported. */
4876 else
4877 {
4878 /* Update ADC state machine to error */
4879 hadc->State = HAL_ADC_STATE_ERROR;
4880
4881 tmpHALStatus = HAL_ERROR;
4882 }
4883
4884 }
4885 else
4886 {
4887 /* Case of scan mode enabled, several channels to set into injected group */
4888 /* sequencer. */
4889 /* Procedure to define injected context register JSQR over successive */
4890 /* calls of this function, for each injected channel rank: */
4891
4892 /* 1. Start new context and set parameters related to all injected */
4893 /* channels: injected sequence length and trigger */
4894 if (tmp_JSQR_ContextQueueBeingBuilt_Channel_Count == 0)
4895 {
4896 /* Memorize ADC instance on the context being built */
4897 tmp_JSQR_ContextQueueBeingBuilt_ADCInstance = (uint32_t)hadc->Instance;
4898 /* Initialize number of channels that will be configured on the context */
4899 /* being built */
4900 tmp_JSQR_ContextQueueBeingBuilt_Channel_Count = sConfigInjected->InjectedNbrOfConversion;
4901 /* Initialize value that will be set into register JSQR */
4902 tmp_JSQR_ContextQueueBeingBuilt = (uint32_t)0x00000000;
4903
4904 /* Configuration of context register JSQR: */
4905 /* - number of ranks in injected group sequencer */
4906 /* - external trigger to start conversion */
4907 /* - external trigger polarity */
4908 tmp_JSQR_ContextQueueBeingBuilt = 0;
4909
4910 /* Enable external trigger if trigger selection is different of */
4911 /* software start. */
4912 /* Note: This configuration keeps the hardware feature of parameter */
4913 /* ExternalTrigInjecConvEdge "trigger edge none" equivalent to */
4914 /* software start. */
4915 if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
4916 {
4917 tmp_JSQR_ContextQueueBeingBuilt |= ((sConfigInjected->InjectedNbrOfConversion - (uint32_t)1) |
4918 __HAL_ADC_JSQR_JEXTSEL(hadc, sConfigInjected->ExternalTrigInjecConv) |
4919 sConfigInjected->ExternalTrigInjecConvEdge );
4920 }
4921 else
4922 {
4923 tmp_JSQR_ContextQueueBeingBuilt |= ((sConfigInjected->InjectedNbrOfConversion - (uint32_t)1) );
4924 }
4925
4926 }
4927
4928 /* Verification that context being built is still targeting the same ADC */
4929 /* instance. If ADC instance mixing during context being built, ADC state */
4930 /* changed to error */
4931 if ((uint32_t)hadc->Instance == tmp_JSQR_ContextQueueBeingBuilt_ADCInstance)
4932 {
4933 /* 2. Continue setting of context under definition with parameter */
4934 /* related to each channel: channel rank sequence */
4935 /* Clear the old JSQx bits for the selected rank */
4936 tmp_JSQR_ContextQueueBeingBuilt &= ~__HAL_ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank);
4937
4938 /* Set the JSQx bits for the selected rank */
4939 tmp_JSQR_ContextQueueBeingBuilt |= __HAL_ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank);
4940
4941 /* Decrease channel count after setting into temporary JSQR variable */
4942 tmp_JSQR_ContextQueueBeingBuilt_Channel_Count --;
4943
4944 /* 3. End of context setting: If last channel set, then write context */
4945 /* into register JSQR and make it enter into queue */
4946 if (tmp_JSQR_ContextQueueBeingBuilt_Channel_Count == 0)
4947 {
4948 hadc->Instance->JSQR = tmp_JSQR_ContextQueueBeingBuilt;
4949
4950 /* Reset context channels count for next context configuration */
4951 tmp_JSQR_ContextQueueBeingBuilt_Channel_Count =0;
4952 }
4953 }
4954 else
4955 {
4956 /* Update ADC state machine to error */
4957 hadc->State = HAL_ADC_STATE_ERROR;
4958
4959 /* Process unlocked */
4960 __HAL_UNLOCK(hadc);
4961
4962 return HAL_ERROR;
4963 }
4964 }
4965
4966
4967 /* Parameters update conditioned to ADC state: */
4968 /* Parameters that can be updated when ADC is disabled or enabled without */
4969 /* conversion on going on injected group: */
4970 /* - Injected context queue: Queue disable (active context is kept) or */
4971 /* enable (context decremented, up to 2 contexts queued) */
4972 /* - Injected discontinuous mode: can be enabled only if auto-injected */
4973 /* mode is disabled. */
4974 if (__HAL_ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
4975 {
4976 hadc->Instance->CFGR &= ~(ADC_CFGR_JQM |
4977 ADC_CFGR_JDISCEN );
4978
4979 /* If auto-injected mode is disabled: no constraint */
4980 if (sConfigInjected->AutoInjectedConv == DISABLE)
4981 {
4982 hadc->Instance->CFGR |= (__HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext) |
4983 __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS(sConfigInjected->InjectedDiscontinuousConvMode) );
4984 }
4985 /* If auto-injected mode is enabled: Injected discontinuous setting is */
4986 /* discarded. */
4987 else
4988 {
4989 hadc->Instance->CFGR |= __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext);
4990
4991 /* If injected discontinuous mode was intended to be set and could not */
4992 /* due to auto-injected enabled, error is reported. */
4993 if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
4994 {
4995 /* Update ADC state machine to error */
4996 hadc->State = HAL_ADC_STATE_ERROR;
4997
4998 tmpHALStatus = HAL_ERROR;
4999 }
5000 }
5001
5002 }
5003
5004
5005 /* Parameters update conditioned to ADC state: */
5006 /* Parameters that can be updated when ADC is disabled or enabled without */
5007 /* conversion on going on regular and injected groups: */
5008 /* - Automatic injected conversion: can be enabled if injected group */
5009 /* external triggers are disabled. */
5010 /* - Channel sampling time */
5011 /* - Channel offset */
5012 if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
5013 {
5014 /* Configure Automatic injected conversion */
5015 hadc->Instance->CFGR &= ~(ADC_CFGR_JAUTO);
5016
5017 /* If injected group external triggers are disabled (set to injected */
5018 /* software start): no constraint */
5019 if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
5020 {
5021 hadc->Instance->CFGR |= __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION(sConfigInjected->AutoInjectedConv);
5022 }
5023 /* If Automatic injected conversion was intended to be set and could not */
5024 /* due to injected group external triggers enabled, error is reported. */
5025 else
5026 {
5027 if (sConfigInjected->AutoInjectedConv == ENABLE)
5028 {
5029 /* Update ADC state machine to error */
5030 hadc->State = HAL_ADC_STATE_ERROR;
5031
5032 tmpHALStatus = HAL_ERROR;
5033 }
5034 }
5035
5036
5037 /* Sampling time configuration of the selected channel */
5038 /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
5039 if (sConfigInjected->InjectedChannel > ADC_CHANNEL_10)
5040 {
5041 /* Clear the old sample time */
5042 hadc->Instance->SMPR2 &= ~__HAL_ADC_SMPR2(ADC_SMPR1_SMP0, sConfigInjected->InjectedChannel);
5043
5044 /* Set the new sample time */
5045 hadc->Instance->SMPR2 |= __HAL_ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
5046 }
5047 else /* ADC_Channel include in ADC_Channel_[0..9] */
5048 {
5049 /* Clear the old sample time */
5050 hadc->Instance->SMPR1 &= ~__HAL_ADC_SMPR1(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel);
5051
5052 /* Set the new sample time */
5053 hadc->Instance->SMPR1 |= __HAL_ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
5054 }
5055
5056 /* Configure the offset: offset enable/disable, channel, offset value */
5057
5058 /* Shift the offset in function of the selected ADC resolution. */
5059 /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
5060 tmpOffsetShifted = __HAL_ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
5061
5062 switch (sConfigInjected->InjectedOffsetNumber)
5063 {
5064 case ADC_OFFSET_1:
5065 /* Configure offset register 1: */
5066 /* - Enable offset */
5067 /* - Set channel number */
5068 /* - Set offset value */
5069 hadc->Instance->OFR1 &= ~( ADC_OFR1_OFFSET1_CH |
5070 ADC_OFR1_OFFSET1 );
5071 hadc->Instance->OFR1 |= ( ADC_OFR1_OFFSET1_EN |
5072 __HAL_ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) |
5073 tmpOffsetShifted );
5074 break;
5075
5076 case ADC_OFFSET_2:
5077 /* Configure offset register 2: */
5078 /* - Enable offset */
5079 /* - Set channel number */
5080 /* - Set offset value */
5081 hadc->Instance->OFR2 &= ~( ADC_OFR2_OFFSET2_CH |
5082 ADC_OFR2_OFFSET2 );
5083 hadc->Instance->OFR2 |= ( ADC_OFR2_OFFSET2_EN |
5084 __HAL_ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) |
5085 tmpOffsetShifted );
5086 break;
5087
5088 case ADC_OFFSET_3:
5089 /* Configure offset register 3: */
5090 /* - Enable offset */
5091 /* - Set channel number */
5092 /* - Set offset value */
5093 hadc->Instance->OFR3 &= ~( ADC_OFR3_OFFSET3_CH |
5094 ADC_OFR3_OFFSET3 );
5095 hadc->Instance->OFR3 |= ( ADC_OFR3_OFFSET3_EN |
5096 __HAL_ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) |
5097 tmpOffsetShifted );
5098 break;
5099
5100 case ADC_OFFSET_4:
5101 /* Configure offset register 1: */
5102 /* - Enable offset */
5103 /* - Set channel number */
5104 /* - Set offset value */
5105 hadc->Instance->OFR4 &= ~( ADC_OFR4_OFFSET4_CH |
5106 ADC_OFR4_OFFSET4 );
5107 hadc->Instance->OFR4 |= ( ADC_OFR4_OFFSET4_EN |
5108 __HAL_ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) |
5109 tmpOffsetShifted );
5110 break;
5111
5112 /* Case ADC_OFFSET_NONE */
5113 default :
5114 /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled. If this is the case, offset OFRx is disabled. */
5115 if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == __HAL_ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
5116 {
5117 /* Disable offset OFR1*/
5118 hadc->Instance->OFR1 &= ~ADC_OFR1_OFFSET1_EN;
5119 }
5120 if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == __HAL_ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
5121 {
5122 /* Disable offset OFR2*/
5123 hadc->Instance->OFR2 &= ~ADC_OFR2_OFFSET2_EN;
5124 }
5125 if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == __HAL_ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
5126 {
5127 /* Disable offset OFR3*/
5128 hadc->Instance->OFR3 &= ~ADC_OFR3_OFFSET3_EN;
5129 }
5130 if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == __HAL_ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
5131 {
5132 /* Disable offset OFR4*/
5133 hadc->Instance->OFR4 &= ~ADC_OFR4_OFFSET4_EN;
5134 }
5135 break;
5136 }
5137
5138 }
5139
5140
5141 /* Parameters update conditioned to ADC state: */
5142 /* Parameters that can be updated only when ADC is disabled: */
5143 /* - Single or differential mode */
5144 /* - Internal measurement channels: Vbat/VrefInt/TempSensor */
5145 if (__HAL_ADC_IS_ENABLED(hadc) == RESET)
5146 {
5147 /* Configuration of differential mode */
5148 if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
5149 {
5150 /* Disable differential mode (default mode: single-ended) */
5151 hadc->Instance->DIFSEL &= ~(__HAL_ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel));
5152 }
5153 else
5154 {
5155 /* Enable differential mode */
5156 hadc->Instance->DIFSEL |= __HAL_ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel);
5157
5158 /* Sampling time configuration of channel ADC_IN+1 (negative input) */
5159 /* For channels 10 to 18 */
5160 if (sConfigInjected->InjectedChannel > ADC_CHANNEL_10)
5161 {
5162 /* Clear the old sample time */
5163 hadc->Instance->SMPR2 &= ~__HAL_ADC_SMPR2(ADC_SMPR1_SMP0, (sConfigInjected->InjectedChannel +1));
5164
5165 /* Set the new sample time */
5166 hadc->Instance->SMPR2 |= __HAL_ADC_SMPR2(sConfigInjected->InjectedSamplingTime, (sConfigInjected->InjectedChannel +1));
5167 }
5168 else /* For channels 0 to 9 */
5169 {
5170 /* Clear the old sample time */
5171 hadc->Instance->SMPR1 &= ~__HAL_ADC_SMPR1(ADC_SMPR2_SMP10, (sConfigInjected->InjectedChannel +1));
5172
5173 /* Set the new sample time */
5174 hadc->Instance->SMPR1 |= __HAL_ADC_SMPR1(sConfigInjected->InjectedSamplingTime, (sConfigInjected->InjectedChannel +1));
5175 }
5176 }
5177
5178
5179 /* Management of internal measurement channels: Vbat/VrefInt/TempSensor */
5180 /* internal measurement paths enable: If internal channel selected, */
5181 /* enable dedicated internal buffers and path. */
5182 /* Note: these internal measurement paths can be disabled using */
5183 /* HAL_ADC_deInit(). */
5184
5185 /* Configuration of common ADC parameters */
5186 /* Pointer to the common control register to which is belonging hadc */
5187 /* (Depending on STM32F3 product, there may be up to 4 ADC and 2 common */
5188 /* control registers) */
5189 tmpADC_Common = __HAL_ADC_COMMON_REGISTER(hadc);
5190
5191 /* If the requested internal measurement path has already been enabled, */
5192 /* bypass the configuration processing. */
5193 if (( (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) &&
5194 (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN)) ) ||
5195 ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) &&
5196 (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN)) ) ||
5197 ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) &&
5198 (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
5199 )
5200 {
5201 /* Configuration of common ADC parameters (continuation) */
5202 /* Set handle of the other ADC sharing the same common register */
5203 __HAL_ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
5204
5205 /* Software is allowed to change common parameters only when all ADCs */
5206 /* of the common group are disabled. */
5207 if ((__HAL_ADC_IS_ENABLED(hadc) == RESET) &&
5208 ( (tmphadcSharingSameCommonRegister.Instance == HAL_NULL) ||
5209 (__HAL_ADC_IS_ENABLED(&tmphadcSharingSameCommonRegister) == RESET) ))
5210 {
5211 /* If Channel_16 is selected, enable Temp. sensor measurement path */
5212 /* Note: Temp. sensor internal channels available on ADC1 only */
5213 if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) && (hadc->Instance == ADC1))
5214 {
5215 tmpADC_Common->CCR |= ADC_CCR_TSEN;
5216
5217 /* Delay for temperature sensor stabilization time */
5218 while(WaitLoopIndex < ADC_TEMPSENSOR_DELAY_CPU_CYCLES)
5219 {
5220 WaitLoopIndex++;
5221 }
5222 }
5223 /* If Channel_17 is selected, enable VBAT measurement path */
5224 /* Note: VBAT internal channels available on ADC1 only */
5225 else if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT) && (hadc->Instance == ADC1))
5226 {
5227 tmpADC_Common->CCR |= ADC_CCR_VBATEN;
5228 }
5229 /* If Channel_18 is selected, enable VREFINT measurement path */
5230 /* Note: VrefInt internal channels available on all ADCs, but only */
5231 /* one ADC is allowed to be connected to VrefInt at the same */
5232 /* time. */
5233 else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
5234 {
5235 tmpADC_Common->CCR |= ADC_CCR_VREFEN;
5236 }
5237 }
5238 /* If the requested internal measurement path has already been enabled */
5239 /* and other ADC of the common group are enabled, internal */
5240 /* measurement paths cannot be enabled. */
5241 else
5242 {
5243 /* Update ADC state machine to error */
5244 hadc->State = HAL_ADC_STATE_ERROR;
5245
5246 tmpHALStatus = HAL_ERROR;
5247 }
5248 }
5249
5250 }
5251
5252 /* Process unlocked */
5253 __HAL_UNLOCK(hadc);
5254
5255 /* Return function status */
5256 return tmpHALStatus;
5257 }
5258 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
5259 /* STM32F302xC || STM32F303xC || STM32F358xx || */
5260 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
5261 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
5262
5263 #if defined(STM32F373xC) || defined(STM32F378xx)
5264 /**
5265 * @brief Configures the ADC injected group and the selected channel to be
5266 * linked to the injected group.
5267 * @note Possibility to update parameters on the fly:
5268 * This function initializes injected group, following calls to this
5269 * function can be used to reconfigure some parameters of structure
5270 * "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC.
5271 * The setting of these parameters is conditioned to ADC state:
5272 * this function must be called when ADC is not under conversion.
5273 * @note In case of usage of internal measurement channels:
5274 * Vbat/VrefInt/TempSensor.
5275 * The recommended sampling time is at least:
5276 * - For devices STM32F37x: 17.1us for temperature sensor
5277 * - For the other STM32F3 devices: 2.2us for each of channels
5278 * Vbat/VrefInt/TempSensor.
5279 * These internal paths can be be disabled using function
5280 * HAL_ADC_DeInit().
5281 * @param hadc: ADC handle
5282 * @param sConfigInjected: Structure of ADC injected group and ADC channel for
5283 * injected group.
5284 * @retval None
5285 */
5286 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
5287 {
5288 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
5289
5290 /* Check the parameters */
5291 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
5292 assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
5293 assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
5294 assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
5295 assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
5296 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
5297 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
5298 assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
5299 assert_param(IS_ADC_RANGE(sConfigInjected->InjectedOffset));
5300
5301 /* Process locked */
5302 __HAL_LOCK(hadc);
5303
5304
5305 /* Configuration of injected group sequencer: */
5306 /* - if scan mode is disabled, injected channels sequence length is set to */
5307 /* 0x00: 1 channel converted (channel on regular rank 1) */
5308 /* Parameter "InjectedNbrOfConversion" is discarded. */
5309 /* Note: Scan mode is present by hardware on this device and, if */
5310 /* disabled, discards automatically nb of conversions. Anyway, nb of */
5311 /* conversions is forced to 0x00 for alignment over all STM32 devices. */
5312 /* - if scan mode is enabled, injected channels sequence length is set to */
5313 /* parameter ""InjectedNbrOfConversion". */
5314 if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
5315 {
5316 if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
5317 {
5318 /* Clear the old SQx bits for all injected ranks */
5319 hadc->Instance->JSQR &= ~ (ADC_JSQR_JL |
5320 ADC_JSQR_JSQ4 |
5321 ADC_JSQR_JSQ3 |
5322 ADC_JSQR_JSQ2 |
5323 ADC_JSQR_JSQ1 );
5324
5325 /* Set the SQx bits for the selected rank */
5326 hadc->Instance->JSQR |= __HAL_ADC_JSQR_RK(sConfigInjected->InjectedChannel,
5327 ADC_INJECTED_RANK_1,
5328 0x01);
5329 }
5330 /* If another injected rank than rank1 was intended to be set, and could */
5331 /* not due to ScanConvMode disabled, error is reported. */
5332 else
5333 {
5334 /* Update ADC state machine to error */
5335 hadc->State = HAL_ADC_STATE_ERROR;
5336
5337 tmpHALStatus = HAL_ERROR;
5338 }
5339 }
5340 else
5341 {
5342 /* Clear the old SQx bits for the selected rank */
5343 hadc->Instance->JSQR &= ~ (ADC_JSQR_JL |
5344 __HAL_ADC_JSQR_RK(ADC_JSQR_JSQ1,
5345 sConfigInjected->InjectedRank,
5346 sConfigInjected->InjectedNbrOfConversion) );
5347
5348 /* Since injected channels rank conv. order depends on total number of */
5349 /* injected conversions, selected rank must be below or equal to total */
5350 /* number of injected conversions to be updated. */
5351 if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion)
5352 {
5353 /* Set the SQx bits for the selected rank */
5354 hadc->Instance->JSQR |= (__HAL_ADC_JSQR_JL(sConfigInjected->InjectedNbrOfConversion) |
5355 __HAL_ADC_JSQR_RK(sConfigInjected->InjectedChannel,
5356 sConfigInjected->InjectedRank,
5357 sConfigInjected->InjectedNbrOfConversion) );
5358 }
5359 }
5360
5361
5362 /* Configuration of injected group: external trigger */
5363 /* - external trigger to start conversion */
5364 /* - external trigger polarity */
5365 /* If Automatic injected conversion disabled: always set to 1, */
5366 /* because needed for all triggers: external trigger of SW start) */
5367 /* Hardware constraint: ADC must be disabled */
5368 /* Note: In case of ADC already enabled, caution to not launch an unwanted */
5369 /* conversion while modifying register CR2 by writing 1 to bit ADON */
5370 /* These settings are modified only if required parameters are different as */
5371 /* current setting */
5372 if ((__HAL_ADC_IS_ENABLED(hadc) == RESET) &&
5373 ((hadc->Instance->CR2 & ADC_CR2_JEXTSEL) != sConfigInjected->ExternalTrigInjecConv) )
5374 {
5375 hadc->Instance->CR2 &= ~( ADC_CR2_JEXTSEL |
5376 ADC_CR2_JEXTTRIG |
5377 ADC_CR2_ADON );
5378
5379 /* If automatic injected conversion is intended to be enabled and */
5380 /* conditions are fulfilled (injected group external triggers are */
5381 /* disabled), then keep injected external trigger JEXTTRIG cleared */
5382 if (!((sConfigInjected->AutoInjectedConv == ENABLE) &&
5383 (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)))
5384 {
5385 hadc->Instance->CR2 |= ( sConfigInjected->ExternalTrigInjecConv |
5386 ADC_CR2_JEXTTRIG );
5387 }
5388 else
5389 {
5390 hadc->Instance->CR2 |= ( sConfigInjected->ExternalTrigInjecConv );
5391 }
5392 }
5393
5394
5395 /* Configuration of injected group */
5396 /* - Automatic injected conversion */
5397 /* - Injected discontinuous mode */
5398 hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO |
5399 ADC_CR1_JDISCEN );
5400
5401 /* Automatic injected conversion can be enabled if injected group */
5402 /* external triggers are disabled. */
5403 if (sConfigInjected->AutoInjectedConv == ENABLE)
5404 {
5405 if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
5406 {
5407 hadc->Instance->CR1 |= ADC_CR1_JAUTO;
5408 }
5409 else
5410 {
5411 /* Update ADC state machine to error */
5412 hadc->State = HAL_ADC_STATE_ERROR;
5413
5414 tmpHALStatus = HAL_ERROR;
5415 }
5416 }
5417
5418 /* Injected discontinuous can be enabled only if auto-injected mode is */
5419 /* disabled. */
5420 if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
5421 {
5422 if (sConfigInjected->AutoInjectedConv == DISABLE)
5423 {
5424 hadc->Instance->CR1 |= ADC_CR1_JDISCEN;
5425 }
5426 else
5427 {
5428 /* Update ADC state machine to error */
5429 hadc->State = HAL_ADC_STATE_ERROR;
5430
5431 tmpHALStatus = HAL_ERROR;
5432 }
5433 }
5434
5435
5436 /* Channel sampling time configuration */
5437 /* For channels 10 to 18 */
5438 if (sConfigInjected->InjectedChannel > ADC_CHANNEL_10)
5439 {
5440 /* Clear the old sample time */
5441 hadc->Instance->SMPR1 &= ~__HAL_ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel);
5442
5443 /* Set the new sample time */
5444 hadc->Instance->SMPR1 |= __HAL_ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
5445 }
5446 else /* For channels 0 to 9 */
5447 {
5448 /* Clear the old sample time */
5449 hadc->Instance->SMPR2 &= ~__HAL_ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel);
5450
5451 /* Set the new sample time */
5452 hadc->Instance->SMPR2 |= __HAL_ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
5453 }
5454
5455 /* Configure the offset: offset enable/disable, InjectedChannel, offset value */
5456 switch(sConfigInjected->InjectedRank)
5457 {
5458 case 1:
5459 /* Set injected channel 1 offset */
5460 hadc->Instance->JOFR1 &= ~(ADC_JOFR1_JOFFSET1);
5461 hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset;
5462 break;
5463 case 2:
5464 /* Set injected channel 2 offset */
5465 hadc->Instance->JOFR2 &= ~(ADC_JOFR2_JOFFSET2);
5466 hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset;
5467 break;
5468 case 3:
5469 /* Set injected channel 3 offset */
5470 hadc->Instance->JOFR3 &= ~(ADC_JOFR3_JOFFSET3);
5471 hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset;
5472 break;
5473 default:
5474 /* Set injected channel 4 offset */
5475 hadc->Instance->JOFR4 &= ~(ADC_JOFR4_JOFFSET4);
5476 hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset;
5477 break;
5478 }
5479
5480 /* if ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor / VREFINT measurement path */
5481 if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT))
5482 {
5483 hadc->Instance->CR2 |= ADC_CR2_TSVREFE;
5484 }
5485 /* if ADC1 Channel_17 is selected, enable VBAT measurement path */
5486 else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)
5487 {
5488 SYSCFG->CFGR1 |= SYSCFG_CFGR1_VBAT;
5489 }
5490
5491 /* Process unlocked */
5492 __HAL_UNLOCK(hadc);
5493
5494 /* Return function status */
5495 return tmpHALStatus;
5496 }
5497 #endif /* STM32F373xC || STM32F378xx */
5498
5499 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
5500 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
5501 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
5502 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
5503 /**
5504 * @brief Configures the analog watchdog.
5505 * @note Possibility to update parameters on the fly:
5506 * This function initializes the selected analog watchdog, following
5507 * calls to this function can be used to reconfigure some parameters
5508 * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting
5509 * the ADC.
5510 * The setting of these parameters is conditioned to ADC state.
5511 * For parameters constraints, see comments of structure
5512 * "ADC_AnalogWDGConfTypeDef".
5513 * @param hadc: ADC handle
5514 * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
5515 * @retval HAL status
5516 */
5517 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
5518 {
5519 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
5520
5521 uint32_t tmpAWDHighThresholdShifted;
5522 uint32_t tmpAWDLowThresholdShifted;
5523
5524 uint32_t tmpADCFlagAWD2orAWD3;
5525 uint32_t tmpADCITAWD2orAWD3;
5526
5527 /* Check the parameters */
5528 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
5529 assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
5530 assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
5531 assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
5532 assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
5533
5534 /* Verify if threshold is within the selected ADC resolution */
5535 assert_param(IS_ADC_RANGE(__HAL_ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
5536 assert_param(IS_ADC_RANGE(__HAL_ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
5537
5538 /* Process locked */
5539 __HAL_LOCK(hadc);
5540
5541 /* Parameters update conditioned to ADC state: */
5542 /* Parameters that can be updated when ADC is disabled or enabled without */
5543 /* conversion on going on regular and injected groups: */
5544 /* - Analog watchdog channels */
5545 /* - Analog watchdog thresholds */
5546 if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
5547 {
5548
5549 /* Analog watchdogs configuration */
5550 if(AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
5551 {
5552 /* Configuration of analog watchdog: */
5553 /* - Set the analog watchdog enable mode: regular and/or injected */
5554 /* groups, one or overall group of channels. */
5555 /* - Set the Analog watchdog channel (is not used if watchdog */
5556 /* mode "all channels": ADC_CFGR_AWD1SGL=0). */
5557 hadc->Instance->CFGR &= ~( ADC_CFGR_AWD1SGL |
5558 ADC_CFGR_JAWD1EN |
5559 ADC_CFGR_AWD1EN |
5560 ADC_CFGR_AWD1CH );
5561
5562 hadc->Instance->CFGR |= ( AnalogWDGConfig->WatchdogMode |
5563 __HAL_ADC_CFGR_AWD1CH(AnalogWDGConfig->Channel) );
5564
5565 /* Shift the offset in function of the selected ADC resolution: */
5566 /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */
5567 /* are set to 0 */
5568 tmpAWDHighThresholdShifted = __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
5569 tmpAWDLowThresholdShifted = __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
5570
5571 /* Set the high and low thresholds */
5572 hadc->Instance->TR1 &= ~(ADC_TR1_HT1 | ADC_TR1_LT1);
5573 hadc->Instance->TR1 |= ( __HAL_ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) |
5574 tmpAWDLowThresholdShifted );
5575
5576 /* Clear the ADC Analog watchdog flag (in case of let enabled by */
5577 /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
5578 /* or HAL_ADC_PollForEvent(). */
5579 __HAL_ADC_CLEAR_FLAG(hadc, ADC_IT_AWD1);
5580
5581 /* Configure ADC Analog watchdog interrupt */
5582 if(AnalogWDGConfig->ITMode == ENABLE)
5583 {
5584 /* Enable the ADC Analog watchdog interrupt */
5585 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD1);
5586 }
5587 else
5588 {
5589 /* Disable the ADC Analog watchdog interrupt */
5590 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD1);
5591 }
5592
5593 }
5594 /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */
5595 else
5596 {
5597 /* Shift the threshold in function of the selected ADC resolution */
5598 /* have to be left-aligned on bit 7, the LSB (right bits) are set to 0 */
5599 tmpAWDHighThresholdShifted = __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
5600 tmpAWDLowThresholdShifted = __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
5601
5602 if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
5603 {
5604 /* Set the Analog watchdog channel or group of channels. This also */
5605 /* enables the watchdog. */
5606 /* Note: Conditionnal register reset, because several channels can be */
5607 /* set by successive calls of this function. */
5608 if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE)
5609 {
5610 hadc->Instance->AWD2CR |= __HAL_ADC_CFGR_AWD23CR(AnalogWDGConfig->Channel);
5611 }
5612 else
5613 {
5614 hadc->Instance->AWD2CR &= ~ADC_AWD2CR_AWD2CH;
5615 }
5616
5617 /* Set the high and low thresholds */
5618 hadc->Instance->TR2 &= ~(ADC_TR2_HT2 | ADC_TR2_LT2);
5619 hadc->Instance->TR2 |= ( __HAL_ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) |
5620 tmpAWDLowThresholdShifted );
5621
5622 /* Set temporary variable to flag and IT of AWD2 or AWD3 for further */
5623 /* settings. */
5624 tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD2;
5625 tmpADCITAWD2orAWD3 = ADC_IT_AWD2;
5626 }
5627 /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
5628 else
5629 {
5630 /* Set the Analog watchdog channel or group of channels. This also */
5631 /* enables the watchdog. */
5632 /* Note: Conditionnal register reset, because several channels can be */
5633 /* set by successive calls of this function. */
5634 if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE)
5635 {
5636 hadc->Instance->AWD3CR |= __HAL_ADC_CFGR_AWD23CR(AnalogWDGConfig->Channel);
5637 }
5638 else
5639 {
5640 hadc->Instance->AWD3CR &= ~ADC_AWD3CR_AWD3CH;
5641 }
5642
5643 /* Set the high and low thresholds */
5644 hadc->Instance->TR3 &= ~(ADC_TR3_HT3 | ADC_TR3_LT3);
5645 hadc->Instance->TR3 |= ( __HAL_ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) |
5646 tmpAWDLowThresholdShifted );
5647
5648 /* Set temporary variable to flag and IT of AWD2 or AWD3 for further */
5649 /* settings. */
5650 tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD3;
5651 tmpADCITAWD2orAWD3 = ADC_IT_AWD3;
5652 }
5653
5654 /* Clear the ADC Analog watchdog flag (in case of let enabled by */
5655 /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
5656 /* or HAL_ADC_PollForEvent(). */
5657 __HAL_ADC_CLEAR_FLAG(hadc, tmpADCFlagAWD2orAWD3);
5658
5659 /* Configure ADC Analog watchdog interrupt */
5660 if(AnalogWDGConfig->ITMode == ENABLE)
5661 {
5662 __HAL_ADC_ENABLE_IT(hadc, tmpADCITAWD2orAWD3);
5663 }
5664 else
5665 {
5666 __HAL_ADC_DISABLE_IT(hadc, tmpADCITAWD2orAWD3);
5667 }
5668 }
5669
5670 }
5671 /* If a conversion is on going on regular or injected groups, no update */
5672 /* could be done on neither of the AWD configuration structure parameters. */
5673 else
5674 {
5675 /* Update ADC state machine to error */
5676 hadc->State = HAL_ADC_STATE_ERROR;
5677
5678 tmpHALStatus = HAL_ERROR;
5679 }
5680
5681
5682 /* Process unlocked */
5683 __HAL_UNLOCK(hadc);
5684
5685 /* Return function status */
5686 return tmpHALStatus;
5687 }
5688 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
5689 /* STM32F302xC || STM32F303xC || STM32F358xx || */
5690 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
5691 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
5692
5693 #if defined(STM32F373xC) || defined(STM32F378xx)
5694 /**
5695 * @brief Configures the analog watchdog.
5696 * @param hadc: ADC handle
5697 * @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
5698 * @retval HAL status
5699 */
5700 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
5701 {
5702 /* Check the parameters */
5703 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
5704 assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
5705 assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
5706 assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
5707 assert_param(IS_ADC_RANGE(AnalogWDGConfig->HighThreshold));
5708 assert_param(IS_ADC_RANGE(AnalogWDGConfig->LowThreshold));
5709
5710 /* Process locked */
5711 __HAL_LOCK(hadc);
5712
5713 /* Analog watchdog configuration */
5714
5715 /* Configure ADC Analog watchdog interrupt */
5716 if(AnalogWDGConfig->ITMode == ENABLE)
5717 {
5718 /* Enable the ADC Analog watchdog interrupt */
5719 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
5720 }
5721 else
5722 {
5723 /* Disable the ADC Analog watchdog interrupt */
5724 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
5725 }
5726
5727 /* Configuration of analog watchdog: */
5728 /* - Set the analog watchdog enable mode: regular and/or injected groups, */
5729 /* one or all channels. */
5730 /* - Set the Analog watchdog channel (is not used if watchdog */
5731 /* mode "all channels": ADC_CFGR_AWD1SGL=0). */
5732 hadc->Instance->CR1 &= ~( ADC_CR1_AWDSGL |
5733 ADC_CR1_JAWDEN |
5734 ADC_CR1_AWDEN |
5735 ADC_CR1_AWDCH );
5736
5737 hadc->Instance->CR1 |= ( AnalogWDGConfig->WatchdogMode |
5738 AnalogWDGConfig->Channel );
5739
5740 /* Set the high threshold */
5741 hadc->Instance->HTR = AnalogWDGConfig->HighThreshold;
5742
5743 /* Set the low threshold */
5744 hadc->Instance->LTR = AnalogWDGConfig->LowThreshold;
5745
5746 /* Process unlocked */
5747 __HAL_UNLOCK(hadc);
5748
5749 /* Return function status */
5750 return HAL_OK;
5751 }
5752 #endif /* STM32F373xC || STM32F378xx */
5753
5754
5755 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
5756 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
5757 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
5758 /**
5759 * @brief Enable ADC multimode and configure multimode parameters
5760 * @note Possibility to update parameters on the fly:
5761 * This function initializes multimode parameters, following
5762 * calls to this function can be used to reconfigure some parameters
5763 * of structure "ADC_MultiModeTypeDef" on the fly, without reseting
5764 * the ADCs (both ADCs of the common group).
5765 * The setting of these parameters is conditioned to ADC state.
5766 * For parameters constraints, see comments of structure
5767 * "ADC_MultiModeTypeDef".
5768 * @note To change back configuration from multimode to single mode, ADC must
5769 * be reset (using function HAL_ADC_Init() ).
5770 * @param hadc: ADC handle
5771 * @param multimode : Structure of ADC multimode configuration
5772 * @retval HAL status
5773 */
5774 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
5775 {
5776 HAL_StatusTypeDef tmpHALStatus = HAL_OK;
5777 ADC_Common_TypeDef *tmpADC_Common;
5778 ADC_HandleTypeDef tmphadcSharingSameCommonRegister;
5779
5780 /* Check the parameters */
5781 assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
5782 assert_param(IS_ADC_MODE(multimode->Mode));
5783 assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode));
5784 assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
5785
5786 /* Process locked */
5787 __HAL_LOCK(hadc);
5788
5789
5790 /* Set handle of the other ADC sharing the same common register */
5791 __HAL_ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
5792
5793 /* Parameters update conditioned to ADC state: */
5794 /* Parameters that can be updated when ADC is disabled or enabled without */
5795 /* conversion on going on regular group: */
5796 /* - Multimode DMA configuration */
5797 /* - Multimode DMA mode */
5798 /* Parameters that can be updated only when ADC is disabled: */
5799 /* - Multimode mode selection */
5800 /* - Multimode delay */
5801 /* To optimize code, all multimode settings can be set when both ADCs of */
5802 /* the common group are in state: disabled. */
5803 if ((__HAL_ADC_IS_ENABLED(hadc) == RESET) &&
5804 (__HAL_ADC_IS_ENABLED(&tmphadcSharingSameCommonRegister) == RESET) )
5805 {
5806
5807 /* Pointer to the common control register to which is belonging hadc */
5808 /* (Depending on STM32F3 product, there may have up to 4 ADC and 2 common */
5809 /* control registers) */
5810 tmpADC_Common = __HAL_ADC_COMMON_REGISTER(hadc);
5811
5812 /* Configuration of ADC common group ADC1&ADC2, ADC3&ADC4 if available */
5813 /* (ADC2, ADC3, ADC4 availability depends on STM32 product) */
5814 /* - set the selected multimode */
5815 /* - DMA access mode */
5816 /* - Set delay between two sampling phases */
5817 /* Note: Delay range depends on selected resolution: */
5818 /* from 1 to 12 clock cycles for 12 bits */
5819 /* from 1 to 10 clock cycles for 10 bits, */
5820 /* from 1 to 8 clock cycles for 8 bits */
5821 /* from 1 to 6 clock cycles for 6 bits */
5822 /* If a higher delay is selected, it will be clamped to maximum delay */
5823 /* range */
5824 tmpADC_Common->CCR &= ~( ADC_CCR_MULTI |
5825 ADC_CCR_MDMA |
5826 ADC_CCR_DELAY |
5827 ADC_CCR_DMACFG );
5828
5829 tmpADC_Common->CCR |= ( multimode->Mode |
5830 multimode->DMAAccessMode |
5831 multimode->TwoSamplingDelay |
5832 __HAL_ADC_CCR_MULTI_DMACONTREQ(hadc->Init.DMAContinuousRequests) );
5833 }
5834 /* If one of the ADC sharing the same common group is enabled, no update */
5835 /* could be done on neither of the multimode structure parameters. */
5836 else
5837 {
5838 /* Update ADC state machine to error */
5839 hadc->State = HAL_ADC_STATE_ERROR;
5840
5841 tmpHALStatus = HAL_ERROR;
5842 }
5843
5844
5845 /* Process unlocked */
5846 __HAL_UNLOCK(hadc);
5847
5848 /* Return function status */
5849 return tmpHALStatus;
5850 }
5851 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
5852 /* STM32F302xC || STM32F303xC || STM32F358xx || */
5853 /* STM32F303x8 || STM32F328xx || STM32F334x8 */
5854
5855 /**
5856 * @}
5857 */
5858
5859 /**
5860 * @}
5861 */
5862
5863 /** @defgroup ADCEx_Private_Functions ADC Extended Private Functions
5864 * @{
5865 */
5866 /**
5867 * @brief DMA transfer complete callback.
5868 * @param hdma: pointer to DMA handle.
5869 * @retval None
5870 */
5871 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
5872 {
5873 /* Retrieve ADC handle corresponding to current DMA handle */
5874 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
5875
5876 /* Update state machine on conversion status if not in error state */
5877 if(hadc->State != HAL_ADC_STATE_ERROR)
5878 {
5879 /* Update ADC state machine */
5880 if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG)
5881 {
5882 /* Check if a conversion is ready on injected group */
5883 if(hadc->State == HAL_ADC_STATE_EOC_INJ)
5884 {
5885 /* Change ADC state */
5886 hadc->State = HAL_ADC_STATE_EOC_INJ_REG;
5887 }
5888 else
5889 {
5890 /* Change ADC state */
5891 hadc->State = HAL_ADC_STATE_EOC_REG;
5892 }
5893 }
5894 }
5895
5896 /* Conversion complete callback */
5897 HAL_ADC_ConvCpltCallback(hadc);
5898 }
5899
5900 /**
5901 * @brief DMA half transfer complete callback.
5902 * @param hdma: pointer to DMA handle.
5903 * @retval None
5904 */
5905 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
5906 {
5907 /* Retrieve ADC handle corresponding to current DMA handle */
5908 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
5909
5910 /* Half conversion callback */
5911 HAL_ADC_ConvHalfCpltCallback(hadc);
5912 }
5913
5914 /**
5915 * @brief DMA error callback
5916 * @param hdma: pointer to DMA handle.
5917 * @retval None
5918 */
5919 static void ADC_DMAError(DMA_HandleTypeDef *hdma)
5920 {
5921 /* Retrieve ADC handle corresponding to current DMA handle */
5922 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
5923
5924 /* Change ADC state */
5925 hadc->State = HAL_ADC_STATE_ERROR;
5926
5927 /* Set ADC error code to DMA error */
5928 hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
5929
5930 /* Error callback */
5931 HAL_ADC_ErrorCallback(hadc);
5932 }
5933
5934 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
5935 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
5936 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
5937 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
5938 /**
5939 * @brief Enable the selected ADC.
5940 * @note Prerequisite condition to use this function: ADC must be disabled
5941 * and voltage regulator must be enabled (done into HAL_ADC_Init()).
5942 * @param hadc: ADC handle
5943 * @retval HAL status.
5944 */
5945 static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
5946 {
5947 uint32_t tickstart = 0;
5948
5949 /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
5950 /* enabling phase not yet completed: flag ADC ready not yet set). */
5951 /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
5952 /* causes: ADC clock not running, ...). */
5953 if (__HAL_ADC_IS_ENABLED(hadc) == RESET)
5954 {
5955 /* Check if conditions to enable the ADC are fulfilled */
5956 if (__HAL_ADC_ENABLING_CONDITIONS(hadc) == RESET)
5957 {
5958 /* Update ADC state machine to error */
5959 hadc->State = HAL_ADC_STATE_ERROR;
5960
5961 /* Set ADC error code to ADC IP internal error */
5962 hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
5963
5964 return HAL_ERROR;
5965 }
5966
5967 /* Enable the ADC peripheral */
5968 __HAL_ADC_ENABLE(hadc);
5969
5970 /* Wait for ADC effectively enabled */
5971 tickstart = HAL_GetTick();
5972
5973 while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
5974 {
5975 if((HAL_GetTick()-tickstart) > ADC_ENABLE_TIMEOUT)
5976 {
5977 /* Update ADC state machine to error */
5978 hadc->State = HAL_ADC_STATE_ERROR;
5979
5980 /* Set ADC error code to ADC IP internal error */
5981 hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
5982
5983 return HAL_ERROR;
5984 }
5985 }
5986 }
5987
5988 /* Return HAL status */
5989 return HAL_OK;
5990 }
5991
5992 /**
5993 * @brief Disable the selected ADC.
5994 * @note Prerequisite condition to use this function: ADC conversions must be
5995 * stopped.
5996 * @param hadc: ADC handle
5997 * @retval HAL status.
5998 */
5999 static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
6000 {
6001 uint32_t tickstart = 0;
6002
6003 /* Verification if ADC is not already disabled: */
6004 /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
6005 /* disabled. */
6006 if (__HAL_ADC_IS_ENABLED(hadc) != RESET )
6007 {
6008 /* Check if conditions to disable the ADC are fulfilled */
6009 if (__HAL_ADC_DISABLING_CONDITIONS(hadc) != RESET)
6010 {
6011 /* Disable the ADC peripheral */
6012 __HAL_ADC_DISABLE(hadc);
6013 }
6014 else
6015 {
6016 /* Update ADC state machine to error */
6017 hadc->State = HAL_ADC_STATE_ERROR;
6018
6019 /* Set ADC error code to ADC IP internal error */
6020 hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
6021
6022 return HAL_ERROR;
6023 }
6024
6025 /* Wait for ADC effectively disabled */
6026 tickstart = HAL_GetTick();
6027
6028 while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
6029 {
6030 if((HAL_GetTick()-tickstart) > ADC_DISABLE_TIMEOUT)
6031 {
6032 /* Update ADC state machine to error */
6033 hadc->State = HAL_ADC_STATE_ERROR;
6034
6035 /* Set ADC error code to ADC IP internal error */
6036 hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
6037
6038 return HAL_ERROR;
6039 }
6040 }
6041 }
6042
6043 /* Return HAL status */
6044 return HAL_OK;
6045 }
6046
6047
6048 /**
6049 * @brief Stop ADC conversion.
6050 * @note Prerequisite condition to use this function: ADC conversions must be
6051 * stopped to disable the ADC.
6052 * @param hadc: ADC handle
6053 * @param ConversionGroup: ADC group regular and/or injected.
6054 * This parameter can be one of the following values:
6055 * @arg REGULAR_GROUP: ADC regular conversion type.
6056 * @arg INJECTED_GROUP: ADC injected conversion type.
6057 * @arg REGULAR_INJECTED_GROUP: ADC regular and injected conversion type.
6058 * @retval HAL status.
6059 */
6060 static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup)
6061 {
6062 uint32_t tmp_ADC_CR_ADSTART_JADSTART = 0;
6063 uint32_t tickstart = 0;
6064 uint32_t Conversion_Timeout_CPU_cycles = 0;
6065
6066 /* Check the parameters */
6067 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
6068 assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
6069
6070 /* Verification if ADC is not already stopped (on regular and injected */
6071 /* groups) to bypass this function if not needed. */
6072 if (__HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc))
6073 {
6074 /* Particular case of continuous auto-injection mode combined with */
6075 /* auto-delay mode. */
6076 /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */
6077 /* injected group stop ADC_CR_JADSTP). */
6078 /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */
6079 /* (see reference manual). */
6080 if ((HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CFGR_JAUTO))
6081 && (hadc->Init.ContinuousConvMode==ENABLE)
6082 && (hadc->Init.LowPowerAutoWait==ENABLE))
6083 {
6084 /* Use stop of regular group */
6085 ConversionGroup = REGULAR_GROUP;
6086
6087 /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
6088 while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == RESET)
6089 {
6090 if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES *4))
6091 {
6092 /* Update ADC state machine to error */
6093 hadc->State = HAL_ADC_STATE_ERROR;
6094
6095 /* Set ADC error code to ADC IP internal error */
6096 hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
6097
6098 return HAL_ERROR;
6099 }
6100 Conversion_Timeout_CPU_cycles ++;
6101 }
6102
6103 /* Clear JEOS */
6104 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
6105 }
6106
6107 /* Stop potential conversion on going on regular group */
6108 if (ConversionGroup != INJECTED_GROUP)
6109 {
6110 /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
6111 if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) &&
6112 HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
6113 {
6114 /* Stop conversions on regular group */
6115 hadc->Instance->CR |= ADC_CR_ADSTP;
6116 }
6117 }
6118
6119 /* Stop potential conversion on going on injected group */
6120 if (ConversionGroup != REGULAR_GROUP)
6121 {
6122 /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
6123 if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_JADSTART) &&
6124 HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) )
6125 {
6126 /* Stop conversions on injected group */
6127 hadc->Instance->CR |= ADC_CR_JADSTP;
6128 }
6129 }
6130
6131 /* Selection of start and stop bits in function of regular or injected group */
6132 switch(ConversionGroup)
6133 {
6134 case REGULAR_INJECTED_GROUP:
6135 tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
6136 break;
6137 case INJECTED_GROUP:
6138 tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
6139 break;
6140 /* Case REGULAR_GROUP */
6141 default:
6142 tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
6143 break;
6144 }
6145
6146 /* Wait for conversion effectively stopped */
6147 tickstart = HAL_GetTick();
6148
6149 while((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != RESET)
6150 {
6151 if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
6152 {
6153 /* Update ADC state machine to error */
6154 hadc->State = HAL_ADC_STATE_ERROR;
6155
6156 /* Set ADC error code to ADC IP internal error */
6157 hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
6158
6159 return HAL_ERROR;
6160 }
6161 }
6162
6163 }
6164
6165 /* Return HAL status */
6166 return HAL_OK;
6167 }
6168 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
6169 /* STM32F302xC || STM32F303xC || STM32F358xx || */
6170 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
6171 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
6172
6173 #if defined(STM32F373xC) || defined(STM32F378xx)
6174 /**
6175 * @brief Enable the selected ADC.
6176 * @note Prerequisite condition to use this function: ADC must be disabled
6177 * and voltage regulator must be enabled (done into HAL_ADC_Init()).
6178 * @param hadc: ADC handle
6179 * @retval HAL status.
6180 */
6181 static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
6182 {
6183 uint32_t WaitLoopIndex = 0;
6184 uint32_t tickstart = 0;
6185
6186 /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
6187 /* enabling phase not yet completed: flag ADC ready not yet set). */
6188 /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
6189 /* causes: ADC clock not running, ...). */
6190 if (__HAL_ADC_IS_ENABLED(hadc) == RESET)
6191 {
6192 /* Enable the Peripheral */
6193 __HAL_ADC_ENABLE(hadc);
6194
6195 /* Delay for ADC stabilization time. */
6196 /* Delay fixed to worst case: maximum CPU frequency */
6197 while(WaitLoopIndex < ADC_STAB_DELAY_CPU_CYCLES)
6198 {
6199 WaitLoopIndex++;
6200 }
6201
6202 /* Get timeout */
6203 tickstart = HAL_GetTick();
6204
6205 /* Wait for ADC effectively enabled */
6206 while(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
6207 {
6208 if((HAL_GetTick()-tickstart) > ADC_ENABLE_TIMEOUT)
6209 {
6210 /* Update ADC state machine to error */
6211 hadc->State = HAL_ADC_STATE_ERROR;
6212
6213 /* Set ADC error code to ADC IP internal error */
6214 hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
6215
6216 /* Process unlocked */
6217 __HAL_UNLOCK(hadc);
6218
6219 return HAL_ERROR;
6220 }
6221 }
6222 }
6223
6224 /* Return HAL status */
6225 return HAL_OK;
6226 }
6227
6228 /**
6229 * @brief Stop ADC conversion and disable the selected ADC
6230 * @note Prerequisite condition to use this function: ADC conversions must be
6231 * stopped to disable the ADC.
6232 * @param hadc: ADC handle
6233 * @retval HAL status.
6234 */
6235 static HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
6236 {
6237 uint32_t tickstart = 0;
6238
6239 /* Verification if ADC is not already disabled: */
6240 if (__HAL_ADC_IS_ENABLED(hadc) != RESET)
6241 {
6242 /* Disable the ADC peripheral */
6243 __HAL_ADC_DISABLE(hadc);
6244
6245 /* Get timeout */
6246 tickstart = HAL_GetTick();
6247
6248 /* Wait for ADC effectively disabled */
6249 while(__HAL_ADC_IS_ENABLED(hadc) != RESET)
6250 {
6251 if((HAL_GetTick()-tickstart) > ADC_ENABLE_TIMEOUT)
6252 {
6253 /* Update ADC state machine to error */
6254 hadc->State = HAL_ADC_STATE_ERROR;
6255
6256 /* Set ADC error code to ADC IP internal error */
6257 hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
6258
6259 return HAL_ERROR;
6260 }
6261 }
6262 }
6263
6264 /* Return HAL status */
6265 return HAL_OK;
6266 }
6267 #endif /* STM32F373xC || STM32F378xx */
6268 /**
6269 * @}
6270 */
6271
6272 #endif /* HAL_ADC_MODULE_ENABLED */
6273 /**
6274 * @}
6275 */
6276
6277 /**
6278 * @}
6279 */
6280
6281 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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