]> git.gir.st - tmk_keyboard.git/blob - tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_adc_ex.h
git://git.gir.st / tmk_keyboard.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Squashed 'tmk_core/' changes from 7967731..b9e0ea0
[tmk_keyboard.git] / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_STM / TARGET_STM32F3 / stm32f3xx_hal_adc_ex.h
1 /**
2 ******************************************************************************
3 * @file stm32f3xx_hal_adc_ex.h
4 * @author MCD Application Team
5 * @version V1.1.0
6 * @date 12-Sept-2014
7 * @brief Header file containing functions prototypes of ADC HAL library.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F3xx_ADC_EX_H
40 #define __STM32F3xx_ADC_EX_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f3xx_hal_def.h"
48
49 /** @addtogroup STM32F3xx_HAL_Driver
50 * @{
51 */
52
53 /** @addtogroup ADCEx ADC Extended HAL module driver
54 * @{
55 */
56
57 /* Exported types ------------------------------------------------------------*/
58 /** @defgroup ADCEx_Exported_Types ADC Extented Exported Types
59 * @{
60 */
61 struct __ADC_HandleTypeDef;
62
63 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
64 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
65 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
66 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
67 /**
68 * @brief Structure definition of ADC initialization and regular group
69 * @note Parameters of this structure are shared within 2 scopes:
70 * - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, DataAlign,
71 * ScanConvMode, EOCSelection, LowPowerAutoWait.
72 * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv, DMAContinuousRequests, Overrun.
73 * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
74 * ADC state can be either:
75 * - For all parameters: ADC disabled
76 * - For all parameters except 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on regular group.
77 * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on regular and injected groups.
78 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
79 * without error reporting without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly).
80 */
81 typedef struct
82 {
83 uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from AHB clock or asynchronous clock derived from ADC dedicated PLL 72MHz) and clock prescaler.
84 The clock is common for all the ADCs.
85 This parameter can be a value of @ref ADCEx_ClockPrescaler
86 Note: In case of usage of channels on injected group, ADC frequency should be low than AHB clock frequency /4 for resolution 12 or 10 bits,
87 AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
88 Note: In case of usage of the ADC dedicated PLL clock, this clock must be preliminarily enabled and prescaler set at RCC top level.
89 Note: This parameter can be modified only if all ADCs of the common ADC group are disabled (for products with several ADCs) */
90 uint32_t Resolution; /*!< Configures the ADC resolution.
91 This parameter can be a value of @ref ADCEx_Resolution */
92 uint32_t DataAlign; /*!< Specifies ADC data alignment to right (for resolution 12 bits: MSB on register bit 11 and LSB on register bit 0) (default setting)
93 or to left (for resolution 12 bits, if offset disabled: MSB on register bit 15 and LSB on register bit 4, if offset enabled: MSB on register bit 14 and LSB on register bit 3).
94 See reference manual for alignments with other resolutions.
95 This parameter can be a value of @ref ADCEx_Data_align */
96 uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
97 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
98 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
99 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
100 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
101 Scan direction is upward: from rank1 to rank 'n'.
102 This parameter can be a value of @ref ADCEx_Scan_mode */
103 uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
104 This parameter can be a value of @ref ADCEx_EOCSelection. */
105 uint32_t LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous
106 conversion (for regular group) or previous sequence (for injected group) has been treated by user software.
107 This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications.
108 This parameter can be set to ENABLE or DISABLE.
109 Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer.
110 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed
111 and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion. */
112 uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
113 after the selected trigger occurred (software start or external trigger).
114 This parameter can be set to ENABLE or DISABLE. */
115 uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
116 To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
117 This parameter must be a number between Min_Data = 1 and Max_Data = 16.
118 Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without continuous mode or external trigger that could lauch a conversion). */
119 uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
120 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
121 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
122 This parameter can be set to ENABLE or DISABLE. */
123 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
124 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
125 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
126 uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
127 If set to ADC_SOFTWARE_START, external triggers are disabled.
128 This parameter can be a value of @ref ADCEx_External_trigger_source_Regular
129 Caution: For devices with several ADCs, external trigger source is common to ADC common group (for example: ADC1&ADC2, ADC3&ADC4, if available) */
130 uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
131 If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
132 This parameter can be a value of @ref ADCEx_External_trigger_edge_Regular */
133 uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
134 or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
135 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
136 This parameter can be set to ENABLE or DISABLE.
137 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could lauch a conversion). */
138 uint32_t Overrun; /*!< Select the behaviour in case of overrun: data overwritten (default) or preserved.
139 This parameter is for regular group only.
140 This parameter can be a value of @ref ADCEx_Overrun
141 Note: Case of overrun set to data preserved and usage with end on conversion interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved into function HAL_ADC_ConvCpltCallback() (called before end of conversion flags clear).
142 Note: Error reporting in function of conversion mode:
143 - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data overwritten, user can willingly not read the conversion data each time, this is not considered as an erroneous case.
144 - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register, any data missed would be abnormal). */
145 }ADC_InitTypeDef;
146
147 /**
148 * @brief Structure definition of ADC channel for regular group
149 * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
150 * ADC state can be either:
151 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
152 * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group.
153 * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups.
154 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
155 * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
156 */
157 typedef struct
158 {
159 uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
160 This parameter can be a value of @ref ADCEx_channels
161 Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
162 uint32_t Rank; /*!< Specifies the rank in the regular group sequencer.
163 This parameter can be a value of @ref ADCEx_regular_rank
164 Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
165 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
166 Unit: ADC clock cycles
167 Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
168 This parameter can be a value of @ref ADCEx_sampling_times
169 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
170 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
171 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
172 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
173 Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 2.2us min). */
174 uint32_t SingleDiff; /*!< Selection of single-ended or differential input.
175 In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
176 Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
177 This parameter must be a value of @ref ADCEx_SingleDifferential
178 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
179 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
180 Note: Channels 1 to 14 are available in differential mode. Channels 15, 16, 17, 18 can be used only in single-ended mode.
181 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
182 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
183 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) */
184 uint32_t OffsetNumber; /*!< Selects the offset number
185 This parameter can be a value of @ref ADCEx_OffsetNumber
186 Caution: Only one channel is allowed per channel. If another channel was on this offset number, the offset will be changed to the new channel */
187 uint32_t Offset; /*!< Defines the offset to be subtracted from the raw converted data when convert channels.
188 Offset value must be a positive number.
189 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
190 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could lauch a conversion). */
191 }ADC_ChannelConfTypeDef;
192
193 /**
194 * @brief Structure definition of ADC injected group and ADC channel for injected group
195 * @note Parameters of this structure are shared within 2 scopes:
196 * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset
197 * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
198 * AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
199 * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
200 * ADC state can be either:
201 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')
202 * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext': ADC enabled without conversion on going on injected group.
203 * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.
204 * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going on regular and injected groups.
205 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
206 * without error reporting without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
207 */
208 typedef struct
209 {
210 uint32_t InjectedChannel; /*!< Configure the ADC injected channel
211 This parameter can be a value of @ref ADCEx_channels
212 Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
213 uint32_t InjectedRank; /*!< The rank in the regular group sequencer
214 This parameter must be a value of @ref ADCEx_injected_rank
215 Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
216 uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
217 Unit: ADC clock cycles
218 Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
219 This parameter can be a value of @ref ADCEx_sampling_times
220 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
221 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
222 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
223 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
224 Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 2.2us min). */
225 uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input.
226 In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
227 Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
228 This parameter must be a value of @ref ADCEx_SingleDifferential
229 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
230 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
231 Note: Channels 1 to 14 are available in differential mode. Channels 15, 16, 17, 18 can be used only in single-ended mode.
232 Note: When configuring a channel 'i' in differential mode, the channel 'i-1' is not usable separately.
233 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
234 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) */
235 uint32_t InjectedOffsetNumber; /*!< Selects the offset number
236 This parameter can be a value of @ref ADCEx_OffsetNumber
237 Caution: Only one channel is allowed per offset number. If another channel was on this offset number, the offset will be changed to the new channel. */
238 uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data.
239 Offset value must be a positive number.
240 Depending of ADC resolution selected (12, 10, 8 or 6 bits),
241 this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
242 uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
243 To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
244 This parameter must be a number between Min_Data = 1 and Max_Data = 4.
245 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
246 configure a channel on injected group can impact the configuration of other channels previously set. */
247 uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
248 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
249 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
250 This parameter can be set to ENABLE or DISABLE.
251 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
252 Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
253 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
254 configure a channel on injected group can impact the configuration of other channels previously set. */
255 uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
256 This parameter can be set to ENABLE or DISABLE.
257 Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
258 Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
259 Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
260 To maintain JAUTO always enabled, DMA must be configured in circular mode.
261 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
262 configure a channel on injected group can impact the configuration of other channels previously set. */
263 uint32_t QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled.
264 This parameter can be set to ENABLE or DISABLE.
265 If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a
266 new injected context is set when queue is full, error is triggered by interruption and through function 'HAL_ADCEx_InjectedQueueOverflowCallback'.
267 Caution: This feature request that the sequence is fully configured before injected conversion start.
268 Therefore, configure channels with HAL_ADCEx_InjectedConfigChannel() as many times as value of 'InjectedNbrOfConversion' parameter.
269 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
270 configure a channel on injected group can impact the configuration of other channels previously set.
271 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */
272 uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
273 If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
274 This parameter can be a value of @ref ADCEx_External_trigger_source_Injected
275 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
276 configure a channel on injected group can impact the configuration of other channels previously set. */
277 uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
278 This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.
279 If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
280 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
281 configure a channel on injected group can impact the configuration of other channels previously set. */
282 }ADC_InjectionConfTypeDef;
283
284 /**
285 * @brief Structure definition of ADC analog watchdog
286 * @note The setting of these parameters with function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
287 * ADC state can be either: ADC disabled or ADC enabled without conversion on going on regular and injected groups.
288 */
289 typedef struct
290 {
291 uint32_t WatchdogNumber; /*!< Selects which ADC analog watchdog to apply to the selected channel.
292 For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')
293 For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
294 This parameter can be a value of @ref ADCEx_analog_watchdog_number. */
295 uint32_t WatchdogMode; /*!< For Analog Watchdog 1: Configures the ADC analog watchdog mode: single channel/overall group of channels, regular/injected group.
296 For Analog Watchdog 2 and 3: There is no configuration for overall group of channels as AWD1. Set value 'ADC_ANALOGWATCHDOG_NONE' to reset channels group programmed with parameter 'Channel', set any other value to not use this parameter.
297 This parameter can be a value of @ref ADCEx_analog_watchdog_mode. */
298 uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
299 For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel. Only 1 channel can be monitored.
300 For Analog Watchdog 2 and 3: Several channels can be monitored (successive calls of HAL_ADC_AnalogWDGConfig() must be done, one for each channel.
301 Channels group reset can be done by setting WatchdogMode to 'ADC_ANALOGWATCHDOG_NONE').
302 This parameter can be a value of @ref ADCEx_channels. */
303 uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
304 This parameter can be set to ENABLE or DISABLE */
305 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
306 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
307 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
308 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */
309 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
310 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
311 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
312 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */
313 }ADC_AnalogWDGConfTypeDef;
314
315 /**
316 * @brief Structure definition of ADC multimode
317 * @note The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group).
318 * State of ADCs of the common group must be: disabled.
319 */
320 typedef struct
321 {
322 uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
323 This parameter can be a value of @ref ADCEx_Common_mode */
324 uint32_t DMAAccessMode; /*!< Configures the DMA mode for multi ADC mode:
325 selection whether 2 DMA channels (each ADC use its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master)
326 This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multimode
327 Caution: Limitations with multimode DMA access enabled (1 DMA channel used): In case of dual mode in high speed (more than 5Msps) or high activity of DMA by other peripherals, there is a risk of DMA overrun.
328 Therefore, it is recommended to disable multimode DMA access: each ADC use its own DMA channel. */
329 uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
330 This parameter can be a value of @ref ADCEx_delay_between_2_sampling_phases
331 Delay range depends on selected resolution: from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits
332 from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits */
333 }ADC_MultiModeTypeDef;
334 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
335 /* STM32F302xC || STM32F303xC || STM32F358xx || */
336 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
337 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
338
339 #if defined(STM32F373xC) || defined(STM32F378xx)
340 /**
341 * @brief Structure definition of ADC and regular group initialization
342 * @note Parameters of this structure are shared within 2 scopes:
343 * - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode.
344 * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
345 * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
346 * ADC can be either disabled or enabled without conversion on going on regular group.
347 */
348 typedef struct
349 {
350 uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
351 or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
352 This parameter can be a value of @ref ADCEx_Data_align */
353 uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
354 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
355 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
356 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
357 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
358 Scan direction is upward: from rank1 to rank 'n'.
359 This parameter can be a value of @ref ADCEx_Scan_mode
360 Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1)
361 or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the
362 the last conversion of the sequence. All previous conversions would be overwritten by the last one.
363 Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */
364 uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
365 after the selected trigger occurred (software start or external trigger).
366 This parameter can be set to ENABLE or DISABLE. */
367 uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
368 To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
369 This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
370 uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
371 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
372 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
373 This parameter can be set to ENABLE or DISABLE. */
374 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
375 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
376 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
377 uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
378 If set to ADC_SOFTWARE_START, external triggers are disabled.
379 If set to external trigger source, triggering is on event rising edge.
380 This parameter can be a value of @ref ADCEx_External_trigger_source_Regular */
381 }ADC_InitTypeDef;
382
383 /**
384 * @brief Structure definition of ADC channel for regular group
385 * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
386 * ADC can be either disabled or enabled without conversion on going on regular group.
387 */
388 typedef struct
389 {
390 uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
391 This parameter can be a value of @ref ADCEx_channels
392 Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
393 uint32_t Rank; /*!< Specifies the rank in the regular group sequencer
394 This parameter can be a value of @ref ADCEx_regular_rank
395 Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
396 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
397 Unit: ADC clock cycles
398 Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
399 This parameter can be a value of @ref ADCEx_sampling_times
400 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
401 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
402 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
403 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
404 Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17.1us min). */
405 }ADC_ChannelConfTypeDef;
406
407 /**
408 * @brief ADC Configuration injected Channel structure definition
409 * @note Parameters of this structure are shared within 2 scopes:
410 * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
411 * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
412 * AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
413 * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
414 * ADC state can be either:
415 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv')
416 * - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group.
417 */
418 typedef struct
419 {
420 uint32_t InjectedChannel; /*!< Selection of ADC channel to configure
421 This parameter can be a value of @ref ADCEx_channels
422 Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
423 uint32_t InjectedRank; /*!< Rank in the injected group sequencer
424 This parameter must be a value of @ref ADCEx_injected_rank
425 Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
426 uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
427 Unit: ADC clock cycles
428 Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
429 This parameter can be a value of @ref ADCEx_sampling_times
430 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
431 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
432 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
433 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
434 Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17.1us min). */
435 uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
436 Offset value must be a positive number.
437 Depending of ADC resolution selected (12, 10, 8 or 6 bits),
438 this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
439 uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
440 To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
441 This parameter must be a number between Min_Data = 1 and Max_Data = 4.
442 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
443 configure a channel on injected group can impact the configuration of other channels previously set. */
444 uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
445 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
446 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
447 This parameter can be set to ENABLE or DISABLE.
448 Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
449 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
450 configure a channel on injected group can impact the configuration of other channels previously set. */
451 uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
452 This parameter can be set to ENABLE or DISABLE.
453 Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
454 Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
455 Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
456 To maintain JAUTO always enabled, DMA must be configured in circular mode.
457 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
458 configure a channel on injected group can impact the configuration of other channels previously set. */
459 uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
460 If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
461 If set to external trigger source, triggering is on event rising edge.
462 This parameter can be a value of @ref ADCEx_External_trigger_source_Injected
463 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
464 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
465 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
466 configure a channel on injected group can impact the configuration of other channels previously set. */
467 }ADC_InjectionConfTypeDef;
468
469 /**
470 * @brief ADC Configuration analog watchdog definition
471 * @note The setting of these parameters with function is conditioned to ADC state.
472 * ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
473 */
474 typedef struct
475 {
476 uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
477 This parameter can be a value of @ref ADCEx_analog_watchdog_mode. */
478 uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
479 This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
480 This parameter can be a value of @ref ADCEx_channels. */
481 uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
482 This parameter can be set to ENABLE or DISABLE */
483 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
484 This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
485 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
486 This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
487 uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
488 }ADC_AnalogWDGConfTypeDef;
489 #endif /* STM32F373xC || STM32F378xx */
490 /**
491 * @}
492 */
493
494 /* Exported constants --------------------------------------------------------*/
495
496 /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
497 * @{
498 */
499
500 /** @defgroup ADCEx_Error_Code ADC Extended Error Code
501 * @{
502 */
503 #define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */
504 #define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking,
505 enable/disable, erroneous state */
506 #define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< Overrun error */
507 #define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */
508 #define HAL_ADC_ERROR_JQOVF ((uint32_t)0x08) /*!< Injected context queue overflow error */
509 /**
510 * @}
511 */
512
513 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
514 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
515 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
516 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
517 /** @defgroup ADCEx_ClockPrescaler ADC Extended Clock Prescaler
518 * @{
519 */
520 #define ADC_CLOCK_ASYNC ((uint32_t)0x00000000) /*!< ADC asynchronous clock derived from ADC dedicated PLL */
521
522 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
523 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
524 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
525 #define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC12_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */
526 #define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC12_CCR_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2 */
527 #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC12_CCR_CKMODE) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4 */
528 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
529 /* STM32F302xC || STM32F303xC || STM32F358xx || */
530 /* STM32F303x8 || STM32F334x8 || STM32F328xx */
531
532 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
533 #define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC1_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */
534 #define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC1_CCR_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2 */
535 #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC1_CCR_CKMODE) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4 */
536 #endif /* STM32F301x8 || STM32F318xx || STM32F302x8 */
537
538 #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 /* Obsolete naming, kept for compatibility with some other devices */
539 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 /* Obsolete naming, kept for compatibility with some other devices */
540 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 /* Obsolete naming, kept for compatibility with some other devices */
541
542 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC) || \
543 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
544 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
545 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) )
546 /**
547 * @}
548 */
549
550 /** @defgroup ADCEx_Resolution ADC Extended Resolution
551 * @{
552 */
553 #define ADC_RESOLUTION12b ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */
554 #define ADC_RESOLUTION10b ((uint32_t)ADC_CFGR_RES_0) /*!< ADC 10-bit resolution */
555 #define ADC_RESOLUTION8b ((uint32_t)ADC_CFGR_RES_1) /*!< ADC 8-bit resolution */
556 #define ADC_RESOLUTION6b ((uint32_t)ADC_CFGR_RES) /*!< ADC 6-bit resolution */
557
558 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION12b) || \
559 ((RESOLUTION) == ADC_RESOLUTION10b) || \
560 ((RESOLUTION) == ADC_RESOLUTION8b) || \
561 ((RESOLUTION) == ADC_RESOLUTION6b) )
562
563 #define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION8b) || \
564 ((RESOLUTION) == ADC_RESOLUTION6b) )
565 /**
566 * @}
567 */
568
569 /** @defgroup ADCEx_Data_align ADC Extended Data Alignment
570 * @{
571 */
572 #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
573 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR_ALIGN)
574
575 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
576 ((ALIGN) == ADC_DATAALIGN_LEFT) )
577 /**
578 * @}
579 */
580
581 /** @defgroup ADCEx_Scan_mode ADC Extended Scan Mode
582 * @{
583 */
584 #define ADC_SCAN_DISABLE ((uint32_t)0x00000000)
585 #define ADC_SCAN_ENABLE ((uint32_t)0x00000001)
586
587 #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \
588 ((SCAN_MODE) == ADC_SCAN_ENABLE) )
589 /**
590 * @}
591 */
592
593 /** @defgroup ADCEx_External_trigger_edge_Regular ADC Extended External trigger enable and polarity selection for regular channels
594 * @{
595 */
596 #define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
597 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR_EXTEN_0)
598 #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR_EXTEN_1)
599 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR_EXTEN)
600
601 #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
602 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
603 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
604 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
605 /**
606 * @}
607 */
608
609 /** @defgroup ADCEx_External_trigger_source_Regular ADC Extended External trigger selection for regular group
610 * @{
611 */
612 #if defined(STM32F303xE) || defined(STM32F398xx) || \
613 defined(STM32F303xC) || defined(STM32F358xx)
614 /*!< List of external triggers with generic trigger name, independently of */
615 /* ADC target (caution: applies to other ADCs sharing the same common group), */
616 /* sorted by trigger name: */
617
618 /*!< External triggers of regular group for ADC1&ADC2 only */
619 #define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
620 #define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2
621 #define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2
622 #define ADC_EXTERNALTRIGCONV_T3_CC4 ADC1_2_EXTERNALTRIG_T3_CC4
623 #define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4
624 #define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_2_EXTERNALTRIG_T6_TRGO
625 #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
626
627 /*!< External triggers of regular group for ADC3&ADC4 only */
628 #define ADC_EXTERNALTRIGCONV_T2_CC1 ADC3_4_EXTERNALTRIG_T2_CC1
629 #define ADC_EXTERNALTRIGCONV_T2_CC3 ADC3_4_EXTERNALTRIG_T2_CC3
630 #define ADC_EXTERNALTRIGCONV_T3_CC1 ADC3_4_EXTERNALTRIG_T3_CC1
631 #define ADC_EXTERNALTRIGCONV_T4_CC1 ADC3_4_EXTERNALTRIG_T4_CC1
632 #define ADC_EXTERNALTRIGCONV_T7_TRGO ADC3_4_EXTERNALTRIG_T7_TRGO
633 #define ADC_EXTERNALTRIGCONV_T8_CC1 ADC3_4_EXTERNALTRIG_T8_CC1
634 #define ADC_EXTERNALTRIGCONV_EXT_IT2 ADC3_4_EXTERNALTRIG_EXT_IT2
635
636 /*!< External triggers of regular group for ADC1&ADC2, ADC3&ADC4 */
637 /* Note: Triggers affected to group ADC1_2 by default, redirected to group */
638 /* ADC3_4 by driver when needed. */
639 #define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_EXTERNALTRIG_T1_CC3
640 #define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO
641 #define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_2_EXTERNALTRIG_T1_TRGO2
642 #define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO
643 #define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
644 #define ADC_EXTERNALTRIGCONV_T4_TRGO ADC1_2_EXTERNALTRIG_T4_TRGO
645 #define ADC_EXTERNALTRIGCONV_T8_TRGO ADC1_2_EXTERNALTRIG_T8_TRGO
646 #define ADC_EXTERNALTRIGCONV_T8_TRGO2 ADC1_2_EXTERNALTRIG_T8_TRGO2
647 #define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO
648
649 #define ADC_SOFTWARE_START ((uint32_t)0x00000001)
650
651 #if defined(STM32F303xE) || defined(STM32F398xx)
652 /* ADC external triggers specific to device STM303xE: mask to differentiate */
653 /* standard triggers from specific timer 20, needed for reallocation of */
654 /* triggers common to ADC1&2/ADC3&4 and to avoind mixing with standard */
655 /* triggers without remap. */
656 #define ADC_EXTERNALTRIGCONV_T20_MASK 0x1000
657
658 /*!< List of external triggers specific to device STM303xE: using Timer20 */
659 /* with ADC trigger input remap. */
660 /* To remap ADC trigger from other timers/ExtLine to timer20: use macro */
661 /* " __HAL_REMAPADCTRIGGER_ENABLE(...) " with parameters described below: */
662
663 /*!< External triggers of regular group for ADC1&ADC2 only, specific to */
664 /* device STM303xE: : using Timer20 with ADC trigger input remap */
665 #define ADC_EXTERNALTRIGCONV_T20_CC2 ADC_EXTERNALTRIGCONV_T6_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT13) */
666 #define ADC_EXTERNALTRIGCONV_T20_CC3 ADC_EXTERNALTRIGCONV_T3_CC4 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT15) */
667
668 /*!< External triggers of regular group for ADC3&ADC4 only, specific to */
669 /* device STM303xE: : using Timer20 with ADC trigger input remap */
670 /* None */
671
672 /*!< External triggers of regular group for ADC1&ADC2, ADC3&ADC4, specific to */
673 /* device STM303xE: : using Timer20 with ADC trigger input remap */
674 /* Note: Triggers affected to group ADC1_2 by default, redirected to group */
675 /* ADC3_4 by driver when needed. */
676 #define ADC_EXTERNALTRIGCONV_T20_CC1 (ADC_EXTERNALTRIGCONV_T4_CC4 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT5) */
677 /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_EXT15) */
678 #define ADC_EXTERNALTRIGCONV_T20_TRGO (ADC_EXTERNALTRIGCONV_T1_CC3 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT2) */
679 /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_EXT5) */
680 #define ADC_EXTERNALTRIGCONV_T20_TRGO2 (ADC_EXTERNALTRIGCONV_T2_CC2 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT3) */
681 /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_EXT6) */
682 #endif /* STM32F303xE || STM32F398xx */
683
684 #if defined(STM32F303xC) || defined(STM32F358xx)
685 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
686 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
687 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
688 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
689 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
690 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
691 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
692 \
693 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC1) || \
694 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
695 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
696 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC1) || \
697 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T7_TRGO) || \
698 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
699 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT2) || \
700 \
701 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
702 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
703 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
704 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
705 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
706 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \
707 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
708 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \
709 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
710 \
711 ((REGTRIG) == ADC_SOFTWARE_START) )
712 #endif /* STM32F303xC || STM32F358xx */
713
714 #if defined(STM32F303xE) || defined(STM32F398xx)
715 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
716 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
717 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
718 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
719 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
720 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
721 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
722 \
723 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC1) || \
724 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
725 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
726 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC1) || \
727 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T7_TRGO) || \
728 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
729 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT2) || \
730 \
731 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
732 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
733 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
734 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
735 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
736 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \
737 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
738 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \
739 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
740 \
741 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC2) || \
742 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC3) || \
743 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC1) || \
744 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_TRGO) || \
745 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_TRGO2) || \
746 \
747 ((REGTRIG) == ADC_SOFTWARE_START) )
748 #endif /* STM32F303xE || STM32F398xx */
749
750 #endif /* STM32F303xE || STM32F398xx || */
751 /* STM32F303xC || STM32F358xx */
752
753 #if defined(STM32F302xE) || \
754 defined(STM32F302xC)
755 /*!< List of external triggers with generic trigger name, independently of */
756 /* ADC target (caution: applies to other ADCs sharing the same common group), */
757 /* sorted by trigger name: */
758
759 /*!< External triggers of regular group for ADC1&ADC2 */
760 #define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
761 #define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2
762 #define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_EXTERNALTRIG_T1_CC3
763 #define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO
764 #define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_2_EXTERNALTRIG_T1_TRGO2
765 #define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2
766 #define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO
767 #define ADC_EXTERNALTRIGCONV_T3_CC4 ADC1_2_EXTERNALTRIG_T3_CC4
768 #define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
769 #define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4
770 #define ADC_EXTERNALTRIGCONV_T4_TRGO ADC1_2_EXTERNALTRIG_T4_TRGO
771 #define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_2_EXTERNALTRIG_T6_TRGO
772 #define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO
773 #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
774 #define ADC_SOFTWARE_START ((uint32_t)0x00000001)
775
776 #if defined(STM32F302xE)
777 /* ADC external triggers specific to device STM302xE: mask to differentiate */
778 /* standard triggers from specific timer 20, needed for reallocation of */
779 /* triggers common to ADC1&2 and to avoind mixing with standard */
780 /* triggers without remap. */
781 #define ADC_EXTERNALTRIGCONV_T20_MASK 0x1000
782
783 /*!< List of external triggers specific to device STM302xE: using Timer20 */
784 /* with ADC trigger input remap. */
785 /* To remap ADC trigger from other timers/ExtLine to timer20: use macro */
786 /* " __HAL_REMAPADCTRIGGER_ENABLE(...) " with parameters described below: */
787
788 /*!< External triggers of regular group for ADC1&ADC2 only, specific to */
789 /* device STM302xE: : using Timer20 with ADC trigger input remap */
790 #define ADC_EXTERNALTRIGCONV_T20_CC2 ADC_EXTERNALTRIGCONV_T6_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT13) */
791 #define ADC_EXTERNALTRIGCONV_T20_CC3 ADC_EXTERNALTRIGCONV_T3_CC4 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT15) */
792 #endif /* STM32F302xE */
793
794 #if defined(STM32F302xE)
795 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
796 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
797 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
798 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
799 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
800 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
801 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
802 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
803 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
804 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
805 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \
806 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
807 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
808 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
809 \
810 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC2) || \
811 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC3) || \
812 \
813 ((REGTRIG) == ADC_SOFTWARE_START) )
814 #endif /* STM32F302xE */
815
816 #if defined(STM32F302xC)
817 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
818 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
819 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
820 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
821 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
822 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
823 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
824 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
825 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
826 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
827 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \
828 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
829 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
830 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
831 \
832 ((REGTRIG) == ADC_SOFTWARE_START) )
833 #endif /* STM32F302xC */
834
835 #endif /* STM32F302xE || */
836 /* STM32F302xC */
837
838 #if defined(STM32F303x8) || defined(STM32F328xx)
839 /*!< List of external triggers with generic trigger name, independently of */
840 /* ADC target (caution: applies to other ADCs sharing the same common group), */
841 /* sorted by trigger name: */
842
843 /*!< External triggers of regular group for ADC1&ADC2 */
844 #define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
845 #define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2
846 #define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_EXTERNALTRIG_T1_CC3
847 #define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO
848 #define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_2_EXTERNALTRIG_T1_TRGO2
849 #define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2
850 #define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO
851 #define ADC_EXTERNALTRIGCONV_T3_CC4 ADC1_2_EXTERNALTRIG_T3_CC4
852 #define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
853 #define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4
854 #define ADC_EXTERNALTRIGCONV_T4_TRGO ADC1_2_EXTERNALTRIG_T4_TRGO
855 #define ADC_EXTERNALTRIGCONV_T8_TRGO ADC1_2_EXTERNALTRIG_T8_TRGO
856 #define ADC_EXTERNALTRIGCONV_T8_TRGO2 ADC1_2_EXTERNALTRIG_T8_TRGO2
857 #define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_2_EXTERNALTRIG_T6_TRGO
858 #define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO
859 #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
860 #define ADC_SOFTWARE_START ((uint32_t)0x00000001)
861
862 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
863 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
864 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
865 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
866 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
867 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
868 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
869 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
870 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \
871 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
872 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
873 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
874 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \
875 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
876 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
877 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
878 \
879 ((REGTRIG) == ADC_SOFTWARE_START) )
880 #endif /* STM32F303x8 || STM32F328xx */
881
882 #if defined(STM32F334x8)
883 /*!< List of external triggers with generic trigger name, independently of */
884 /* ADC target (caution: applies to other ADCs sharing the same common group), */
885 /* sorted by trigger name: */
886
887 /*!< External triggers of regular group for ADC1&ADC2 */
888 #define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
889 #define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2
890 #define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_EXTERNALTRIG_T1_CC3
891 #define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO
892 #define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_2_EXTERNALTRIG_T1_TRGO2
893 #define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2
894 #define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO
895 #define ADC_EXTERNALTRIGCONV_T3_CC4 ADC1_2_EXTERNALTRIG_T3_CC4
896 #define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
897 #define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_2_EXTERNALTRIG_T6_TRGO
898 #define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO
899 #define ADC_EXTERNALTRIGCONVHRTIM_TRG1 ADC1_2_EXTERNALTRIG_HRTIM_TRG1
900 #define ADC_EXTERNALTRIGCONVHRTIM_TRG3 ADC1_2_EXTERNALTRIG_HRTIM_TRG3
901 #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
902 #define ADC_SOFTWARE_START ((uint32_t)0x00000001)
903
904 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
905 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
906 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
907 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
908 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
909 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
910 ((REGTRIG) == ADC_EXTERNALTRIGCONVHRTIM_TRG1) || \
911 ((REGTRIG) == ADC_EXTERNALTRIGCONVHRTIM_TRG3) || \
912 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
913 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
914 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
915 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
916 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
917 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
918 \
919 ((REGTRIG) == ADC_SOFTWARE_START) )
920 #endif /* STM32F334x8 */
921
922 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
923 /* List of external triggers with generic trigger name, sorted by trigger */
924 /* name: */
925
926 /* External triggers of regular group for ADC1 */
927 #define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_EXTERNALTRIG_T1_CC1
928 #define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_EXTERNALTRIG_T1_CC2
929 #define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_EXTERNALTRIG_T1_CC3
930 #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_EXTERNALTRIG_EXT_IT11
931 #define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_EXTERNALTRIG_T1_TRGO
932 #define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_EXTERNALTRIG_T1_TRGO2
933 #define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_EXTERNALTRIG_T2_TRGO
934 #define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_EXTERNALTRIG_T6_TRGO
935 #define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_EXTERNALTRIG_T15_TRGO
936 #define ADC_SOFTWARE_START ((uint32_t)0x00000001)
937
938 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
939 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
940 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
941 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
942 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
943 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
944 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
945 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
946 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) || \
947 ((REGTRIG) == ADC_SOFTWARE_START) )
948 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
949 /**
950 * @}
951 */
952
953 /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended External trigger selection for regular group (Used Internally)
954 * @{
955 */
956 #if defined(STM32F303xE) || defined(STM32F398xx) || \
957 defined(STM32F303xC) || defined(STM32F358xx)
958 /* List of external triggers for common groups ADC1&ADC2 and/or ADC3&ADC4: */
959 /* (used internally by HAL driver. To not use into HAL structure parameters) */
960
961 /* External triggers of regular group for ADC1 & ADC2 */
962 #define ADC1_2_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000)
963 #define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
964 #define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
965 #define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
966 #define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)
967 #define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
968 #define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
969 #define ADC1_2_EXTERNALTRIG_T8_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
970 #define ADC1_2_EXTERNALTRIG_T8_TRGO2 ((uint32_t) ADC_CFGR_EXTSEL_3)
971 #define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
972 #define ADC1_2_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
973 #define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
974 #define ADC1_2_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2))
975 #define ADC1_2_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
976 #define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
977 #define ADC1_2_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL)
978
979 /* External triggers of regular group for ADC3 & ADC4 */
980 #define ADC3_4_EXTERNALTRIG_T3_CC1 ((uint32_t)0x00000000)
981 #define ADC3_4_EXTERNALTRIG_T2_CC3 ((uint32_t)ADC_CFGR_EXTSEL_0)
982 #define ADC3_4_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
983 #define ADC3_4_EXTERNALTRIG_T8_CC1 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
984 #define ADC3_4_EXTERNALTRIG_T8_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)
985 #define ADC3_4_EXTERNALTRIG_EXT_IT2 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
986 #define ADC3_4_EXTERNALTRIG_T4_CC1 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
987 #define ADC3_4_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
988 #define ADC3_4_EXTERNALTRIG_T8_TRGO2 ((uint32_t)ADC_CFGR_EXTSEL_3)
989 #define ADC3_4_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
990 #define ADC3_4_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
991 #define ADC3_4_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
992 #define ADC3_4_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2))
993 #define ADC3_4_EXTERNALTRIG_T7_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
994 #define ADC3_4_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
995 #define ADC3_4_EXTERNALTRIG_T2_CC1 ((uint32_t)ADC_CFGR_EXTSEL)
996 #endif /* STM32F303xE || STM32F398xx || */
997 /* STM32F303xC || STM32F358xx */
998
999 #if defined(STM32F302xE) || \
1000 defined(STM32F302xC)
1001 /* List of external triggers of common group ADC1&ADC2: */
1002 /* (used internally by HAL driver. To not use into HAL structure parameters) */
1003 #define ADC1_2_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000)
1004 #define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
1005 #define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
1006 #define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
1007 #define ADC1_2_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
1008 #define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
1009 #define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
1010 #define ADC1_2_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL)
1011 #define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)
1012 #define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
1013 #define ADC1_2_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2))
1014 #define ADC1_2_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
1015 #define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
1016 #define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
1017 #endif /* STM32F302xE || */
1018 /* STM32F302xC */
1019
1020 #if defined(STM32F303x8) || defined(STM32F328xx)
1021 /* List of external triggers of common group ADC1&ADC2: */
1022 /* (used internally by HAL driver. To not use into HAL structure parameters) */
1023 #define ADC1_2_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000)
1024 #define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
1025 #define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
1026 #define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
1027 #define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)
1028 #define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
1029 #define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
1030 #define ADC1_2_EXTERNALTRIG_T8_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
1031 #define ADC1_2_EXTERNALTRIG_T8_TRGO2 ((uint32_t) ADC_CFGR_EXTSEL_3)
1032 #define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
1033 #define ADC1_2_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
1034 #define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
1035 #define ADC1_2_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2))
1036 #define ADC1_2_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
1037 #define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
1038 #define ADC1_2_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL)
1039 #endif /* STM32F303x8 || STM32F328xx */
1040
1041 #if defined(STM32F334x8)
1042 /* List of external triggers of common group ADC1&ADC2: */
1043 /* (used internally by HAL driver. To not use into HAL structure parameters) */
1044 #define ADC1_2_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000)
1045 #define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
1046 #define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
1047 #define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
1048 #define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)
1049 #define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
1050 #define ADC1_2_EXTERNALTRIG_HRTIM_TRG1 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
1051 #define ADC1_2_EXTERNALTRIG_HRTIM_TRG3 ((uint32_t) ADC_CFGR_EXTSEL_3)
1052 #define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
1053 #define ADC1_2_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
1054 #define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
1055 #define ADC1_2_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
1056 #define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
1057 #define ADC1_2_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL)
1058 #endif /* STM32F334x8 */
1059
1060 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
1061 /* List of external triggers of regular group for ADC1: */
1062 /* (used internally by HAL driver. To not use into HAL structure parameters) */
1063 #define ADC1_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000)
1064 #define ADC1_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
1065 #define ADC1_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
1066 #define ADC1_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
1067 #define ADC1_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
1068 #define ADC1_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
1069 #define ADC1_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
1070 #define ADC1_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
1071 #define ADC1_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
1072 #define ADC_SOFTWARE_START ((uint32_t)0x00000001)
1073 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
1074 /**
1075 * @}
1076 */
1077
1078
1079 /** @defgroup ADCEx_EOCSelection ADC Extended End of Regular Sequence/Conversion
1080 * @{
1081 */
1082 #define EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC)
1083 #define EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS)
1084 #define EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS)) /*!< reserved for future use */
1085
1086 #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == EOC_SINGLE_CONV) || \
1087 ((EOC_SELECTION) == EOC_SEQ_CONV) || \
1088 ((EOC_SELECTION) == EOC_SINGLE_SEQ_CONV) )
1089 /**
1090 * @}
1091 */
1092
1093 /** @defgroup ADCEx_Overrun ADC Extended overrun
1094 * @{
1095 */
1096 #define OVR_DATA_OVERWRITTEN ((uint32_t)0x00000000) /*!< Default setting, to be used for compatibility with other STM32 devices */
1097 #define OVR_DATA_PRESERVED ((uint32_t)0x00000001)
1098
1099 #define IS_ADC_OVERRUN(OVR) (((OVR) == OVR_DATA_PRESERVED) || \
1100 ((OVR) == OVR_DATA_OVERWRITTEN) )
1101 /**
1102 * @}
1103 */
1104
1105 /** @defgroup ADCEx_channels ADC Extended Channels
1106 * @{
1107 */
1108 /* Note: Depending on devices, some channels may not be available on package */
1109 /* pins. Refer to device datasheet for channels availability. */
1110 #define ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ10_0))
1111 #define ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ10_1))
1112 #define ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
1113 #define ADC_CHANNEL_4 ((uint32_t)(ADC_SQR3_SQ10_2))
1114 #define ADC_CHANNEL_5 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))
1115 #define ADC_CHANNEL_6 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))
1116 #define ADC_CHANNEL_7 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
1117 #define ADC_CHANNEL_8 ((uint32_t)(ADC_SQR3_SQ10_3))
1118 #define ADC_CHANNEL_9 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_0))
1119 #define ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1))
1120 #define ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
1121 #define ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2))
1122 #define ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))
1123 #define ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))
1124 #define ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
1125 #define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ10_4))
1126 #define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_0))
1127 #define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_1))
1128
1129 /* Note: Vopamp1, TempSensor and Vbat internal channels available on ADC1 only */
1130 #define ADC_CHANNEL_VOPAMP1 ADC_CHANNEL_15
1131 #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16
1132 #define ADC_CHANNEL_VBAT ADC_CHANNEL_17
1133
1134 /* Note: Vopamp2/3/4 internal channels available on ADC2/3/4 respectively */
1135 #define ADC_CHANNEL_VOPAMP2 ADC_CHANNEL_17
1136 #define ADC_CHANNEL_VOPAMP3 ADC_CHANNEL_17
1137 #define ADC_CHANNEL_VOPAMP4 ADC_CHANNEL_17
1138
1139 /* Note: VrefInt internal channels available on all ADCs, but only */
1140 /* one ADC is allowed to be connected to VrefInt at the same time. */
1141 #define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_18)
1142
1143 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_1) || \
1144 ((CHANNEL) == ADC_CHANNEL_2) || \
1145 ((CHANNEL) == ADC_CHANNEL_3) || \
1146 ((CHANNEL) == ADC_CHANNEL_4) || \
1147 ((CHANNEL) == ADC_CHANNEL_5) || \
1148 ((CHANNEL) == ADC_CHANNEL_6) || \
1149 ((CHANNEL) == ADC_CHANNEL_7) || \
1150 ((CHANNEL) == ADC_CHANNEL_8) || \
1151 ((CHANNEL) == ADC_CHANNEL_9) || \
1152 ((CHANNEL) == ADC_CHANNEL_10) || \
1153 ((CHANNEL) == ADC_CHANNEL_11) || \
1154 ((CHANNEL) == ADC_CHANNEL_12) || \
1155 ((CHANNEL) == ADC_CHANNEL_13) || \
1156 ((CHANNEL) == ADC_CHANNEL_14) || \
1157 ((CHANNEL) == ADC_CHANNEL_15) || \
1158 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \
1159 ((CHANNEL) == ADC_CHANNEL_VBAT) || \
1160 ((CHANNEL) == ADC_CHANNEL_VREFINT) || \
1161 ((CHANNEL) == ADC_CHANNEL_VOPAMP1) || \
1162 ((CHANNEL) == ADC_CHANNEL_VOPAMP2) || \
1163 ((CHANNEL) == ADC_CHANNEL_VOPAMP3) || \
1164 ((CHANNEL) == ADC_CHANNEL_VOPAMP4) )
1165
1166 #define IS_ADC_DIFF_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_1) || \
1167 ((CHANNEL) == ADC_CHANNEL_2) || \
1168 ((CHANNEL) == ADC_CHANNEL_3) || \
1169 ((CHANNEL) == ADC_CHANNEL_4) || \
1170 ((CHANNEL) == ADC_CHANNEL_5) || \
1171 ((CHANNEL) == ADC_CHANNEL_6) || \
1172 ((CHANNEL) == ADC_CHANNEL_7) || \
1173 ((CHANNEL) == ADC_CHANNEL_8) || \
1174 ((CHANNEL) == ADC_CHANNEL_9) || \
1175 ((CHANNEL) == ADC_CHANNEL_10) || \
1176 ((CHANNEL) == ADC_CHANNEL_11) || \
1177 ((CHANNEL) == ADC_CHANNEL_12) || \
1178 ((CHANNEL) == ADC_CHANNEL_13) || \
1179 ((CHANNEL) == ADC_CHANNEL_14) )
1180
1181 /**
1182 * @}
1183 */
1184
1185 /** @defgroup ADCEx_sampling_times ADC Extended Sampling Times
1186 * @{
1187 */
1188 #define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000) /*!< Sampling time 1.5 ADC clock cycle */
1189 #define ADC_SAMPLETIME_2CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_0) /*!< Sampling time 2.5 ADC clock cycles */
1190 #define ADC_SAMPLETIME_4CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_1) /*!< Sampling time 4.5 ADC clock cycles */
1191 #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 7.5 ADC clock cycles */
1192 #define ADC_SAMPLETIME_19CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_2) /*!< Sampling time 19.5 ADC clock cycles */
1193 #define ADC_SAMPLETIME_61CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 61.5 ADC clock cycles */
1194 #define ADC_SAMPLETIME_181CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1)) /*!< Sampling time 181.5 ADC clock cycles */
1195 #define ADC_SAMPLETIME_601CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10) /*!< Sampling time 601.5 ADC clock cycles */
1196
1197 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \
1198 ((TIME) == ADC_SAMPLETIME_2CYCLES_5) || \
1199 ((TIME) == ADC_SAMPLETIME_4CYCLES_5) || \
1200 ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \
1201 ((TIME) == ADC_SAMPLETIME_19CYCLES_5) || \
1202 ((TIME) == ADC_SAMPLETIME_61CYCLES_5) || \
1203 ((TIME) == ADC_SAMPLETIME_181CYCLES_5) || \
1204 ((TIME) == ADC_SAMPLETIME_601CYCLES_5) )
1205 /**
1206 * @}
1207 */
1208
1209 /** @defgroup ADCEx_SingleDifferential ADC Extended Single-ended/Differential input mode
1210 * @{
1211 */
1212 #define ADC_SINGLE_ENDED ((uint32_t)0x00000000)
1213 #define ADC_DIFFERENTIAL_ENDED ((uint32_t)0x00000001)
1214
1215 #define IS_ADC_SINGLE_DIFFERENTIAL(SING_DIFF) (((SING_DIFF) == ADC_SINGLE_ENDED) || \
1216 ((SING_DIFF) == ADC_DIFFERENTIAL_ENDED) )
1217 /**
1218 * @}
1219 */
1220
1221 /** @defgroup ADCEx_OffsetNumber ADC Extended Offset Number
1222 * @{
1223 */
1224 #define ADC_OFFSET_NONE ((uint32_t)0x00)
1225 #define ADC_OFFSET_1 ((uint32_t)0x01)
1226 #define ADC_OFFSET_2 ((uint32_t)0x02)
1227 #define ADC_OFFSET_3 ((uint32_t)0x03)
1228 #define ADC_OFFSET_4 ((uint32_t)0x04)
1229
1230 #define IS_ADC_OFFSET_NUMBER(OFFSET_NUMBER) (((OFFSET_NUMBER) == ADC_OFFSET_NONE) || \
1231 ((OFFSET_NUMBER) == ADC_OFFSET_1) || \
1232 ((OFFSET_NUMBER) == ADC_OFFSET_2) || \
1233 ((OFFSET_NUMBER) == ADC_OFFSET_3) || \
1234 ((OFFSET_NUMBER) == ADC_OFFSET_4) )
1235 /**
1236 * @}
1237 */
1238
1239 /** @defgroup ADCEx_regular_rank ADC Extended Regular Channel Rank
1240 * @{
1241 */
1242 #define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001)
1243 #define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002)
1244 #define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003)
1245 #define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004)
1246 #define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005)
1247 #define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006)
1248 #define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007)
1249 #define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008)
1250 #define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009)
1251 #define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A)
1252 #define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B)
1253 #define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C)
1254 #define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D)
1255 #define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E)
1256 #define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F)
1257 #define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010)
1258
1259 #define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \
1260 ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \
1261 ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \
1262 ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \
1263 ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \
1264 ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
1265 ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
1266 ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
1267 ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
1268 ((CHANNEL) == ADC_REGULAR_RANK_10) || \
1269 ((CHANNEL) == ADC_REGULAR_RANK_11) || \
1270 ((CHANNEL) == ADC_REGULAR_RANK_12) || \
1271 ((CHANNEL) == ADC_REGULAR_RANK_13) || \
1272 ((CHANNEL) == ADC_REGULAR_RANK_14) || \
1273 ((CHANNEL) == ADC_REGULAR_RANK_15) || \
1274 ((CHANNEL) == ADC_REGULAR_RANK_16) )
1275 /**
1276 * @}
1277 */
1278
1279 /** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank
1280 * @{
1281 */
1282 #define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001)
1283 #define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002)
1284 #define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003)
1285 #define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004)
1286
1287 #define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \
1288 ((CHANNEL) == ADC_INJECTED_RANK_2) || \
1289 ((CHANNEL) == ADC_INJECTED_RANK_3) || \
1290 ((CHANNEL) == ADC_INJECTED_RANK_4) )
1291 /**
1292 * @}
1293 */
1294
1295 /** @defgroup ADCEx_External_trigger_edge_Injected External Trigger Edge of Injected Group
1296 * @{
1297 */
1298 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000)
1299 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_JSQR_JEXTEN_0)
1300 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_JSQR_JEXTEN_1)
1301 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_JSQR_JEXTEN)
1302
1303 #define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
1304 ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \
1305 ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \
1306 ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
1307 /**
1308 * @}
1309 */
1310
1311 /** @defgroup ADCEx_External_trigger_source_Injected External Trigger Source of Injected Group
1312 * @{
1313 */
1314 #if defined(STM32F303xE) || defined(STM32F398xx) || \
1315 defined(STM32F303xC) || defined(STM32F358xx)
1316 /* List of external triggers with generic trigger name, independently of ADC */
1317 /* target (caution: applies to other ADCs sharing the same common group), */
1318 /* sorted by trigger name: */
1319
1320 /* External triggers of injected group for ADC1&ADC2 only */
1321 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
1322 #define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ADC1_2_EXTERNALTRIGINJEC_T3_CC1
1323 #define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ADC1_2_EXTERNALTRIGINJEC_T3_CC3
1324 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
1325 #define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_2_EXTERNALTRIGINJEC_T6_TRGO
1326 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
1327
1328 /* External triggers of injected group for ADC3&ADC4 only */
1329 #define ADC_EXTERNALTRIGINJECCONV_T1_CC3 ADC3_4_EXTERNALTRIGINJEC_T1_CC3
1330 #define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ADC3_4_EXTERNALTRIGINJEC_T4_CC3
1331 #define ADC_EXTERNALTRIGINJECCONV_T4_CC4 ADC3_4_EXTERNALTRIGINJEC_T4_CC4
1332 #define ADC_EXTERNALTRIGINJECCONV_T7_TRGO ADC3_4_EXTERNALTRIGINJEC_T7_TRGO
1333 #define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ADC3_4_EXTERNALTRIGINJEC_T8_CC2
1334
1335 /* External triggers of injected group for ADC1&ADC2, ADC3&ADC4 */
1336 /* Note: Triggers affected to group ADC1_2 by default, redirected to group */
1337 /* ADC3_4 by driver when needed. */
1338 #define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_EXTERNALTRIGINJEC_T1_CC4
1339 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_EXTERNALTRIGINJEC_T1_TRGO
1340 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2
1341 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
1342 #define ADC_EXTERNALTRIGINJECCONV_T3_TRGO ADC1_2_EXTERNALTRIGINJEC_T3_TRGO
1343 #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
1344 #define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T8_CC4
1345 #define ADC_EXTERNALTRIGINJECCONV_T8_TRGO ADC1_2_EXTERNALTRIGINJEC_T8_TRGO
1346 #define ADC_EXTERNALTRIGINJECCONV_T8_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2
1347 #define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO
1348
1349 #define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001)
1350
1351 #if defined(STM32F303xE) || defined(STM32F398xx)
1352 /*!< List of external triggers specific to device STM303xE: using Timer20 */
1353 /* with ADC trigger input remap. */
1354 /* To remap ADC trigger from other timers/ExtLine to timer20: use macro */
1355 /* " __HAL_REMAPADCTRIGGER_ENABLE(...) " with parameters described below: */
1356
1357 /*!< External triggers of injected group for ADC1&ADC2 only, specific to */
1358 /* device STM303xE: : using Timer20 with ADC trigger input remap */
1359 #define ADC_EXTERNALTRIGINJECCONV_T20_CC4 ADC_EXTERNALTRIGINJECCONV_T3_CC1 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT13) */
1360
1361 /*!< External triggers of injected group for ADC3&ADC4 only, specific to */
1362 /* device STM303xE: : using Timer20 with ADC trigger input remap */
1363 #define ADC_EXTERNALTRIGINJECCONV_T20_CC2 ADC_EXTERNALTRIGINJECCONV_T7_TRGO /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT14) */
1364
1365 /*!< External triggers of regular group for ADC1&ADC2, ADC3&ADC4, specific to */
1366 /* device STM303xE: : using Timer20 with ADC trigger input remap */
1367 /* Note: Triggers affected to group ADC1_2 by default, redirected to group */
1368 /* ADC3_4 by driver when needed. */
1369 #define ADC_EXTERNALTRIGINJECCONV_T20_TRGO (ADC_EXTERNALTRIGINJECCONV_T2_CC1 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT3) */
1370 /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT5) */
1371 #define ADC_EXTERNALTRIGINJECCONV_T20_TRGO2 (ADC_EXTERNALTRIGINJECCONV_EXT_IT15 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT6) */
1372 /*!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT11) */
1373 #endif /* STM32F303xE || STM32F398xx */
1374
1375 #if defined(STM32F303xC) || defined(STM32F358xx)
1376 #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
1377 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
1378 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
1379 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
1380 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
1381 \
1382 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
1383 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC4) || \
1384 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \
1385 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
1386 \
1387 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
1388 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
1389 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
1390 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
1391 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \
1392 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \
1393 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
1394 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
1395 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \
1396 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \
1397 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
1398 \
1399 ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
1400 #endif /* STM32F303xC || STM32F358xx */
1401
1402 #if defined(STM32F303xE) || defined(STM32F398xx)
1403 #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
1404 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
1405 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
1406 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
1407 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
1408 \
1409 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
1410 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC4) || \
1411 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) || \
1412 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
1413 \
1414 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
1415 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
1416 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
1417 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
1418 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \
1419 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \
1420 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
1421 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
1422 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \
1423 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \
1424 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
1425 \
1426 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC4) || \
1427 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC2) || \
1428 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO) || \
1429 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO2) || \
1430 \
1431 ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
1432 #endif /* STM32F303xE || STM32F398xx */
1433
1434 #endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */
1435
1436 #if defined(STM32F302xE) || \
1437 defined(STM32F302xC)
1438 /*!< List of external triggers with generic trigger name, independently of */
1439 /* ADC target (caution: applies to other ADCs sharing the same common group), */
1440 /* sorted by trigger name: */
1441
1442 /* External triggers of injected group for ADC1&ADC2 */
1443 #define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_EXTERNALTRIGINJEC_T1_CC4
1444 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_EXTERNALTRIGINJEC_T1_TRGO
1445 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2
1446 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
1447 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
1448 #define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ADC1_2_EXTERNALTRIGINJEC_T3_CC1
1449 #define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ADC1_2_EXTERNALTRIGINJEC_T3_CC3
1450 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
1451 #define ADC_EXTERNALTRIGINJECCONV_T3_TRGO ADC1_2_EXTERNALTRIGINJEC_T3_TRGO
1452 #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
1453 #define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_2_EXTERNALTRIGINJEC_T6_TRGO
1454 #define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO
1455 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
1456
1457 #define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001)
1458
1459 #if defined(STM32F302xE)
1460 /*!< List of external triggers specific to device STM302xE: using Timer20 */
1461 /* with ADC trigger input remap. */
1462 /* To remap ADC trigger from other timers/ExtLine to timer20: use macro */
1463 /* " __HAL_REMAPADCTRIGGER_ENABLE(...) " with parameters described below: */
1464
1465 /*!< External triggers of injected group for ADC1&ADC2 only, specific to */
1466 /* device STM302xE: : using Timer20 with ADC trigger input remap */
1467 #define ADC_EXTERNALTRIGINJECCONV_T20_CC4 ADC_EXTERNALTRIGINJECCONV_T3_CC1 /*!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT13) */
1468 #define ADC_EXTERNALTRIGINJECCONV_T20_TRGO (ADC_EXTERNALTRIGINJECCONV_T2_CC1 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT3) */
1469 #define ADC_EXTERNALTRIGINJECCONV_T20_TRGO2 (ADC_EXTERNALTRIGINJECCONV_EXT_IT15 | ADC_EXTERNALTRIGCONV_T20_MASK) /*!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT6) */
1470 #endif /* STM32F302xE */
1471
1472 #if defined(STM32F302xE)
1473 #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
1474 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
1475 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
1476 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
1477 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
1478 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
1479 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \
1480 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
1481 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \
1482 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
1483 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
1484 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
1485 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
1486 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC4) || \
1487 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO) || \
1488 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO2) || \
1489 ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
1490 #endif /* STM32F302xE */
1491
1492 #if defined(STM32F302xC)
1493 #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
1494 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
1495 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
1496 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
1497 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
1498 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
1499 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \
1500 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
1501 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \
1502 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
1503 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
1504 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
1505 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
1506 ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
1507 #endif /* STM32F302xC */
1508
1509 #endif /* STM32F302xE || */
1510 /* STM32F302xC */
1511
1512 #if defined(STM32F303x8) || defined(STM32F328xx)
1513 /*!< List of external triggers with generic trigger name, independently of */
1514 /* ADC target (caution: applies to other ADCs sharing the same common group), */
1515 /* sorted by trigger name: */
1516
1517 /* External triggers of injected group for ADC1&ADC2 */
1518 #define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_EXTERNALTRIGINJEC_T1_CC4
1519 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_EXTERNALTRIGINJEC_T1_TRGO
1520 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2
1521 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
1522 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
1523 #define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ADC1_2_EXTERNALTRIGINJEC_T3_CC1
1524 #define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ADC1_2_EXTERNALTRIGINJEC_T3_CC3
1525 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
1526 #define ADC_EXTERNALTRIGINJECCONV_T3_TRGO ADC1_2_EXTERNALTRIGINJEC_T3_TRGO
1527 #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
1528 #define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_2_EXTERNALTRIGINJEC_T6_TRGO
1529 #define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T8_CC4
1530 #define ADC_EXTERNALTRIGINJECCONV_T8_TRGO ADC1_2_EXTERNALTRIGINJEC_T8_TRGO
1531 #define ADC_EXTERNALTRIGINJECCONV_T8_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2
1532 #define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO
1533 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
1534
1535 #define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001)
1536
1537 #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
1538 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
1539 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
1540 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
1541 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
1542 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
1543 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
1544 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
1545 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
1546 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \
1547 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \
1548 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \
1549 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \
1550 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
1551 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
1552 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
1553 ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
1554 #endif /* STM32F303x8 || STM32F328xx */
1555
1556 #if defined(STM32F334x8)
1557 /*!< List of external triggers with generic trigger name, independently of */
1558 /* ADC target (caution: applies to other ADCs sharing the same common group), */
1559 /* sorted by trigger name: */
1560
1561 /* External triggers of injected group for ADC1&ADC2 */
1562 #define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_EXTERNALTRIGINJEC_T1_CC4
1563 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_EXTERNALTRIGINJEC_T1_TRGO
1564 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2
1565 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
1566 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
1567 #define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ADC1_2_EXTERNALTRIGINJEC_T3_CC1
1568 #define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ADC1_2_EXTERNALTRIGINJEC_T3_CC3
1569 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
1570 #define ADC_EXTERNALTRIGINJECCONV_T3_TRGO ADC1_2_EXTERNALTRIGINJEC_T3_TRGO
1571 #define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_2_EXTERNALTRIGINJEC_T6_TRGO
1572 #define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO
1573 #define ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG2 ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG2
1574 #define ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG4 ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG4
1575 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
1576
1577 #define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001)
1578
1579 #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
1580 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
1581 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
1582 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
1583 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
1584 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
1585 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
1586 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG2) || \
1587 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG4) || \
1588 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \
1589 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) || \
1590 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \
1591 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
1592 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
1593 ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
1594 #endif /* STM32F334x8 */
1595
1596 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
1597 /* List of external triggers with generic trigger name, sorted by trigger */
1598 /* name: */
1599
1600 /* External triggers of injected group for ADC1 */
1601 #define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_EXTERNALTRIGINJEC_T1_CC4
1602 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_EXTERNALTRIGINJEC_T1_TRGO
1603 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_EXTERNALTRIGINJEC_T1_TRGO2
1604 #define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_EXTERNALTRIGINJEC_T6_TRGO
1605 #define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_EXTERNALTRIGINJEC_T15_TRGO
1606 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_EXTERNALTRIGINJEC_EXT_IT15
1607
1608 #define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001)
1609
1610 #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
1611 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
1612 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
1613 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \
1614 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \
1615 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) || \
1616 ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
1617 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
1618 /**
1619 * @}
1620 */
1621
1622 /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended External Trigger Source of Injected Group (Internal)
1623 * @{
1624 */
1625 #if defined(STM32F303xE) || defined(STM32F398xx) || \
1626 defined(STM32F303xC) || defined(STM32F358xx)
1627 /* List of external triggers sorted of groups ADC1&ADC2 and/or ADC3&ADC4: */
1628 /* (used internally by HAL driver. To not use into HAL structure parameters) */
1629
1630 /* External triggers for injected groups of ADC1 & ADC2 */
1631 #define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000)
1632 #define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
1633 #define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)
1634 #define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
1635 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2)
1636 #define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
1637 #define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
1638 #define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
1639 #define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
1640 #define ADC1_2_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0))
1641 #define ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1))
1642 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
1643 #define ADC1_2_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))
1644 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
1645 #define ADC1_2_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
1646 #define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)
1647
1648 /* External triggers for injected groups of ADC3 & ADC4 */
1649 /* Note: External triggers JEXT2 and JEXT5 are the same (TIM4_CC3 event). */
1650 /* JEXT2 is the main trigger, JEXT5 could be redirected to another */
1651 /* in future devices. */
1652 /* However, this channel is implemented with a SW offset of 0x10000 for */
1653 /* differentiation between similar triggers of common groups ADC1&ADC2, */
1654 /* ADC3&ADC4 (Differentiation processed into macro */
1655 /* __HAL_ADC_JSQR_JEXTSEL) */
1656 #define ADC3_4_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000)
1657 #define ADC3_4_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
1658 #define ADC3_4_EXTERNALTRIGINJEC_T4_CC3 ((uint32_t)ADC_JSQR_JEXTSEL_1 | 0x10000)
1659 #define ADC3_4_EXTERNALTRIGINJEC_T8_CC2 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
1660 #define ADC3_4_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2)
1661
1662 #if defined(STM32F303xE) || defined(STM32F398xx)
1663 #define ADC3_4_EXTERNALTRIGINJEC_T20_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
1664 #endif /* STM32F303xE || STM32F398xx */
1665
1666 #define ADC3_4_EXTERNALTRIGINJEC_T4_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
1667 #define ADC3_4_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
1668 #define ADC3_4_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
1669 #define ADC3_4_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0))
1670 #define ADC3_4_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1))
1671 #define ADC3_4_EXTERNALTRIGINJEC_T1_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
1672 #define ADC3_4_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))
1673 #define ADC3_4_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
1674 #define ADC3_4_EXTERNALTRIGINJEC_T7_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
1675 #define ADC3_4_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)
1676 #endif /* STM32F303xE || STM32F398xx || */
1677 /* STM32F303xC || STM32F358xx */
1678
1679 #if defined(STM32F302xE) || \
1680 defined(STM32F302xC)
1681 /* List of external triggers of group ADC1&ADC2: */
1682 /* (used internally by HAL driver. To not use into HAL structure parameters) */
1683 #define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000)
1684 #define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
1685 #define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)
1686 #define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
1687 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2)
1688 #define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
1689 #define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
1690 #define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
1691 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
1692 #define ADC1_2_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))
1693 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
1694 #define ADC1_2_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
1695 #define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)
1696 #endif /* STM32F302xE || */
1697 /* STM32F302xC */
1698
1699 #if defined(STM32F303x8) || defined(STM32F328xx)
1700 /* List of external triggers of group ADC1&ADC2: */
1701 /* (used internally by HAL driver. To not use into HAL structure parameters) */
1702 #define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000)
1703 #define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
1704 #define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)
1705 #define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
1706 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2)
1707 #define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
1708 #define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
1709 #define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
1710 #define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
1711 #define ADC1_2_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0))
1712 #define ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1))
1713 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
1714 #define ADC1_2_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))
1715 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
1716 #define ADC1_2_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
1717 #define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)
1718 #endif /* STM32F303x8 || STM32F328xx */
1719
1720 #if defined(STM32F334x8)
1721 /* List of external triggers of group ADC1&ADC2: */
1722 /* (used internally by HAL driver. To not use into HAL structure parameters) */
1723 #define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000)
1724 #define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
1725 #define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)
1726 #define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
1727 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2)
1728 #define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
1729 #define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
1730 #define ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0))
1731 #define ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG4 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1))
1732 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0))
1733 #define ADC1_2_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2))
1734 #define ADC1_2_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0))
1735 #define ADC1_2_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
1736 #define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)
1737 #endif /* STM32F334x8 */
1738
1739 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
1740 /* List of external triggers of injected group for ADC1: */
1741 /* (used internally by HAL driver. To not use into HAL structure parameters) */
1742 #define ADC1_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000)
1743 #define ADC1_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
1744 #define ADC1_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
1745 #define ADC1_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
1746 #define ADC1_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1))
1747 #define ADC1_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)
1748 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
1749 /**
1750 * @}
1751 */
1752
1753 /** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode
1754 * @{
1755 */
1756 #define ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000))
1757 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC12_CCR_MULTI_0))
1758 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)(ADC12_CCR_MULTI_1))
1759 #define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC12_CCR_MULTI_2 | ADC12_CCR_MULTI_0))
1760 #define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC12_CCR_MULTI_2 | ADC12_CCR_MULTI_1))
1761 #define ADC_DUALMODE_INTERL ((uint32_t)(ADC12_CCR_MULTI_2 | ADC12_CCR_MULTI_1 | ADC12_CCR_MULTI_0))
1762 #define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC12_CCR_MULTI_3 | ADC12_CCR_MULTI_0))
1763
1764 #define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \
1765 ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
1766 ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
1767 ((MODE) == ADC_DUALMODE_INJECSIMULT) || \
1768 ((MODE) == ADC_DUALMODE_REGSIMULT) || \
1769 ((MODE) == ADC_DUALMODE_INTERL) || \
1770 ((MODE) == ADC_DUALMODE_ALTERTRIG) )
1771 /**
1772 * @}
1773 */
1774
1775
1776 /** @defgroup ADCEx_Direct_memory_access_mode_for_multimode ADC Extended DMA Mode for Dual ADC Mode
1777 * @{
1778 */
1779 #define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000) /*!< DMA multimode disabled: each ADC will use its own DMA channel */
1780 #define ADC_DMAACCESSMODE_12_10_BITS ((uint32_t)ADC12_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */
1781 #define ADC_DMAACCESSMODE_8_6_BITS ((uint32_t)ADC12_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */
1782
1783 #define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAACCESSMODE_DISABLED) || \
1784 ((MODE) == ADC_DMAACCESSMODE_12_10_BITS) || \
1785 ((MODE) == ADC_DMAACCESSMODE_8_6_BITS) )
1786 /**
1787 * @}
1788 */
1789
1790 /** @defgroup ADCEx_delay_between_2_sampling_phases ADC Extended Delay Between 2 Sampling Phases
1791 * @{
1792 */
1793 #define ADC_TWOSAMPLINGDELAY_1CYCLE ((uint32_t)(0x00000000))
1794 #define ADC_TWOSAMPLINGDELAY_2CYCLES ((uint32_t)(ADC12_CCR_DELAY_0))
1795 #define ADC_TWOSAMPLINGDELAY_3CYCLES ((uint32_t)(ADC12_CCR_DELAY_1))
1796 #define ADC_TWOSAMPLINGDELAY_4CYCLES ((uint32_t)(ADC12_CCR_DELAY_1 | ADC12_CCR_DELAY_0))
1797 #define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)(ADC12_CCR_DELAY_2))
1798 #define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)(ADC12_CCR_DELAY_2 | ADC12_CCR_DELAY_0))
1799 #define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)(ADC12_CCR_DELAY_2 | ADC12_CCR_DELAY_1))
1800 #define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC12_CCR_DELAY_2 | ADC12_CCR_DELAY_1 | ADC12_CCR_DELAY_0))
1801 #define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)(ADC12_CCR_DELAY_3))
1802 #define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC12_CCR_DELAY_3 | ADC12_CCR_DELAY_0))
1803 #define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC12_CCR_DELAY_3 | ADC12_CCR_DELAY_1))
1804 #define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC12_CCR_DELAY_3 | ADC12_CCR_DELAY_1 | ADC12_CCR_DELAY_0))
1805
1806 #define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \
1807 ((DELAY) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \
1808 ((DELAY) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \
1809 ((DELAY) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \
1810 ((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
1811 ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
1812 ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
1813 ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
1814 ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
1815 ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
1816 ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
1817 ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) )
1818 /**
1819 * @}
1820 */
1821
1822 /** @defgroup ADCEx_analog_watchdog_number ADC Extended Analog Watchdog Selection
1823 * @{
1824 */
1825 #define ADC_ANALOGWATCHDOG_1 ((uint32_t)0x00000001)
1826 #define ADC_ANALOGWATCHDOG_2 ((uint32_t)0x00000002)
1827 #define ADC_ANALOGWATCHDOG_3 ((uint32_t)0x00000003)
1828
1829 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_1) || \
1830 ((WATCHDOG) == ADC_ANALOGWATCHDOG_2) || \
1831 ((WATCHDOG) == ADC_ANALOGWATCHDOG_3) )
1832 /**
1833 * @}
1834 */
1835
1836 /** @defgroup ADCEx_analog_watchdog_mode ADC Extended Analog Watchdog Mode
1837 * @{
1838 */
1839 #define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000)
1840 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN))
1841 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN))
1842 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN))
1843 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR_AWD1EN)
1844 #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CFGR_JAWD1EN)
1845 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN))
1846
1847 #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \
1848 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
1849 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
1850 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
1851 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
1852 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
1853 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
1854 /**
1855 * @}
1856 */
1857
1858 /** @defgroup ADC_conversion_group ADC Conversion Group
1859 * @{
1860 */
1861 #define REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS))
1862 #define INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC | ADC_FLAG_JEOS))
1863 #define REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS))
1864
1865 #define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == REGULAR_GROUP) || \
1866 ((CONVERSION) == INJECTED_GROUP) || \
1867 ((CONVERSION) == REGULAR_INJECTED_GROUP) )
1868 /**
1869 * @}
1870 */
1871
1872 /** @defgroup ADCEx_Event_type ADC Extended Event Type
1873 * @{
1874 */
1875 #define AWD1_EVENT ((uint32_t)ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices) */
1876 #define AWD2_EVENT ((uint32_t)ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, present only on STM32F3 devices) */
1877 #define AWD3_EVENT ((uint32_t)ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, present only on STM32F3 devices) */
1878 #define OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */
1879 #define JQOVF_EVENT ((uint32_t)ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */
1880
1881 #define AWD_EVENT AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only 1 analog watchdog */
1882
1883 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == AWD_EVENT) || \
1884 ((EVENT) == AWD2_EVENT) || \
1885 ((EVENT) == AWD3_EVENT) || \
1886 ((EVENT) == OVR_EVENT) || \
1887 ((EVENT) == JQOVF_EVENT) )
1888 /**
1889 * @}
1890 */
1891
1892 /** @defgroup ADCEx_interrupts_definition ADC Extended Interrupts Definition
1893 * @{
1894 */
1895 #define ADC_IT_RDY ADC_IER_RDY /*!< ADC Ready (ADRDY) interrupt source */
1896 #define ADC_IT_EOSMP ADC_IER_EOSMP /*!< ADC End of Sampling interrupt source */
1897 #define ADC_IT_EOC ADC_IER_EOC /*!< ADC End of Regular Conversion interrupt source */
1898 #define ADC_IT_EOS ADC_IER_EOS /*!< ADC End of Regular sequence of Conversions interrupt source */
1899 #define ADC_IT_OVR ADC_IER_OVR /*!< ADC overrun interrupt source */
1900 #define ADC_IT_JEOC ADC_IER_JEOC /*!< ADC End of Injected Conversion interrupt source */
1901 #define ADC_IT_JEOS ADC_IER_JEOS /*!< ADC End of Injected sequence of Conversions interrupt source */
1902 #define ADC_IT_AWD1 ADC_IER_AWD1 /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog, present on all STM32 devices) */
1903 #define ADC_IT_AWD2 ADC_IER_AWD2 /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog, present only on STM32F3 devices) */
1904 #define ADC_IT_AWD3 ADC_IER_AWD3 /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog, present only on STM32F3 devices) */
1905 #define ADC_IT_JQOVF ADC_IER_JQOVF /*!< ADC Injected Context Queue Overflow interrupt source */
1906
1907 #define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: Naming for compatibility with other STM32 devices having only 1 analog watchdog */
1908
1909 /* Check of single flag */
1910 #define IS_ADC_IT(IT) (((IT) == ADC_IT_RDY) || ((IT) == ADC_IT_EOSMP) || \
1911 ((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_EOS) || \
1912 ((IT) == ADC_IT_OVR) || ((IT) == ADC_IT_EOS) || \
1913 ((IT) == ADC_IT_JEOS) || ((IT) == ADC_IT_AWD1) || \
1914 ((IT) == ADC_IT_AWD2) || ((IT) == ADC_IT_AWD3) || \
1915 ((IT) == ADC_IT_JQOVF) )
1916 /**
1917 * @}
1918 */
1919
1920 /** @defgroup ADCEx_flags_definition ADC Extended Flags Definition
1921 * @{
1922 */
1923 #define ADC_FLAG_RDY ADC_ISR_ADRD /*!< ADC Ready (ADRDY) flag */
1924 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */
1925 #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */
1926 #define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */
1927 #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */
1928 #define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */
1929 #define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */
1930 #define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog, present on all STM32 devices) */
1931 #define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog, present only on STM32F3 devices) */
1932 #define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog, present only on STM32F3 devices) */
1933 #define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */
1934
1935 #define ADC_FLAG_AWD ADC_FLAG_AWD1 /*!< ADC Analog watchdog 1 flag: Naming for compatibility with other STM32 devices having only 1 analog watchdog */
1936
1937 #define ADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | \
1938 ADC_FLAG_JEOC | ADC_FLAG_JEOS | ADC_FLAG_OVR | ADC_FLAG_AWD1 | \
1939 ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | ADC_FLAG_JQOVF)
1940
1941 /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
1942 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS | \
1943 ADC_FLAG_OVR | ADC_FLAG_AWD1 | ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | \
1944 ADC_FLAG_JQOVF)
1945
1946 /* Check of single flag */
1947 #define IS_ADC_FLAG(FLAG) (((FLAG) == ADC_FLAG_RDY) || ((FLAG) == ADC_FLAG_EOSMP) || \
1948 ((FLAG) == ADC_FLAG_EOC) || ((FLAG) == ADC_FLAG_EOS) || \
1949 ((FLAG) == ADC_FLAG_OVR) || ((FLAG) == ADC_FLAG_JEOC) || \
1950 ((FLAG) == ADC_FLAG_JEOS) || ((FLAG) == ADC_FLAG_AWD1) || \
1951 ((FLAG) == ADC_FLAG_AWD2) || ((FLAG) == ADC_FLAG_AWD3) || \
1952 ((FLAG) == ADC_FLAG_JQOVF) )
1953 /**
1954 * @}
1955 */
1956
1957 /** @defgroup ADC_multimode_bits ADC Multimode Bits
1958 * @{
1959 */
1960 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
1961 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
1962 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
1963 #define ADC_CCR_MULTI ADC12_CCR_MULTI /*!< Multi ADC mode selection */
1964 #define ADC_CCR_MULTI_0 ADC12_CCR_MULTI_0 /*!< MULTI bit 0 */
1965 #define ADC_CCR_MULTI_1 ADC12_CCR_MULTI_1 /*!< MULTI bit 1 */
1966 #define ADC_CCR_MULTI_2 ADC12_CCR_MULTI_2 /*!< MULTI bit 2 */
1967 #define ADC_CCR_MULTI_3 ADC12_CCR_MULTI_3 /*!< MULTI bit 3 */
1968 #define ADC_CCR_MULTI_4 ADC12_CCR_MULTI_4 /*!< MULTI bit 4 */
1969 #define ADC_CCR_DELAY ADC12_CCR_DELAY /*!< Delay between 2 sampling phases */
1970 #define ADC_CCR_DELAY_0 ADC12_CCR_DELAY_0 /*!< DELAY bit 0 */
1971 #define ADC_CCR_DELAY_1 ADC12_CCR_DELAY_1 /*!< DELAY bit 1 */
1972 #define ADC_CCR_DELAY_2 ADC12_CCR_DELAY_2 /*!< DELAY bit 2 */
1973 #define ADC_CCR_DELAY_3 ADC12_CCR_DELAY_3 /*!< DELAY bit 3 */
1974 #define ADC_CCR_DMACFG ADC12_CCR_DMACFG /*!< DMA configuration for multi-ADC mode */
1975 #define ADC_CCR_MDMA ADC12_CCR_MDMA /*!< DMA mode for multi-ADC mode */
1976 #define ADC_CCR_MDMA_0 ADC12_CCR_MDMA_0 /*!< MDMA bit 0 */
1977 #define ADC_CCR_MDMA_1 ADC12_CCR_MDMA_1 /*!< MDMA bit 1 */
1978 #define ADC_CCR_CKMODE ADC12_CCR_CKMODE /*!< ADC clock mode */
1979 #define ADC_CCR_CKMODE_0 ADC12_CCR_CKMODE_0 /*!< CKMODE bit 0 */
1980 #define ADC_CCR_CKMODE_1 ADC12_CCR_CKMODE_1 /*!< CKMODE bit 1 */
1981 #define ADC_CCR_VREFEN ADC12_CCR_VREFEN /*!< VREFINT enable */
1982 #define ADC_CCR_TSEN ADC12_CCR_TSEN /*!< Temperature sensor enable */
1983 #define ADC_CCR_VBATEN ADC12_CCR_VBATEN /*!< VBAT enable */
1984 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
1985 /* STM32F302xC || STM32F303xC || STM32F358xx || */
1986 /* STM32F303x8 || STM32F334x8 || STM32F328xx */
1987
1988 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
1989 #define ADC_CCR_MULTI ADC1_CCR_MULTI /*!< Multi ADC mode selection */
1990 #define ADC_CCR_MULTI_0 ADC1_CCR_MULTI_0 /*!< MULTI bit 0 */
1991 #define ADC_CCR_MULTI_1 ADC1_CCR_MULTI_1 /*!< MULTI bit 1 */
1992 #define ADC_CCR_MULTI_2 ADC1_CCR_MULTI_2 /*!< MULTI bit 2 */
1993 #define ADC_CCR_MULTI_3 ADC1_CCR_MULTI_3 /*!< MULTI bit 3 */
1994 #define ADC_CCR_MULTI_4 ADC1_CCR_MULTI_4 /*!< MULTI bit 4 */
1995 #define ADC_CCR_DELAY ADC1_CCR_DELAY /*!< Delay between 2 sampling phases */
1996 #define ADC_CCR_DELAY_0 ADC1_CCR_DELAY_0 /*!< DELAY bit 0 */
1997 #define ADC_CCR_DELAY_1 ADC1_CCR_DELAY_1 /*!< DELAY bit 1 */
1998 #define ADC_CCR_DELAY_2 ADC1_CCR_DELAY_2 /*!< DELAY bit 2 */
1999 #define ADC_CCR_DELAY_3 ADC1_CCR_DELAY_3 /*!< DELAY bit 3 */
2000 #define ADC_CCR_DMACFG ADC1_CCR_DMACFG /*!< DMA configuration for multi-ADC mode */
2001 #define ADC_CCR_MDMA ADC1_CCR_MDMA /*!< DMA mode for multi-ADC mode */
2002 #define ADC_CCR_MDMA_0 ADC1_CCR_MDMA_0 /*!< MDMA bit 0 */
2003 #define ADC_CCR_MDMA_1 ADC1_CCR_MDMA_1 /*!< MDMA bit 1 */
2004 #define ADC_CCR_CKMODE ADC1_CCR_CKMODE /*!< ADC clock mode */
2005 #define ADC_CCR_CKMODE_0 ADC1_CCR_CKMODE_0 /*!< CKMODE bit 0 */
2006 #define ADC_CCR_CKMODE_1 ADC1_CCR_CKMODE_1 /*!< CKMODE bit 1 */
2007 #define ADC_CCR_VREFEN ADC1_CCR_VREFEN /*!< VREFINT enable */
2008 #define ADC_CCR_TSEN ADC1_CCR_TSEN /*!< Temperature sensor enable */
2009 #define ADC_CCR_VBATEN ADC1_CCR_VBATEN /*!< VBAT enable */
2010 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2011
2012
2013 /**
2014 * @}
2015 */
2016
2017 /** @defgroup ADCEx_range_verification ADC Extended Range Verification
2018 * in function of ADC resolution selected (12, 10, 8 or 6 bits)
2019 * @{
2020 */
2021 #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
2022 ((((RESOLUTION) == ADC_RESOLUTION12b) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \
2023 (((RESOLUTION) == ADC_RESOLUTION10b) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \
2024 (((RESOLUTION) == ADC_RESOLUTION8b) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \
2025 (((RESOLUTION) == ADC_RESOLUTION6b) && ((ADC_VALUE) <= ((uint32_t)0x003F))) )
2026 /**
2027 * @}
2028 */
2029
2030 /** @defgroup ADC_injected_nb_conv_verification ADC Injected Conversion Number Verification
2031 * @{
2032 */
2033 #define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4)))
2034 /**
2035 * @}
2036 */
2037
2038 /** @defgroup ADC_regular_nb_conv_verification ADC Regular Conversion Number Verification
2039 * @{
2040 */
2041 #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
2042 /**
2043 * @}
2044 */
2045
2046 /** @defgroup ADC_regular_discontinuous_mode_number_verification ADC Regular Discontinuous Mode NumberVerification
2047 * @{
2048 */
2049 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
2050 /**
2051 * @}
2052 */
2053
2054 /** @defgroup ADC_calibration_factor_length_verification ADC Calibration Factor Length Verification
2055 * @{
2056 */
2057 /**
2058 * @brief Calibration factor length verification (7 bits maximum)
2059 * @param _Calibration_Factor_: Calibration factor value
2060 * @retval None
2061 */
2062 #define IS_ADC_CALFACT(_Calibration_Factor_) ((_Calibration_Factor_) <= ((uint32_t)0x7F))
2063 /**
2064 * @}
2065 */
2066 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2067 /* STM32F302xC || STM32F303xC || STM32F358xx || */
2068 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2069 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2070
2071
2072 #if defined(STM32F373xC) || defined(STM32F378xx)
2073 /** @defgroup ADCEx_Data_align ADC Extended Data Alignment
2074 * @{
2075 */
2076 #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
2077 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
2078
2079 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
2080 ((ALIGN) == ADC_DATAALIGN_LEFT) )
2081 /**
2082 * @}
2083 */
2084
2085 /** @defgroup ADCEx_Scan_mode ADC Extended Scan Mode
2086 * @{
2087 */
2088 #define ADC_SCAN_DISABLE ((uint32_t)0x00000000)
2089 #define ADC_SCAN_ENABLE ((uint32_t)0x00000001)
2090
2091 #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \
2092 ((SCAN_MODE) == ADC_SCAN_ENABLE) )
2093 /**
2094 * @}
2095 */
2096
2097 /** @defgroup ADCEx_External_trigger_edge_Regular ADC Extended External trigger enable for regular channels
2098 * @{
2099 */
2100 #define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
2101 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG)
2102
2103 #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
2104 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) )
2105 /**
2106 * @}
2107 */
2108
2109 /** @defgroup ADCEx_External_trigger_source_Regular ADC Extended External trigger selection for regular group
2110 * @{
2111 */
2112 /* List of external triggers with generic trigger name, sorted by trigger */
2113 /* name: */
2114
2115 /* External triggers of regular group for ADC1 */
2116 #define ADC_EXTERNALTRIGCONV_T2_CC2 ADC_EXTERNALTRIG_T2_CC2
2117 #define ADC_EXTERNALTRIGCONV_T3_TRGO ADC_EXTERNALTRIG_T3_TRGO
2118 #define ADC_EXTERNALTRIGCONV_T4_CC2 ADC_EXTERNALTRIG_T4_CC2
2119 #define ADC_EXTERNALTRIGCONV_T19_TRGO ADC_EXTERNALTRIG_T19_TRGO
2120 #define ADC_EXTERNALTRIGCONV_T19_CC3 ADC_EXTERNALTRIG_T19_CC3
2121 #define ADC_EXTERNALTRIGCONV_T19_CC4 ADC_EXTERNALTRIG_T19_CC4
2122 #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC_EXTERNALTRIG_EXT_IT11
2123 #define ADC_SOFTWARE_START ADC_SWSTART
2124
2125 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
2126 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
2127 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC2) || \
2128 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T19_TRGO) || \
2129 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T19_CC3) || \
2130 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T19_CC4) || \
2131 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
2132 ((REGTRIG) == ADC_SOFTWARE_START) )
2133 /**
2134 * @}
2135 */
2136
2137
2138 /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended External trigger selection for regular group (Used Internally)
2139 * @{
2140 */
2141
2142 /* List of external triggers of regular group for ADC1: */
2143 /* (used internally by HAL driver. To not use into HAL structure parameters) */
2144
2145 /* External triggers of regular group for ADC1 */
2146 #define ADC_EXTERNALTRIG_T19_TRGO ((uint32_t)0x00000000)
2147 #define ADC_EXTERNALTRIG_T19_CC3 ((uint32_t)ADC_CR2_EXTSEL_0)
2148 #define ADC_EXTERNALTRIG_T19_CC4 ((uint32_t)ADC_CR2_EXTSEL_1)
2149 #define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
2150 #define ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_2)
2151 #define ADC_EXTERNALTRIG_T4_CC2 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
2152 #define ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
2153 #define ADC_SWSTART ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
2154
2155 /**
2156 * @}
2157 */
2158
2159
2160 /** @defgroup ADCEx_channels ADC Extended Channels
2161 * @{
2162 */
2163 /* Note: Depending on devices, some channels may not be available on package */
2164 /* pins. Refer to device datasheet for channels availability. */
2165 #define ADC_CHANNEL_0 ((uint32_t)0x00000000)
2166 #define ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ1_0))
2167 #define ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ1_1))
2168 #define ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
2169 #define ADC_CHANNEL_4 ((uint32_t)(ADC_SQR3_SQ1_2))
2170 #define ADC_CHANNEL_5 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
2171 #define ADC_CHANNEL_6 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1))
2172 #define ADC_CHANNEL_7 ((uint32_t)(ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
2173 #define ADC_CHANNEL_8 ((uint32_t)(ADC_SQR3_SQ1_3))
2174 #define ADC_CHANNEL_9 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0))
2175 #define ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1))
2176 #define ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
2177 #define ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2))
2178 #define ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
2179 #define ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1))
2180 #define ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
2181 #define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4))
2182 #define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0))
2183 #define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_1))
2184
2185 #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16
2186 #define ADC_CHANNEL_VREFINT ADC_CHANNEL_17
2187 #define ADC_CHANNEL_VBAT ADC_CHANNEL_18
2188
2189 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
2190 ((CHANNEL) == ADC_CHANNEL_1) || \
2191 ((CHANNEL) == ADC_CHANNEL_2) || \
2192 ((CHANNEL) == ADC_CHANNEL_3) || \
2193 ((CHANNEL) == ADC_CHANNEL_4) || \
2194 ((CHANNEL) == ADC_CHANNEL_5) || \
2195 ((CHANNEL) == ADC_CHANNEL_6) || \
2196 ((CHANNEL) == ADC_CHANNEL_7) || \
2197 ((CHANNEL) == ADC_CHANNEL_8) || \
2198 ((CHANNEL) == ADC_CHANNEL_9) || \
2199 ((CHANNEL) == ADC_CHANNEL_10) || \
2200 ((CHANNEL) == ADC_CHANNEL_11) || \
2201 ((CHANNEL) == ADC_CHANNEL_12) || \
2202 ((CHANNEL) == ADC_CHANNEL_13) || \
2203 ((CHANNEL) == ADC_CHANNEL_14) || \
2204 ((CHANNEL) == ADC_CHANNEL_15) || \
2205 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \
2206 ((CHANNEL) == ADC_CHANNEL_VREFINT) || \
2207 ((CHANNEL) == ADC_CHANNEL_VBAT) )
2208 /**
2209 * @}
2210 */
2211
2212 /** @defgroup ADCEx_sampling_times ADC Extended Sampling Times
2213 * @{
2214 */
2215 #define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000) /*!< Sampling time 1.5 ADC clock cycle */
2216 #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_0) /*!< Sampling time 7.5 ADC clock cycles */
2217 #define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_1) /*!< Sampling time 13.5 ADC clock cycles */
2218 #define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 28.5 ADC clock cycles */
2219 #define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_2) /*!< Sampling time 41.5 ADC clock cycles */
2220 #define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 55.5 ADC clock cycles */
2221 #define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1)) /*!< Sampling time 71.5 ADC clock cycles */
2222 #define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0) /*!< Sampling time 239.5 ADC clock cycles */
2223
2224 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \
2225 ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \
2226 ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \
2227 ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \
2228 ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \
2229 ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \
2230 ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \
2231 ((TIME) == ADC_SAMPLETIME_239CYCLES_5) )
2232 /**
2233 * @}
2234 */
2235
2236 /** @defgroup ADCEx_sampling_times_all_channels ADC Extended Sampling Times All Channels
2237 * @{
2238 */
2239 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \
2240 (ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 | \
2241 ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 | \
2242 ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2)
2243 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
2244 (ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | \
2245 ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2 )
2246
2247 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \
2248 (ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 | \
2249 ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 | \
2250 ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1)
2251 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
2252 (ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | \
2253 ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1 )
2254
2255 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \
2256 (ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 | \
2257 ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 | \
2258 ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0)
2259 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
2260 (ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | \
2261 ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0 )
2262
2263 #define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS ((uint32_t)0x00000000)
2264 #define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
2265 #define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
2266 #define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
2267 #define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2)
2268 #define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
2269 #define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
2270 #define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
2271
2272 #define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS ((uint32_t)0x00000000)
2273 #define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
2274 #define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
2275 #define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
2276 #define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2)
2277 #define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
2278 #define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
2279 #define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
2280
2281 /**
2282 * @}
2283 */
2284
2285 /** @defgroup ADCEx_regular_rank ADC Extended Regular Channel Rank
2286 * @{
2287 */
2288 #define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001)
2289 #define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002)
2290 #define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003)
2291 #define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004)
2292 #define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005)
2293 #define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006)
2294 #define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007)
2295 #define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008)
2296 #define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009)
2297 #define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A)
2298 #define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B)
2299 #define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C)
2300 #define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D)
2301 #define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E)
2302 #define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F)
2303 #define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010)
2304
2305 #define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \
2306 ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \
2307 ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \
2308 ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \
2309 ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \
2310 ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
2311 ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
2312 ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
2313 ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
2314 ((CHANNEL) == ADC_REGULAR_RANK_10) || \
2315 ((CHANNEL) == ADC_REGULAR_RANK_11) || \
2316 ((CHANNEL) == ADC_REGULAR_RANK_12) || \
2317 ((CHANNEL) == ADC_REGULAR_RANK_13) || \
2318 ((CHANNEL) == ADC_REGULAR_RANK_14) || \
2319 ((CHANNEL) == ADC_REGULAR_RANK_15) || \
2320 ((CHANNEL) == ADC_REGULAR_RANK_16) )
2321 /**
2322 * @}
2323 */
2324
2325 /** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank
2326 * @{
2327 */
2328 #define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001)
2329 #define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002)
2330 #define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003)
2331 #define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004)
2332
2333 #define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \
2334 ((CHANNEL) == ADC_INJECTED_RANK_2) || \
2335 ((CHANNEL) == ADC_INJECTED_RANK_3) || \
2336 ((CHANNEL) == ADC_INJECTED_RANK_4) )
2337 /**
2338 * @}
2339 */
2340
2341 /** @defgroup ADCEx_External_trigger_edge_Injected External Trigger Edge of Injected Group
2342 * @{
2343 */
2344 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000)
2345 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTTRIG)
2346
2347 #define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
2348 ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) )
2349 /**
2350 * @}
2351 */
2352
2353 /** @defgroup ADCEx_External_trigger_source_Injected External Trigger Source of Injected Group
2354 * @{
2355 */
2356 /* External triggers for injected groups of ADC1 */
2357 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC_EXTERNALTRIGINJEC_T2_CC1
2358 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC_EXTERNALTRIGINJEC_T2_TRGO
2359 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC_EXTERNALTRIGINJEC_T3_CC4
2360 #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC_EXTERNALTRIGINJEC_T4_TRGO
2361 #define ADC_EXTERNALTRIGINJECCONV_T19_CC1 ADC_EXTERNALTRIGINJEC_T19_CC1
2362 #define ADC_EXTERNALTRIGINJECCONV_T19_CC2 ADC_EXTERNALTRIGINJEC_T19_CC2
2363 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC_EXTERNALTRIGINJEC_EXT_IT15
2364 #define ADC_INJECTED_SOFTWARE_START ADC_JSWSTART
2365
2366 #define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
2367 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
2368 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
2369 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
2370 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T19_CC1) || \
2371 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T19_CC2) || \
2372 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
2373 ((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
2374 /**
2375 * @}
2376 */
2377
2378
2379 /** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended External Trigger Source of Injected Group (Internal)
2380 * @{
2381 */
2382
2383 /* List of external triggers of injected group for ADC1: */
2384 /* (used internally by HAL driver. To not use into HAL structure parameters) */
2385 #define ADC_EXTERNALTRIGINJEC_T19_CC1 ((uint32_t) 0x00000000)
2386 #define ADC_EXTERNALTRIGINJEC_T19_CC2 ((uint32_t) ADC_CR2_JEXTSEL_0)
2387 #define ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t) ADC_CR2_JEXTSEL_1)
2388 #define ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
2389 #define ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t) ADC_CR2_JEXTSEL_2)
2390 #define ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
2391 #define ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
2392 #define ADC_JSWSTART ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
2393
2394 /**
2395 * @}
2396 */
2397
2398
2399 /** @defgroup ADCEx_analog_watchdog_mode ADC Extended analog watchdog mode
2400 * @{
2401 */
2402 #define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)
2403 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
2404 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
2405 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
2406 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CR1_AWDEN)
2407 #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CR1_JAWDEN)
2408 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
2409
2410 #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \
2411 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
2412 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
2413 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
2414 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
2415 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
2416 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
2417 /**
2418 * @}
2419 */
2420
2421 /** @defgroup ADC_conversion_group ADC Conversion Group
2422 * @{
2423 */
2424 #define REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC))
2425 #define INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC))
2426 #define REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC))
2427
2428 #define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == REGULAR_GROUP) || \
2429 ((CONVERSION) == INJECTED_GROUP) || \
2430 ((CONVERSION) == REGULAR_INJECTED_GROUP) )
2431 /**
2432 * @}
2433 */
2434
2435 /** @defgroup ADCEx_Event_type ADC Extended Event Type
2436 * @{
2437 */
2438 #define AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */
2439
2440 #define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == AWD_EVENT)
2441 /**
2442 * @}
2443 */
2444
2445 /** @defgroup ADCEx_interrupts_definition ADC Extended Interrupts Definition
2446 * @{
2447 */
2448 #define ADC_IT_EOC ADC_CR1_EOCIE /*!< ADC End of Regular Conversion interrupt source */
2449 #define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */
2450 #define ADC_IT_AWD ADC_CR1_AWDIE /*!< ADC Analog watchdog interrupt source */
2451
2452 /* Check of single flag */
2453 #define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC ) || \
2454 ((IT) == ADC_IT_JEOC) || \
2455 ((IT) == ADC_IT_AWD ) )
2456 /**
2457 * @}
2458 */
2459
2460 /** @defgroup ADCEx_flags_definition ADC Extended Flags Definition
2461 * @{
2462 */
2463 #define ADC_FLAG_AWD ADC_SR_AWD /*!< ADC Analog watchdog flag */
2464 #define ADC_FLAG_EOC ADC_SR_EOC /*!< ADC End of Regular conversion flag */
2465 #define ADC_FLAG_JEOC ADC_SR_JEOC /*!< ADC End of Injected conversion flag */
2466 #define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */
2467 #define ADC_FLAG_STRT ADC_SR_STRT /*!< ADC Regular group start flag */
2468
2469 /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
2470 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD )
2471
2472 /* Check of single flag */
2473 #define IS_ADC_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \
2474 ((FLAG) == ADC_FLAG_EOC) || \
2475 ((FLAG) == ADC_FLAG_JEOC) || \
2476 ((FLAG) == ADC_FLAG_JSTRT) || \
2477 ((FLAG) == ADC_FLAG_STRT) )
2478 /**
2479 * @}
2480 */
2481
2482 /** @defgroup ADCEx_range_verification ADC Extended Range Verification
2483 * For a unique ADC resolution: 12 bits
2484 * @{
2485 */
2486 #define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= ((uint32_t)0x0FFF))
2487 /**
2488 * @}
2489 */
2490
2491 /** @defgroup ADC_injected_nb_conv_verification ADC Injected Conversion Number Verification
2492 * @{
2493 */
2494 #define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4)))
2495 /**
2496 * @}
2497 */
2498
2499 /** @defgroup ADC_regular_nb_conv_verification ADC Regular Conversion Number Verification
2500 * @{
2501 */
2502 #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
2503 /**
2504 * @}
2505 */
2506
2507 /** @defgroup ADC_regular_discontinuous_mode_number_verification ADC Regular Discontinuous Mode NumberVerification
2508 * @{
2509 */
2510 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
2511 /**
2512 * @}
2513 */
2514 #endif /* STM32F373xC || STM32F378xx */
2515
2516 /**
2517 * @}
2518 */
2519
2520 /* Exported macros -----------------------------------------------------------*/
2521
2522 /** @addtogroup ADC_Exported_Macro ADC Exported Macros
2523 * @{
2524 */
2525 /* Macro for internal HAL driver usage, and possibly can be used into code of */
2526 /* final user. */
2527
2528 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
2529 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
2530 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
2531 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2532 /**
2533 * @brief Verification of ADC state: enabled or disabled
2534 * @param __HANDLE__: ADC handle
2535 * @retval SET (ADC enabled) or RESET (ADC disabled)
2536 */
2537 #define __HAL_ADC_IS_ENABLED(__HANDLE__) \
2538 (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
2539 ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \
2540 ) ? SET : RESET)
2541
2542 /**
2543 * @brief Test if conversion trigger of regular group is software start
2544 * or external trigger.
2545 * @param __HANDLE__: ADC handle
2546 * @retval SET (software start) or RESET (external trigger)
2547 */
2548 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
2549 (((__HANDLE__)->Instance->CFGR & ADC_CFGR_EXTEN) == RESET)
2550
2551 /**
2552 * @brief Test if conversion trigger of injected group is software start
2553 * or external trigger.
2554 * @param __HANDLE__: ADC handle
2555 * @retval SET (software start) or RESET (external trigger)
2556 */
2557 #define __HAL_ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
2558 (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET)
2559
2560 /**
2561 * @brief Check if no conversion on going on regular and/or injected groups
2562 * @param __HANDLE__: ADC handle
2563 * @retval SET (conversion is on going) or RESET (no conversion is on going)
2564 */
2565 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \
2566 (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == RESET \
2567 ) ? RESET : SET)
2568
2569 /**
2570 * @brief Check if no conversion on going on regular group
2571 * @param __HANDLE__: ADC handle
2572 * @retval SET (conversion is on going) or RESET (no conversion is on going)
2573 */
2574 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \
2575 (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \
2576 ) ? RESET : SET)
2577
2578 /**
2579 * @brief Check if no conversion on going on injected group
2580 * @param __HANDLE__: ADC handle
2581 * @retval SET (conversion is on going) or RESET (no conversion is on going)
2582 */
2583 #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \
2584 (( (((__HANDLE__)->Instance->CR) & ADC_CR_JADSTART) == RESET \
2585 ) ? RESET : SET)
2586
2587 /**
2588 * @brief Returns resolution bits in CFGR1 register: RES[1:0].
2589 * Returned value is among parameters to @ref ADCEx_Resolution.
2590 * @param __HANDLE__: ADC handle
2591 * @retval None
2592 */
2593 #define __HAL_ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)
2594
2595 /** @brief Checks if the specified ADC interrupt source is enabled or disabled.
2596 * @param __HANDLE__: ADC handle
2597 * @param __INTERRUPT__: ADC interrupt source to check
2598 * @retval State of interruption (SET or RESET)
2599 */
2600 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
2601 (( ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__) \
2602 )? SET : RESET \
2603 )
2604
2605 /**
2606 * @brief Enable the ADC end of conversion interrupt.
2607 * @param __HANDLE__: ADC handle
2608 * @param __INTERRUPT__: ADC Interrupt
2609 * @retval None
2610 */
2611 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
2612
2613 /**
2614 * @brief Disable the ADC end of conversion interrupt.
2615 * @param __HANDLE__: ADC handle
2616 * @param __INTERRUPT__: ADC Interrupt
2617 * @retval None
2618 */
2619 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
2620
2621 /**
2622 * @brief Get the selected ADC's flag status.
2623 * @param __HANDLE__: ADC handle
2624 * @param __FLAG__: ADC flag
2625 * @retval None
2626 */
2627 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
2628
2629 /**
2630 * @brief Clear the ADC's pending flags
2631 * @param __HANDLE__: ADC handle
2632 * @param __FLAG__: ADC flag
2633 * @retval None
2634 */
2635 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */
2636 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__))
2637
2638 /**
2639 * @brief Clear ADC error code (set it to error code: "no error")
2640 * @param __HANDLE__: ADC handle
2641 * @retval None
2642 */
2643 #define __HAL_ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
2644 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2645 /* STM32F302xC || STM32F303xC || STM32F358xx || */
2646 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2647 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2648
2649 #if defined(STM32F373xC) || defined(STM32F378xx)
2650 /**
2651 * @brief Verification of ADC state: enabled or disabled
2652 * @param __HANDLE__: ADC handle
2653 * @retval SET (ADC enabled) or RESET (ADC disabled)
2654 */
2655 #define __HAL_ADC_IS_ENABLED(__HANDLE__) \
2656 ((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON ) \
2657 ) ? SET : RESET)
2658
2659 /**
2660 * @brief Test if conversion trigger of regular group is software start
2661 * or external trigger.
2662 * @param __HANDLE__: ADC handle
2663 * @retval SET (software start) or RESET (external trigger)
2664 */
2665 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
2666 (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)
2667
2668 /**
2669 * @brief Test if conversion trigger of injected group is software start
2670 * or external trigger.
2671 * @param __HANDLE__: ADC handle
2672 * @retval SET (software start) or RESET (external trigger)
2673 */
2674 #define __HAL_ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
2675 (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)
2676
2677 /** @brief Checks if the specified ADC interrupt source is enabled or disabled.
2678 * @param __HANDLE__: ADC handle
2679 * @param __INTERRUPT__: ADC interrupt source to check
2680 * @retval State of interruption (SET or RESET)
2681 */
2682 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
2683 (( ((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__) \
2684 )? SET : RESET \
2685 )
2686
2687
2688 /**
2689 * @brief Enable the ADC end of conversion interrupt.
2690 * @param __HANDLE__: ADC handle
2691 * @param __INTERRUPT__: ADC Interrupt
2692 * @retval None
2693 */
2694 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
2695
2696 /**
2697 * @brief Disable the ADC end of conversion interrupt.
2698 * @param __HANDLE__: ADC handle
2699 * @param __INTERRUPT__: ADC Interrupt
2700 * @retval None
2701 */
2702 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
2703
2704 /**
2705 * @brief Get the selected ADC's flag status.
2706 * @param __HANDLE__: ADC handle
2707 * @param __FLAG__: ADC flag
2708 * @retval None
2709 */
2710 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
2711
2712 /**
2713 * @brief Clear the ADC's pending flags
2714 * @param __HANDLE__: ADC handle
2715 * @param __FLAG__: ADC flag
2716 * @retval None
2717 */
2718 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
2719
2720 /**
2721 * @brief Clear ADC error code (set it to error code: "no error")
2722 * @param __HANDLE__: ADC handle
2723 * @retval None
2724 */
2725 #define __HAL_ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
2726
2727 #endif /* STM32F373xC || STM32F378xx */
2728 /**
2729 * @}
2730 */
2731
2732
2733 /* Macro reserved for internal HAL driver usage, not intended to be used in */
2734 /* code of final user. */
2735
2736 /** @defgroup ADCEx_Exported_Macro_internal_HAL_driver ADC Extended Exported Macros (Internal)
2737 * @{
2738 */
2739 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
2740 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
2741 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
2742 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2743
2744 /**
2745 * @brief Set the ADC's sample time for Channels numbers between 0 and 9.
2746 * @param _SAMPLETIME_: Sample time parameter.
2747 * @param _CHANNELNB_: Channel number.
2748 * @retval None
2749 */
2750 #define __HAL_ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (_CHANNELNB_)))
2751
2752 /**
2753 * @brief Set the ADC's sample time for Channels numbers between 10 and 18.
2754 * @param _SAMPLETIME_: Sample time parameter.
2755 * @param _CHANNELNB_: Channel number.
2756 * @retval None
2757 */
2758 #define __HAL_ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10)))
2759
2760 /**
2761 * @brief Set the selected regular Channel rank for rank between 1 and 4.
2762 * @param _CHANNELNB_: Channel number.
2763 * @param _RANKNB_: Rank number.
2764 * @retval None
2765 */
2766 #define __HAL_ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6 * (_RANKNB_)))
2767
2768 /**
2769 * @brief Set the selected regular Channel rank for rank between 5 and 9.
2770 * @param _CHANNELNB_: Channel number.
2771 * @param _RANKNB_: Rank number.
2772 * @retval None
2773 */
2774 #define __HAL_ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6 * ((_RANKNB_) - 5)))
2775
2776 /**
2777 * @brief Set the selected regular Channel rank for rank between 10 and 14.
2778 * @param _CHANNELNB_: Channel number.
2779 * @param _RANKNB_: Rank number.
2780 * @retval None
2781 */
2782 #define __HAL_ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6 * ((_RANKNB_) - 10)))
2783
2784 /**
2785 * @brief Set the selected regular Channel rank for rank between 15 and 16.
2786 * @param _CHANNELNB_: Channel number.
2787 * @param _RANKNB_: Rank number.
2788 * @retval None
2789 */
2790 #define __HAL_ADC_SQR4_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6 * ((_RANKNB_) - 15)))
2791
2792 /**
2793 * @brief Set the selected injected Channel rank.
2794 * @param _CHANNELNB_: Channel number.
2795 * @param _RANKNB_: Rank number.
2796 * @retval None
2797 */
2798 #define __HAL_ADC_JSQR_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6 * (_RANKNB_) +2))
2799
2800
2801 /**
2802 * @brief Set the Analog Watchdog 1 channel.
2803 * @param _CHANNEL_: channel to be monitored by Analog Watchdog 1.
2804 * @retval None
2805 */
2806 #define __HAL_ADC_CFGR_AWD1CH(_CHANNEL_) ((_CHANNEL_) << 26)
2807
2808 /**
2809 * @brief Configure the channel number into Analog Watchdog 2 or 3.
2810 * @param _CHANNEL_: ADC Channel
2811 * @retval None
2812 */
2813 #define __HAL_ADC_CFGR_AWD23CR(_CHANNEL_) (1U << (_CHANNEL_))
2814
2815 /**
2816 * @brief Enable automatic conversion of injected group
2817 * @param _INJECT_AUTO_CONVERSION_: Injected automatic conversion.
2818 * @retval None
2819 */
2820 #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION(_INJECT_AUTO_CONVERSION_) ((_INJECT_AUTO_CONVERSION_) << 25)
2821
2822 /**
2823 * @brief Enable ADC injected context queue
2824 * @param _INJECT_CONTEXT_QUEUE_MODE_: Injected context queue mode.
2825 * @retval None
2826 */
2827 #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE(_INJECT_CONTEXT_QUEUE_MODE_) ((_INJECT_CONTEXT_QUEUE_MODE_) << 21)
2828
2829 /**
2830 * @brief Enable ADC discontinuous conversion mode for injected group
2831 * @param _INJECT_DISCONTINUOUS_MODE_: Injected discontinuous mode.
2832 * @retval None
2833 */
2834 #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS(_INJECT_DISCONTINUOUS_MODE_) ((_INJECT_DISCONTINUOUS_MODE_) << 20)
2835
2836 /**
2837 * @brief Enable ADC discontinuous conversion mode for regular group
2838 * @param _REG_DISCONTINUOUS_MODE_: Regular discontinuous mode.
2839 * @retval None
2840 */
2841 #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) ((_REG_DISCONTINUOUS_MODE_) << 16)
2842
2843 /**
2844 * @brief Configures the number of discontinuous conversions for regular group.
2845 * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
2846 * @retval None
2847 */
2848 #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1) << 17)
2849
2850 /**
2851 * @brief Enable the ADC auto delay mode.
2852 * @param _AUTOWAIT_: Auto delay bit enable or disable.
2853 * @retval None
2854 */
2855 #define __HAL_ADC_CFGR_AUTOWAIT(_AUTOWAIT_) ((_AUTOWAIT_) << 14)
2856
2857 /**
2858 * @brief Enable ADC continuous conversion mode.
2859 * @param _CONTINUOUS_MODE_: Continuous mode.
2860 * @retval None
2861 */
2862 #define __HAL_ADC_CFGR_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13)
2863
2864 /**
2865 * @brief Enable ADC overrun mode.
2866 * @param _OVERRUN_MODE_: Overrun mode.
2867 * @retval Overrun bit setting to be programmed into CFGR register
2868 */
2869 /* Note: Bit ADC_CFGR_OVRMOD not used directly in constant */
2870 /* "OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it as the */
2871 /* default case to be compliant with other STM32 devices. */
2872 #define __HAL_ADC_CFGR_OVERRUN(_OVERRUN_MODE_) \
2873 ( ( (_OVERRUN_MODE_) != (OVR_DATA_PRESERVED) \
2874 )? (ADC_CFGR_OVRMOD) : (0x00000000) \
2875 )
2876
2877 /**
2878 * @brief Enable the ADC DMA continuous request.
2879 * @param _DMACONTREQ_MODE_: DMA continuous request mode.
2880 * @retval None
2881 */
2882 #define __HAL_ADC_CFGR_DMACONTREQ(_DMACONTREQ_MODE_) ((_DMACONTREQ_MODE_) << 1)
2883
2884 /**
2885 * @brief For devices with 3 ADCs or more: Defines the external trigger source
2886 * for regular group according to ADC into common group ADC1&ADC2 or
2887 * ADC3&ADC4 (some triggers with same source have different value to
2888 * be programmed into ADC EXTSEL bits of CFGR register).
2889 * Note: No risk of trigger bits value of common group ADC1&ADC2
2890 * misleading to another trigger at same bits value, because the 3
2891 * exceptions below are circular and do not point to any other trigger
2892 * with direct treatment.
2893 * For devices with 2 ADCs or less: this macro makes no change.
2894 * @param __HANDLE__: ADC handle
2895 * @param __EXT_TRIG_CONV__: External trigger selected for regular group.
2896 * @retval External trigger to be programmed into EXTSEL bits of CFGR register
2897 */
2898 #if defined(STM32F303xE) || defined(STM32F398xx) || \
2899 defined(STM32F303xC) || defined(STM32F358xx)
2900
2901 #if defined(STM32F303xC) || defined(STM32F358xx)
2902 #define __HAL_ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \
2903 (( ((((__HANDLE__)->Instance) == ADC3) || (((__HANDLE__)->Instance) == ADC4)) \
2904 )? \
2905 ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T2_TRGO \
2906 )? \
2907 (ADC3_4_EXTERNALTRIG_T2_TRGO) \
2908 : \
2909 ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T3_TRGO \
2910 )? \
2911 (ADC3_4_EXTERNALTRIG_T3_TRGO) \
2912 : \
2913 ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO \
2914 )? \
2915 (ADC3_4_EXTERNALTRIG_T8_TRGO) \
2916 : \
2917 (__EXT_TRIG_CONV__) \
2918 ) \
2919 ) \
2920 ) \
2921 : \
2922 (__EXT_TRIG_CONV__) \
2923 )
2924 #endif /* STM32F303xC || STM32F358xx */
2925
2926 #if defined(STM32F303xE) || defined(STM32F398xx)
2927 /* Note: Macro including external triggers specific to device STM303xE: using */
2928 /* Timer20 with ADC trigger input remap. */
2929 #define __HAL_ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \
2930 (( ((((__HANDLE__)->Instance) == ADC3) || (((__HANDLE__)->Instance) == ADC4)) \
2931 )? \
2932 ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T2_TRGO \
2933 )? \
2934 (ADC3_4_EXTERNALTRIG_T2_TRGO) \
2935 : \
2936 ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T3_TRGO \
2937 )? \
2938 (ADC3_4_EXTERNALTRIG_T3_TRGO) \
2939 : \
2940 ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO \
2941 )? \
2942 (ADC3_4_EXTERNALTRIG_T8_TRGO) \
2943 : \
2944 ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T20_CC1 \
2945 )? \
2946 (ADC3_4_EXTERNALTRIG_T2_CC1) \
2947 : \
2948 ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T20_TRGO \
2949 )? \
2950 (ADC3_4_EXTERNALTRIG_EXT_IT2) \
2951 : \
2952 ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T20_TRGO2 \
2953 )? \
2954 (ADC3_4_EXTERNALTRIG_T4_CC1) \
2955 : \
2956 (__EXT_TRIG_CONV__) \
2957 ) \
2958 ) \
2959 ) \
2960 ) \
2961 ) \
2962 ) \
2963 : \
2964 (__EXT_TRIG_CONV__ & (~ADC_EXTERNALTRIGCONV_T20_MASK)) \
2965 )
2966 #endif /* STM32F303xE || STM32F398xx */
2967 #else
2968 #define __HAL_ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \
2969 (__EXT_TRIG_CONV__)
2970 #endif /* STM32F303xE || STM32F398xx || */
2971 /* STM32F303xC || STM32F358xx */
2972
2973 /**
2974 * @brief For devices with 3 ADCs or more: Defines the external trigger source
2975 * for injected group according to ADC into common group ADC1&ADC2 or
2976 * ADC3&ADC4 (some triggers with same source have different value to
2977 * be programmed into ADC JEXTSEL bits of JSQR register).
2978 * Note: No risk of trigger bits value of common group ADC1&ADC2
2979 * misleading to another trigger at same bits value, because the 3
2980 * exceptions below are circular and do not point to any other trigger
2981 * with direct treatment, except trigger
2982 * ADC_EXTERNALTRIGINJECCONV_T4_CC3 differentiated with SW offset.
2983 * For devices with 2 ADCs or less: this macro makes no change.
2984 * @param __HANDLE__: ADC handle
2985 * @param __EXT_TRIG_INJECTCONV__: External trigger selected for injected group
2986 * @retval External trigger to be programmed into JEXTSEL bits of JSQR register
2987 */
2988 #if defined(STM32F303xC) || defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F358xx)
2989 #if defined(STM32F303xC) || defined(STM32F358xx)
2990 #define __HAL_ADC_JSQR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
2991 (( ((((__HANDLE__)->Instance) == ADC3) || (((__HANDLE__)->Instance) == ADC4)) \
2992 )? \
2993 ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO \
2994 )? \
2995 (ADC3_4_EXTERNALTRIGINJEC_T2_TRGO) \
2996 : \
2997 ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO \
2998 )? \
2999 (ADC3_4_EXTERNALTRIGINJEC_T4_TRGO) \
3000 : \
3001 ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4 \
3002 )? \
3003 (ADC3_4_EXTERNALTRIGINJEC_T8_CC4) \
3004 : \
3005 ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T4_CC3 \
3006 )? \
3007 (ADC3_4_EXTERNALTRIGINJEC_T4_CC3) \
3008 : \
3009 (__EXT_TRIG_INJECTCONV__) \
3010 ) \
3011 ) \
3012 ) \
3013 ) \
3014 : \
3015 (__EXT_TRIG_INJECTCONV__) \
3016 )
3017 #endif /* STM32F303xC || STM32F358xx */
3018
3019 #if defined(STM32F303xE) || defined(STM32F398xx)
3020 /* Note: Macro including external triggers specific to device STM303xE: using */
3021 /* Timer20 with ADC trigger input remap. */
3022 #define __HAL_ADC_JSQR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
3023 (( ((((__HANDLE__)->Instance) == ADC3) || (((__HANDLE__)->Instance) == ADC4)) \
3024 )? \
3025 ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO \
3026 )? \
3027 (ADC3_4_EXTERNALTRIGINJEC_T2_TRGO) \
3028 : \
3029 ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO \
3030 )? \
3031 (ADC3_4_EXTERNALTRIGINJEC_T4_TRGO) \
3032 : \
3033 ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4 \
3034 )? \
3035 (ADC3_4_EXTERNALTRIGINJEC_T8_CC4) \
3036 : \
3037 ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T4_CC3 \
3038 )? \
3039 (ADC3_4_EXTERNALTRIGINJEC_T4_CC3) \
3040 : \
3041 ( ( (__EXT_TRIG_INJECTCONV__) \
3042 == ADC_EXTERNALTRIGINJECCONV_T20_TRGO \
3043 )? \
3044 (ADC3_4_EXTERNALTRIGINJEC_T20_TRGO) \
3045 : \
3046 ( ( (__EXT_TRIG_INJECTCONV__) \
3047 == ADC_EXTERNALTRIGINJECCONV_T20_TRGO2 \
3048 )? \
3049 (ADC3_4_EXTERNALTRIGINJEC_T1_CC3) \
3050 : \
3051 (__EXT_TRIG_INJECTCONV__) \
3052 ) \
3053 ) \
3054 ) \
3055 ) \
3056 ) \
3057 ) \
3058 : \
3059 (__EXT_TRIG_INJECTCONV__ & (~ADC_EXTERNALTRIGCONV_T20_MASK)) \
3060 )
3061 #endif /* STM32F303xE || STM32F398xx */
3062 #else
3063 #define __HAL_ADC_JSQR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
3064 (__EXT_TRIG_INJECTCONV__)
3065 #endif /* STM32F303xE || STM32F398xx || */
3066 /* STM32F303xC || STM32F358xx */
3067
3068 /**
3069 * @brief Configure the channel number into offset OFRx register
3070 * @param _CHANNEL_: ADC Channel
3071 * @retval None
3072 */
3073 #define __HAL_ADC_OFR_CHANNEL(_CHANNEL_) ((_CHANNEL_) << 26)
3074
3075 /**
3076 * @brief Configure the channel number into differential mode selection register
3077 * @param _CHANNEL_: ADC Channel
3078 * @retval None
3079 */
3080 #define __HAL_ADC_DIFSEL_CHANNEL(_CHANNEL_) (1U << (_CHANNEL_))
3081
3082 /**
3083 * @brief Calibration factor in differential mode to be set into calibration register
3084 * @param _Calibration_Factor_: Calibration factor value
3085 * @retval None
3086 */
3087 #define __HAL_ADC_CALFACT_DIFF_SET(_Calibration_Factor_) ((_Calibration_Factor_) << 16)
3088
3089 /**
3090 * @brief Calibration factor in differential mode to be retrieved from calibration register
3091 * @param _Calibration_Factor_: Calibration factor value
3092 * @retval None
3093 */
3094 #define __HAL_ADC_CALFACT_DIFF_GET(_Calibration_Factor_) ((_Calibration_Factor_) >> 16)
3095
3096 /**
3097 * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
3098 * @param _Threshold_: Threshold value
3099 * @retval None
3100 */
3101 #define __HAL_ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16)
3102
3103 /**
3104 * @brief Enable the ADC DMA continuous request for ADC multimode.
3105 * @param _DMAContReq_MODE_: DMA continuous request mode.
3106 * @retval None
3107 */
3108 #define __HAL_ADC_CCR_MULTI_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 13)
3109
3110
3111 /**
3112 * @brief Enable the ADC peripheral
3113 * @param __HANDLE__: ADC handle
3114 * @retval None
3115 */
3116 #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN)
3117
3118 /**
3119 * @brief Verification of hardware constraints before ADC can be enabled
3120 * @param __HANDLE__: ADC handle
3121 * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
3122 */
3123 #define __HAL_ADC_ENABLING_CONDITIONS(__HANDLE__) \
3124 (( ( ((__HANDLE__)->Instance->CR) & \
3125 (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | \
3126 ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN ) \
3127 ) == RESET \
3128 ) ? SET : RESET)
3129
3130 /**
3131 * @brief Disable the ADC peripheral
3132 * @param __HANDLE__: ADC handle
3133 * @retval None
3134 */
3135 #define __HAL_ADC_DISABLE(__HANDLE__) \
3136 do{ \
3137 (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; \
3138 __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \
3139 } while(0)
3140
3141 /**
3142 * @brief Verification of hardware constraints before ADC can be disabled
3143 * @param __HANDLE__: ADC handle
3144 * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
3145 */
3146 #define __HAL_ADC_DISABLING_CONDITIONS(__HANDLE__) \
3147 (( ( ((__HANDLE__)->Instance->CR) & \
3148 (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \
3149 ) ? SET : RESET)
3150
3151
3152 /**
3153 * @brief Shift the offset in function of the selected ADC resolution.
3154 * Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0
3155 * If resolution 12 bits, no shift.
3156 * If resolution 10 bits, shift of 2 ranks on the left.
3157 * If resolution 8 bits, shift of 4 ranks on the left.
3158 * If resolution 6 bits, shift of 6 ranks on the left.
3159 * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
3160 * @param __HANDLE__: ADC handle
3161 * @param _Offset_: Value to be shifted
3162 * @retval None
3163 */
3164 #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, _Offset_) \
3165 ((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))
3166
3167 /**
3168 * @brief Shift the AWD1 threshold in function of the selected ADC resolution.
3169 * Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
3170 * If resolution 12 bits, no shift.
3171 * If resolution 10 bits, shift of 2 ranks on the left.
3172 * If resolution 8 bits, shift of 4 ranks on the left.
3173 * If resolution 6 bits, shift of 6 ranks on the left.
3174 * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
3175 * @param __HANDLE__: ADC handle
3176 * @param _Threshold_: Value to be shifted
3177 * @retval None
3178 */
3179 #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
3180 ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))
3181
3182 /**
3183 * @brief Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution.
3184 * Thresholds have to be left-aligned on bit 7.
3185 * If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded)
3186 * If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded)
3187 * If resolution 8 bits, no shift.
3188 * If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0)
3189 * @param __HANDLE__: ADC handle
3190 * @param _Threshold_: Value to be shifted
3191 * @retval None
3192 */
3193 #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
3194 ( ((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ? \
3195 ((_Threshold_) >> (4- ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))) : \
3196 (_Threshold_) << 2 )
3197
3198 /**
3199 * @brief Defines if the selected ADC is within ADC common register ADC1_2 or ADC3_4
3200 * if available (ADC2, ADC3, ADC4 availability depends on STM32 product)
3201 * @param __HANDLE__: ADC handle
3202 * @retval Common control register ADC1_2 or ADC3_4
3203 */
3204 #if defined(STM32F303xE) || defined(STM32F398xx) || \
3205 defined(STM32F303xC) || defined(STM32F358xx)
3206 #define __HAL_ADC_COMMON_REGISTER(__HANDLE__) \
3207 ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
3208 )? (ADC1_2_COMMON) : (ADC3_4_COMMON) \
3209 )
3210 #endif /* STM32F303xE || STM32F398xx || */
3211 /* STM32F303xC || STM32F358xx */
3212
3213 #if defined(STM32F302xE) || \
3214 defined(STM32F302xC) || \
3215 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
3216 #define __HAL_ADC_COMMON_REGISTER(__HANDLE__) \
3217 (ADC1_2_COMMON)
3218 #endif /* STM32F302xE || */
3219 /* STM32F302xC || */
3220 /* STM32F303x8 || STM32F328xx || STM32F334x8 */
3221
3222 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
3223 #define __HAL_ADC_COMMON_REGISTER(__HANDLE__) \
3224 (ADC1_COMMON)
3225 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
3226
3227 /**
3228 * @brief Selection of ADC common register CCR bits MULTI[4:0]corresponding to the selected ADC (applicable for devices with several ADCs)
3229 * @param __HANDLE__: ADC handle
3230 * @retval None
3231 */
3232 #if defined(STM32F303xE) || defined(STM32F398xx) || \
3233 defined(STM32F303xC) || defined(STM32F358xx)
3234 #define __HAL_ADC_COMMON_CCR_MULTI(__HANDLE__) \
3235 ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \
3236 )? \
3237 (ADC1_2_COMMON->CCR & ADC12_CCR_MULTI) \
3238 : \
3239 (ADC3_4_COMMON->CCR & ADC34_CCR_MULTI) \
3240 )
3241 #endif /* STM32F303xE || STM32F398xx || */
3242 /* STM32F303xC || STM32F358xx */
3243
3244 #if defined(STM32F302xE) || \
3245 defined(STM32F302xC) || \
3246 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
3247 #define __HAL_ADC_COMMON_CCR_MULTI(__HANDLE__) \
3248 (ADC1_2_COMMON->CCR & ADC12_CCR_MULTI)
3249 #endif /* STM32F302xE || */
3250 /* STM32F302xC || */
3251 /* STM32F303x8 || STM32F328xx || STM32F334x8 */
3252
3253 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
3254 #define __HAL_ADC_COMMON_CCR_MULTI(__HANDLE__) \
3255 (RESET)
3256 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
3257
3258 /**
3259 * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode, or multimode with handle of ADC master (applicable for devices with several ADCs)
3260 * @param __HANDLE__: ADC handle
3261 * @retval None
3262 */
3263 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
3264 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
3265 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
3266 #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
3267 ((__HAL_ADC_COMMON_CCR_MULTI(__HANDLE__) == RESET) || (IS_ADC_MULTIMODE_MASTER_INSTANCE((__HANDLE__)->Instance)))
3268 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
3269 /* STM32F302xC || STM32F303xC || STM32F358xx || */
3270 /* STM32F303x8 || STM32F334x8 || STM32F328xx */
3271
3272 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
3273 #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
3274 (!RESET)
3275 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
3276
3277 /**
3278 * @brief Set handle of the other ADC sharing the same common register ADC1_2 or ADC3_4
3279 * if available (ADC2, ADC3, ADC4 availability depends on STM32 product)
3280 * @param __HANDLE__: ADC handle
3281 * @param __HANDLE_OTHER_ADC__: other ADC handle
3282 * @retval None
3283 */
3284 #if defined(STM32F303xE) || defined(STM32F398xx) || \
3285 defined(STM32F303xC) || defined(STM32F358xx)
3286 #define __HAL_ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \
3287 ( ( ((__HANDLE__)->Instance == ADC1) \
3288 )? \
3289 ((__HANDLE_OTHER_ADC__)->Instance = ADC2) \
3290 : \
3291 ( ( ((__HANDLE__)->Instance == ADC2) \
3292 )? \
3293 ((__HANDLE_OTHER_ADC__)->Instance = ADC1) \
3294 : \
3295 ( ( ((__HANDLE__)->Instance == ADC3) \
3296 )? \
3297 ((__HANDLE_OTHER_ADC__)->Instance = ADC4) \
3298 : \
3299 ( ( ((__HANDLE__)->Instance == ADC4) \
3300 )? \
3301 ((__HANDLE_OTHER_ADC__)->Instance = ADC3) \
3302 : \
3303 ((__HANDLE_OTHER_ADC__)->Instance = HAL_NULL) \
3304 ) \
3305 ) \
3306 ) \
3307 )
3308 #endif /* STM32F303xE || STM32F398xx || */
3309 /* STM32F303xC || STM32F358xx */
3310
3311 #if defined(STM32F302xE) || \
3312 defined(STM32F302xC) || \
3313 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
3314 #define __HAL_ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \
3315 ( ( ((__HANDLE__)->Instance == ADC1) \
3316 )? \
3317 ((__HANDLE_OTHER_ADC__)->Instance = ADC2) \
3318 : \
3319 ((__HANDLE_OTHER_ADC__)->Instance = ADC1) \
3320 )
3321 #endif /* STM32F302xE || */
3322 /* STM32F302xC || */
3323 /* STM32F303x8 || STM32F328xx || STM32F334x8 */
3324
3325 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
3326 #define __HAL_ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \
3327 ((__HANDLE_OTHER_ADC__)->Instance = HAL_NULL)
3328 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
3329
3330 /**
3331 * @brief Set handle of the ADC slave associated to the ADC master
3332 * if available (ADC2, ADC3, ADC4 availability depends on STM32 product)
3333 * @param __HANDLE_MASTER__: ADC master handle
3334 * @param __HANDLE_SLAVE__: ADC slave handle
3335 * @retval None
3336 */
3337 #if defined(STM32F303xE) || defined(STM32F398xx) || \
3338 defined(STM32F303xC) || defined(STM32F358xx)
3339 #define __HAL_ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
3340 ( ( ((__HANDLE_MASTER__)->Instance == ADC1) \
3341 )? \
3342 ((__HANDLE_SLAVE__)->Instance = ADC2) \
3343 : \
3344 ( ( ((__HANDLE_MASTER__)->Instance == ADC3) \
3345 )? \
3346 ((__HANDLE_SLAVE__)->Instance = ADC4) \
3347 : \
3348 ((__HANDLE_SLAVE__)->Instance = HAL_NULL) \
3349 ) \
3350 )
3351 #endif /* STM32F303xE || STM32F398xx || */
3352 /* STM32F303xC || STM32F358xx */
3353
3354 #if defined(STM32F302xE) || \
3355 defined(STM32F302xC) || \
3356 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
3357 #define __HAL_ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
3358 ( ( ((__HANDLE_MASTER__)->Instance == ADC1) \
3359 )? \
3360 ((__HANDLE_SLAVE__)->Instance = ADC2) \
3361 : \
3362 ( HAL_NULL ) \
3363 )
3364 #endif /* STM32F302xE || */
3365 /* STM32F302xC || */
3366 /* STM32F303x8 || STM32F328xx || STM32F334x8 */
3367
3368 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
3369 /* STM32F302xC || STM32F303xC || STM32F358xx || */
3370 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
3371 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
3372
3373
3374 #if defined(STM32F373xC) || defined(STM32F378xx)
3375 /**
3376 * @brief Set ADC number of conversions into regular channel sequence length.
3377 * @param _NbrOfConversion_: Regular channel sequence length
3378 * @retval None
3379 */
3380 #define __HAL_ADC_SQR1_L(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20)
3381
3382 /**
3383 * @brief Set the ADC's sample time for channel numbers between 10 and 18.
3384 * @param _SAMPLETIME_: Sample time parameter.
3385 * @param _CHANNELNB_: Channel number.
3386 * @retval None
3387 */
3388 #define __HAL_ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10)))
3389
3390 /**
3391 * @brief Set the ADC's sample time for channel numbers between 0 and 9.
3392 * @param _SAMPLETIME_: Sample time parameter.
3393 * @param _CHANNELNB_: Channel number.
3394 * @retval None
3395 */
3396 #define __HAL_ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (_CHANNELNB_)))
3397
3398 /**
3399 * @brief Set the selected regular channel rank for rank between 1 and 6.
3400 * @param _CHANNELNB_: Channel number.
3401 * @param _RANKNB_: Rank number.
3402 * @retval None
3403 */
3404 #define __HAL_ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 1)))
3405
3406 /**
3407 * @brief Set the selected regular channel rank for rank between 7 and 12.
3408 * @param _CHANNELNB_: Channel number.
3409 * @param _RANKNB_: Rank number.
3410 * @retval None
3411 */
3412 #define __HAL_ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 7)))
3413
3414 /**
3415 * @brief Set the selected regular channel rank for rank between 13 and 16.
3416 * @param _CHANNELNB_: Channel number.
3417 * @param _RANKNB_: Rank number.
3418 * @retval None
3419 */
3420 #define __HAL_ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 13)))
3421
3422 /**
3423 * @brief Set the injected sequence length.
3424 * @param _JSQR_JL_: Sequence length.
3425 * @retval None
3426 */
3427 #define __HAL_ADC_JSQR_JL(_JSQR_JL_) (((_JSQR_JL_) -1) << 20)
3428
3429 /**
3430 * @brief Set the selected injected Channel rank (channels sequence starting from 4-JL)
3431 * @param _CHANNELNB_: Channel number.
3432 * @param _RANKNB_: Rank number.
3433 * @param _JSQR_JL_: Sequence length.
3434 * @retval None
3435 */
3436 #define __HAL_ADC_JSQR_RK(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \
3437 ((_CHANNELNB_) << (5 * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
3438
3439 /**
3440 * @brief Enable ADC continuous conversion mode.
3441 * @param _CONTINUOUS_MODE_: Continuous mode.
3442 * @retval None
3443 */
3444 #define __HAL_ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1)
3445
3446 /**
3447 * @brief Configures the number of discontinuous conversions for the regular group channels.
3448 * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
3449 * @retval None
3450 */
3451 #define __HAL_ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1) << 13)
3452
3453 /**
3454 * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
3455 * @param _SCAN_MODE_: Scan conversion mode.
3456 * @retval None
3457 */
3458 #define __HAL_ADC_CR1_SCAN(_SCAN_MODE_) \
3459 ( ( (_SCAN_MODE_) == (ADC_SCAN_ENABLE) \
3460 )? (ADC_CR1_SCAN) : (0x00000000) \
3461 )
3462
3463 /**
3464 * @brief Calibration factor in differential mode to be set into calibration register
3465 * @param _Calibration_Factor_: Calibration factor value
3466 * @retval None
3467 */
3468 #define __HAL_ADC_CALFACT_DIFF_SET(_Calibration_Factor_) ((_Calibration_Factor_) << 16)
3469
3470 /**
3471 * @brief Calibration factor in differential mode to be retrieved from calibration register
3472 * @param _Calibration_Factor_: Calibration factor value
3473 * @retval None
3474 */
3475 #define __HAL_ADC_CALFACT_DIFF_GET(_Calibration_Factor_) ((_Calibration_Factor_) >> 16)
3476
3477
3478 /**
3479 * @brief Get the maximum ADC conversion cycles on all channels.
3480 * Returns the selected sampling time + conversion time (12.5 ADC clock cycles)
3481 * Approximation of sampling time within 4 ranges, returns the higher value:
3482 * below 7.5 cycles {1.5 cycle; 7.5 cycles},
3483 * between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles}
3484 * between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles}
3485 * equal to 239.5 cycles
3486 * Unit: ADC clock cycles
3487 * @param __HANDLE__: ADC handle
3488 * @retval ADC conversion cycles on all channels
3489 */
3490 #define __HAL_ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \
3491 (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \
3492 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \
3493 \
3494 (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \
3495 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ? \
3496 ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5) \
3497 : \
3498 ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \
3499 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) || \
3500 ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && \
3501 (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ? \
3502 ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \
3503 )
3504
3505 /**
3506 * @brief Get the total ADC clock prescaler (APB2 prescaler x ADC prescaler)
3507 * from system clock configuration register.
3508 * Approximation within 3 ranges, returns the higher value:
3509 * total prescaler minimum: 2 (ADC presc 2, APB2 presc 0)
3510 * total prescaler 32 (ADC presc 0 and APB2 presc all, or
3511 * ADC presc {4, 6, 8} and APB2 presc {0, 2, 4})
3512 * total prescaler maximum: 128 (ADC presc {4, 6, 8} and APB2 presc {8, 16})
3513 * Unit: none (prescaler factor)
3514 * @param __HANDLE__: ADC handle
3515 * @retval ADC and APB2 prescaler factor
3516 */
3517 #define __HAL_ADC_CLOCK_PRECSALER_RANGE(__HANDLE__) \
3518 (( (RCC->CFGR & (RCC_CFGR_ADCPRE_1 | RCC_CFGR_ADCPRE_0)) == RESET) ? \
3519 (( (RCC->CFGR & RCC_CFGR_PPRE2_2) == RESET) ? 2 : 32 ) \
3520 : \
3521 (( (RCC->CFGR & RCC_CFGR_PPRE2_1) == RESET) ? 32 : 128 ) \
3522 )
3523
3524 /**
3525 * @brief Get the ADC clock prescaler from system clock configuration register.
3526 * @retval None
3527 */
3528 #define __HAL_ADC_GET_CLOCK_PRESCALER() (((RCC->CFGR & RCC_CFGR_ADCPRE) >> 14) +1)
3529
3530 /**
3531 * @brief Enable the ADC peripheral (if not already enable to not trig a conversion)
3532 * @param __HANDLE__: ADC handle
3533 * @retval None
3534 */
3535 #define __HAL_ADC_ENABLE(__HANDLE__) \
3536 (__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON
3537
3538 /**
3539 * @brief Disable the ADC peripheral
3540 * @param __HANDLE__: ADC handle
3541 * @retval None
3542 */
3543 #define __HAL_ADC_DISABLE(__HANDLE__) \
3544 (__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON
3545
3546 #endif /* STM32F373xC || STM32F378xx */
3547 /**
3548 * @}
3549 */
3550
3551
3552 /* Exported functions --------------------------------------------------------*/
3553 /** @addtogroup ADCEx_Exported_Functions ADC Extended Exported Functions
3554 * @{
3555 */
3556
3557 /* Initialization/de-initialization functions *********************************/
3558
3559 /** @addtogroup ADCEx_Exported_Functions_Group2 Extended Input and Output operation functions
3560 * @brief Extended IO operation functions
3561 * @{
3562 */
3563 /* I/O operation functions ****************************************************/
3564
3565 /* ADC calibration */
3566 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
3567 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
3568 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
3569 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
3570 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(struct __ADC_HandleTypeDef* hadc, uint32_t SingleDiff);
3571 uint32_t HAL_ADCEx_Calibration_GetValue(struct __ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
3572 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(struct __ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor);
3573 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
3574 /* STM32F302xC || STM32F303xC || STM32F358xx || */
3575 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
3576 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
3577
3578 #if defined(STM32F373xC) || defined(STM32F378xx)
3579 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(struct __ADC_HandleTypeDef* hadc);
3580 #endif /* STM32F373xC || STM32F378xx */
3581
3582 /* Blocking mode: Polling */
3583 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(struct __ADC_HandleTypeDef* hadc);
3584 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(struct __ADC_HandleTypeDef* hadc);
3585 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(struct __ADC_HandleTypeDef* hadc, uint32_t Timeout);
3586
3587 /* Non-blocking mode: Interruption */
3588 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(struct __ADC_HandleTypeDef* hadc);
3589 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(struct __ADC_HandleTypeDef* hadc);
3590
3591 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
3592 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
3593 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
3594 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
3595 /* ADC multimode */
3596 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(struct __ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
3597 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(struct __ADC_HandleTypeDef *hadc);
3598 uint32_t HAL_ADCEx_MultiModeGetValue(struct __ADC_HandleTypeDef *hadc);
3599 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
3600 /* STM32F302xC || STM32F303xC || STM32F358xx || */
3601 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
3602 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
3603
3604 /* ADC retrieve conversion value intended to be used with polling or interruption */
3605 uint32_t HAL_ADCEx_InjectedGetValue(struct __ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
3606
3607 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
3608 void HAL_ADCEx_InjectedConvCpltCallback(struct __ADC_HandleTypeDef* hadc);
3609
3610 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
3611 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
3612 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
3613 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
3614 void HAL_ADCEx_InjectedQueueOverflowCallback(struct __ADC_HandleTypeDef* hadc);
3615 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
3616 /* STM32F302xC || STM32F303xC || STM32F358xx || */
3617 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
3618 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
3619 /**
3620 * @}
3621 */
3622
3623 /** @addtogroup ADCEx_Exported_Functions_Group3 Extended Peripheral Control functions
3624 * @brief Extended Peripheral Control functions
3625 * @{
3626 */
3627 /* Peripheral Control functions ***********************************************/
3628 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(struct __ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
3629
3630 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
3631 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
3632 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
3633 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
3634 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(struct __ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
3635 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
3636 /* STM32F302xC || STM32F303xC || STM32F358xx || */
3637 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
3638 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
3639 /**
3640 * @}
3641 */
3642
3643 /**
3644 * @}
3645 */
3646
3647 /**
3648 * @}
3649 */
3650
3651 /**
3652 * @}
3653 */
3654
3655 #ifdef __cplusplus
3656 }
3657 #endif
3658
3659 #endif /*__STM32F3xx_ADC_H */
3660
3661
3662 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
custom keymap for my minivan; forked from http://github.com/evangs/tmk_keyboard
Imprint / Impressum