tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_cec.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f3xx_hal_cec.h
   4   * @author  MCD Application Team
   5   * @version V1.1.0
   6   * @date    12-Sept-2014
   7   * @brief   Header file of CEC HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32F3xx_HAL_CEC_H
  40 #define __STM32F3xx_HAL_CEC_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 #if defined(STM32F373xC) || defined(STM32F378xx)
  47 /* Includes ------------------------------------------------------------------*/
  48 #include "stm32f3xx_hal_def.h"
  49
  50 /** @addtogroup STM32F3xx_HAL_Driver
  51   * @{
  52   */
  53
  54 /** @addtogroup CEC
  55   * @{
  56   */
  57
  58 /* Exported types ------------------------------------------------------------*/
  59 /** @defgroup CEC_Exported_Types CEC Exported Types
  60   * @{
  61   */
  62 /**
  63   * @brief CEC Init Structure definition
  64   */
  65 typedef struct
  66 {
  67   uint32_t SignalFreeTime;               /*!< Set SFT field, specifies the Signal Free Time.
  68                                               It can be one of @ref CEC_Signal_Free_Time
  69                                               and belongs to the set {0,...,7} where
  70                                               0x0 is the default configuration
  71                                               else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
  72
  73   uint32_t Tolerance;                    /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
  74                                               it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
  75                                               or CEC_EXTENDED_TOLERANCE */
  76
  77   uint32_t BRERxStop;                    /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
  78                                               CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
  79                                               CEC_RX_STOP_ON_BRE:    reception is stopped. */
  80
  81   uint32_t BREErrorBitGen;               /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
  82                                               CEC line upon Bit Rising Error detection.
  83                                               CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
  84                                               CEC_BRE_ERRORBIT_GENERATION:    error-bit generation if BRESTP is set. */
  85
  86   uint32_t LBPEErrorBitGen;              /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
  87                                               CEC line upon Long Bit Period Error detection.
  88                                               CEC_LBPE_ERRORBIT_NO_GENERATION:  no error-bit generation.
  89                                               CEC_LBPE_ERRORBIT_GENERATION:     error-bit generation. */
  90
  91   uint32_t BroadcastMsgNoErrorBitGen;    /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
  92                                               upon an error detected on a broadcast message.
  93
  94                                               It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
  95
  96                                               1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
  97                                                  a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
  98                                                     and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
  99                                                  b) LBPE detection: error-bit generation on the CEC line
 100                                                     if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
 101
 102                                               2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
 103                                                  no error-bit generation in case neither a) nor b) are satisfied. Additionally,
 104                                                  there is no error-bit generation in case of Short Bit Period Error detection in
 105                                                  a broadcast message while LSTN bit is set. */
 106
 107   uint32_t SignalFreeTimeOption;         /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
 108                                               CEC_SFT_START_ON_TXSOM SFT:    timer starts when TXSOM is set by software.
 109                                               CEC_SFT_START_ON_TX_RX_END:  SFT timer starts automatically at the end of message transmission/reception. */
 110
 111   uint32_t OwnAddress;                   /*!< Set OAR field, specifies CEC device address within a 15-bit long field */
 112
 113   uint32_t ListenMode;                   /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
 114
 115                                               CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
 116                                                 own address (OAR). Messages addressed to different destination are ignored.
 117                                                 Broadcast messages are always received.
 118
 119                                               CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
 120                                                 address (OAR) with positive acknowledge. Messages addressed to different destination
 121                                                 are received, but without interfering with the CEC bus: no acknowledge sent.  */
 122
 123   uint8_t  InitiatorAddress;             /* Initiator address (source logical address, sent in each header) */
 124
 125 }CEC_InitTypeDef;
 126
 127 /**
 128   * @brief HAL CEC State structures definition
 129   */
 130 typedef enum
 131 {
 132   HAL_CEC_STATE_RESET             = 0x00,    /*!< Peripheral Reset state                              */
 133   HAL_CEC_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use            */
 134   HAL_CEC_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing                      */
 135   HAL_CEC_STATE_BUSY_TX           = 0x03,    /*!< Data Transmission process is ongoing                */
 136   HAL_CEC_STATE_BUSY_RX           = 0x04,    /*!< Data Reception process is ongoing                   */
 137   HAL_CEC_STATE_STANDBY_RX        = 0x05,    /*!< IP ready to receive, doesn't prevent IP to transmit */
 138   HAL_CEC_STATE_TIMEOUT           = 0x06,    /*!< Timeout state                                       */
 139   HAL_CEC_STATE_ERROR             = 0x07     /*!< State Error                                         */
 140 }HAL_CEC_StateTypeDef;
 141
 142 /**
 143   * @brief  HAL Error structures definition
 144   */
 145 typedef enum
 146 {
 147   HAL_CEC_ERROR_NONE   = (uint32_t) 0x0,         /*!< no error                      */
 148   HAL_CEC_ERROR_RXOVR  = CEC_ISR_RXOVR,          /*!< CEC Rx-Overrun                */
 149   HAL_CEC_ERROR_BRE    = CEC_ISR_BRE,            /*!< CEC Rx Bit Rising Error       */
 150   HAL_CEC_ERROR_SBPE   = CEC_ISR_SBPE,           /*!< CEC Rx Short Bit period Error */
 151   HAL_CEC_ERROR_LBPE   = CEC_ISR_LBPE,           /*!< CEC Rx Long Bit period Error  */
 152   HAL_CEC_ERROR_RXACKE = CEC_ISR_RXACKE,         /*!< CEC Rx Missing Acknowledge    */
 153   HAL_CEC_ERROR_ARBLST = CEC_ISR_ARBLST,         /*!< CEC Arbitration Lost          */
 154   HAL_CEC_ERROR_TXUDR  = CEC_ISR_TXUDR,          /*!< CEC Tx-Buffer Underrun        */
 155   HAL_CEC_ERROR_TXERR  = CEC_ISR_TXERR,          /*!< CEC Tx-Error                  */
 156   HAL_CEC_ERROR_TXACKE = CEC_ISR_TXACKE          /*!< CEC Tx Missing Acknowledge    */
 157 }
 158 HAL_CEC_ErrorTypeDef;
 159
 160 /**
 161   * @brief  CEC handle Structure definition
 162   */
 163 typedef struct
 164 {
 165   CEC_TypeDef             *Instance;      /* CEC registers base address */
 166
 167   CEC_InitTypeDef         Init;           /* CEC communication parameters */
 168
 169   uint8_t                 *pTxBuffPtr;    /* Pointer to CEC Tx transfer Buffer */
 170
 171   uint16_t                TxXferCount;    /* CEC Tx Transfer Counter */
 172
 173   uint8_t                 *pRxBuffPtr;    /* Pointer to CEC Rx transfer Buffer */
 174
 175   uint16_t                RxXferSize;     /* CEC Rx Transfer size, 0: header received only */
 176
 177   uint32_t                ErrorCode;      /* For errors handling purposes, copy of ISR register
 178                                             in case error is reported */
 179
 180   HAL_LockTypeDef         Lock;           /* Locking object */
 181
 182   HAL_CEC_StateTypeDef    State;          /* CEC communication state */
 183
 184 }CEC_HandleTypeDef;
 185
 186 /**
 187  * @}
 188  */
 189
 190 /* Exported constants --------------------------------------------------------*/
 191 /** @defgroup CEC_Exported_Constants CEC Exported Constants
 192   * @{
 193   */
 194
 195 /** @defgroup CEC_Signal_Free_Time  Signal Free Time setting parameter
 196   * @{
 197   */
 198 #define CEC_DEFAULT_SFT                    ((uint32_t)0x00000000)
 199 #define CEC_0_5_BITPERIOD_SFT              ((uint32_t)0x00000001)
 200 #define CEC_1_5_BITPERIOD_SFT              ((uint32_t)0x00000002)
 201 #define CEC_2_5_BITPERIOD_SFT              ((uint32_t)0x00000003)
 202 #define CEC_3_5_BITPERIOD_SFT              ((uint32_t)0x00000004)
 203 #define CEC_4_5_BITPERIOD_SFT              ((uint32_t)0x00000005)
 204 #define CEC_5_5_BITPERIOD_SFT              ((uint32_t)0x00000006)
 205 #define CEC_6_5_BITPERIOD_SFT              ((uint32_t)0x00000007)
 206 #define IS_CEC_SIGNALFREETIME(SFT)         ((SFT) <= CEC_CFGR_SFT)
 207 /**
 208   * @}
 209   */
 210
 211 /** @defgroup CEC_Tolerance   Receiver Tolerance
 212   * @{
 213   */
 214 #define CEC_STANDARD_TOLERANCE             ((uint32_t)0x00000000)
 215 #define CEC_EXTENDED_TOLERANCE             ((uint32_t)CEC_CFGR_RXTOL)
 216 #define IS_CEC_TOLERANCE(RXTOL)            (((RXTOL) == CEC_STANDARD_TOLERANCE) || \
 217                                             ((RXTOL) == CEC_EXTENDED_TOLERANCE))
 218 /**
 219   * @}
 220   */
 221
 222 /** @defgroup CEC_BRERxStop   Reception Stop on Error
 223   * @{
 224   */
 225 #define CEC_NO_RX_STOP_ON_BRE             ((uint32_t)0x00000000)
 226 #define CEC_RX_STOP_ON_BRE                ((uint32_t)CEC_CFGR_BRESTP)
 227 #define IS_CEC_BRERXSTOP(BRERXSTOP)       (((BRERXSTOP) == CEC_NO_RX_STOP_ON_BRE) || \
 228                                            ((BRERXSTOP) == CEC_RX_STOP_ON_BRE))
 229 /**
 230   * @}
 231   */
 232
 233 /** @defgroup CEC_BREErrorBitGen   Error Bit Generation if Bit Rise Error reported
 234   * @{
 235   */
 236 #define CEC_BRE_ERRORBIT_NO_GENERATION     ((uint32_t)0x00000000)
 237 #define CEC_BRE_ERRORBIT_GENERATION        ((uint32_t)CEC_CFGR_BREGEN)
 238 #define IS_CEC_BREERRORBITGEN(ERRORBITGEN) (((ERRORBITGEN) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
 239                                             ((ERRORBITGEN) == CEC_BRE_ERRORBIT_GENERATION))
 240 /**
 241   * @}
 242   */
 243
 244 /** @defgroup CEC_LBPEErrorBitGen   Error Bit Generation if Long Bit Period Error reported
 245   * @{
 246   */
 247 #define CEC_LBPE_ERRORBIT_NO_GENERATION     ((uint32_t)0x00000000)
 248 #define CEC_LBPE_ERRORBIT_GENERATION        ((uint32_t)CEC_CFGR_LBPEGEN)
 249 #define IS_CEC_LBPEERRORBITGEN(ERRORBITGEN) (((ERRORBITGEN) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
 250                                              ((ERRORBITGEN) == CEC_LBPE_ERRORBIT_GENERATION))
 251 /**
 252   * @}
 253   */
 254
 255 /** @defgroup CEC_BroadCastMsgErrorBitGen   Error Bit Generation on Broadcast message
 256   * @{
 257   */
 258 #define CEC_BROADCASTERROR_ERRORBIT_GENERATION     ((uint32_t)0x00000000)
 259 #define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION  ((uint32_t)CEC_CFGR_BRDNOGEN)
 260 #define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(ERRORBITGEN) (((ERRORBITGEN) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
 261                                                                    ((ERRORBITGEN) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
 262 /**
 263   * @}
 264   */
 265
 266 /** @defgroup CEC_SFT_Option         Signal Free Time start option
 267   * @{
 268   */
 269 #define CEC_SFT_START_ON_TXSOM           ((uint32_t)0x00000000)
 270 #define CEC_SFT_START_ON_TX_RX_END       ((uint32_t)CEC_CFGR_SFTOPT)
 271 #define IS_CEC_SFTOP(SFTOP)              (((SFTOP) == CEC_SFT_START_ON_TXSOM) || \
 272                                           ((SFTOP) == CEC_SFT_START_ON_TX_RX_END))
 273 /**
 274   * @}
 275   */
 276
 277 /** @defgroup CEC_Listening_Mode        Listening mode option
 278   * @{
 279   */
 280 #define CEC_REDUCED_LISTENING_MODE          ((uint32_t)0x00000000)
 281 #define CEC_FULL_LISTENING_MODE             ((uint32_t)CEC_CFGR_LSTN)
 282 #define IS_CEC_LISTENING_MODE(MODE)         (((MODE) == CEC_REDUCED_LISTENING_MODE) || \
 283                                              ((MODE) == CEC_FULL_LISTENING_MODE))
 284 /**
 285   * @}
 286   */
 287
 288 /** @defgroup CEC_ALL_ERROR all RX or TX errors flags in CEC ISR register
 289   * @{
 290   */
 291 #define CEC_ISR_ALL_ERROR              ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
 292                                                   CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
 293 /**
 294   * @}
 295   */
 296
 297 /** @defgroup CEC_IER_ALL_RX all RX errors interrupts enabling flag
 298   * @{
 299   */
 300 #define CEC_IER_RX_ALL_ERR              ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
 301 /**
 302   * @}
 303   */
 304
 305 /** @defgroup CEC_IER_ALL_TX all TX errors interrupts enabling flag
 306   * @{
 307   */
 308 #define CEC_IER_TX_ALL_ERR              ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
 309 /**
 310   * @}
 311   */
 312
 313 /** @defgroup CEC_OAR_Position    Device Own Address position in CEC CFGR register
 314   * @{
 315   */
 316 #define CEC_CFGR_OAR_LSB_POS            ((uint32_t) 16)
 317 /**
 318   * @}
 319   */
 320
 321 /** @defgroup CEC_Initiator_Position    Initiator logical address position in message header
 322   * @{
 323   */
 324 #define CEC_INITIATOR_LSB_POS           ((uint32_t) 4)
 325 /**
 326   * @}
 327   */
 328
 329 /**
 330   * @}
 331   */
 332
 333 /* Exported macros -----------------------------------------------------------*/
 334 /** @defgroup CEC_Exported_Macros CEC Exported Macros
 335   * @{
 336   */
 337
 338 /** @brief  Reset CEC handle state
 339   * @param  __HANDLE__: CEC handle.
 340   * @retval None
 341   */
 342 #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CEC_STATE_RESET)
 343
 344 /** @brief  Checks whether or not the specified CEC interrupt flag is set.
 345   * @param  __HANDLE__: specifies the CEC Handle.
 346   * @param  __INTERRUPT__: specifies the interrupt to check.
 347   *        This parameter can be one of the following values:
 348   *            @arg CEC_ISR_RXBR      : Rx-Byte Received
 349   *            @arg CEC_ISR_RXEND     : End of Reception
 350   *            @arg CEC_ISR_RXOVR     : Rx Overrun
 351   *            @arg CEC_ISR_BRE       : Rx Bit Rising Error
 352   *            @arg CEC_ISR_SBPE      : Rx Short Bit Period Error
 353   *            @arg CEC_ISR_LBPE      : Rx Long Bit Period Error
 354   *            @arg CEC_ISR_RXACKE    : Rx Missing Acknowledge
 355   *            @arg CEC_ISR_ARBLST    : Arbitration lost
 356   *            @arg CEC_ISR_TXBR      : Tx-Byte Request
 357   *            @arg CEC_ISR_TXEND     : End of Transmission
 358   *            @arg CEC_ISR_TXUDR     : Tx-buffer Underrun
 359   *            @arg CEC_ISR_TXERR     : Tx Error
 360   *            @arg CEC_ISR_TXACKE    : Tx Missing Acknowledge
 361   * @retval ITStatus
 362   */
 363 #define __HAL_CEC_GET_IT(__HANDLE__, __INTERRUPT__)        ((__HANDLE__)->Instance->ISR & (__INTERRUPT__))
 364
 365 /** @brief  Clears the interrupt or status flag when raised (write at 1)
 366   * @param  __HANDLE__: specifies the CEC Handle.
 367   * @param  __FLAG__: specifies the interrupt/status flag to clear.
 368   *        This parameter can be one of the following values:
 369   *            @arg CEC_ISR_RXBR      : Rx-Byte Received
 370   *            @arg CEC_ISR_RXEND     : End of Reception
 371   *            @arg CEC_ISR_RXOVR     : Rx Overrun
 372   *            @arg CEC_ISR_BRE       : Rx Bit Rising Error
 373   *            @arg CEC_ISR_SBPE      : Rx Short Bit Period Error
 374   *            @arg CEC_ISR_LBPE      : Rx Long Bit Period Error
 375   *            @arg CEC_ISR_RXACKE    : Rx Missing Acknowledge
 376   *            @arg CEC_ISR_ARBLST    : Arbitration lost
 377   *            @arg CEC_ISR_TXBR      : Tx-Byte Request
 378   *            @arg CEC_ISR_TXEND     : End of Transmission
 379   *            @arg CEC_ISR_TXUDR     : Tx-buffer Underrun
 380   *            @arg CEC_ISR_TXERR     : Tx Error
 381   *            @arg CEC_ISR_TXACKE    : Tx Missing Acknowledge
 382   * @retval none
 383   */
 384 #define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->ISR = (__FLAG__))
 385
 386 /** @brief  Enables the specified CEC interrupt.
 387   * @param  __HANDLE__: specifies the CEC Handle.
 388   * @param  __INTERRUPT__: specifies the CEC interrupt to enable.
 389   *          This parameter can be one of the following values:
 390   *            @arg CEC_IER_RXBRIE         : Rx-Byte Received IT Enable
 391   *            @arg CEC_IER_RXENDIE        : End Of Reception IT Enable
 392   *            @arg CEC_IER_RXOVRIE        : Rx-Overrun IT Enable
 393   *            @arg CEC_IER_BREIE          : Rx Bit Rising Error IT Enable
 394   *            @arg CEC_IER_SBPEIE         : Rx Short Bit period Error IT Enable
 395   *            @arg CEC_IER_LBPEIE         : Rx Long Bit period Error IT Enable
 396   *            @arg CEC_IER_RXACKEIE       : Rx Missing Acknowledge IT Enable
 397   *            @arg CEC_IER_ARBLSTIE       : Arbitration Lost IT Enable
 398   *            @arg CEC_IER_TXBRIE         : Tx Byte Request IT Enable
 399   *            @arg CEC_IER_TXENDIE        : End of Transmission IT Enable
 400   *            @arg CEC_IER_TXUDRIE        : Tx-Buffer Underrun IT Enable
 401   *            @arg CEC_IER_TXERRIE        : Tx-Error IT Enable
 402   *            @arg CEC_IER_TXACKEIE       : Tx Missing Acknowledge IT Enable
 403   * @retval none
 404   */
 405 #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
 406
 407 /** @brief  Disables the specified CEC interrupt.
 408   * @param  __HANDLE__: specifies the CEC Handle.
 409   * @param  __INTERRUPT__: specifies the CEC interrupt to disable.
 410   *          This parameter can be one of the following values:
 411   *            @arg CEC_IER_RXBRIE         : Rx-Byte Received IT Enable
 412   *            @arg CEC_IER_RXENDIE        : End Of Reception IT Enable
 413   *            @arg CEC_IER_RXOVRIE        : Rx-Overrun IT Enable
 414   *            @arg CEC_IER_BREIE          : Rx Bit Rising Error IT Enable
 415   *            @arg CEC_IER_SBPEIE         : Rx Short Bit period Error IT Enable
 416   *            @arg CEC_IER_LBPEIE         : Rx Long Bit period Error IT Enable
 417   *            @arg CEC_IER_RXACKEIE       : Rx Missing Acknowledge IT Enable
 418   *            @arg CEC_IER_ARBLSTIE       : Arbitration Lost IT Enable
 419   *            @arg CEC_IER_TXBRIE         : Tx Byte Request IT Enable
 420   *            @arg CEC_IER_TXENDIE        : End of Transmission IT Enable
 421   *            @arg CEC_IER_TXUDRIE        : Tx-Buffer Underrun IT Enable
 422   *            @arg CEC_IER_TXERRIE        : Tx-Error IT Enable
 423   *            @arg CEC_IER_TXACKEIE       : Tx Missing Acknowledge IT Enable
 424   * @retval none
 425   */
 426 #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
 427
 428 /** @brief  Checks whether or not the specified CEC interrupt is enabled.
 429   * @param  __HANDLE__: specifies the CEC Handle.
 430   * @param  __INTERRUPT__: specifies the CEC interrupt to check.
 431   *          This parameter can be one of the following values:
 432   *            @arg CEC_IER_RXBRIE         : Rx-Byte Received IT Enable
 433   *            @arg CEC_IER_RXENDIE        : End Of Reception IT Enable
 434   *            @arg CEC_IER_RXOVRIE        : Rx-Overrun IT Enable
 435   *            @arg CEC_IER_BREIE          : Rx Bit Rising Error IT Enable
 436   *            @arg CEC_IER_SBPEIE         : Rx Short Bit period Error IT Enable
 437   *            @arg CEC_IER_LBPEIE         : Rx Long Bit period Error IT Enable
 438   *            @arg CEC_IER_RXACKEIE       : Rx Missing Acknowledge IT Enable
 439   *            @arg CEC_IER_ARBLSTIE       : Arbitration Lost IT Enable
 440   *            @arg CEC_IER_TXBRIE         : Tx Byte Request IT Enable
 441   *            @arg CEC_IER_TXENDIE        : End of Transmission IT Enable
 442   *            @arg CEC_IER_TXUDRIE        : Tx-Buffer Underrun IT Enable
 443   *            @arg CEC_IER_TXERRIE        : Tx-Error IT Enable
 444   *            @arg CEC_IER_TXACKEIE       : Tx Missing Acknowledge IT Enable
 445   * @retval FlagStatus
 446   */
 447 #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
 448
 449 /** @brief  Enables the CEC device
 450   * @param  __HANDLE__: specifies the CEC Handle.
 451   * @retval none
 452   */
 453 #define __HAL_CEC_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR |=  CEC_CR_CECEN)
 454
 455 /** @brief  Disables the CEC device
 456   * @param  __HANDLE__: specifies the CEC Handle.
 457   * @retval none
 458   */
 459 #define __HAL_CEC_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR &=  ~CEC_CR_CECEN)
 460
 461 /** @brief  Set Transmission Start flag
 462   * @param  __HANDLE__: specifies the CEC Handle.
 463   * @retval none
 464   */
 465 #define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__)        ((__HANDLE__)->Instance->CR |=  CEC_CR_TXSOM)
 466
 467 /** @brief  Set Transmission End flag
 468   * @param  __HANDLE__: specifies the CEC Handle.
 469   * @retval none
 470   * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
 471   */
 472 #define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__)         ((__HANDLE__)->Instance->CR |=  CEC_CR_TXEOM)
 473
 474 /** @brief  Get Transmission Start flag
 475   * @param  __HANDLE__: specifies the CEC Handle.
 476   * @retval FlagStatus
 477   */
 478 #define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
 479
 480 /** @brief  Get Transmission End flag
 481   * @param  __HANDLE__: specifies the CEC Handle.
 482   * @retval FlagStatus
 483   */
 484 #define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__)   ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
 485
 486 /** @brief  Clear OAR register
 487   * @param  __HANDLE__: specifies the CEC Handle.
 488   * @retval none
 489   */
 490 #define __HAL_CEC_CLEAR_OAR(__HANDLE__)   CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
 491
 492 /** @brief  Set OAR register (without resetting previously set address in case of multi-address mode)
 493   *          To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
 494   * @param  __HANDLE__: specifies the CEC Handle.
 495   * @param  __ADDRESS__: Own Address value (CEC logical address is identified by bit position)
 496   * @retval none
 497   */
 498 #define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__)   SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
 499
 500 /** @brief Check CEC device Own Address Register (OAR) setting.
 501   *        OAR address is written in a 15-bit field within CEC_CFGR register.
 502   * @param  __ADDRESS__: CEC own address.
 503   * @retval Test result (TRUE or FALSE).
 504   */
 505 #define IS_CEC_OAR_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x07FFF)
 506
 507 /** @brief Check CEC initiator or destination logical address setting.
 508   *        Initiator and destination addresses are coded over 4 bits.
 509   * @param  __ADDRESS__: CEC initiator or logical address.
 510   * @retval Test result (TRUE or FALSE).
 511   */
 512 #define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
 513
 514 /** @brief Check CEC message size.
 515   *       The message size is the payload size: without counting the header,
 516   *       it varies from 0 byte (ping operation, one header only, no payload) to
 517   *       15 bytes (1 opcode and up to 14 operands following the header).
 518   * @param  __SIZE__: CEC message size.
 519   * @retval Test result (TRUE or FALSE).
 520   */
 521 #define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0xF)
 522
 523 /**
 524   * @}
 525   */
 526
 527 /* Exported functions --------------------------------------------------------*/
 528 /** @addtogroup CEC_Exported_Functions CEC Exported Functions
 529   * @{
 530   */
 531
 532 /** @addtogroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
 533   *  @brief    Initialization and Configuration functions
 534   * @{
 535   */
 536 /* Initialization and de-initialization functions  ****************************/
 537 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
 538 HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
 539 void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
 540 void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
 541 /**
 542   * @}
 543   */
 544
 545 /** @addtogroup CEC_Exported_Functions_Group2 Input and Output operation functions
 546   *  @brief CEC Transmit/Receive functions
 547   * @{
 548   */
 549 /* IO operation functions *****************************************************/
 550 HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout);
 551 HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout);
 552 HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
 553 HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData);
 554 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
 555 void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
 556 void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec);
 557 void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
 558 /**
 559   * @}
 560   */
 561
 562 /** @defgroup CEC_Exported_Functions_Group3 Peripheral Control functions
 563   *  @brief   CEC control functions
 564   * @{
 565   */
 566 /* Peripheral State and Error functions ***************************************/
 567 HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
 568 uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
 569 /**
 570   * @}
 571   */
 572
 573 /**
 574   * @}
 575   */
 576
 577 /**
 578   * @}
 579   */
 580
 581 /**
 582   * @}
 583   */
 584
 585 #endif /* defined(STM32F373xC) || defined(STM32F378xx) */
 586
 587 #ifdef __cplusplus
 588 }
 589 #endif
 590
 591 #endif /* __STM32F3xx_HAL_CEC_H */
 592
 593 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/