tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_dma.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f3xx_hal_dma.h
   4   * @author  MCD Application Team
   5   * @version V1.1.0
   6   * @date    12-Sept-2014
   7   * @brief   Header file of DMA HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32F3xx_HAL_DMA_H
  40 #define __STM32F3xx_HAL_DMA_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #include "stm32f3xx_hal_def.h"
  48
  49 /** @addtogroup STM32F3xx_HAL_Driver
  50   * @{
  51   */
  52
  53 /** @addtogroup DMA DMA HAL module driver
  54   * @{
  55   */
  56
  57 /* Exported types ------------------------------------------------------------*/
  58 /** @defgroup DMA_Exported_Types DMA Exported Types
  59   * @{
  60   */
  61
  62 /**
  63   * @brief  DMA Configuration Structure definition
  64   */
  65 typedef struct
  66 {
  67   uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral,
  68                                            from memory to memory or from peripheral to memory.
  69                                            This parameter can be a value of @ref DMA_Data_transfer_direction */
  70
  71   uint32_t PeriphInc;                 /*!< Specifies whether the Peripheral address register should be incremented or not.
  72                                            This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
  73
  74   uint32_t MemInc;                    /*!< Specifies whether the memory address register should be incremented or not.
  75                                            This parameter can be a value of @ref DMA_Memory_incremented_mode */
  76
  77   uint32_t PeriphDataAlignment;       /*!< Specifies the Peripheral data width.
  78                                            This parameter can be a value of @ref DMA_Peripheral_data_size */
  79
  80   uint32_t MemDataAlignment;          /*!< Specifies the Memory data width.
  81                                            This parameter can be a value of @ref DMA_Memory_data_size */
  82
  83   uint32_t Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.
  84                                            This parameter can be a value of @ref DMA_mode
  85                                            @note The circular buffer mode cannot be used if the memory-to-memory
  86                                                  data transfer is configured on the selected Channel */
  87
  88   uint32_t Priority;                   /*!< Specifies the software priority for the DMAy Channelx.
  89                                             This parameter can be a value of @ref DMA_Priority_level */
  90
  91 } DMA_InitTypeDef;
  92
  93 /**
  94   * @brief DMA Configuration enumeration values definition
  95   */
  96 typedef enum
  97 {
  98   DMA_MODE            = 0,      /*!< Control related DMA mode Parameter in DMA_InitTypeDef        */
  99   DMA_PRIORITY        = 1,      /*!< Control related priority level Parameter in DMA_InitTypeDef  */
 100
 101 } DMA_ControlTypeDef;
 102
 103 /**
 104   * @brief  HAL DMA State structures definition
 105   */
 106 typedef enum
 107 {
 108   HAL_DMA_STATE_RESET             = 0x00,  /*!< DMA not yet initialized or disabled */
 109   HAL_DMA_STATE_READY             = 0x01,  /*!< DMA process success and ready for use   */
 110   HAL_DMA_STATE_READY_HALF        = 0x11,  /*!< DMA Half process success            */
 111   HAL_DMA_STATE_BUSY              = 0x02,  /*!< DMA process is ongoing              */
 112   HAL_DMA_STATE_TIMEOUT           = 0x03,  /*!< DMA timeout state                   */
 113   HAL_DMA_STATE_ERROR             = 0x04,  /*!< DMA error state                     */
 114
 115 }HAL_DMA_StateTypeDef;
 116
 117 /**
 118   * @brief  HAL DMA Error Code structure definition
 119   */
 120 typedef enum
 121 {
 122   HAL_DMA_FULL_TRANSFER      = 0x00,    /*!< Full transfer     */
 123   HAL_DMA_HALF_TRANSFER      = 0x01,    /*!< Half Transfer     */
 124
 125 }HAL_DMA_LevelCompleteTypeDef;
 126
 127
 128 /**
 129   * @brief  DMA handle Structure definition
 130   */
 131 typedef struct __DMA_HandleTypeDef
 132 {
 133   DMA_Channel_TypeDef    *Instance;                                                   /*!< Register base address                  */
 134
 135   DMA_InitTypeDef       Init;                                                         /*!< DMA communication parameters           */
 136
 137   HAL_LockTypeDef       Lock;                                                         /*!< DMA locking object                     */
 138
 139   HAL_DMA_StateTypeDef  State;                                                        /*!< DMA transfer state                     */
 140
 141   void                  *Parent;                                                      /*!< Parent object state                    */
 142
 143   void                  (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback         */
 144
 145   void                  (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback    */
 146
 147   void                  (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback            */
 148
 149   __IO uint32_t              ErrorCode;                                                    /*!< DMA Error code                         */
 150
 151 } DMA_HandleTypeDef;
 152 /**
 153   * @}
 154   */
 155
 156 /* Exported constants --------------------------------------------------------*/
 157 /** @defgroup DMA_Exported_Constants DMA Exported Constants
 158   * @{
 159   */
 160
 161 /** @defgroup DMA_Error_Code  DMA Error Code
 162   * @{
 163   */
 164 #define HAL_DMA_ERROR_NONE      ((uint32_t)0x00000000)    /*!< No error             */
 165 #define HAL_DMA_ERROR_TE        ((uint32_t)0x00000001)    /*!< Transfer error       */
 166 #define HAL_DMA_ERROR_TIMEOUT   ((uint32_t)0x00000020)    /*!< Timeout error        */
 167 /**
 168   * @}
 169   */
 170
 171
 172 /** @defgroup DMA_Data_transfer_direction  DMA Data transfer direction
 173   * @{
 174   */
 175 #define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000)        /*!< Peripheral to memory direction */
 176 #define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_CCR_DIR)       /*!< Memory to peripheral direction */
 177 #define DMA_MEMORY_TO_MEMORY         ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction     */
 178
 179 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
 180                                      ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
 181                                      ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
 182 /**
 183   * @}
 184   */
 185
 186 /** @defgroup DMA_Data_buffer_size DMA Data buffer size
 187   * @{
 188   */
 189 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
 190 /**
 191   * @}
 192   */
 193
 194 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
 195   * @{
 196   */
 197 #define DMA_PINC_ENABLE        ((uint32_t)DMA_CCR_PINC)  /*!< Peripheral increment mode Enable */
 198 #define DMA_PINC_DISABLE       ((uint32_t)0x00000000)    /*!< Peripheral increment mode Disable */
 199
 200 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
 201                                             ((STATE) == DMA_PINC_DISABLE))
 202 /**
 203   * @}
 204   */
 205
 206 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
 207   * @{
 208   */
 209 #define DMA_MINC_ENABLE         ((uint32_t)DMA_CCR_MINC)  /*!< Memory increment mode Enable  */
 210 #define DMA_MINC_DISABLE        ((uint32_t)0x00000000)    /*!< Memory increment mode Disable */
 211
 212 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
 213                                         ((STATE) == DMA_MINC_DISABLE))
 214 /**
 215   * @}
 216   */
 217
 218 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
 219   * @{
 220   */
 221 #define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000)       /*!< Peripheral data alignment : Byte     */
 222 #define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_PSIZE_0)  /*!< Peripheral data alignment : HalfWord */
 223 #define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_CCR_PSIZE_1)  /*!< Peripheral data alignment : Word     */
 224
 225 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
 226                                            ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
 227                                            ((SIZE) == DMA_PDATAALIGN_WORD))
 228 /**
 229   * @}
 230   */
 231
 232
 233 /** @defgroup DMA_Memory_data_size DMA Memory data size
 234   * @{
 235   */
 236 #define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000)       /*!< Memory data alignment : Byte     */
 237 #define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_MSIZE_0)  /*!< Memory data alignment : HalfWord */
 238 #define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_CCR_MSIZE_1)  /*!< Memory data alignment : Word     */
 239
 240 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
 241                                        ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
 242                                        ((SIZE) == DMA_MDATAALIGN_WORD ))
 243 /**
 244   * @}
 245   */
 246
 247 /** @defgroup DMA_mode DMA mode
 248   * @{
 249   */
 250 #define DMA_NORMAL         ((uint32_t)0x00000000)       /*!< Normal Mode                  */
 251 #define DMA_CIRCULAR       ((uint32_t)DMA_CCR_CIRC)    /*!< Circular Mode                */
 252
 253 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
 254                            ((MODE) == DMA_CIRCULAR))
 255 /**
 256   * @}
 257   */
 258
 259 /** @defgroup DMA_Priority_level DMA Priority level
 260   * @{
 261   */
 262 #define DMA_PRIORITY_LOW             ((uint32_t)0x00000000)    /*!< Priority level : Low       */
 263 #define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_CCR_PL_0)  /*!< Priority level : Medium    */
 264 #define DMA_PRIORITY_HIGH            ((uint32_t)DMA_CCR_PL_1)  /*!< Priority level : High      */
 265 #define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_CCR_PL)    /*!< Priority level : Very_High */
 266
 267 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
 268                                    ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
 269                                    ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
 270                                    ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
 271 /**
 272   * @}
 273   */
 274
 275
 276 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
 277   * @{
 278   */
 279
 280 #define DMA_IT_TC                         ((uint32_t)DMA_CCR_TCIE)
 281 #define DMA_IT_HT                         ((uint32_t)DMA_CCR_HTIE)
 282 #define DMA_IT_TE                         ((uint32_t)DMA_CCR_TEIE)
 283
 284 /**
 285   * @}
 286   */
 287
 288 /** @defgroup DMA_flag_definitions DMA flag definitions
 289   * @{
 290   */
 291
 292 #define DMA_FLAG_GL1                      ((uint32_t)0x00000001)
 293 #define DMA_FLAG_TC1                      ((uint32_t)0x00000002)
 294 #define DMA_FLAG_HT1                      ((uint32_t)0x00000004)
 295 #define DMA_FLAG_TE1                      ((uint32_t)0x00000008)
 296 #define DMA_FLAG_GL2                      ((uint32_t)0x00000010)
 297 #define DMA_FLAG_TC2                      ((uint32_t)0x00000020)
 298 #define DMA_FLAG_HT2                      ((uint32_t)0x00000040)
 299 #define DMA_FLAG_TE2                      ((uint32_t)0x00000080)
 300 #define DMA_FLAG_GL3                      ((uint32_t)0x00000100)
 301 #define DMA_FLAG_TC3                      ((uint32_t)0x00000200)
 302 #define DMA_FLAG_HT3                      ((uint32_t)0x00000400)
 303 #define DMA_FLAG_TE3                      ((uint32_t)0x00000800)
 304 #define DMA_FLAG_GL4                      ((uint32_t)0x00001000)
 305 #define DMA_FLAG_TC4                      ((uint32_t)0x00002000)
 306 #define DMA_FLAG_HT4                      ((uint32_t)0x00004000)
 307 #define DMA_FLAG_TE4                      ((uint32_t)0x00008000)
 308 #define DMA_FLAG_GL5                      ((uint32_t)0x00010000)
 309 #define DMA_FLAG_TC5                      ((uint32_t)0x00020000)
 310 #define DMA_FLAG_HT5                      ((uint32_t)0x00040000)
 311 #define DMA_FLAG_TE5                      ((uint32_t)0x00080000)
 312 #define DMA_FLAG_GL6                      ((uint32_t)0x00100000)
 313 #define DMA_FLAG_TC6                      ((uint32_t)0x00200000)
 314 #define DMA_FLAG_HT6                      ((uint32_t)0x00400000)
 315 #define DMA_FLAG_TE6                      ((uint32_t)0x00800000)
 316 #define DMA_FLAG_GL7                      ((uint32_t)0x01000000)
 317 #define DMA_FLAG_TC7                      ((uint32_t)0x02000000)
 318 #define DMA_FLAG_HT7                      ((uint32_t)0x04000000)
 319 #define DMA_FLAG_TE7                      ((uint32_t)0x08000000)
 320
 321
 322 /**
 323   * @}
 324   */
 325
 326 /**
 327   * @}
 328   */
 329
 330 /* Exported macros -----------------------------------------------------------*/
 331 /** @defgroup DMA_Exported_Macros DMA Exported Macros
 332   * @{
 333   */
 334
 335 /** @brief  Reset DMA handle state
 336   * @param  __HANDLE__: DMA handle.
 337   * @retval None
 338   */
 339 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
 340
 341 /**
 342   * @brief  Enable the specified DMA Channel.
 343   * @param  __HANDLE__: DMA handle
 344   * @retval None.
 345   */
 346 #define __HAL_DMA_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CCR |=  DMA_CCR_EN)
 347
 348 /**
 349   * @brief  Disable the specified DMA Channel.
 350   * @param  __HANDLE__: DMA handle
 351   * @retval None.
 352   */
 353 #define __HAL_DMA_DISABLE(__HANDLE__)       ((__HANDLE__)->Instance->CCR &=  ~DMA_CCR_EN)
 354
 355
 356 /* Interrupt & Flag management */
 357
 358 /**
 359   * @brief  Enables the specified DMA Channel interrupts.
 360   * @param  __HANDLE__: DMA handle
 361   * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
 362   *          This parameter can be any combination of the following values:
 363   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
 364   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
 365   *            @arg DMA_IT_TE:  Transfer error interrupt mask
 366   * @retval None
 367   */
 368 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
 369
 370 /**
 371   * @brief  Disables the specified DMA Channel interrupts.
 372   * @param  __HANDLE__: DMA handle
 373   * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
 374   *          This parameter can be any combination of the following values:
 375   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
 376   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
 377   *            @arg DMA_IT_TE:  Transfer error interrupt mask
 378   * @retval None
 379   */
 380 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
 381
 382 /**
 383   * @brief  Checks whether the specified DMA Channel interrupt has occurred or not.
 384   * @param  __HANDLE__: DMA handle
 385   * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
 386   *          This parameter can be one of the following values:
 387   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
 388   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
 389   *            @arg DMA_IT_TE:  Transfer error interrupt mask
 390   * @retval The state of DMA_IT (SET or RESET).
 391   */
 392 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 393
 394 /**
 395   * @}
 396   */
 397
 398 /* Include DMA HAL Extended module */
 399 #include "stm32f3xx_hal_dma_ex.h"
 400
 401 /* Exported functions --------------------------------------------------------*/
 402 /** @addtogroup DMA_Exported_Functions DMA Exported Functions
 403   * @{
 404   */
 405
 406 /** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
 407   * @{
 408   */
 409 /* Initialization and de-initialization functions *****************************/
 410 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
 411 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
 412
 413 /**
 414   * @}
 415   */
 416
 417 /** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions
 418   * @{
 419   */
 420 /* IO operation functions *****************************************************/
 421 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 422 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 423 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
 424 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
 425 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
 426
 427 /**
 428   * @}
 429   */
 430
 431 /** @addtogroup DMA_Exported_Functions_Group3 Peripheral State functions
 432   * @{
 433   */
 434 /* Peripheral State and Error functions ***************************************/
 435 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
 436 uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
 437
 438 /**
 439   * @}
 440   */
 441
 442 /**
 443   * @}
 444   */
 445
 446 /**
 447   * @}
 448   */
 449
 450 /**
 451   * @}
 452   */
 453
 454 #ifdef __cplusplus
 455 }
 456 #endif
 457
 458 #endif /* __STM32F3xx_HAL_DMA_H */
 459
 460 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/