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[tmk_keyboard.git] / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_STM / TARGET_STM32F3 / stm32f3xx_hal_hrtim.c
1 /**
2 ******************************************************************************
3 * @file stm32f3xx_hal_hrtim.c
4 * @author MCD Application Team
5 * @version V1.1.0
6 * @date 12-Sept-2014
7 * @brief TIM HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the High Resolution Timer (HRTIM) peripheral:
10 * + HRTIM Initialization
11 * + DLL Calibration Start
12 * + Timer Time Base Unit Configuration
13 * + Simple Time Base Start/Stop
14 * + Simple Time Base Start/Stop Interrupt
15 * + Simple Time Base Start/Stop DMA Request
16 * + Simple Output Compare/PWM Channel Configuration
17 * + Simple Output Compare/PWM Channel Start/Stop Interrupt
18 * + Simple Output Compare/PWM Channel Start/Stop DMA Request
19 * + Simple Input Capture Channel Configuration
20 * + Simple Input Capture Channel Start/Stop Interrupt
21 * + Simple Input Capture Channel Start/Stop DMA Request
22 * + Simple One Pulse Channel Configuration
23 * + Simple One Pulse Channel Start/Stop Interrupt
24 * + HRTIM External Synchronization Configuration
25 * + HRTIM Burst Mode Controller Configuration
26 * + HRTIM Burst Mode Controller Enabling
27 * + HRTIM External Events Conditioning Configuration
28 * + HRTIM Faults Conditioning Configuration
29 * + HRTIM Faults Enabling
30 * + HRTIM ADC trigger Configuration
31 * + Waveform Timer Configuration
32 * + Waveform Event Filtering Configuration
33 * + Waveform Dead Time Insertion Configuration
34 * + Waveform Chopper Mode Configuration
35 * + Waveform Compare Unit Configuration
36 * + Waveform Capture Unit Configuration
37 * + Waveform Output Configuration
38 * + Waveform Counter Start/Stop
39 * + Waveform Counter Start/Stop Interrupt
40 * + Waveform Counter Start/Stop DMA Request
41 * + Waveform Output Enabling
42 * + Waveform Output Level Set/Get
43 * + Waveform Output State Get
44 * + Waveform Burst DMA Operation Configuration
45 * + Waveform Burst DMA Operation Start
46 * + Waveform Timer Counter Software Reset
47 * + Waveform Capture Software Trigger
48 * + Waveform Burst Mode Controller Software Trigger
49 * + Waveform Timer Pre-loadable Registers Update Enabling
50 * + Waveform Timer Pre-loadable Registers Software Update
51 * + Waveform Timer Delayed Protection Status Get
52 * + Waveform Timer Burst Status Get
53 * + Waveform Timer Push-Pull Status Get
54 * + Peripheral State Get
55 @verbatim
56 ==============================================================================
57 ##### Simple mode v.s. waveform mode #####
58 ==============================================================================
59 [..] The HRTIM HAL API is split into 2 categories:
60 (#)Simple functions: these functions allow for using a HRTIM timer as a
61 general purpose timer with high resolution capabilities.
62 Following simple modes are proposed:
63 (+)Output compare mode
64 (+)PWM output mode
65 (+)Input capture mode
66 (+)One pulse mode
67 HRTIM simple modes are managed through the set of functions named
68 HAL_HRTIM_Simple<Function>. These functions are similar in name and usage
69 to the one defined for the TIM peripheral. When a HRTIM timer operates in
70 simple mode, only a very limited set of HRTIM features are used.
71 (#)Waveform functions: These functions allow taking advantage of the HRTIM
72 flexibility to produce numerous types of control signal. When a HRTIM timer
73 operates in waveform mode, all the HRTIM features are accessible without
74 any restriction. HRTIM waveform modes are managed through the set of
75 functions named HAL_HRTIM_Waveform<Function>
76
77 ==============================================================================
78 ##### How to use this driver #####
79 ==============================================================================
80 [..]
81 (#)Initialize the HRTIM low level resources by implementing the
82 HAL_HRTIM_MspInit() function:
83 (##)Enable the HRTIM clock source using __HRTIMx_CLK_ENABLE()
84 (##)Connect HRTIM pins to MCU I/Os
85 (+++) Enable the clock for the HRTIM GPIOs using the following
86 function: __GPIOx_CLK_ENABLE()
87 (+++) Configure these GPIO pins in Alternate Function mode using
88 HAL_GPIO_Init()
89 (##)When using DMA to control data transfer (e.g HAL_HRTIM_SimpleBaseStart_DMA())
90 (+++)Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
91 (+++)Initialize the DMA handle
92 (+++)Associate the initialized DMA handle to the appropriate DMA
93 handle of the HRTIM handle using __HAL_LINKDMA()
94 (+++)Initialize the DMA channel using HAL_DMA_Init()
95 (+++)Configure the priority and enable the NVIC for the transfer
96 complete interrupt on the DMA channel using HAL_NVIC_SetPriority()
97 and HAL_NVIC_EnableIRQ()
98 (##)In case of using interrupt mode (e.g HAL_HRTIM_SimpleBaseStart_IT())
99 (+++)Configure the priority and enable the NVIC for the concerned
100 HRTIM interrupt using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
101
102 (#)Initialize the HRTIM HAL using HAL_HRTIM_Init(). The HRTIM configuration
103 structure (field of the HRTIM handle) specifies which global interrupt of
104 whole HRTIM must be enabled (Burst mode period, System fault, Faults).
105 It also contains the HRTIM external synchronization configuration. HRTIM
106 can act as a master (generating a synchronization signal) or as a slave
107 (waiting for a trigger to be synchronized).
108
109 (#)Start the high resolution unit using HAL_HRTIM_DLLCalibrationStart(). DLL
110 calibration is executed periodically and compensate for potential voltage
111 and temperature drifts. DLL calibration period is specified by the
112 CalibrationRate argument.
113
114 (#)HRTIM timers cannot be used until the high resolution unit is ready. This
115 can be checked using HAL_HRTIM_PollForDLLCalibration(): this function returns
116 HAL_OK if DLL calibration is completed or HAL_TIMEOUT if the DLL calibration
117 is still going on when timeout given is argument expires. DLL calibration
118 can also be started in interrupt mode using HAL_HRTIM_DLLCalibrationStart_IT().
119 In that case an interrupt is generated when the DLL calibration is completed.
120 Note that as DLL calibration is executed on a periodic basis an interrupt
121 will be generated at the end of every DLL calibration operation
122 (worst case: one interrupt every 14 micro seconds !).
123
124 (#) Configure HRTIM resources shared by all HRTIM timers
125 (##)Burst Mode Controller:
126 (+++)HAL_HRTIM_BurstModeConfig(): configures the HRTIM burst mode
127 controller: operating mode (continuous or -shot mode), clock
128 (source, prescaler) , trigger(s), period, idle duration.
129 (##)External Events Conditionning:
130 (+++)HAL_HRTIM_EventConfig(): configures the conditioning of an
131 external event channel: source, polarity, edge-sensitivity.
132 External event can be used as triggers (timer reset, input
133 capture, burst mode, ADC triggers, delayed protection, \85)
134 They can also be used to set or reset timer outputs. Up to
135 10 event channels are available.
136 (+++)HAL_HRTIM_EventPrescalerConfig(): configures the external
137 event sampling clock (used for digital filtering).
138 (##)Fault Conditionning:
139 (+++)HAL_HRTIM_FaultConfig(): configures the conditioning of a
140 fault channel: source, polarity, edge-sensitivity. Fault
141 channels are used to disable the outputs in case of an
142 abnormal operation. Up to 5 fault channels are available.
143 (+++)HAL_HRTIM_FaultPrescalerConfig(): configures the fault
144 sampling clock (used for digital filtering).
145 (+++)HAL_HRTIM_FaultModeCtl(): Enables or disables fault input(s)
146 circuitry. By default all fault inputs are disabled.
147 (##)ADC trigger:
148 (+++)HAL_HRTIM_ADCTriggerConfig(): configures the source triggering
149 the update of the ADC trigger register and the ADC trigger.
150 4 independent triggers are available to start both the regular
151 and the injected sequencers of the 2 ADCs
152
153 (#) Configure HRTIM timer time base using HAL_HRTIM_TimeBaseConfig(). This
154 function must be called whatever the HRTIM timer operating mode is
155 (simple v.s. waveform). It configures mainly:
156 (##)The HRTIM timer counter operating mode (continuous, one shot)
157 (##)The HRTIM timer clock prescaler
158 (##)The HRTIM timer period
159 (##)The HRTIM timer repetition counter
160
161 (#) If the HRTIM timer operates in simple mode:
162 (##)Simple time base: HAL_HRTIM_SimpleBaseStart(),HAL_HRTIM_SimpleBaseStop(),
163 HAL_HRTIM_SimpleBaseStart_IT(),HAL_HRTIM_SimpleBaseStop_IT(),
164 HAL_HRTIM_SimpleBaseStart_DMA(),HAL_HRTIM_SimpleBaseStop_DMA().
165 (##)Simple output compare: HAL_HRTIM_SimpleOCChannelConfig(),
166 HAL_HRTIM_SimpleOCStart(),HAL_HRTIM_SimpleOCStop(),
167 HAL_HRTIM_SimpleOCStart_IT(),HAL_HRTIM_SimpleOCStop_IT(),
168 HAL_HRTIM_SimpleOCStart_DMA(),HAL_HRTIM_SimpleOCStop_DMA(),
169 (##)Simple PWM output: HAL_HRTIM_SimplePWMChannelConfig(),
170 HAL_HRTIM_SimplePWMStart(),HAL_HRTIM_SimplePWMStop(),
171 HAL_HRTIM_SimplePWMStart_IT(),HAL_HRTIM_SimplePWMStop_IT(),
172 HAL_HRTIM_SimplePWMStart_DMA(),HAL_HRTIM_SimplePWMStop_DMA(),
173 (##)Simple input capture: HAL_HRTIM_SimpleCaptureChannelConfig(),
174 HAL_HRTIM_SimpleCaptureStart(),HAL_HRTIM_SimpleCaptureStop(),
175 HAL_HRTIM_SimpleCaptureStart_IT(),HAL_HRTIM_SimpleCaptureStop_IT(),
176 HAL_HRTIM_SimpleCaptureStart_DMA(),HAL_HRTIM_SimpleCaptureStop_DMA().
177 (##)Simple one pulse: HAL_HRTIM_SimpleOnePulseChannelConfig(),
178 HAL_HRTIM_SimpleOnePulseStart(),HAL_HRTIM_SimpleOnePulseStop(),
179 HAL_HRTIM_SimpleOnePulseStart_IT(),HAL_HRTIM_SimpleOnePulseStop_It().
180
181 (#) If the HRTIM timer operates in waveform mode:
182 (##)Completes waveform timer configuration
183 (+++)HAL_HRTIM_WaveformTimerConfig(): configuration of a HRTIM
184 timer operating in wave form mode mainly consists in:
185 - Enabling the HRTIM timer interrupts and DMA requests,
186 - Enabling the half mode for the HRTIM timer,
187 - Defining how the HRTIM timer reacts to external
188 synchronization input,
189 - Enabling the push-pull mode for the HRTIM timer,
190 - Enabling the fault channels for the HRTIM timer,
191 - Enabling the deadtime insertion for the HRTIM timer,
192 - Setting the delayed protection mode for the HRTIM timer
193 (source and outputs on which the delayed protection are applied),
194 - Specifying the HRTIM timer update and reset triggers,
195 - Specifying the HRTIM timer registers update policy (preload enabling, \85).
196 (+++)HAL_HRTIM_TimerEventFilteringConfig(): configures external
197 event blanking and windowingcircuitry of a HRTIM timer:
198 - Blanking: to mask external events during a defined
199 time period
200 - Windowing: to enable external events only during
201 a defined time period
202 (+++)HAL_HRTIM_DeadTimeConfig(): configures the deadtime insertion
203 unit for a HRTIM timer. Allows to generate a couple of
204 complementary signals from a single reference waveform,
205 with programmable delays between active state.
206 (+++)HAL_HRTIM_ChopperModeConfig(): configures the parameters of
207 the high-frequency carrier signal added on top of the timing
208 unit output. Chopper mode can be enabled or disabled for each
209 timer output separately (see HAL_HRTIM_WaveformOutputConfig()).
210 (+++)HAL_HRTIM_BurstDMAConfig(): configures the burst DMA burst
211 controller. Allows having multiple HRTIM registers updated
212 with a single DMA request. The burst DMA operation is started
213 by calling HAL_HRTIM_BurstDMATransfer().
214 (+++)HAL_HRTIM_WaveformCompareConfig():configures the compare unit
215 of a HRTIM timer. This operation consists in setting the
216 compare value and possibly specifying the auto delayed mode
217 for compare units 2 and 4 (allows to have compare events
218 generated relatively to capture events). Note that when auto
219 delayed mode is needed, the capture unit associated to the
220 compare unit must be configured separately.
221 (+++)HAL_HRTIM_WaveformCaptureConfig(): configures the capture unit
222 of a HRTIM timer. This operation consists in specifying the
223 source(s) triggering the capture (timer register update event,
224 external event, timer output set/reset event, other HRTIM
225 timer related events).
226 (+++)HAL_HRTIM_WaveformOutputConfig(): configuration HRTIM timer
227 output manly consists in:
228 - Setting the output polarity (active high or active low),
229 - Defining the set/reset crossbar for the output,
230 - Specifying the fault level (active or inactive) in IDLE
231 and FAULT states.,
232 (##)Set waveform timer output(s) level
233 (+++)HAL_HRTIM_WaveformSetOutputLevel(): forces the output to its
234 active or inactive level. For example, when deadtime insertion
235 is enabled it is necessary to force the output level by software
236 to have the outputs in a complementary state as soon as the RUN mode is entered.
237 (##)Enable/Disable waveform timer output(s)
238 (+++)HAL_HRTIM_WaveformOutputStart(),HAL_HRTIM_WaveformOutputStop().
239 (##)Start/Stop waveform HRTIM timer(s).
240 (+++)HAL_HRTIM_WaveformCounterStart(),HAL_HRTIM_WaveformCounterStop(),
241 (+++)HAL_HRTIM_WaveformCounterStart_IT(),HAL_HRTIM_WaveformCounterStop_IT(),
242 (+++)HAL_HRTIM_WaveformCounterStart()_DMA,HAL_HRTIM_WaveformCounterStop_DMA(),
243
244 (##)Burst mode controller enabling:
245 (+++)HAL_HRTIM_BurstModeCtl(): activates or de-activates the
246 burst mode controller.
247
248 (##)Some HRTIM operations can be triggered by software:
249 (+++)HAL_HRTIM_BurstModeSoftwareTrigger(): calling this function
250 trigs the burst operation.
251 (+++)HAL_HRTIM_SoftwareCapture(): calling this function trigs the
252 capture of the HRTIM timer counter.
253 (+++)HAL_HRTIM_SoftwareUpdate(): calling this function trigs the
254 update of the pre-loadable registers of the HRTIM timer ()
255 (+++)HAL_HRTIM_SoftwareReset():calling this function resets the
256 HRTIM timer counter.
257
258 (##)Some functions can be used anytime to retrieve HRTIM timer related
259 information
260 (+++)HAL_HRTIM_GetCapturedValue(): returns actual value of the
261 capture register of the designated capture unit.
262 (+++)HAL_HRTIM_WaveformGetOutputLevel(): returns actual level
263 (ACTIVE/INACTIVE) of the designated timer output.
264 (+++)HAL_HRTIM_WaveformGetOutputState():returns actual state
265 (IDLE/RUN/FAULT) of the designated timer output.
266 (+++)HAL_HRTIM_GetDelayedProtectionStatus():returns actual level
267 (ACTIVE/INACTIVE) of the designated output when the delayed
268 protection was triggered.
269 (+++)HAL_HRTIM_GetBurstStatus(): returns the actual status
270 (ACTIVE/INACTIVE) of the burst mode controller.
271 (+++)HAL_HRTIM_GetCurrentPushPullStatus(): when the push-pull mode
272 is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
273 the push-pull indicates on which output the signal is currently
274 active (e.g signal applied on output 1 and output 2 forced
275 inactive or vice versa).
276 (+++)HAL_HRTIM_GetIdlePushPullStatus(): when the push-pull mode
277 is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
278 the idle push-pull status indicates during which period the
279 delayed protection request occurred (e.g. protection occurred
280 when the output 1 was active and output 2 forced inactive or
281 vice versa).
282
283 (##)Some functions can be used anytime to retrieve actual HRTIM status
284 (+++)HAL_HRTIM_GetState(): returns actual HRTIM instance HAL state.
285
286 @endverbatim
287
288 ******************************************************************************
289 * @attention
290 *
291 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
292 *
293 * Redistribution and use in source and binary forms, with or without modification,
294 * are permitted provided that the following conditions are met:
295 * 1. Redistributions of source code must retain the above copyright notice,
296 * this list of conditions and the following disclaimer.
297 * 2. Redistributions in binary form must reproduce the above copyright notice,
298 * this list of conditions and the following disclaimer in the documentation
299 * and/or other materials provided with the distribution.
300 * 3. Neither the name of STMicroelectronics nor the names of its contributors
301 * may be used to endorse or promote products derived from this software
302 * without specific prior written permission.
303 *
304 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
305 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
306 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
307 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
308 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
309 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
310 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
311 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
312 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
313 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
314 *
315 ******************************************************************************
316 */
317
318 /* Includes ------------------------------------------------------------------*/
319 #include "stm32f3xx_hal.h"
320
321 /** @addtogroup STM32F3xx_HAL_Driver
322 * @{
323 */
324
325 #ifdef HAL_HRTIM_MODULE_ENABLED
326
327 #if defined(STM32F334x8)
328
329 /** @defgroup HRTIM HRTIM HAL module driver
330 * @brief HRTIM HAL module driver
331 * @{
332 */
333
334 /* Private typedef -----------------------------------------------------------*/
335 /* Private define ------------------------------------------------------------*/
336 /** @defgroup HRTIM_Private_Defines HRTIM Private Define
337 * @{
338 */
339 #define HRTIM_FLTR_FLTxEN (HRTIM_FLTR_FLT1EN |\
340 HRTIM_FLTR_FLT2EN |\
341 HRTIM_FLTR_FLT3EN |\
342 HRTIM_FLTR_FLT4EN | \
343 HRTIM_FLTR_FLT5EN)
344
345 #define HRTIM_TIMCR_TIMUPDATETRIGGER (HRTIM_TIMUPDATETRIGGER_MASTER |\
346 HRTIM_TIMUPDATETRIGGER_TIMER_A |\
347 HRTIM_TIMUPDATETRIGGER_TIMER_B |\
348 HRTIM_TIMUPDATETRIGGER_TIMER_C |\
349 HRTIM_TIMUPDATETRIGGER_TIMER_D |\
350 HRTIM_TIMUPDATETRIGGER_TIMER_E)
351 /**
352 * @}
353 */
354
355 /* Private macro -------------------------------------------------------------*/
356 /* Private variables ---------------------------------------------------------*/
357 /** @defgroup HRTIM_Private_Variables HRTIM Private Variables
358 * @{
359 */
360 static uint32_t TimerIdxToTimerId[] =
361 {
362 HRTIM_TIMERID_TIMER_A,
363 HRTIM_TIMERID_TIMER_B,
364 HRTIM_TIMERID_TIMER_C,
365 HRTIM_TIMERID_TIMER_D,
366 HRTIM_TIMERID_TIMER_E,
367 HRTIM_TIMERID_MASTER,
368 };
369 /**
370 * @}
371 */
372
373 /* Private function prototypes -----------------------------------------------*/
374 /** @defgroup HRTIM_Private_Functions HRTIM Private Functions
375 * @{
376 */
377 static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
378 HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
379
380 static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
381 uint32_t TimerIdx,
382 HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
383
384 static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
385 HRTIM_TimerCfgTypeDef * pTimerCfg);
386
387 static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
388 uint32_t TimerIdx,
389 HRTIM_TimerCfgTypeDef * pTimerCfg);
390
391 static void HRTIM_CompareUnitConfig(HRTIM_HandleTypeDef * hhrtim,
392 uint32_t TimerIdx,
393 uint32_t CompareUnit,
394 HRTIM_CompareCfgTypeDef * pCompareCfg);
395
396 static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
397 uint32_t TimerIdx,
398 uint32_t CaptureUnit,
399 uint32_t Event);
400
401 static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
402 uint32_t TimerIdx,
403 uint32_t Output,
404 HRTIM_OutputCfgTypeDef * pOutputCfg);
405
406 static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
407 uint32_t Event,
408 HRTIM_EventCfgTypeDef * pEventCfg);
409
410 static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
411 uint32_t TimerIdx,
412 uint32_t Event);
413
414 static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim,
415 uint32_t TimerIdx,
416 uint32_t OCChannel);
417
418 static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim,
419 uint32_t TimerIdx,
420 uint32_t OCChannel);
421
422 static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hhrtim,
423 uint32_t TimerIdx);
424
425 static uint32_t GetTimerIdxFromDMAHandle(DMA_HandleTypeDef *hdma);
426
427 static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
428 uint32_t TimerIdx);
429
430 static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim);
431
432 static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim);
433
434 static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
435 uint32_t TimerIdx);
436
437 static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma);
438
439 static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma);
440
441 static void HRTIM_DMAError(DMA_HandleTypeDef *hdma);
442
443 static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma);
444 /**
445 * @}
446 */
447
448 /* Exported functions ---------------------------------------------------------*/
449 /** @defgroup HRTIM_Exported_Functions HRTIM Exported Functions
450 * @{
451 */
452
453 /** @defgroup HRTIM_Exported_Functions_Group1 Initialization and de-initialization functions
454 * @brief Initialization and Configuration functions
455 *
456 @verbatim
457 ===============================================================================
458 ##### Initialization and Time Base Configuration functions #####
459 ===============================================================================
460 [..] This section provides functions allowing to:
461 (+) Initialize a HRTIM instance
462 (+) De-initialize a HRTIM instance
463 (+) Initialize the HRTIM MSP
464 (+) De-initialize the HRTIM MSP
465 (+) Start the high-resolution unit (start DLL calibration)
466 (+) Check that the high resolution unit is ready (DLL calibration done)
467 (+) Configure the time base unit of a HRTIM timer
468
469 @endverbatim
470 * @{
471 */
472
473 /**
474 * @brief Initializes a HRTIM instance
475 * @param hhrtim: pointer to HAL HRTIM handle
476 * @retval HAL status
477 */
478 HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim)
479 {
480 uint8_t timer_idx;
481 uint32_t hrtim_mcr;
482
483 /* Check the HRTIM handle allocation */
484 if(hhrtim == HAL_NULL)
485 {
486 return HAL_ERROR;
487 }
488
489 /* Check the parameters */
490 assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
491 assert_param(IS_HRTIM_IT(hhrtim->Init.HRTIMInterruptResquests));
492
493 /* Set the HRTIM state */
494 hhrtim->State = HAL_HRTIM_STATE_BUSY;
495
496 /* Initialize the DMA handles */
497 hhrtim->hdmaMaster = (DMA_HandleTypeDef *)HAL_NULL;
498 hhrtim->hdmaTimerA = (DMA_HandleTypeDef *)HAL_NULL;
499 hhrtim->hdmaTimerB = (DMA_HandleTypeDef *)HAL_NULL;
500 hhrtim->hdmaTimerC = (DMA_HandleTypeDef *)HAL_NULL;
501 hhrtim->hdmaTimerD = (DMA_HandleTypeDef *)HAL_NULL;
502 hhrtim->hdmaTimerE = (DMA_HandleTypeDef *)HAL_NULL;
503
504 /* HRTIM output synchronization configuration (if required) */
505 if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_MASTER) != RESET)
506 {
507 /* Check parameters */
508 assert_param(IS_HRTIM_SYNCOUTPUTSOURCE(hhrtim->Init.SyncOutputSource));
509 assert_param(IS_HRTIM_SYNCOUTPUTPOLARITY(hhrtim->Init.SyncOutputPolarity));
510
511 /* The synchronization output initialization procedure must be done prior
512 to the configuration of the MCU outputs (done within HAL_HRTIM_MspInit)
513 */
514 if (hhrtim->Instance == HRTIM1)
515 {
516 /* Enable the HRTIM peripheral clock */
517 __HRTIM1_CLK_ENABLE();
518 }
519
520 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
521
522 /* Set the event to be sent on the synchronization output */
523 hrtim_mcr &= ~(HRTIM_MCR_SYNC_SRC);
524 hrtim_mcr |= (hhrtim->Init.SyncOutputSource & HRTIM_MCR_SYNC_SRC);
525
526 /* Set the polarity of the synchronization output */
527 hrtim_mcr &= ~(HRTIM_MCR_SYNC_OUT);
528 hrtim_mcr |= (hhrtim->Init.SyncOutputPolarity & HRTIM_MCR_SYNC_OUT);
529
530 /* Update the HRTIM registers */
531 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
532 }
533
534 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
535 HAL_HRTIM_MspInit(hhrtim);
536
537 /* HRTIM input synchronization configuration (if required) */
538 if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_SLAVE) != RESET)
539 {
540 /* Check parameters */
541 assert_param(IS_HRTIM_SYNCINPUTSOURCE(hhrtim->Init.SyncInputSource));
542
543 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
544
545 /* Set the synchronization input source */
546 hrtim_mcr &= ~(HRTIM_MCR_SYNC_IN);
547 hrtim_mcr |= (hhrtim->Init.SyncInputSource & HRTIM_MCR_SYNC_IN);
548
549 /* Update the HRTIM registers */
550 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
551 }
552
553 /* Initialize the HRTIM state*/
554 hhrtim->State = HAL_HRTIM_STATE_READY;
555
556 /* Initialize the lock status of the HRTIM HAL API */
557 __HAL_UNLOCK(hhrtim);
558
559 /* Tnitialize timer related parameters */
560 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
561 timer_idx <= HRTIM_TIMERINDEX_MASTER ;
562 timer_idx++)
563 {
564 hhrtim->TimerParam[timer_idx].CaptureTrigger1 = HRTIM_CAPTURETRIGGER_NONE;
565 hhrtim->TimerParam[timer_idx].CaptureTrigger2 = HRTIM_CAPTURETRIGGER_NONE;
566 hhrtim->TimerParam[timer_idx].InterruptRequests = HRTIM_IT_NONE;
567 hhrtim->TimerParam[timer_idx].DMARequests = HRTIM_IT_NONE;
568 hhrtim->TimerParam[timer_idx].DMASrcAddress = 0;
569 hhrtim->TimerParam[timer_idx].DMASize = 0;
570 }
571
572 return HAL_OK;
573 }
574
575 /**
576 * @brief De-initializes a timer operating in waveform mode
577 * @param hhrtim: pointer to HAL HRTIM handle
578 * @retval HAL status
579 */
580 HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef * hhrtim)
581 {
582 /* Check the HRTIM handle allocation */
583 if(hhrtim == HAL_NULL)
584 {
585 return HAL_ERROR;
586 }
587
588 /* Check the parameters */
589 assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
590
591 /* Set the HRTIM state */
592 hhrtim->State = HAL_HRTIM_STATE_BUSY;
593
594 /* DeInit the low level hardware */
595 HAL_HRTIM_MspDeInit(hhrtim);
596
597 hhrtim->State = HAL_HRTIM_STATE_READY;
598
599 return HAL_OK;
600 }
601
602 /**
603 * @brief MSP initialization for a HRTIM instance
604 * @param hhrtim: pointer to HAL HRTIM handle
605 * @retval None
606 */
607 __weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim)
608 {
609 /* NOTE: This function should not be modified, when the callback is needed,
610 the HAL_HRTIM_MspInit could be implemented in the user file
611 */
612 }
613
614 /**
615 * @brief MSP initialization for a for a HRTIM instance
616 * @param hhrtim: pointer to HAL HRTIM handle
617 * @retval None
618 */
619 __weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim)
620 {
621 /* NOTE: This function should not be modified, when the callback is needed,
622 the HAL_HRTIM_MspDeInit could be implemented in the user file
623 */
624 }
625
626 /**
627 * @brief Starts the DLL calibration
628 * @param hhrtim: pointer to HAL HRTIM handle
629 * @param CalibrationRate: DLL calibration period
630 * This parameter can be one of the following values:
631 * @arg HRTIM_SINGLE_CALIBRATION: One shot DLL calibration
632 * @arg HRTIM_CALIBRATIONRATE_7300: Periodic DLL calibration. T=7.3 ms
633 * @arg HRTIM_CALIBRATIONRATE_910: Periodic DLL calibration. T=910 us
634 * @arg HRTIM_CALIBRATIONRATE_114: Periodic DLL calibration. T=114 us
635 * @arg HRTIM_CALIBRATIONRATE_14: Periodic DLL calibration. T=14 us
636 * @retval HAL status
637 * @note This function locks the HRTIM instance. HRTIM instance is unlocked
638 * within the HAL_HRTIM_PollForDLLCalibration function, just before
639 * exiting the function.
640 */
641 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef * hhrtim,
642 uint32_t CalibrationRate)
643 {
644 uint32_t hrtim_dllcr;
645
646 /* Check the parameters */
647 assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
648
649 /* Process Locked */
650 __HAL_LOCK(hhrtim);
651
652 hhrtim->State = HAL_HRTIM_STATE_BUSY;
653
654 /* Configure DLL Calibration */
655 hrtim_dllcr = hhrtim->Instance->sCommonRegs.DLLCR;
656
657 if (CalibrationRate == HRTIM_SINGLE_CALIBRATION)
658 {
659 /* One shot DLL calibration */
660 hrtim_dllcr &= ~(HRTIM_DLLCR_CALEN);
661 hrtim_dllcr |= HRTIM_DLLCR_CAL;
662 }
663 else
664 {
665 /* Periodic DLL calibration */
666 hrtim_dllcr &= ~(HRTIM_DLLCR_CALRTE | HRTIM_DLLCR_CAL);
667 hrtim_dllcr |= (CalibrationRate | HRTIM_DLLCR_CALEN);
668 }
669
670 /* Update HRTIM register */
671 hhrtim->Instance->sCommonRegs.DLLCR = hrtim_dllcr;
672
673 return HAL_OK;
674 }
675
676 /**
677 * @brief Starts the DLL calibration
678 * DLL ready interrupt is enabled
679 * @param hhrtim: pointer to HAL HRTIM handle
680 * @param CalibrationRate: DLL calibration period
681 * This parameter can be one of the following values:
682 * @arg HRTIM_SINGLE_CALIBRATION: One shot DLL calibration
683 * @arg HRTIM_CALIBRATIONRATE_7300: Periodic DLL calibration. T=7.3 ms
684 * @arg HRTIM_CALIBRATIONRATE_910: Periodic DLL calibration. T=910 us
685 * @arg HRTIM_CALIBRATIONRATE_114: Periodic DLL calibration. T=114 us
686 * @arg HRTIM_CALIBRATIONRATE_14: Periodic DLL calibration. T=14 us
687 * @retval HAL status
688 * @note This function locks the HRTIM instance. HRTIM instance is unlocked
689 * within the IRQ processing function when processing the DLL ready
690 * interrupt.
691 * @note If this function is called for periodic calibration, the DLLRDY
692 * interrupt is generated every time the calibration completes which
693 * will significantly increases the overall interrupt rate.
694 */
695 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef * hhrtim,
696 uint32_t CalibrationRate)
697 {
698 uint32_t hrtim_dllcr;
699
700 /* Check the parameters */
701 assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
702
703 /* Process Locked */
704 __HAL_LOCK(hhrtim);
705
706 hhrtim->State = HAL_HRTIM_STATE_BUSY;
707
708 /* Enable DLL Ready interrupt flag */
709 __HAL_HRTIM_ENABLE_IT(hhrtim, HRTIM_IT_DLLRDY);
710
711 /* Configure DLL Calibration */
712 hrtim_dllcr = hhrtim->Instance->sCommonRegs.DLLCR;
713
714 if (CalibrationRate == HRTIM_SINGLE_CALIBRATION)
715 {
716 /* One shot DLL calibration */
717 hrtim_dllcr &= ~(HRTIM_DLLCR_CALEN);
718 hrtim_dllcr |= HRTIM_DLLCR_CAL;
719 }
720 else
721 {
722 /* Periodic DLL calibration */
723 hrtim_dllcr &= ~(HRTIM_DLLCR_CALRTE | HRTIM_DLLCR_CAL);
724 hrtim_dllcr |= (CalibrationRate | HRTIM_DLLCR_CALEN);
725 }
726
727 /* Update HRTIM register */
728 hhrtim->Instance->sCommonRegs.DLLCR = hrtim_dllcr;
729
730 return HAL_OK;
731 }
732
733 /**
734 * @brief Polls the DLL calibration ready flag and returns when the flag is
735 * set (DLL calibration completed) or upon timeout expiration
736 * @param hhrtim: pointer to HAL HRTIM handle
737 * @param Timeout: Timeout duration in millisecond
738 * @retval HAL status
739 */
740 HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef * hhrtim,
741 uint32_t Timeout)
742 {
743 uint32_t tickstart=0;
744
745 tickstart = HAL_GetTick();
746
747 /* Check End of conversion flag */
748 while(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_IT_DLLRDY) == RESET)
749 {
750 if (Timeout != HAL_MAX_DELAY)
751 {
752 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
753 {
754 hhrtim->State = HAL_HRTIM_STATE_ERROR;
755 return HAL_TIMEOUT;
756 }
757 }
758 }
759
760 /* Set HRTIM State */
761 hhrtim->State = HAL_HRTIM_STATE_READY;
762
763 /* Process unlocked */
764 __HAL_UNLOCK(hhrtim);
765
766 return HAL_OK;
767 }
768
769 /**
770 * @brief Configures the time base unit of a timer
771 * @param hhrtim: pointer to HAL HRTIM handle
772 * @param TimerIdx: Timer index
773 * This parameter can be one of the following values:
774 * @arg HRTIM_TIMERINDEX_MASTER for master timer
775 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
776 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
777 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
778 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
779 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
780 * @param pTimeBaseCfg: pointer to the time base configuration structure
781 * @note This function must be called prior starting the timer
782 * @note The time-base unit initialization parameters specify:
783 * The timer counter operating mode (continuous, one shot)
784 * The timer clock prescaler
785 * The timer period
786 * The timer repetition counter.
787 * @retval HAL status
788 */
789 HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
790 uint32_t TimerIdx,
791 HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
792 {
793 /* Check the parameters */
794 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
795 assert_param(IS_HRTIM_PRESCALERRATIO(pTimeBaseCfg->PrescalerRatio));
796 assert_param(IS_HRTIM_MODE(pTimeBaseCfg->Mode));
797
798 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
799 {
800 return HAL_BUSY;
801 }
802
803 /* Set the HRTIM state */
804 hhrtim->State = HAL_HRTIM_STATE_BUSY;
805
806 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
807 {
808 /* Configure master timer time base unit */
809 HRTIM_MasterBase_Config(hhrtim, pTimeBaseCfg);
810 }
811 else
812 {
813 /* Configure timing unit time base unit */
814 HRTIM_TimingUnitBase_Config(hhrtim, TimerIdx, pTimeBaseCfg);
815 }
816
817 /* Set HRTIM state */
818 hhrtim->State = HAL_HRTIM_STATE_READY;
819
820 return HAL_OK;
821 }
822
823 /**
824 * @}
825 */
826
827 /** @defgroup HRTIM_Exported_Functions_Group2 Simple time base mode functions
828 * @brief When à HRTIM timer operates in simple time base mode, the
829 * timer counter counts from 0 to the period value.
830 *
831 @verbatim
832 ===============================================================================
833 ##### Simple time base mode functions #####
834 ===============================================================================
835 [..] This section provides functions allowing to:
836 (+) Start simple time base
837 (+) Stop simple time base
838 (+) Start simple time base and enable interrupt
839 (+) Stop simple time base and disable interrupt
840 (+) Start simple time base and enable DMA transfer
841 (+) Stop simple time base and disable DMA transfer
842
843 @endverbatim
844 * @{
845 */
846
847 /**
848 * @brief Starts the counter of a timer operating in basic time base mode
849 * @param hhrtim: pointer to HAL HRTIM handle
850 * @param TimerIdx: Timer index
851 * This parameter can be one of the following values:
852 * @arg HRTIM_TIMERINDEX_MASTER for master timer
853 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
854 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
855 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
856 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
857 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
858 * @retval HAL status
859 */
860 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim,
861 uint32_t TimerIdx)
862 {
863 /* Check the parameters */
864 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
865
866 /* Process Locked */
867 __HAL_LOCK(hhrtim);
868
869 hhrtim->State = HAL_HRTIM_STATE_BUSY;
870
871 /* Enable the timer counter */
872 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
873
874 hhrtim->State = HAL_HRTIM_STATE_READY;
875
876 /* Process Unlocked */
877 __HAL_UNLOCK(hhrtim);
878
879 return HAL_OK;
880 }
881
882 /**
883 * @brief Stops the counter of a timer operating in basic time base mode
884 * @param hhrtim: pointer to HAL HRTIM handle
885 * @param TimerIdx: Timer index
886 * This parameter can be one of the following values:
887 * @arg HRTIM_TIMERINDEX_MASTER for master timer
888 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
889 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
890 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
891 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
892 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
893 * @retval HAL status
894 */
895 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim,
896 uint32_t TimerIdx)
897 {
898 /* Check the parameters */
899 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
900
901 /* Process Locked */
902 __HAL_LOCK(hhrtim);
903
904 hhrtim->State = HAL_HRTIM_STATE_BUSY;
905
906 /* Disable the timer counter */
907 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
908
909 hhrtim->State = HAL_HRTIM_STATE_READY;
910
911 /* Process Unlocked */
912 __HAL_UNLOCK(hhrtim);
913
914 return HAL_OK;
915 }
916
917 /**
918 * @brief Starts the counter of a timer operating in basic time base mode
919 * Timer repetition interrupt is enabled.
920 * @param hhrtim: pointer to HAL HRTIM handle
921 * @param TimerIdx: Timer index
922 * This parameter can be one of the following values:
923 * @arg HRTIM_TIMERINDEX_MASTER for master timer
924 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
925 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
926 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
927 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
928 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
929 * @retval HAL status
930 */
931 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim,
932 uint32_t TimerIdx)
933 {
934 /* Check the parameters */
935 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
936
937 /* Process Locked */
938 __HAL_LOCK(hhrtim);
939
940 hhrtim->State = HAL_HRTIM_STATE_BUSY;
941
942 /* Enable the repetition interrupt */
943 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
944 {
945 __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
946 }
947 else
948 {
949 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
950 }
951
952 /* Enable the timer counter */
953 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
954
955 hhrtim->State = HAL_HRTIM_STATE_READY;
956
957 /* Process Unlocked */
958 __HAL_UNLOCK(hhrtim);
959
960 return HAL_OK;
961 }
962
963 /**
964 * @brief Starts the counter of a timer operating in basic time base mode
965 * Timer repetition interrupt is disabled.
966 * @param hhrtim: pointer to HAL HRTIM handle
967 * @param TimerIdx: Timer index
968 * This parameter can be one of the following values:
969 * @arg HRTIM_TIMERINDEX_MASTER for master timer
970 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
971 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
972 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
973 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
974 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
975 * @retval HAL status
976 */
977 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim,
978 uint32_t TimerIdx)
979 {
980 /* Check the parameters */
981 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
982
983 /* Process Locked */
984 __HAL_LOCK(hhrtim);
985
986 hhrtim->State = HAL_HRTIM_STATE_BUSY;
987
988 /* Disable the repetition interrupt */
989 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
990 {
991 __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
992 }
993 else
994 {
995 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
996 }
997
998 /* Disable the timer counter */
999 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1000
1001 hhrtim->State = HAL_HRTIM_STATE_READY;
1002
1003 /* Process Unlocked */
1004 __HAL_UNLOCK(hhrtim);
1005
1006 return HAL_OK;
1007 }
1008
1009 /**
1010 * @brief Starts the counter of a timer operating in basic time base mode
1011 * Timer repetition DMA request is enabled.
1012 * @param hhrtim: pointer to HAL HRTIM handle
1013 * @param TimerIdx: Timer index
1014 * This parameter can be one of the following values:
1015 * @arg HRTIM_TIMERINDEX_MASTER for master timer
1016 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1017 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1018 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1019 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1020 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1021 * @param SrcAddr: DMA transfer source address
1022 * @param DestAddr: DMA transfer destination address
1023 * @param Length: The length of data items (data size) to be transferred
1024 * from source to destination
1025 */
1026 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim,
1027 uint32_t TimerIdx,
1028 uint32_t SrcAddr,
1029 uint32_t DestAddr,
1030 uint32_t Length)
1031 {
1032 DMA_HandleTypeDef * hdma;
1033
1034 /* Check the parameters */
1035 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1036
1037 if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
1038 {
1039 return HAL_BUSY;
1040 }
1041 if((hhrtim->State == HAL_HRTIM_STATE_READY))
1042 {
1043 if((SrcAddr == 0 ) || (DestAddr == 0 ) || (Length == 0))
1044 {
1045 return HAL_ERROR;
1046 }
1047 else
1048 {
1049 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1050 }
1051 }
1052
1053 /* Process Locked */
1054 __HAL_LOCK(hhrtim);
1055
1056 /* Get the timer DMA handler */
1057 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1058
1059 /* Set the DMA transfer completed callback */
1060 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1061 {
1062 hdma->XferCpltCallback = HRTIM_DMAMasterCplt;
1063 }
1064 else
1065 {
1066 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
1067 }
1068
1069 /* Set the DMA error callback */
1070 hdma->XferErrorCallback = HRTIM_DMAError ;
1071
1072 /* Enable the DMA channel */
1073 HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length);
1074
1075 /* Enable the timer repetition DMA request */
1076 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1077 {
1078 __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
1079 }
1080 else
1081 {
1082 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
1083 }
1084
1085 /* Enable the timer counter */
1086 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1087
1088 hhrtim->State = HAL_HRTIM_STATE_READY;
1089
1090 /* Process Unlocked */
1091 __HAL_UNLOCK(hhrtim);
1092
1093 return HAL_OK;
1094 }
1095
1096 /**
1097 * @brief Starts the counter of a timer operating in basic time base mode
1098 * Timer repetition DMA request is disabled.
1099 * @param hhrtim: pointer to HAL HRTIM handle
1100 * @param TimerIdx: Timer index
1101 * This parameter can be one of the following values:
1102 * @arg HRTIM_TIMERINDEX_MASTER for master timer
1103 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1104 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1105 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1106 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1107 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1108 * @retval HAL status
1109 */
1110 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim,
1111 uint32_t TimerIdx)
1112 {
1113 DMA_HandleTypeDef * hdma;
1114
1115 /* Check the parameters */
1116 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1117
1118 /* Process Locked */
1119 __HAL_LOCK(hhrtim);
1120
1121 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1122 {
1123 /* Disable the DMA */
1124 HAL_DMA_Abort(hhrtim->hdmaMaster);
1125
1126 /* Disable the timer repetition DMA request */
1127 __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
1128 }
1129 else
1130 {
1131 /* Get the timer DMA handler */
1132 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1133
1134 /* Disable the DMA */
1135 HAL_DMA_Abort(hdma);
1136
1137 /* Disable the timer repetition DMA request */
1138 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
1139 }
1140
1141 /* Disable the timer counter */
1142 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1143
1144 hhrtim->State = HAL_HRTIM_STATE_READY;
1145
1146 /* Process Unlocked */
1147 __HAL_UNLOCK(hhrtim);
1148
1149 return HAL_OK;
1150 }
1151
1152 /**
1153 * @}
1154 */
1155
1156 /** @defgroup HRTIM_Exported_Functions_Group3 Simple output compare mode functions
1157 * @brief When a HRTIM timer operates in simple output compare mode
1158 * the output level is set to a programmable value when a match
1159 * is found between the compare register and the counter.
1160 * Compare unit 1 is automatically associated to output 1
1161 * Compare unit 2 is automatically associated to output 2
1162 *
1163 @verbatim
1164 ===============================================================================
1165 ##### Simple output compare functions #####
1166 ===============================================================================
1167 [..] This section provides functions allowing to:
1168 (+) Configure simple output channel
1169 (+) Start simple output compare
1170 (+) Stop simple output compare
1171 (+) Start simple output compare and enable interrupt
1172 (+) Stop simple output compare and disable interrupt
1173 (+) Start simple output compare and enable DMA transfer
1174 (+) Stop simple output compare and disable DMA transfer
1175
1176 @endverbatim
1177 * @{
1178 */
1179
1180 /**
1181 * @brief Configures an output in basic output compare mode
1182 * @param hhrtim: pointer to HAL HRTIM handle
1183 * @param TimerIdx: Timer index
1184 * This parameter can be one of the following values:
1185 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1186 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1187 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1188 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1189 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1190 * @param OCChannel: Timer output
1191 * This parameter can be one of the following values:
1192 * @arg HRTIM_OUTPUT_TA1: Timer A - Ouput 1
1193 * @arg HRTIM_OUTPUT_TA2: Timer A - Ouput 2
1194 * @arg HRTIM_OUTPUT_TB1: Timer B - Ouput 1
1195 * @arg HRTIM_OUTPUT_TB2: Timer B - Ouput 2
1196 * @arg HRTIM_OUTPUT_TC1: Timer C - Ouput 1
1197 * @arg HRTIM_OUTPUT_TC2: Timer C - Ouput 2
1198 * @arg HRTIM_OUTPUT_TD1: Timer D - Ouput 1
1199 * @arg HRTIM_OUTPUT_TD2: Timer D - Ouput 2
1200 * @arg HRTIM_OUTPUT_TE1: Timer E - Ouput 1
1201 * @arg HRTIM_OUTPUT_TE2: Timer E - Ouput 2
1202 * @param pSimpleOCChannelCfg: pointer to the basic output compare output configuration structure
1203 * @note When the timer operates in basic output compare mode:
1204 * Output 1 is implicitely controled by the compare unit 1
1205 * Output 2 is implicitely controled by the compare unit 2
1206 * Output Set/Reset crossbar is set according to the selected output compare mode:
1207 * Toggle: SETxyR = RSTxyR = CMPy
1208 * Active: SETxyR = CMPy, RSTxyR = 0
1209 * Inactive: SETxy =0, RSTxy = CMPy
1210 * @retval HAL status
1211 */
1212 HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim,
1213 uint32_t TimerIdx,
1214 uint32_t OCChannel,
1215 HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg)
1216 {
1217 uint32_t CompareUnit = 0xFFFFFFFF;
1218 HRTIM_CompareCfgTypeDef CompareCfg;
1219 HRTIM_OutputCfgTypeDef OutputCfg;
1220
1221 /* Check parameters */
1222 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1223 assert_param(IS_HRTIM_BASICOCMODE(pSimpleOCChannelCfg->Mode));
1224 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOCChannelCfg->Polarity));
1225 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOCChannelCfg->IdleLevel));
1226
1227 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
1228 {
1229 return HAL_BUSY;
1230 }
1231
1232 /* Set HRTIM state */
1233 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1234
1235 /* Configure timer compare unit */
1236 switch (OCChannel)
1237 {
1238 case HRTIM_OUTPUT_TA1:
1239 case HRTIM_OUTPUT_TB1:
1240 case HRTIM_OUTPUT_TC1:
1241 case HRTIM_OUTPUT_TD1:
1242 case HRTIM_OUTPUT_TE1:
1243 {
1244 CompareUnit = HRTIM_COMPAREUNIT_1;
1245 }
1246 break;
1247 case HRTIM_OUTPUT_TA2:
1248 case HRTIM_OUTPUT_TB2:
1249 case HRTIM_OUTPUT_TC2:
1250 case HRTIM_OUTPUT_TD2:
1251 case HRTIM_OUTPUT_TE2:
1252 {
1253 CompareUnit = HRTIM_COMPAREUNIT_2;
1254 }
1255 break;
1256 }
1257
1258 CompareCfg.CompareValue = pSimpleOCChannelCfg->Pulse;
1259 CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
1260 CompareCfg.AutoDelayedTimeout = 0;
1261
1262 HRTIM_CompareUnitConfig(hhrtim,
1263 TimerIdx,
1264 CompareUnit,
1265 &CompareCfg);
1266
1267 /* Configure timer output */
1268 OutputCfg.Polarity = pSimpleOCChannelCfg->Polarity;
1269 OutputCfg.IdleLevel = pSimpleOCChannelCfg->IdleLevel;
1270 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
1271 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
1272 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
1273 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
1274
1275 switch (pSimpleOCChannelCfg->Mode)
1276 {
1277 case HRTIM_BASICOCMODE_TOGGLE:
1278 {
1279 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1280 {
1281 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1282 }
1283 else
1284 {
1285 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1286 }
1287 OutputCfg.ResetSource = OutputCfg.SetSource;
1288 }
1289 break;
1290 case HRTIM_BASICOCMODE_ACTIVE:
1291 {
1292 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1293 {
1294 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1295 }
1296 else
1297 {
1298 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1299 }
1300 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
1301 }
1302 break;
1303 case HRTIM_BASICOCMODE_INACTIVE:
1304 {
1305 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1306 {
1307 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP1;
1308 }
1309 else
1310 {
1311 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP2;
1312 }
1313 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
1314 }
1315 break;
1316 }
1317
1318 HRTIM_OutputConfig(hhrtim,
1319 TimerIdx,
1320 OCChannel,
1321 &OutputCfg);
1322
1323 /* Set HRTIM state */
1324 hhrtim->State = HAL_HRTIM_STATE_READY;
1325
1326 return HAL_OK;
1327 }
1328
1329 /**
1330 * @brief Starts the output compare signal generation on the designed timer output
1331 * @param hhrtim: pointer to HAL HRTIM handle
1332 * @param TimerIdx: Timer index
1333 * This parameter can be one of the following values:
1334 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1335 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1336 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1337 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1338 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1339 * @param OCChannel: Timer output
1340 * This parameter can be one of the following values:
1341 * @arg HRTIM_OUTPUT_TA1: Timer A - Ouput 1
1342 * @arg HRTIM_OUTPUT_TA2: Timer A - Ouput 2
1343 * @arg HRTIM_OUTPUT_TB1: Timer B - Ouput 1
1344 * @arg HRTIM_OUTPUT_TB2: Timer B - Ouput 2
1345 * @arg HRTIM_OUTPUT_TC1: Timer C - Ouput 1
1346 * @arg HRTIM_OUTPUT_TC2: Timer C - Ouput 2
1347 * @arg HRTIM_OUTPUT_TD1: Timer D - Ouput 1
1348 * @arg HRTIM_OUTPUT_TD2: Timer D - Ouput 2
1349 * @arg HRTIM_OUTPUT_TE1: Timer E - Ouput 1
1350 * @arg HRTIM_OUTPUT_TE2: Timer E - Ouput 2
1351 * @retval HAL status
1352 */
1353 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim,
1354 uint32_t TimerIdx,
1355 uint32_t OCChannel)
1356 {
1357 /* Check the parameters */
1358 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1359
1360 /* Process Locked */
1361 __HAL_LOCK(hhrtim);
1362
1363 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1364
1365 /* Enable the timer output */
1366 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1367
1368 /* Enable the timer counter */
1369 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1370
1371 hhrtim->State = HAL_HRTIM_STATE_READY;
1372
1373 /* Process Unlocked */
1374 __HAL_UNLOCK(hhrtim);
1375
1376 return HAL_OK;
1377 }
1378
1379 /**
1380 * @brief Stops the output compare signal generation on the designed timer output
1381 * @param hhrtim: pointer to HAL HRTIM handle
1382 * @param TimerIdx: Timer index
1383 * This parameter can be one of the following values:
1384 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1385 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1386 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1387 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1388 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1389 * @param OCChannel: Timer output
1390 * This parameter can be one of the following values:
1391 * @arg HRTIM_OUTPUT_TA1: Timer A - Ouput 1
1392 * @arg HRTIM_OUTPUT_TA2: Timer A - Ouput 2
1393 * @arg HRTIM_OUTPUT_TB1: Timer B - Ouput 1
1394 * @arg HRTIM_OUTPUT_TB2: Timer B - Ouput 2
1395 * @arg HRTIM_OUTPUT_TC1: Timer C - Ouput 1
1396 * @arg HRTIM_OUTPUT_TC2: Timer C - Ouput 2
1397 * @arg HRTIM_OUTPUT_TD1: Timer D - Ouput 1
1398 * @arg HRTIM_OUTPUT_TD2: Timer D - Ouput 2
1399 * @arg HRTIM_OUTPUT_TE1: Timer E - Ouput 1
1400 * @arg HRTIM_OUTPUT_TE2: Timer E - Ouput 2
1401 * @retval HAL status
1402 */
1403 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim,
1404 uint32_t TimerIdx,
1405 uint32_t OCChannel)
1406 {
1407 /* Check the parameters */
1408 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1409
1410 /* Process Locked */
1411 __HAL_LOCK(hhrtim);
1412
1413 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1414
1415 /* Disable the timer output */
1416 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1417
1418 /* Disable the timer counter */
1419 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1420
1421 hhrtim->State = HAL_HRTIM_STATE_READY;
1422
1423 /* Process Unlocked */
1424 __HAL_UNLOCK(hhrtim);
1425
1426 return HAL_OK;
1427 }
1428
1429 /**
1430 * @brief Starts the output compare signal generation on the designed timer output
1431 * Interrupt is enabled (see note below)
1432 * @param hhrtim: pointer to HAL HRTIM handle
1433 * @param TimerIdx: Timer index
1434 * This parameter can be one of the following values:
1435 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1436 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1437 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1438 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1439 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1440 * @param OCChannel: Timer output
1441 * This parameter can be one of the following values:
1442 * @arg HRTIM_OUTPUT_TA1: Timer A - Ouput 1
1443 * @arg HRTIM_OUTPUT_TA2: Timer A - Ouput 2
1444 * @arg HRTIM_OUTPUT_TB1: Timer B - Ouput 1
1445 * @arg HRTIM_OUTPUT_TB2: Timer B - Ouput 2
1446 * @arg HRTIM_OUTPUT_TC1: Timer C - Ouput 1
1447 * @arg HRTIM_OUTPUT_TC2: Timer C - Ouput 2
1448 * @arg HRTIM_OUTPUT_TD1: Timer D - Ouput 1
1449 * @arg HRTIM_OUTPUT_TD2: Timer D - Ouput 2
1450 * @arg HRTIM_OUTPUT_TE1: Timer E - Ouput 1
1451 * @arg HRTIM_OUTPUT_TE2: Timer E - Ouput 2
1452 * @note Interrupt enabling depends on the chosen output compare mode
1453 * Output toggle: compare match interrupt is enabled
1454 * Output set active: output set interrupt is enabled
1455 * Output set inactive: output reset interrupt is enabled
1456 * @retval HAL status
1457 */
1458 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim,
1459 uint32_t TimerIdx,
1460 uint32_t OCChannel)
1461 {
1462 uint32_t interrupt;
1463
1464 /* Check the parameters */
1465 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1466
1467 /* Process Locked */
1468 __HAL_LOCK(hhrtim);
1469
1470 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1471
1472 /* Get the interrupt to enable (depends on the output compare mode) */
1473 interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
1474
1475 /* Enable the timer output */
1476 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1477
1478 /* Enable the timer interrupt (depends on the output compare mode) */
1479 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, interrupt);
1480
1481 /* Enable the timer counter */
1482 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1483
1484 hhrtim->State = HAL_HRTIM_STATE_READY;
1485
1486 /* Process Unlocked */
1487 __HAL_UNLOCK(hhrtim);
1488
1489 return HAL_OK;
1490 }
1491
1492 /**
1493 * @brief Stops the output compare signal generation on the designed timer output
1494 * Interrupt is disabled
1495 * @param hhrtim: pointer to HAL HRTIM handle
1496 * @param TimerIdx: Timer index
1497 * This parameter can be one of the following values:
1498 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1499 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1500 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1501 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1502 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1503 * @param OCChannel: Timer output
1504 * This parameter can be one of the following values:
1505 * @arg HRTIM_OUTPUT_TA1: Timer A - Ouput 1
1506 * @arg HRTIM_OUTPUT_TA2: Timer A - Ouput 2
1507 * @arg HRTIM_OUTPUT_TB1: Timer B - Ouput 1
1508 * @arg HRTIM_OUTPUT_TB2: Timer B - Ouput 2
1509 * @arg HRTIM_OUTPUT_TC1: Timer C - Ouput 1
1510 * @arg HRTIM_OUTPUT_TC2: Timer C - Ouput 2
1511 * @arg HRTIM_OUTPUT_TD1: Timer D - Ouput 1
1512 * @arg HRTIM_OUTPUT_TD2: Timer D - Ouput 2
1513 * @arg HRTIM_OUTPUT_TE1: Timer E - Ouput 1
1514 * @arg HRTIM_OUTPUT_TE2: Timer E - Ouput 2
1515 * @retval HAL status
1516 */
1517 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim,
1518 uint32_t TimerIdx,
1519 uint32_t OCChannel)
1520 {
1521 uint32_t interrupt;
1522
1523 /* Check the parameters */
1524 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1525
1526 /* Process Locked */
1527 __HAL_LOCK(hhrtim);
1528
1529 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1530
1531 /* Disable the timer output */
1532 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1533
1534 /* Get the interrupt to disable (depends on the output compare mode) */
1535 interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
1536
1537 /* Disable the timer interrupt */
1538 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, interrupt);
1539
1540 /* Disable the timer counter */
1541 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1542
1543 hhrtim->State = HAL_HRTIM_STATE_READY;
1544
1545 /* Process Unlocked */
1546 __HAL_UNLOCK(hhrtim);
1547
1548 return HAL_OK;
1549 }
1550
1551 /**
1552 * @brief Starts the output compare signal generation on the designed timer output
1553 * DMA request is enabled (see note below)
1554 * @param hhrtim: pointer to HAL HRTIM handle
1555 * @param TimerIdx: Timer index
1556 * This parameter can be one of the following values:
1557 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1558 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1559 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1560 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1561 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1562 * @param OCChannel: Timer output
1563 * This parameter can be one of the following values:
1564 * @arg HRTIM_OUTPUT_TA1: Timer A - Ouput 1
1565 * @arg HRTIM_OUTPUT_TA2: Timer A - Ouput 2
1566 * @arg HRTIM_OUTPUT_TB1: Timer B - Ouput 1
1567 * @arg HRTIM_OUTPUT_TB2: Timer B - Ouput 2
1568 * @arg HRTIM_OUTPUT_TC1: Timer C - Ouput 1
1569 * @arg HRTIM_OUTPUT_TC2: Timer C - Ouput 2
1570 * @arg HRTIM_OUTPUT_TD1: Timer D - Ouput 1
1571 * @arg HRTIM_OUTPUT_TD2: Timer D - Ouput 2
1572 * @arg HRTIM_OUTPUT_TE1: Timer E - Ouput 1
1573 * @arg HRTIM_OUTPUT_TE2: Timer E - Ouput 2
1574 * @param SrcAddr: DMA transfer source address
1575 * @param DestAddr: DMA transfer destination address
1576 * @param Length: The length of data items (data size) to be transferred
1577 * from source to destination
1578 * @note DMA request enabling depends on the chosen output compare mode
1579 * Output toggle: compare match DMA request is enabled
1580 * Output set active: output set DMA request is enabled
1581 * Output set inactive: output reset DMA request is enabled
1582 * @retval HAL status
1583 */
1584 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim,
1585 uint32_t TimerIdx,
1586 uint32_t OCChannel,
1587 uint32_t SrcAddr,
1588 uint32_t DestAddr,
1589 uint32_t Length)
1590 {
1591 DMA_HandleTypeDef * hdma;
1592 uint32_t dma_request;
1593
1594 /* Check the parameters */
1595 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1596
1597 if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
1598 {
1599 return HAL_BUSY;
1600 }
1601 if((hhrtim->State == HAL_HRTIM_STATE_READY))
1602 {
1603 if((SrcAddr == 0 ) || (DestAddr == 0 ) || (Length == 0))
1604 {
1605 return HAL_ERROR;
1606 }
1607 else
1608 {
1609 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1610 }
1611 }
1612
1613 /* Process Locked */
1614 __HAL_LOCK(hhrtim);
1615
1616 /* Enable the timer output */
1617 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1618
1619 /* Get the DMA request to enable */
1620 dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
1621
1622 /* Get the timer DMA handler */
1623 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1624
1625 /* Set the DMA error callback */
1626 hdma->XferErrorCallback = HRTIM_DMAError ;
1627
1628 /* Set the DMA transfer completed callback */
1629 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
1630
1631 /* Enable the DMA channel */
1632 HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length);
1633
1634 /* Enable the timer DMA request */
1635 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, dma_request);
1636
1637 /* Enable the timer counter */
1638 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1639
1640 hhrtim->State = HAL_HRTIM_STATE_READY;
1641
1642 /* Process Unlocked */
1643 __HAL_UNLOCK(hhrtim);
1644
1645 return HAL_OK;
1646 }
1647
1648 /**
1649 * @brief Stops the output compare signal generation on the designed timer output
1650 * DMA request is disabled
1651 * @param hhrtim: pointer to HAL HRTIM handle
1652 * @param TimerIdx: Timer index
1653 * This parameter can be one of the following values:
1654 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1655 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1656 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1657 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1658 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1659 * @param OCChannel: Timer output
1660 * This parameter can be one of the following values:
1661 * @arg HRTIM_OUTPUT_TA1: Timer A - Ouput 1
1662 * @arg HRTIM_OUTPUT_TA2: Timer A - Ouput 2
1663 * @arg HRTIM_OUTPUT_TB1: Timer B - Ouput 1
1664 * @arg HRTIM_OUTPUT_TB2: Timer B - Ouput 2
1665 * @arg HRTIM_OUTPUT_TC1: Timer C - Ouput 1
1666 * @arg HRTIM_OUTPUT_TC2: Timer C - Ouput 2
1667 * @arg HRTIM_OUTPUT_TD1: Timer D - Ouput 1
1668 * @arg HRTIM_OUTPUT_TD2: Timer D - Ouput 2
1669 * @arg HRTIM_OUTPUT_TE1: Timer E - Ouput 1
1670 * @arg HRTIM_OUTPUT_TE2: Timer E - Ouput 2
1671 * @retval HAL status
1672 */
1673 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim,
1674 uint32_t TimerIdx,
1675 uint32_t OCChannel)
1676 {
1677 DMA_HandleTypeDef * hdma;
1678 uint32_t dma_request;
1679
1680 /* Check the parameters */
1681 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1682
1683 /* Process Locked */
1684 __HAL_LOCK(hhrtim);
1685
1686 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1687
1688 /* Disable the timer output */
1689 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1690
1691 /* Get the timer DMA handler */
1692 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1693
1694 /* Disable the DMA */
1695 HAL_DMA_Abort(hdma);
1696
1697 /* Get the DMA request to disable */
1698 dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
1699
1700 /* Disable the timer DMA request */
1701 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, dma_request);
1702
1703 /* Disable the timer counter */
1704 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1705
1706 hhrtim->State = HAL_HRTIM_STATE_READY;
1707
1708 /* Process Unlocked */
1709 __HAL_UNLOCK(hhrtim);
1710
1711 return HAL_OK;
1712 }
1713
1714 /**
1715 * @}
1716 */
1717
1718 /** @defgroup HRTIM_Exported_Functions_Group4 Simple PWM output mode functions
1719 * @brief When a HRTIM timer operates in simple PWM output mode
1720 * the output level is set to a programmable value when a match is
1721 * found between the compare register and the counter and reset when
1722 * the timer period is reached. Duty cycle is determined by the
1723 * comparison value.
1724 * Compare unit 1 is automatically associated to output 1
1725 * Compare unit 2 is automatically associated to output 2
1726 *
1727 @verbatim
1728 ===============================================================================
1729 ##### Simple PWM output functions #####
1730 ===============================================================================
1731 [..] This section provides functions allowing to:
1732 (+) Configure simple PWM output channel
1733 (+) Start simple PWM output
1734 (+) Stop simple PWM output
1735 (+) Start simple PWM output and enable interrupt
1736 (+) Stop simple PWM output and disable interrupt
1737 (+) Start simple PWM output and enable DMA transfer
1738 (+) Stop simple PWM output and disable DMA transfer
1739
1740 @endverbatim
1741 * @{
1742 */
1743
1744 /**
1745 * @brief Configures an output in basic PWM mode
1746 * @param hhrtim: pointer to HAL HRTIM handle
1747 * @param TimerIdx: Timer index
1748 * This parameter can be one of the following values:
1749 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1750 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1751 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1752 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1753 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1754 * @param PWMChannel: Timer output
1755 * This parameter can be one of the following values:
1756 * @arg HRTIM_OUTPUT_TA1: Timer A - Ouput 1
1757 * @arg HRTIM_OUTPUT_TA2: Timer A - Ouput 2
1758 * @arg HRTIM_OUTPUT_TB1: Timer B - Ouput 1
1759 * @arg HRTIM_OUTPUT_TB2: Timer B - Ouput 2
1760 * @arg HRTIM_OUTPUT_TC1: Timer C - Ouput 1
1761 * @arg HRTIM_OUTPUT_TC2: Timer C - Ouput 2
1762 * @arg HRTIM_OUTPUT_TD1: Timer D - Ouput 1
1763 * @arg HRTIM_OUTPUT_TD2: Timer D - Ouput 2
1764 * @arg HRTIM_OUTPUT_TE1: Timer E - Ouput 1
1765 * @arg HRTIM_OUTPUT_TE2: Timer E - Ouput 2
1766 * @param pSimplePWMChannelCfg: pointer to the basic PWM output configuration structure
1767 * @note When the timer operates in basic PWM output mode:
1768 * Output 1 is implicitely controled by the compare unit 1
1769 * Output 2 is implicitely controled by the compare unit 2
1770 * Output Set/Reset crossbar is set as follows:
1771 * Ouput 1: SETx1R = CMP1, RSTx1R = PER
1772 * Output 2: SETx2R = CMP2, RST2R = PER
1773 * @note When Simple PWM mode is used the registers preload mechanism is
1774 * enabled (otherwise the behavior is not guaranteed).
1775 * @retval HAL status
1776 */
1777 HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim,
1778 uint32_t TimerIdx,
1779 uint32_t PWMChannel,
1780 HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg)
1781 {
1782 uint32_t CompareUnit = 0xFFFFFFFF;
1783 HRTIM_CompareCfgTypeDef CompareCfg;
1784 HRTIM_OutputCfgTypeDef OutputCfg;
1785 uint32_t hrtim_timcr;
1786
1787 /* Check parameters */
1788 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
1789 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimplePWMChannelCfg->Polarity));
1790 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimplePWMChannelCfg->IdleLevel));
1791
1792 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
1793 {
1794 return HAL_BUSY;
1795 }
1796
1797 /* Process Locked */
1798 __HAL_LOCK(hhrtim); hhrtim->State = HAL_HRTIM_STATE_BUSY;
1799
1800 /* Configure timer compare unit */
1801 switch (PWMChannel)
1802 {
1803 case HRTIM_OUTPUT_TA1:
1804 case HRTIM_OUTPUT_TB1:
1805 case HRTIM_OUTPUT_TC1:
1806 case HRTIM_OUTPUT_TD1:
1807 case HRTIM_OUTPUT_TE1:
1808 {
1809 CompareUnit = HRTIM_COMPAREUNIT_1;
1810 }
1811 break;
1812 case HRTIM_OUTPUT_TA2:
1813 case HRTIM_OUTPUT_TB2:
1814 case HRTIM_OUTPUT_TC2:
1815 case HRTIM_OUTPUT_TD2:
1816 case HRTIM_OUTPUT_TE2:
1817 {
1818 CompareUnit = HRTIM_COMPAREUNIT_2;
1819 }
1820 break;
1821 }
1822
1823 CompareCfg.CompareValue = pSimplePWMChannelCfg->Pulse;
1824 CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
1825 CompareCfg.AutoDelayedTimeout = 0;
1826
1827 HRTIM_CompareUnitConfig(hhrtim,
1828 TimerIdx,
1829 CompareUnit,
1830 &CompareCfg);
1831
1832 /* Configure timer output */
1833 OutputCfg.Polarity = pSimplePWMChannelCfg->Polarity;
1834 OutputCfg.IdleLevel = pSimplePWMChannelCfg->IdleLevel;
1835 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
1836 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
1837 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
1838 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
1839
1840 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1841 {
1842 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1843 }
1844 else
1845 {
1846 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1847 }
1848 OutputCfg.ResetSource = HRTIM_OUTPUTSET_TIMPER;
1849
1850 HRTIM_OutputConfig(hhrtim,
1851 TimerIdx,
1852 PWMChannel,
1853 &OutputCfg);
1854
1855 /* Enable the registers preload mechanism */
1856 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
1857 hrtim_timcr |= HRTIM_TIMCR_PREEN;
1858 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
1859
1860 hhrtim->State = HAL_HRTIM_STATE_READY;
1861
1862 /* Process Unlocked */
1863 __HAL_UNLOCK(hhrtim);
1864
1865 return HAL_OK;
1866 }
1867
1868 /**
1869 * @brief Starts the PWM output signal generation on the designed timer output
1870 * @param hhrtim: pointer to HAL HRTIM handle
1871 * @param TimerIdx: Timer index
1872 * This parameter can be one of the following values:
1873 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1874 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1875 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1876 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1877 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1878 * @param PWMChannel: Timer output
1879 * This parameter can be one of the following values:
1880 * @arg HRTIM_OUTPUT_TA1: Timer A - Ouput 1
1881 * @arg HRTIM_OUTPUT_TA2: Timer A - Ouput 2
1882 * @arg HRTIM_OUTPUT_TB1: Timer B - Ouput 1
1883 * @arg HRTIM_OUTPUT_TB2: Timer B - Ouput 2
1884 * @arg HRTIM_OUTPUT_TC1: Timer C - Ouput 1
1885 * @arg HRTIM_OUTPUT_TC2: Timer C - Ouput 2
1886 * @arg HRTIM_OUTPUT_TD1: Timer D - Ouput 1
1887 * @arg HRTIM_OUTPUT_TD2: Timer D - Ouput 2
1888 * @arg HRTIM_OUTPUT_TE1: Timer E - Ouput 1
1889 * @arg HRTIM_OUTPUT_TE2: Timer E - Ouput 2
1890 * @retval HAL status
1891 */
1892 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim,
1893 uint32_t TimerIdx,
1894 uint32_t PWMChannel)
1895 {
1896 /* Check the parameters */
1897 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
1898
1899 /* Process Locked */
1900 __HAL_LOCK(hhrtim);
1901
1902 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1903
1904 /* Enable the timer output */
1905 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
1906
1907 /* Enable the timer counter */
1908 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1909
1910 hhrtim->State = HAL_HRTIM_STATE_READY;
1911
1912 /* Process Unlocked */
1913 __HAL_UNLOCK(hhrtim);
1914
1915 return HAL_OK;
1916 }
1917
1918 /**
1919 * @brief Stops the PWM output signal generation on the designed timer output
1920 * @param hhrtim: pointer to HAL HRTIM handle
1921 * @param TimerIdx: Timer index
1922 * This parameter can be one of the following values:
1923 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1924 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1925 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1926 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1927 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1928 * @param PWMChannel: Timer output
1929 * This parameter can be one of the following values:
1930 * @arg HRTIM_OUTPUT_TA1: Timer A - Ouput 1
1931 * @arg HRTIM_OUTPUT_TA2: Timer A - Ouput 2
1932 * @arg HRTIM_OUTPUT_TB1: Timer B - Ouput 1
1933 * @arg HRTIM_OUTPUT_TB2: Timer B - Ouput 2
1934 * @arg HRTIM_OUTPUT_TC1: Timer C - Ouput 1
1935 * @arg HRTIM_OUTPUT_TC2: Timer C - Ouput 2
1936 * @arg HRTIM_OUTPUT_TD1: Timer D - Ouput 1
1937 * @arg HRTIM_OUTPUT_TD2: Timer D - Ouput 2
1938 * @arg HRTIM_OUTPUT_TE1: Timer E - Ouput 1
1939 * @arg HRTIM_OUTPUT_TE2: Timer E - Ouput 2
1940 * @retval HAL status
1941 */
1942 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim,
1943 uint32_t TimerIdx,
1944 uint32_t PWMChannel)
1945 {
1946 /* Check the parameters */
1947 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
1948
1949 /* Process Locked */
1950 __HAL_LOCK(hhrtim);
1951
1952 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1953
1954 /* Disable the timer output */
1955 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
1956
1957 /* Disable the timer counter */
1958 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1959
1960 hhrtim->State = HAL_HRTIM_STATE_READY;
1961
1962 /* Process Unlocked */
1963 __HAL_UNLOCK(hhrtim);
1964
1965 return HAL_OK;
1966 }
1967
1968 /**
1969 * @brief Starts the PWM output signal generation on the designed timer output
1970 * The compare interrupt is enabled.
1971 * @param hhrtim: pointer to HAL HRTIM handle
1972 * @param TimerIdx: Timer index
1973 * This parameter can be one of the following values:
1974 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1975 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1976 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1977 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1978 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1979 * @param PWMChannel: Timer output
1980 * This parameter can be one of the following values:
1981 * @arg HRTIM_OUTPUT_TA1: Timer A - Ouput 1
1982 * @arg HRTIM_OUTPUT_TA2: Timer A - Ouput 2
1983 * @arg HRTIM_OUTPUT_TB1: Timer B - Ouput 1
1984 * @arg HRTIM_OUTPUT_TB2: Timer B - Ouput 2
1985 * @arg HRTIM_OUTPUT_TC1: Timer C - Ouput 1
1986 * @arg HRTIM_OUTPUT_TC2: Timer C - Ouput 2
1987 * @arg HRTIM_OUTPUT_TD1: Timer D - Ouput 1
1988 * @arg HRTIM_OUTPUT_TD2: Timer D - Ouput 2
1989 * @arg HRTIM_OUTPUT_TE1: Timer E - Ouput 1
1990 * @arg HRTIM_OUTPUT_TE2: Timer E - Ouput 2
1991 * @retval HAL status
1992 */
1993 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim,
1994 uint32_t TimerIdx,
1995 uint32_t PWMChannel)
1996 {
1997 /* Check the parameters */
1998 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
1999
2000 /* Process Locked */
2001 __HAL_LOCK(hhrtim);
2002
2003 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2004
2005 /* Enable the timer output */
2006 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
2007
2008 /* Enable the timer interrupt (depends on the PWM output) */
2009 switch (PWMChannel)
2010 {
2011 case HRTIM_OUTPUT_TA1:
2012 case HRTIM_OUTPUT_TB1:
2013 case HRTIM_OUTPUT_TC1:
2014 case HRTIM_OUTPUT_TD1:
2015 case HRTIM_OUTPUT_TE1:
2016 {
2017 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
2018 }
2019 break;
2020 case HRTIM_OUTPUT_TA2:
2021 case HRTIM_OUTPUT_TB2:
2022 case HRTIM_OUTPUT_TC2:
2023 case HRTIM_OUTPUT_TD2:
2024 case HRTIM_OUTPUT_TE2:
2025 {
2026 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
2027 }
2028 break;
2029 }
2030
2031 /* Enable the timer counter */
2032 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2033
2034 hhrtim->State = HAL_HRTIM_STATE_READY;
2035
2036 /* Process Unlocked */
2037 __HAL_UNLOCK(hhrtim);
2038
2039 return HAL_OK;
2040 }
2041
2042 /**
2043 * @brief Stops the PWM output signal generation on the designed timer output
2044 * The compare interrupt is disabled.
2045 * @param hhrtim: pointer to HAL HRTIM handle
2046 * @param TimerIdx: Timer index
2047 * This parameter can be one of the following values:
2048 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2049 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2050 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2051 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2052 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2053 * @param PWMChannel: Timer output
2054 * This parameter can be one of the following values:
2055 * @arg HRTIM_OUTPUT_TA1: Timer A - Ouput 1
2056 * @arg HRTIM_OUTPUT_TA2: Timer A - Ouput 2
2057 * @arg HRTIM_OUTPUT_TB1: Timer B - Ouput 1
2058 * @arg HRTIM_OUTPUT_TB2: Timer B - Ouput 2
2059 * @arg HRTIM_OUTPUT_TC1: Timer C - Ouput 1
2060 * @arg HRTIM_OUTPUT_TC2: Timer C - Ouput 2
2061 * @arg HRTIM_OUTPUT_TD1: Timer D - Ouput 1
2062 * @arg HRTIM_OUTPUT_TD2: Timer D - Ouput 2
2063 * @arg HRTIM_OUTPUT_TE1: Timer E - Ouput 1
2064 * @arg HRTIM_OUTPUT_TE2: Timer E - Ouput 2
2065 * @retval HAL status
2066 */
2067 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim,
2068 uint32_t TimerIdx,
2069 uint32_t PWMChannel)
2070 {
2071 /* Check the parameters */
2072 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2073
2074 /* Process Locked */
2075 __HAL_LOCK(hhrtim);
2076
2077 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2078
2079 /* Disable the timer output */
2080 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
2081
2082 /* Disable the timer interrupt (depends on the PWM output) */
2083 switch (PWMChannel)
2084 {
2085 case HRTIM_OUTPUT_TA1:
2086 case HRTIM_OUTPUT_TB1:
2087 case HRTIM_OUTPUT_TC1:
2088 case HRTIM_OUTPUT_TD1:
2089 case HRTIM_OUTPUT_TE1:
2090 {
2091 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
2092 }
2093 break;
2094 case HRTIM_OUTPUT_TA2:
2095 case HRTIM_OUTPUT_TB2:
2096 case HRTIM_OUTPUT_TC2:
2097 case HRTIM_OUTPUT_TD2:
2098 case HRTIM_OUTPUT_TE2:
2099 {
2100 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
2101 }
2102 break;
2103 }
2104
2105 /* Disable the timer counter */
2106 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2107
2108 hhrtim->State = HAL_HRTIM_STATE_READY;
2109
2110 /* Process Unlocked */
2111 __HAL_UNLOCK(hhrtim);
2112
2113 return HAL_OK;
2114 }
2115
2116 /**
2117 * @brief Starts the PWM output signal generation on the designed timer output
2118 * The compare DMA request is enabled.
2119 * @param hhrtim: pointer to HAL HRTIM handle
2120 * @param TimerIdx: Timer index
2121 * This parameter can be one of the following values:
2122 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2123 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2124 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2125 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2126 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2127 * @param PWMChannel: Timer output
2128 * This parameter can be one of the following values:
2129 * @arg HRTIM_OUTPUT_TA1: Timer A - Ouput 1
2130 * @arg HRTIM_OUTPUT_TA2: Timer A - Ouput 2
2131 * @arg HRTIM_OUTPUT_TB1: Timer B - Ouput 1
2132 * @arg HRTIM_OUTPUT_TB2: Timer B - Ouput 2
2133 * @arg HRTIM_OUTPUT_TC1: Timer C - Ouput 1
2134 * @arg HRTIM_OUTPUT_TC2: Timer C - Ouput 2
2135 * @arg HRTIM_OUTPUT_TD1: Timer D - Ouput 1
2136 * @arg HRTIM_OUTPUT_TD2: Timer D - Ouput 2
2137 * @arg HRTIM_OUTPUT_TE1: Timer E - Ouput 1
2138 * @arg HRTIM_OUTPUT_TE2: Timer E - Ouput 2
2139 * @param SrcAddr: DMA transfer source address
2140 * @param DestAddr: DMA transfer destination address
2141 * @param Length: The length of data items (data size) to be transferred
2142 * from source to destination
2143 * @retval HAL status
2144 */
2145 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim,
2146 uint32_t TimerIdx,
2147 uint32_t PWMChannel,
2148 uint32_t SrcAddr,
2149 uint32_t DestAddr,
2150 uint32_t Length)
2151 {
2152 DMA_HandleTypeDef * hdma;
2153
2154 /* Check the parameters */
2155 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2156
2157 if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
2158 {
2159 return HAL_BUSY;
2160 }
2161 if((hhrtim->State == HAL_HRTIM_STATE_READY))
2162 {
2163 if((SrcAddr == 0 ) || (DestAddr == 0 ) || (Length == 0))
2164 {
2165 return HAL_ERROR;
2166 }
2167 else
2168 {
2169 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2170 }
2171 }
2172
2173 /* Process Locked */
2174 __HAL_LOCK(hhrtim);
2175
2176 /* Enable the timer output */
2177 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
2178
2179 /* Get the timer DMA handler */
2180 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
2181
2182 /* Set the DMA error callback */
2183 hdma->XferErrorCallback = HRTIM_DMAError ;
2184
2185 /* Set the DMA transfer completed callback */
2186 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
2187
2188 /* Enable the DMA channel */
2189 HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length);
2190
2191 /* Enable the timer DMA request */
2192 switch (PWMChannel)
2193 {
2194 case HRTIM_OUTPUT_TA1:
2195 case HRTIM_OUTPUT_TB1:
2196 case HRTIM_OUTPUT_TC1:
2197 case HRTIM_OUTPUT_TD1:
2198 case HRTIM_OUTPUT_TE1:
2199 {
2200 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
2201 }
2202 break;
2203 case HRTIM_OUTPUT_TA2:
2204 case HRTIM_OUTPUT_TB2:
2205 case HRTIM_OUTPUT_TC2:
2206 case HRTIM_OUTPUT_TD2:
2207 case HRTIM_OUTPUT_TE2:
2208 {
2209 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
2210 }
2211 break;
2212 }
2213
2214 /* Enable the timer counter */
2215 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2216
2217 hhrtim->State = HAL_HRTIM_STATE_READY;
2218
2219 /* Process Unlocked */
2220 __HAL_UNLOCK(hhrtim);
2221
2222 return HAL_OK;
2223 }
2224
2225 /**
2226 * @brief Stops the PWM output signal generation on the designed timer output
2227 * The compare DMA request is disabled.
2228 * @param hhrtim: pointer to HAL HRTIM handle
2229 * @param TimerIdx: Timer index
2230 * This parameter can be one of the following values:
2231 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2232 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2233 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2234 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2235 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2236 * @param PWMChannel: Timer output
2237 * This parameter can be one of the following values:
2238 * @arg HRTIM_OUTPUT_TA1: Timer A - Ouput 1
2239 * @arg HRTIM_OUTPUT_TA2: Timer A - Ouput 2
2240 * @arg HRTIM_OUTPUT_TB1: Timer B - Ouput 1
2241 * @arg HRTIM_OUTPUT_TB2: Timer B - Ouput 2
2242 * @arg HRTIM_OUTPUT_TC1: Timer C - Ouput 1
2243 * @arg HRTIM_OUTPUT_TC2: Timer C - Ouput 2
2244 * @arg HRTIM_OUTPUT_TD1: Timer D - Ouput 1
2245 * @arg HRTIM_OUTPUT_TD2: Timer D - Ouput 2
2246 * @arg HRTIM_OUTPUT_TE1: Timer E - Ouput 1
2247 * @arg HRTIM_OUTPUT_TE2: Timer E - Ouput 2
2248 * @retval HAL status
2249 */
2250 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim,
2251 uint32_t TimerIdx,
2252 uint32_t PWMChannel)
2253 {
2254 DMA_HandleTypeDef * hdma;
2255
2256 /* Check the parameters */
2257 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2258
2259 /* Process Locked */
2260 __HAL_LOCK(hhrtim);
2261
2262 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2263
2264 /* Disable the timer output */
2265 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
2266
2267 /* Get the timer DMA handler */
2268 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
2269
2270 /* Disable the DMA */
2271 HAL_DMA_Abort(hdma);
2272
2273 /* Disable the timer DMA request */
2274 switch (PWMChannel)
2275 {
2276 case HRTIM_OUTPUT_TA1:
2277 case HRTIM_OUTPUT_TB1:
2278 case HRTIM_OUTPUT_TC1:
2279 case HRTIM_OUTPUT_TD1:
2280 case HRTIM_OUTPUT_TE1:
2281 {
2282 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
2283 }
2284 break;
2285 case HRTIM_OUTPUT_TA2:
2286 case HRTIM_OUTPUT_TB2:
2287 case HRTIM_OUTPUT_TC2:
2288 case HRTIM_OUTPUT_TD2:
2289 case HRTIM_OUTPUT_TE2:
2290 {
2291 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
2292 }
2293 break;
2294 }
2295
2296 /* Disable the timer counter */
2297 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2298
2299 hhrtim->State = HAL_HRTIM_STATE_READY;
2300
2301 /* Process Unlocked */
2302 __HAL_UNLOCK(hhrtim);
2303
2304 return HAL_OK;
2305 }
2306
2307 /**
2308 * @}
2309 */
2310
2311 /** @defgroup HRTIM_Exported_Functions_Group5 Simple input capture functions
2312 * @brief When a HRTIM timer operates in simple input capture mode
2313 * the Capture Register (HRTIM_CPT1/2xR) is used to latch the
2314 * value of the timer counter counter after a transition detected
2315 * on a given external event input.
2316 *
2317 @verbatim
2318 ===============================================================================
2319 ##### Simple input capture functions #####
2320 ===============================================================================
2321 [..] This section provides functions allowing to:
2322 (+) Configure simple input capture channel
2323 (+) Start simple input capture
2324 (+) Stop simple input capture
2325 (+) Start simple input capture and enable interrupt
2326 (+) Stop simple input capture and disable interrupt
2327 (+) Start simple input capture and enable DMA transfer
2328 (+) Stop simple input capture and disable DMA transfer
2329
2330 @endverbatim
2331 * @{
2332 */
2333
2334 /**
2335 * @brief Configures a basic capture
2336 * @param hhrtim: pointer to HAL HRTIM handle
2337 * @param TimerIdx: Timer index
2338 * This parameter can be one of the following values:
2339 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2340 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2341 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2342 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2343 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2344 * @param CaptureChannel: Capture unit
2345 * This parameter can be one of the following values:
2346 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2347 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2348 * @param pSimpleCaptureChannelCfg: pointer to the basic capture configuration structure
2349 * @note When the timer operates in basic capture mode the capture is trigerred
2350 * by the designated external event and GPIO input is implicitely used as event source.
2351 * The cature can be triggered by a rising edge, a falling edge or both
2352 * edges on event channel.
2353 * @retval HAL status
2354 */
2355 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhrtim,
2356 uint32_t TimerIdx,
2357 uint32_t CaptureChannel,
2358 HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg)
2359 {
2360 HRTIM_EventCfgTypeDef EventCfg;
2361
2362 /* Check parameters */
2363 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2364 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2365 assert_param(IS_HRTIM_EVENT(pSimpleCaptureChannelCfg->Event));
2366 assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleCaptureChannelCfg->EventSensitivity,
2367 pSimpleCaptureChannelCfg->EventPolarity));
2368 assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleCaptureChannelCfg->EventSensitivity));
2369 assert_param(IS_HRTIM_EVENTFILTER(pSimpleCaptureChannelCfg->Event,
2370 pSimpleCaptureChannelCfg->EventFilter));
2371
2372 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
2373 {
2374 return HAL_BUSY;
2375 }
2376
2377 /* Process Locked */
2378 __HAL_LOCK(hhrtim);
2379
2380 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2381
2382 /* Configure external event channel */
2383 EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
2384 EventCfg.Filter = pSimpleCaptureChannelCfg->EventFilter;
2385 EventCfg.Polarity = pSimpleCaptureChannelCfg->EventPolarity;
2386 EventCfg.Sensitivity = pSimpleCaptureChannelCfg->EventSensitivity;
2387 EventCfg.Source = HRTIM_EVENTSRC_1;
2388
2389 HRTIM_EventConfig(hhrtim,
2390 pSimpleCaptureChannelCfg->Event,
2391 &EventCfg);
2392
2393 /* Memorize capture trigger (will be configured when the capture is started */
2394 HRTIM_CaptureUnitConfig(hhrtim,
2395 TimerIdx,
2396 CaptureChannel,
2397 pSimpleCaptureChannelCfg->Event);
2398
2399 hhrtim->State = HAL_HRTIM_STATE_READY;
2400
2401 /* Process Unlocked */
2402 __HAL_UNLOCK(hhrtim);
2403
2404 return HAL_OK;
2405 }
2406
2407 /**
2408 * @brief Enables a basic capture on the designed capture unit
2409 * @param hhrtim: pointer to HAL HRTIM handle
2410 * @param TimerIdx: Timer index
2411 * This parameter can be one of the following values:
2412 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2413 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2414 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2415 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2416 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2417 * @param CaptureChannel: Timer output
2418 * This parameter can be one of the following values:
2419 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2420 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2421 * @retval HAL status
2422 * @note The external event triggering the capture is available for all timing
2423 * units. It can be used directly and is active as soon as the timing
2424 * unit counter is enabled.
2425 */
2426 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim,
2427 uint32_t TimerIdx,
2428 uint32_t CaptureChannel)
2429 {
2430 /* Check the parameters */
2431 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2432 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2433
2434 /* Process Locked */
2435 __HAL_LOCK(hhrtim);
2436
2437 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2438
2439 /* Set the capture unit trigger */
2440 switch (CaptureChannel)
2441 {
2442 case HRTIM_CAPTUREUNIT_1:
2443 {
2444 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
2445 }
2446 break;
2447 case HRTIM_CAPTUREUNIT_2:
2448 {
2449 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
2450 }
2451 break;
2452 }
2453
2454 /* Enable the timer counter */
2455 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2456
2457 hhrtim->State = HAL_HRTIM_STATE_READY;
2458
2459 /* Process Unlocked */
2460 __HAL_UNLOCK(hhrtim);
2461
2462 return HAL_OK;
2463 }
2464
2465 /**
2466 * @brief Disables a basic capture on the designed capture unit
2467 * @param hhrtim: pointer to HAL HRTIM handle
2468 * @param TimerIdx: Timer index
2469 * This parameter can be one of the following values:
2470 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2471 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2472 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2473 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2474 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2475 * @param CaptureChannel: Timer output
2476 * This parameter can be one of the following values:
2477 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2478 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2479 * @retval HAL status
2480 */
2481 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim,
2482 uint32_t TimerIdx,
2483 uint32_t CaptureChannel)
2484 {
2485 /* Check the parameters */
2486 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2487 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2488
2489 /* Process Locked */
2490 __HAL_LOCK(hhrtim);
2491
2492 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2493
2494 /* Set the capture unit trigger */
2495 switch (CaptureChannel)
2496 {
2497 case HRTIM_CAPTUREUNIT_1:
2498 {
2499 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
2500 }
2501 break;
2502 case HRTIM_CAPTUREUNIT_2:
2503 {
2504 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
2505 }
2506 break;
2507 }
2508
2509 /* Disable the timer counter */
2510 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR == HRTIM_CAPTURETRIGGER_NONE) &&
2511 (hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR == HRTIM_CAPTURETRIGGER_NONE))
2512 {
2513 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2514 }
2515
2516 hhrtim->State = HAL_HRTIM_STATE_READY;
2517
2518 /* Process Unlocked */
2519 __HAL_UNLOCK(hhrtim);
2520
2521 return HAL_OK;
2522 }
2523
2524 /**
2525 * @brief Enables a basic capture on the designed capture unit
2526 * Capture interrupt is enabled
2527 * @param hhrtim: pointer to HAL HRTIM handle
2528 * @param TimerIdx: Timer index
2529 * This parameter can be one of the following values:
2530 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2531 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2532 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2533 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2534 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2535 * @param CaptureChannel: Timer output
2536 * This parameter can be one of the following values:
2537 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2538 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2539 * @retval HAL status
2540 */
2541 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim,
2542 uint32_t TimerIdx,
2543 uint32_t CaptureChannel)
2544 {
2545 /* Check the parameters */
2546 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2547 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2548
2549 /* Process Locked */
2550 __HAL_LOCK(hhrtim);
2551
2552 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2553
2554 /* Set the capture unit trigger */
2555 switch (CaptureChannel)
2556 {
2557 case HRTIM_CAPTUREUNIT_1:
2558 {
2559 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
2560
2561 /* Enable the capture unit 1 interrupt */
2562 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
2563 }
2564 break;
2565 case HRTIM_CAPTUREUNIT_2:
2566 {
2567 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
2568
2569 /* Enable the capture unit 2 interrupt */
2570 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
2571 }
2572 break;
2573 }
2574
2575 /* Enable the timer counter */
2576 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2577
2578 hhrtim->State = HAL_HRTIM_STATE_READY;
2579
2580 /* Process Unlocked */
2581 __HAL_UNLOCK(hhrtim);
2582
2583 return HAL_OK;
2584 }
2585
2586 /**
2587 * @brief Disables a basic capture on the designed capture unit
2588 * Capture interrupt is disabled
2589 * @param hhrtim: pointer to HAL HRTIM handle
2590 * @param TimerIdx: Timer index
2591 * This parameter can be one of the following values:
2592 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2593 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2594 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2595 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2596 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2597 * @param CaptureChannel: Timer output
2598 * This parameter can be one of the following values:
2599 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2600 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2601 * @retval HAL status
2602 */
2603 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim,
2604 uint32_t TimerIdx,
2605 uint32_t CaptureChannel)
2606 {
2607 /* Check the parameters */
2608 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2609 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2610
2611 /* Process Locked */
2612 __HAL_LOCK(hhrtim);
2613
2614 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2615
2616 /* Set the capture unit trigger */
2617 switch (CaptureChannel)
2618 {
2619 case HRTIM_CAPTUREUNIT_1:
2620 {
2621 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
2622
2623 /* Disable the capture unit 1 interrupt */
2624 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
2625 }
2626 break;
2627 case HRTIM_CAPTUREUNIT_2:
2628 {
2629 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
2630
2631 /* Disable the capture unit 2 interrupt */
2632 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
2633 }
2634 break;
2635 }
2636
2637 /* Disable the timer counter */
2638 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR == HRTIM_CAPTURETRIGGER_NONE) &&
2639 (hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR == HRTIM_CAPTURETRIGGER_NONE))
2640 {
2641 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2642 }
2643
2644 hhrtim->State = HAL_HRTIM_STATE_READY;
2645
2646 /* Process Unlocked */
2647 __HAL_UNLOCK(hhrtim);
2648
2649 return HAL_OK;
2650 }
2651
2652 /**
2653 * @brief Enables a basic capture on the designed capture unit
2654 * Capture DMA request is enabled
2655 * @param hhrtim: pointer to HAL HRTIM handle
2656 * @param TimerIdx: Timer index
2657 * This parameter can be one of the following values:
2658 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2659 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2660 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2661 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2662 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2663 * @param CaptureChannel: Timer output
2664 * This parameter can be one of the following values:
2665 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2666 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2667 * @param SrcAddr: DMA transfer source address
2668 * @param DestAddr: DMA transfer destination address
2669 * @param Length: The length of data items (data size) to be transferred
2670 * from source to destination
2671 * @retval HAL status
2672 */
2673 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim,
2674 uint32_t TimerIdx,
2675 uint32_t CaptureChannel,
2676 uint32_t SrcAddr,
2677 uint32_t DestAddr,
2678 uint32_t Length)
2679 {
2680 DMA_HandleTypeDef * hdma;
2681
2682 /* Check the parameters */
2683 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2684 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2685
2686 /* Process Locked */
2687 __HAL_LOCK(hhrtim);
2688
2689 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2690
2691 /* Get the timer DMA handler */
2692 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
2693
2694 /* Set the DMA error callback */
2695 hdma->XferErrorCallback = HRTIM_DMAError ;
2696
2697 /* Set the DMA transfer completed callback */
2698 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
2699
2700 /* Enable the DMA channel */
2701 HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length);
2702
2703 switch (CaptureChannel)
2704 {
2705 case HRTIM_CAPTUREUNIT_1:
2706 {
2707 /* Set the capture unit trigger */
2708 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
2709
2710 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
2711 }
2712 break;
2713 case HRTIM_CAPTUREUNIT_2:
2714 {
2715 /* Set the capture unit trigger */
2716 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
2717
2718 /* Enable the timer DMA request */
2719 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
2720 }
2721 break;
2722 }
2723
2724 /* Enable the timer counter */
2725 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2726
2727 hhrtim->State = HAL_HRTIM_STATE_READY;
2728
2729 /* Process Unlocked */
2730 __HAL_UNLOCK(hhrtim);
2731
2732 return HAL_OK;
2733 }
2734
2735 /**
2736 * @brief Disables a basic capture on the designed capture unit
2737 * Capture DMA request is disabled
2738 * @param hhrtim: pointer to HAL HRTIM handle
2739 * @param TimerIdx: Timer index
2740 * This parameter can be one of the following values:
2741 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2742 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2743 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2744 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2745 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2746 * @param CaptureChannel: Timer output
2747 * This parameter can be one of the following values:
2748 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2749 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2750 * @retval HAL status
2751 */
2752 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim,
2753 uint32_t TimerIdx,
2754 uint32_t CaptureChannel)
2755 {
2756 DMA_HandleTypeDef * hdma;
2757
2758 /* Check the parameters */
2759 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2760 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2761
2762 /* Process Locked */
2763 __HAL_LOCK(hhrtim);
2764
2765 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2766
2767 /* Get the timer DMA handler */
2768 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
2769
2770 /* Disable the DMA */
2771 HAL_DMA_Abort(hdma);
2772
2773 switch (CaptureChannel)
2774 {
2775 case HRTIM_CAPTUREUNIT_1:
2776 {
2777 /* Reset the capture unit trigger */
2778 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
2779
2780 /* Disable the capture unit 1 DMA request */
2781 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
2782 }
2783 break;
2784 case HRTIM_CAPTUREUNIT_2:
2785 {
2786 /* Reset the capture unit trigger */
2787 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
2788
2789 /* Disable the capture unit 2 DMA request */
2790 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
2791 }
2792 break;
2793 }
2794
2795 /* Disable the timer counter */
2796 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR == HRTIM_CAPTURETRIGGER_NONE) &&
2797 (hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR == HRTIM_CAPTURETRIGGER_NONE))
2798 {
2799 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2800 }
2801
2802 hhrtim->State = HAL_HRTIM_STATE_READY;
2803
2804 /* Process Unlocked */
2805 __HAL_UNLOCK(hhrtim);
2806
2807 return HAL_OK;
2808 }
2809
2810 /**
2811 * @}
2812 */
2813
2814 /** @defgroup HRTIM_Exported_Functions_Group6 Simple one pulse functions
2815 * @brief When a HRTIM timer operates in simple one pulse mode
2816 * the timer counter is started in response to transition detected
2817 * on a given external event input to generate a pulse with a
2818 * programmable length after a programmable delay.
2819 *
2820 @verbatim
2821 ===============================================================================
2822 ##### Simple one pulse functions #####
2823 ===============================================================================
2824 [..] This section provides functions allowing to:
2825 (+) Configure one pulse channel
2826 (+) Start one pulse generation
2827 (+) Stop one pulse generation
2828 (+) Start one pulse generation and enable interrupt
2829 (+) Stop one pulse generation and disable interrupt
2830
2831 @endverbatim
2832 * @{
2833 */
2834
2835 /**
2836 * @brief Configures an output basic one pulse mode
2837 * @param hhrtim: pointer to HAL HRTIM handle
2838 * @param TimerIdx: Timer index
2839 * This parameter can be one of the following values:
2840 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2841 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2842 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2843 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2844 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2845 * @param OnePulseChannel: Timer output
2846 * This parameter can be one of the following values:
2847 * @arg HRTIM_OUTPUT_TA1: Timer A - Ouput 1
2848 * @arg HRTIM_OUTPUT_TA2: Timer A - Ouput 2
2849 * @arg HRTIM_OUTPUT_TB1: Timer B - Ouput 1
2850 * @arg HRTIM_OUTPUT_TB2: Timer B - Ouput 2
2851 * @arg HRTIM_OUTPUT_TC1: Timer C - Ouput 1
2852 * @arg HRTIM_OUTPUT_TC2: Timer C - Ouput 2
2853 * @arg HRTIM_OUTPUT_TD1: Timer D - Ouput 1
2854 * @arg HRTIM_OUTPUT_TD2: Timer D - Ouput 2
2855 * @arg HRTIM_OUTPUT_TE1: Timer E - Ouput 1
2856 * @arg HRTIM_OUTPUT_TE2: Timer E - Ouput 2
2857 * @param pSimpleOnePulseChannelCfg: pointer to the basic one pulse output configuration structure
2858 * @note When the timer operates in basic one pulse mode:
2859 * the timer counter is implicitely started by the reset event,
2860 * the reset of the timer counter is triggered by the designated external event
2861 * GPIO input is implicitely used as event source,
2862 * Output 1 is implicitely controled by the compare unit 1,
2863 * Output 2 is implicitely controled by the compare unit 2.
2864 * Output Set/Reset crossbar is set as follows:
2865 * Ouput 1: SETx1R = CMP1, RSTx1R = PER
2866 * Output 2: SETx2R = CMP2, RST2R = PER
2867 * @retval HAL status
2868 * @note If HAL_HRTIM_SimpleOnePulseChannelConfig is called for both timer
2869 * outputs, the reset event related configuration data provided in the
2870 * second call will override the reset event related configuration data
2871 * provided in the first call.
2872 */
2873 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hhrtim,
2874 uint32_t TimerIdx,
2875 uint32_t OnePulseChannel,
2876 HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg)
2877 {
2878 uint32_t CompareUnit = 0xFFFFFFFF;
2879 HRTIM_CompareCfgTypeDef CompareCfg;
2880 HRTIM_OutputCfgTypeDef OutputCfg;
2881 HRTIM_EventCfgTypeDef EventCfg;
2882
2883 /* Check parameters */
2884 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
2885 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOnePulseChannelCfg->OutputPolarity));
2886 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOnePulseChannelCfg->OutputIdleLevel));
2887 assert_param(IS_HRTIM_EVENT(pSimpleOnePulseChannelCfg->Event));
2888 assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleOnePulseChannelCfg->EventSensitivity,
2889 pSimpleOnePulseChannelCfg->EventPolarity));
2890 assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleOnePulseChannelCfg->EventSensitivity));
2891 assert_param(IS_HRTIM_EVENTFILTER(pSimpleOnePulseChannelCfg->Event,
2892 pSimpleOnePulseChannelCfg->EventFilter));
2893
2894 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
2895 {
2896 return HAL_BUSY;
2897 }
2898
2899 /* Process Locked */
2900 __HAL_LOCK(hhrtim);
2901
2902 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2903
2904 /* Configure timer compare unit */
2905 switch (OnePulseChannel)
2906 {
2907 case HRTIM_OUTPUT_TA1:
2908 case HRTIM_OUTPUT_TB1:
2909 case HRTIM_OUTPUT_TC1:
2910 case HRTIM_OUTPUT_TD1:
2911 case HRTIM_OUTPUT_TE1:
2912 {
2913 CompareUnit = HRTIM_COMPAREUNIT_1;
2914 }
2915 break;
2916 case HRTIM_OUTPUT_TA2:
2917 case HRTIM_OUTPUT_TB2:
2918 case HRTIM_OUTPUT_TC2:
2919 case HRTIM_OUTPUT_TD2:
2920 case HRTIM_OUTPUT_TE2:
2921 {
2922 CompareUnit = HRTIM_COMPAREUNIT_2;
2923 }
2924 break;
2925 }
2926
2927 CompareCfg.CompareValue = pSimpleOnePulseChannelCfg->Pulse;
2928 CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
2929 CompareCfg.AutoDelayedTimeout = 0;
2930
2931 HRTIM_CompareUnitConfig(hhrtim,
2932 TimerIdx,
2933 CompareUnit,
2934 &CompareCfg);
2935
2936 /* Configure timer output */
2937 OutputCfg.Polarity = pSimpleOnePulseChannelCfg->OutputPolarity;
2938 OutputCfg.IdleLevel = pSimpleOnePulseChannelCfg->OutputIdleLevel;
2939 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
2940 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
2941 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
2942 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
2943
2944 if (CompareUnit == HRTIM_COMPAREUNIT_1)
2945 {
2946 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
2947 }
2948 else
2949 {
2950 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
2951 }
2952 OutputCfg.ResetSource = HRTIM_OUTPUTSET_TIMPER;
2953
2954 HRTIM_OutputConfig(hhrtim,
2955 TimerIdx,
2956 OnePulseChannel,
2957 &OutputCfg);
2958
2959 /* Configure external event channel */
2960 EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
2961 EventCfg.Filter = pSimpleOnePulseChannelCfg->EventFilter;
2962 EventCfg.Polarity = pSimpleOnePulseChannelCfg->EventPolarity;
2963 EventCfg.Sensitivity = pSimpleOnePulseChannelCfg->EventSensitivity;
2964 EventCfg.Source = HRTIM_EVENTSRC_1;
2965
2966 HRTIM_EventConfig(hhrtim,
2967 pSimpleOnePulseChannelCfg->Event,
2968 &EventCfg);
2969
2970 /* Configure the timer reset register */
2971 HRTIM_TIM_ResetConfig(hhrtim,
2972 TimerIdx,
2973 pSimpleOnePulseChannelCfg->Event);
2974
2975 hhrtim->State = HAL_HRTIM_STATE_READY;
2976
2977 /* Process Unlocked */
2978 __HAL_UNLOCK(hhrtim);
2979
2980 return HAL_OK;
2981 }
2982
2983 /**
2984 * @brief Enables the basic one pulse signal generation on the designed output
2985 * @param hhrtim: pointer to HAL HRTIM handle
2986 * @param TimerIdx: Timer index
2987 * This parameter can be one of the following values:
2988 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2989 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2990 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2991 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2992 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2993 * @param OnePulseChannel: Timer output
2994 * This parameter can be one of the following values:
2995 * @arg HRTIM_OUTPUT_TA1: Timer A - Ouput 1
2996 * @arg HRTIM_OUTPUT_TA2: Timer A - Ouput 2
2997 * @arg HRTIM_OUTPUT_TB1: Timer B - Ouput 1
2998 * @arg HRTIM_OUTPUT_TB2: Timer B - Ouput 2
2999 * @arg HRTIM_OUTPUT_TC1: Timer C - Ouput 1
3000 * @arg HRTIM_OUTPUT_TC2: Timer C - Ouput 2
3001 * @arg HRTIM_OUTPUT_TD1: Timer D - Ouput 1
3002 * @arg HRTIM_OUTPUT_TD2: Timer D - Ouput 2
3003 * @arg HRTIM_OUTPUT_TE1: Timer E - Ouput 1
3004 * @arg HRTIM_OUTPUT_TE2: Timer E - Ouput 2
3005 * @retval HAL status
3006 */
3007 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim,
3008 uint32_t TimerIdx,
3009 uint32_t OnePulseChannel)
3010 {
3011 /* Check the parameters */
3012 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3013
3014 /* Process Locked */
3015 __HAL_LOCK(hhrtim);
3016
3017 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3018
3019 /* Enable the timer output */
3020 hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
3021
3022 /* Enable the timer counter */
3023 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3024
3025 hhrtim->State = HAL_HRTIM_STATE_READY;
3026
3027 /* Process Unlocked */
3028 __HAL_UNLOCK(hhrtim);
3029
3030 return HAL_OK;
3031 }
3032
3033 /**
3034 * @brief Disables the basic one pulse signal generation on the designed output
3035 * @param hhrtim: pointer to HAL HRTIM handle
3036 * @param TimerIdx: Timer index
3037 * This parameter can be one of the following values:
3038 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3039 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3040 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3041 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3042 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3043 * @param OnePulseChannel: Timer output
3044 * This parameter can be one of the following values:
3045 * @arg HRTIM_OUTPUT_TA1: Timer A - Ouput 1
3046 * @arg HRTIM_OUTPUT_TA2: Timer A - Ouput 2
3047 * @arg HRTIM_OUTPUT_TB1: Timer B - Ouput 1
3048 * @arg HRTIM_OUTPUT_TB2: Timer B - Ouput 2
3049 * @arg HRTIM_OUTPUT_TC1: Timer C - Ouput 1
3050 * @arg HRTIM_OUTPUT_TC2: Timer C - Ouput 2
3051 * @arg HRTIM_OUTPUT_TD1: Timer D - Ouput 1
3052 * @arg HRTIM_OUTPUT_TD2: Timer D - Ouput 2
3053 * @arg HRTIM_OUTPUT_TE1: Timer E - Ouput 1
3054 * @arg HRTIM_OUTPUT_TE2: Timer E - Ouput 2
3055 * @retval HAL status
3056 */
3057 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim,
3058 uint32_t TimerIdx,
3059 uint32_t OnePulseChannel)
3060 {
3061 /* Check the parameters */
3062 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3063
3064 /* Process Locked */
3065 __HAL_LOCK(hhrtim);
3066
3067 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3068
3069 /* Disable the timer output */
3070 hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
3071
3072 /* Disable the timer counter */
3073 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3074
3075 hhrtim->State = HAL_HRTIM_STATE_READY;
3076
3077 /* Process Unlocked */
3078 __HAL_UNLOCK(hhrtim);
3079
3080 return HAL_OK;
3081 }
3082
3083 /**
3084 * @brief Enables the basic one pulse signal generation on the designed output
3085 * The compare interrupt is enabled (pulse start)
3086 * @param hhrtim: pointer to HAL HRTIM handle
3087 * @param TimerIdx: Timer index
3088 * This parameter can be one of the following values:
3089 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3090 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3091 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3092 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3093 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3094 * @param OnePulseChannel: Timer output
3095 * This parameter can be one of the following values:
3096 * @arg HRTIM_OUTPUT_TA1: Timer A - Ouput 1
3097 * @arg HRTIM_OUTPUT_TA2: Timer A - Ouput 2
3098 * @arg HRTIM_OUTPUT_TB1: Timer B - Ouput 1
3099 * @arg HRTIM_OUTPUT_TB2: Timer B - Ouput 2
3100 * @arg HRTIM_OUTPUT_TC1: Timer C - Ouput 1
3101 * @arg HRTIM_OUTPUT_TC2: Timer C - Ouput 2
3102 * @arg HRTIM_OUTPUT_TD1: Timer D - Ouput 1
3103 * @arg HRTIM_OUTPUT_TD2: Timer D - Ouput 2
3104 * @arg HRTIM_OUTPUT_TE1: Timer E - Ouput 1
3105 * @arg HRTIM_OUTPUT_TE2: Timer E - Ouput 2
3106 * @retval HAL status
3107 */
3108 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim,
3109 uint32_t TimerIdx,
3110 uint32_t OnePulseChannel)
3111 {
3112 /* Check the parameters */
3113 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3114
3115 /* Process Locked */
3116 __HAL_LOCK(hhrtim);
3117
3118 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3119
3120 /* Enable the timer output */
3121 hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
3122
3123 /* Enable the timer interrupt (depends on the OnePulse output) */
3124 switch (OnePulseChannel)
3125 {
3126 case HRTIM_OUTPUT_TA1:
3127 case HRTIM_OUTPUT_TB1:
3128 case HRTIM_OUTPUT_TC1:
3129 case HRTIM_OUTPUT_TD1:
3130 case HRTIM_OUTPUT_TE1:
3131 {
3132 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
3133 }
3134 break;
3135 case HRTIM_OUTPUT_TA2:
3136 case HRTIM_OUTPUT_TB2:
3137 case HRTIM_OUTPUT_TC2:
3138 case HRTIM_OUTPUT_TD2:
3139 case HRTIM_OUTPUT_TE2:
3140 {
3141 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
3142 }
3143 break;
3144 }
3145
3146 /* Enable the timer counter */
3147 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3148
3149 hhrtim->State = HAL_HRTIM_STATE_READY;
3150
3151 /* Process Unlocked */
3152 __HAL_UNLOCK(hhrtim);
3153
3154 return HAL_OK;
3155 }
3156
3157 /**
3158 * @brief Disables the basic one pulse signal generation on the designed output
3159 * The compare interrupt is disabled
3160 * @param hhrtim: pointer to HAL HRTIM handle
3161 * @param TimerIdx: Timer index
3162 * This parameter can be one of the following values:
3163 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3164 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3165 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3166 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3167 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3168 * @param OnePulseChannel: Timer output
3169 * This parameter can be one of the following values:
3170 * @arg HRTIM_OUTPUT_TA1: Timer A - Ouput 1
3171 * @arg HRTIM_OUTPUT_TA2: Timer A - Ouput 2
3172 * @arg HRTIM_OUTPUT_TB1: Timer B - Ouput 1
3173 * @arg HRTIM_OUTPUT_TB2: Timer B - Ouput 2
3174 * @arg HRTIM_OUTPUT_TC1: Timer C - Ouput 1
3175 * @arg HRTIM_OUTPUT_TC2: Timer C - Ouput 2
3176 * @arg HRTIM_OUTPUT_TD1: Timer D - Ouput 1
3177 * @arg HRTIM_OUTPUT_TD2: Timer D - Ouput 2
3178 * @arg HRTIM_OUTPUT_TE1: Timer E - Ouput 1
3179 * @arg HRTIM_OUTPUT_TE2: Timer E - Ouput 2
3180 * @retval HAL status
3181 */
3182 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim,
3183 uint32_t TimerIdx,
3184 uint32_t OnePulseChannel)
3185 {
3186 /* Check the parameters */
3187 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3188
3189 /* Process Locked */
3190 __HAL_LOCK(hhrtim);
3191
3192 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3193
3194 /* Disable the timer output */
3195 hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
3196
3197 /* Disable the timer interrupt (depends on the OnePulse output) */
3198 switch (OnePulseChannel)
3199 {
3200 case HRTIM_OUTPUT_TA1:
3201 case HRTIM_OUTPUT_TB1:
3202 case HRTIM_OUTPUT_TC1:
3203 case HRTIM_OUTPUT_TD1:
3204 case HRTIM_OUTPUT_TE1:
3205 {
3206 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
3207 }
3208 break;
3209 case HRTIM_OUTPUT_TA2:
3210 case HRTIM_OUTPUT_TB2:
3211 case HRTIM_OUTPUT_TC2:
3212 case HRTIM_OUTPUT_TD2:
3213 case HRTIM_OUTPUT_TE2:
3214 {
3215 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
3216 }
3217 break;
3218 }
3219
3220 /* Disable the timer counter */
3221 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3222
3223 hhrtim->State = HAL_HRTIM_STATE_READY;
3224
3225 /* Process Unlocked */
3226 __HAL_UNLOCK(hhrtim);
3227
3228 return HAL_OK;
3229 }
3230
3231 /**
3232 * @}
3233 */
3234
3235 /** @defgroup HRTIM_Exported_Functions_Group7 Configuration functions
3236 * @brief Functions configuring the HRTIM resources shared by all the
3237 * HRTIM timers operating in waveform mode.
3238 *
3239 @verbatim
3240 ===============================================================================
3241 ##### HRTIM configuration functions #####
3242 ===============================================================================
3243 [..] This section provides functions allowing to:
3244 (+) Configure the burst mode controller
3245 (+) Configure an external event conditionning
3246 (+) Configure the external events sampling clock
3247 (+) Configure a fault conditionning
3248 (+) Enable or disable fault inputs
3249 (+) Configure the faults sampling clock
3250 (+) Configure an ADC trigger
3251
3252 @endverbatim
3253 * @{
3254 */
3255
3256 /**
3257 * @brief Configures the burst mode feature of the HRTIM
3258 * @param hhrtim: pointer to HAL HRTIM handle
3259 * @param pBurstModeCfg: pointer to the burst mode configuration structure
3260 * @retval HAL status
3261 * @note This function must be called before starting the burst mode
3262 * controller
3263 */
3264 HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim,
3265 HRTIM_BurstModeCfgTypeDef* pBurstModeCfg)
3266 {
3267 uint32_t hrtim_bmcr;
3268
3269 /* Check parameters */
3270 assert_param(IS_HRTIM_BURSTMODE(pBurstModeCfg->Mode));
3271 assert_param(IS_HRTIM_BURSTMODECLOCKSOURCE(pBurstModeCfg->ClockSource));
3272 assert_param(IS_HRTIM_HRTIM_BURSTMODEPRESCALER(pBurstModeCfg->Prescaler));
3273 assert_param(IS_HRTIM_BURSTMODEPRELOAD(pBurstModeCfg->PreloadEnable));
3274
3275 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3276 {
3277 return HAL_BUSY;
3278 }
3279
3280 /* Process Locked */
3281 __HAL_LOCK(hhrtim);
3282
3283 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3284
3285 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
3286
3287 /* Set the burst mode operating mode */
3288 hrtim_bmcr &= ~(HRTIM_BMCR_BMOM);
3289 hrtim_bmcr |= pBurstModeCfg->Mode;
3290
3291 /* Set the burst mode clock source */
3292 hrtim_bmcr &= ~(HRTIM_BMCR_BMCLK);
3293 hrtim_bmcr |= pBurstModeCfg->ClockSource;
3294
3295 /* Set the burst mode prescaler */
3296 hrtim_bmcr &= ~(HRTIM_BMCR_BMPRSC);
3297 hrtim_bmcr |= pBurstModeCfg->Prescaler;
3298
3299 /* Enable/disable burst mode registers preload */
3300 hrtim_bmcr &= ~(HRTIM_BMCR_BMPREN);
3301 hrtim_bmcr |= pBurstModeCfg->PreloadEnable;
3302
3303 /* Set the burst mode trigger */
3304 hhrtim->Instance->sCommonRegs.BMTRGR = pBurstModeCfg->Trigger;
3305
3306 /* Set the burst mode compare value */
3307 hhrtim->Instance->sCommonRegs.BMCMPR = pBurstModeCfg->IdleDuration;
3308
3309 /* Set the burst mode period */
3310 hhrtim->Instance->sCommonRegs.BMPER = pBurstModeCfg->Period;
3311
3312 /* Update the HRTIM registers */
3313 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
3314
3315 hhrtim->State = HAL_HRTIM_STATE_READY;
3316
3317 /* Process Unlocked */
3318 __HAL_UNLOCK(hhrtim);
3319
3320 return HAL_OK;
3321 }
3322
3323 /**
3324 * @brief Configures the conditioning of an external event
3325 * @param hhrtim: pointer to HAL HRTIM handle
3326 * @param Event: external event to configure
3327 * This parameter can be one of the following values:
3328 * @arg HRTIM_EVENT_1: External event 1
3329 * @arg HRTIM_EVENT_2: External event 2
3330 * @arg HRTIM_EVENT_3: External event 3
3331 * @arg HRTIM_EVENT_4: External event 4
3332 * @arg HRTIM_EVENT_5: External event 5
3333 * @arg HRTIM_EVENT_6: External event 6
3334 * @arg HRTIM_EVENT_7: External event 7
3335 * @arg HRTIM_EVENT_8: External event 8
3336 * @arg HRTIM_EVENT_9: External event 9
3337 * @arg HRTIM_EVENT_10: External event 10
3338 * @param pEventCfg: pointer to the event conditioning configuration structure
3339 * @note This function must be called before starting the timer
3340 * @retval HAL status
3341 */
3342 HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
3343 uint32_t Event,
3344 HRTIM_EventCfgTypeDef* pEventCfg)
3345 {
3346 /* Check parameters */
3347 assert_param(IS_HRTIM_EVENTSRC(pEventCfg->Source));
3348 assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Sensitivity, pEventCfg->Polarity));
3349 assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity));
3350 assert_param(IS_HRTIM_EVENTFASTMODE(Event, pEventCfg->FastMode));
3351 assert_param(IS_HRTIM_EVENTFILTER(Event, pEventCfg->Filter));
3352
3353 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3354 {
3355 return HAL_BUSY;
3356 }
3357
3358 /* Process Locked */
3359 __HAL_LOCK(hhrtim);
3360
3361 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3362
3363 /* Configure the event channel */
3364 HRTIM_EventConfig(hhrtim, Event, pEventCfg);
3365
3366 hhrtim->State = HAL_HRTIM_STATE_READY;
3367
3368 /* Process Unlocked */
3369 __HAL_UNLOCK(hhrtim);
3370
3371 return HAL_OK;
3372 }
3373
3374 /**
3375 * @brief Configures the external event conditioning block prescaler
3376 * @param hhrtim: pointer to HAL HRTIM handle
3377 * @param Prescaler: Prescaler value
3378 * This parameter can be one of the following values:
3379 * @arg HRTIM_EVENTPRESCALER_DIV1: fEEVS=fHRTIM
3380 * @arg HRTIM_EVENTPRESCALER_DIV2: fEEVS=fHRTIM / 2
3381 * @arg HRTIM_EVENTPRESCALER_DIV4: fEEVS=fHRTIM / 4
3382 * @arg HRTIM_EVENTPRESCALER_DIV8: fEEVS=fHRTIM / 8
3383 * @note This function must be called before starting the timer
3384 * @retval HAL status
3385 */
3386 HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
3387 uint32_t Prescaler)
3388 {
3389 uint32_t hrtim_eecr3;
3390
3391 /* Check parameters */
3392 assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler));
3393
3394 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3395 {
3396 return HAL_BUSY;
3397 }
3398
3399 /* Process Locked */
3400 __HAL_LOCK(hhrtim);
3401
3402 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3403
3404 /* Set the external event prescaler */
3405 hrtim_eecr3 = hhrtim->Instance->sCommonRegs.EECR3;
3406 hrtim_eecr3 &= ~(HRTIM_EECR3_EEVSD);
3407 hrtim_eecr3 |= Prescaler;
3408
3409 /* Update the HRTIM registers */
3410 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
3411
3412 hhrtim->State = HAL_HRTIM_STATE_READY;
3413
3414 /* Process Unlocked */
3415 __HAL_UNLOCK(hhrtim);
3416
3417 return HAL_OK;
3418 }
3419
3420 /**
3421 * @brief Configures the conditioning of fault input
3422 * @param hhrtim: pointer to HAL HRTIM handle
3423 * @param Fault: fault input to configure
3424 * This parameter can be one of the following values:
3425 * @arg HRTIM_FAULT_1: Fault input 1
3426 * @arg HRTIM_FAULT_2: Fault input 2
3427 * @arg HRTIM_FAULT_3: Fault input 3
3428 * @arg HRTIM_FAULT_4: Fault input 4
3429 * @arg HRTIM_FAULT_5: Fault input 5
3430 * @param pFaultCfg: pointer to the fault conditioning configuration structure
3431 * @note This function must be called before starting the timer and before
3432 * enabling faults inputs
3433 * @retval HAL status
3434 */
3435 HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim,
3436 uint32_t Fault,
3437 HRTIM_FaultCfgTypeDef* pFaultCfg)
3438 {
3439 uint32_t hrtim_fltinr1;
3440 uint32_t hrtim_fltinr2;
3441
3442 /* Check parameters */
3443 assert_param(IS_HRTIM_FAULT(Fault));
3444 assert_param(IS_HRTIM_FAULTSOURCE(pFaultCfg->Source));
3445 assert_param(IS_HRTIM_FAULTPOLARITY(pFaultCfg->Polarity));
3446 assert_param(IS_HRTIM_FAULTFILTER(pFaultCfg->Filter));
3447 assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock));
3448
3449 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3450 {
3451 return HAL_BUSY;
3452 }
3453
3454 /* Process Locked */
3455 __HAL_LOCK(hhrtim);
3456
3457 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3458
3459 /* Configure fault channel */
3460 hrtim_fltinr1 = hhrtim->Instance->sCommonRegs.FLTINR1;
3461 hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
3462
3463 switch (Fault)
3464 {
3465 case HRTIM_FAULT_1:
3466 {
3467 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK);
3468 hrtim_fltinr1 |= pFaultCfg->Polarity;
3469 hrtim_fltinr1 |= pFaultCfg->Source;
3470 hrtim_fltinr1 |= pFaultCfg->Filter;
3471 hrtim_fltinr1 |= pFaultCfg->Lock;
3472 }
3473 break;
3474 case HRTIM_FAULT_2:
3475 {
3476 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK);
3477 hrtim_fltinr1 |= (pFaultCfg->Polarity << 8);
3478 hrtim_fltinr1 |= (pFaultCfg->Source << 8);
3479 hrtim_fltinr1 |= (pFaultCfg->Filter << 8);
3480 hrtim_fltinr1 |= (pFaultCfg->Lock << 8);
3481 }
3482 break;
3483 case HRTIM_FAULT_3:
3484 {
3485 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK);
3486 hrtim_fltinr1 |= (pFaultCfg->Polarity << 16);
3487 hrtim_fltinr1 |= (pFaultCfg->Source << 16);
3488 hrtim_fltinr1 |= (pFaultCfg->Filter << 16);
3489 hrtim_fltinr1 |= (pFaultCfg->Lock << 16);
3490 }
3491 break;
3492 case HRTIM_FAULT_4:
3493 {
3494 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK);
3495 hrtim_fltinr1 |= (pFaultCfg->Polarity << 24);
3496 hrtim_fltinr1 |= (pFaultCfg->Source << 24);
3497 hrtim_fltinr1 |= (pFaultCfg->Filter << 24);
3498 hrtim_fltinr1 |= (pFaultCfg->Lock << 24);
3499 }
3500 break;
3501 case HRTIM_FAULT_5:
3502 {
3503 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK);
3504 hrtim_fltinr2 |= pFaultCfg->Polarity;
3505 hrtim_fltinr2 |= pFaultCfg->Source;
3506 hrtim_fltinr2 |= pFaultCfg->Filter;
3507 hrtim_fltinr2 |= pFaultCfg->Lock;
3508 }
3509 break;
3510 default:
3511 break;
3512 }
3513
3514 /* Update the HRTIM registers */
3515 hhrtim->Instance->sCommonRegs.FLTINR1 = hrtim_fltinr1;
3516 hhrtim->Instance->sCommonRegs.FLTINR2 = hrtim_fltinr2;
3517
3518 hhrtim->State = HAL_HRTIM_STATE_READY;
3519
3520 /* Process Unlocked */
3521 __HAL_UNLOCK(hhrtim);
3522
3523 return HAL_OK;
3524 }
3525
3526 /**
3527 * @brief Configures the fault conditioning block prescaler
3528 * @param hhrtim: pointer to HAL HRTIM handle
3529 * @param Prescaler: Prescaler value
3530 * This parameter can be one of the following values:
3531 * @arg HRTIM_FAULTPRESCALER_DIV1: fFLTS=fHRTIM
3532 * @arg HRTIM_FAULTPRESCALER_DIV2: fFLTS=fHRTIM / 2
3533 * @arg HRTIM_FAULTPRESCALER_DIV4: fFLTS=fHRTIM / 4
3534 * @arg HRTIM_FAULTPRESCALER_DIV8: fFLTS=fHRTIM / 8
3535 * @retval HAL status
3536 * @note This function must be called before starting the timer and before
3537 * enabling faults inputs
3538 */
3539 HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
3540 uint32_t Prescaler)
3541 {
3542 uint32_t hrtim_fltinr2;
3543
3544 /* Check parameters */
3545 assert_param(IS_HRTIM_FAULTPRESCALER(Prescaler));
3546
3547 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3548 {
3549 return HAL_BUSY;
3550 }
3551
3552 /* Process Locked */
3553 __HAL_LOCK(hhrtim);
3554
3555 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3556
3557 /* Set the external event prescaler */
3558 hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
3559 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLTSD);
3560 hrtim_fltinr2 |= Prescaler;
3561
3562 /* Update the HRTIM registers */
3563 hhrtim->Instance->sCommonRegs.FLTINR2 = hrtim_fltinr2;
3564
3565 hhrtim->State = HAL_HRTIM_STATE_READY;
3566
3567 /* Process Unlocked */
3568 __HAL_UNLOCK(hhrtim);
3569
3570 return HAL_OK;
3571 }
3572
3573 /**
3574 * @brief Enables or disables the HRTIMx Fault mode.
3575 * @param hhrtim: pointer to HAL HRTIM handle
3576 * @param Faults: fault input(s) to enable or disable
3577 * This parameter can be any combination of the following values:
3578 * @arg HRTIM_FAULT_1: Fault input 1
3579 * @arg HRTIM_FAULT_2: Fault input 2
3580 * @arg HRTIM_FAULT_3: Fault input 3
3581 * @arg HRTIM_FAULT_4: Fault input 4
3582 * @arg HRTIM_FAULT_5: Fault input 5
3583 * @param Enable: Fault(s) enabling
3584 * This parameter can be one of the following values:
3585 * @arg HRTIM_FAULTMODECTL_ENABLED: Fault(s) enabled
3586 * @arg HRTIM_FAULTMODECTL_DISABLED: Fault(s) disabled
3587 * @retval None
3588 */
3589 void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
3590 uint32_t Faults,
3591 uint32_t Enable)
3592 {
3593 uint32_t hrtim_fltinr1;
3594 uint32_t hrtim_fltinr2;
3595
3596 /* Check parameters */
3597 assert_param(IS_HRTIM_FAULT(Faults));
3598 assert_param(IS_HRTIM_FAULTMODECTL(Enable));
3599
3600 /* Configure fault channel */
3601 hrtim_fltinr1 = hhrtim->Instance->sCommonRegs.FLTINR1;
3602 hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
3603
3604 if ((Faults & HRTIM_FAULT_1) != RESET)
3605 {
3606 hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT1E;
3607 hrtim_fltinr1 |= Enable;
3608 }
3609 if ((Faults & HRTIM_FAULT_2) != RESET)
3610 {
3611 hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT2E;
3612 hrtim_fltinr1 |= (Enable << 8);
3613 }
3614 if ((Faults & HRTIM_FAULT_3) != RESET)
3615 {
3616 hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT3E;
3617 hrtim_fltinr1 |= (Enable << 16);
3618 }
3619 if ((Faults & HRTIM_FAULT_4) != RESET)
3620 {
3621 hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT4E;
3622 hrtim_fltinr1 |= (Enable << 24);
3623 }
3624 if ((Faults & HRTIM_FAULT_5) != RESET)
3625 {
3626 hrtim_fltinr2 &= ~HRTIM_FLTINR2_FLT5E;
3627 hrtim_fltinr2 |= Enable;
3628 }
3629
3630 /* Update the HRTIMx registers */
3631 hhrtim->Instance->sCommonRegs.FLTINR1 = hrtim_fltinr1;
3632 hhrtim->Instance->sCommonRegs.FLTINR2 = hrtim_fltinr2;
3633 }
3634
3635 /**
3636 * @brief Configures both the ADC trigger register update source and the ADC
3637 * trigger source.
3638 * @param hhrtim: pointer to HAL HRTIM handle
3639 * @param ADCTrigger: ADC trigger to configure
3640 * This parameter can be one of the following values:
3641 * @arg HRTIM_ADCTRIGGER_1: ADC trigger 1
3642 * @arg HRTIM_ADCTRIGGER_2: ADC trigger 2
3643 * @arg HRTIM_ADCTRIGGER_3: ADC trigger 3
3644 * @arg HRTIM_ADCTRIGGER_4: ADC trigger 4
3645 * @param pADCTriggerCfg: pointer to the ADC trigger configuration structure
3646 * @retval HAL status
3647 * @note This function must be called before starting the timer
3648 */
3649 HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim,
3650 uint32_t ADCTrigger,
3651 HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg)
3652 {
3653 uint32_t hrtim_cr1;
3654
3655 /* Check parameters */
3656 assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger));
3657 assert_param(IS_HRTIM_ADCTRIGGERUPDATE(pADCTriggerCfg->UpdateSource));
3658
3659 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3660 {
3661 return HAL_BUSY;
3662 }
3663
3664 /* Process Locked */
3665 __HAL_LOCK(hhrtim);
3666
3667 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3668
3669 /* Set the ADC trigger update source */
3670 hrtim_cr1 = hhrtim->Instance->sCommonRegs.CR1;
3671
3672 switch (ADCTrigger)
3673 {
3674 case HRTIM_ADCTRIGGER_1:
3675 {
3676 hrtim_cr1 &= ~(HRTIM_CR1_ADC1USRC);
3677 hrtim_cr1 |= (pADCTriggerCfg->UpdateSource & HRTIM_CR1_ADC1USRC);
3678
3679 /* Set the ADC trigger 1 source */
3680 hhrtim->Instance->sCommonRegs.ADC1R = pADCTriggerCfg->Trigger;
3681 }
3682 break;
3683 case HRTIM_ADCTRIGGER_2:
3684 {
3685 hrtim_cr1 &= ~(HRTIM_CR1_ADC2USRC);
3686 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 3) & HRTIM_CR1_ADC2USRC);
3687
3688 /* Set the ADC trigger 2 source */
3689 hhrtim->Instance->sCommonRegs.ADC2R = pADCTriggerCfg->Trigger;
3690 }
3691 break;
3692 case HRTIM_ADCTRIGGER_3:
3693 {
3694 hrtim_cr1 &= ~(HRTIM_CR1_ADC3USRC);
3695 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 6) & HRTIM_CR1_ADC3USRC);
3696
3697 /* Set the ADC trigger 3 source */
3698 hhrtim->Instance->sCommonRegs.ADC3R = pADCTriggerCfg->Trigger;
3699 }
3700 break;
3701 case HRTIM_ADCTRIGGER_4:
3702 {
3703 hrtim_cr1 &= ~(HRTIM_CR1_ADC4USRC);
3704 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 9) & HRTIM_CR1_ADC4USRC);
3705
3706 /* Set the ADC trigger 4 source */
3707 hhrtim->Instance->sCommonRegs.ADC4R = pADCTriggerCfg->Trigger;
3708 }
3709 break;
3710 }
3711
3712 /* Update the HRTIM registers */
3713 hhrtim->Instance->sCommonRegs.CR1 = hrtim_cr1;
3714
3715 hhrtim->State = HAL_HRTIM_STATE_READY;
3716
3717 /* Process Unlocked */
3718 __HAL_UNLOCK(hhrtim);
3719
3720 return HAL_OK;
3721 }
3722
3723 /**
3724 * @}
3725 */
3726
3727 /** @defgroup HRTIM_Exported_Functions_Group8 Timer waveform configuration and functions
3728 * @brief Functions used to configure and control a HRTIM timer
3729 * operating in waveform mode.
3730 *
3731 @verbatim
3732 ===============================================================================
3733 ##### HRTIM timer configuration and control functions #####
3734 ===============================================================================
3735 [..] This section provides functions allowing to:
3736 (+) Configure HRTIM timer general behavior
3737 (+) Configure HRTIM timer event filtering
3738 (+) Configure HRTIM timer deadtime insertion
3739 (+) Configure HRTIM timer chopper mode
3740 (+) Configure HRTIM timer burst DMA
3741 (+) Configure HRTIM timer compare unit
3742 (+) Configure HRTIM timer capture unit
3743 (+) Configure HRTIM timer output
3744 (+) Set HRTIM timer output level
3745 (+) Enable HRTIM timer output
3746 (+) Disable HRTIM timer output
3747 (+) Start HRTIM timer
3748 (+) Stop HRTIM timer
3749 (+) Start HRTIM timer and enable interrupt
3750 (+) Stop HRTIM timer and disable interrupt
3751 (+) Start HRTIM timer and enable DMA transfer
3752 (+) Stop HRTIM timer and disable DMA transfer
3753 (+) Enable or disable the burst mode controller
3754 (+) Start the burst mode controller (by software)
3755 (+) Trigger a Capture (by software)
3756 (+) Update the HRTIM timer preloadable registers (by software)
3757 (+) Reset the HRTIM timer counter (by software)
3758 (+) Start a burst DMA transfer
3759 (+) Enable timer register update
3760 (+) Disable timer register update
3761
3762 @endverbatim
3763 * @{
3764 */
3765
3766 /**
3767 * @brief Configures the general behavior of a timer operating in waveform mode
3768 * @param hhrtim: pointer to HAL HRTIM handle
3769 * @param TimerIdx: Timer index
3770 * This parameter can be one of the following values:
3771 * @arg HRTIM_TIMERINDEX_MASTER for master timer
3772 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3773 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3774 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3775 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3776 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3777 * @param pTimerCfg: pointer to the timer configuration structure
3778 * @note When the timer operates in waveform mode, all the features supported by
3779 * the HRTIM are available without any limitation.
3780 * @retval HAL status
3781 * @note This function must be called before starting the timer
3782 */
3783 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim,
3784 uint32_t TimerIdx,
3785 HRTIM_TimerCfgTypeDef * pTimerCfg)
3786 {
3787 /* Check parameters */
3788 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
3789
3790 /* Relevant for all HRTIM timers, including the master */
3791 assert_param(IS_HRTIM_HALFMODE(pTimerCfg->HalfModeEnable));
3792 assert_param(IS_HRTIM_SYNCSTART(pTimerCfg->StartOnSync));
3793 assert_param(IS_HRTIM_SYNCRESET(pTimerCfg->ResetOnSync));
3794 assert_param(IS_HHRTIM_DACSYNC(pTimerCfg->DACSynchro));
3795 assert_param(IS_HRTIM_PRELOAD(pTimerCfg->PreloadEnable));
3796 assert_param(IS_HRTIM_TIMERBURSTMODE(pTimerCfg->BurstMode));
3797 assert_param(IS_HRTIM_UPDATEONREPETITION(pTimerCfg->RepetitionUpdate));
3798
3799 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3800 {
3801 return HAL_BUSY;
3802 }
3803
3804 /* Process Locked */
3805 __HAL_LOCK(hhrtim);
3806
3807 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3808
3809 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
3810 {
3811 /* Check parameters */
3812 assert_param(IS_HRTIM_UPDATEGATING_MASTER(pTimerCfg->UpdateGating));
3813 assert_param(IS_HRTIM_MASTER_IT(pTimerCfg->InterruptRequests));
3814 assert_param(IS_HRTIM_MASTER_DMA(pTimerCfg->DMARequests));
3815
3816 /* Configure master timer */
3817 HRTIM_MasterWaveform_Config(hhrtim, pTimerCfg);
3818 }
3819 else
3820 {
3821 /* Check parameters */
3822 assert_param(IS_HRTIM_UPDATEGATING_TIM(pTimerCfg->UpdateGating));
3823 assert_param(IS_HRTIM_TIM_IT(pTimerCfg->InterruptRequests));
3824 assert_param(IS_HRTIM_TIM_DMA(pTimerCfg->DMARequests));
3825 assert_param(IS_HRTIM_TIMPUSHPULLMODE(pTimerCfg->PushPull));
3826 assert_param(IS_HRTIM_TIMFAULTENABLE(pTimerCfg->FaultEnable));
3827 assert_param(IS_HRTIM_TIMFAULTLOCK(pTimerCfg->FaultLock));
3828 assert_param(IS_HRTIM_TIMDEADTIMEINSERTION(pTimerCfg->PushPull,
3829 pTimerCfg->DeadTimeInsertion));
3830 assert_param(IS_HRTIM_TIMDELAYEDPROTECTION(pTimerCfg->PushPull,
3831 pTimerCfg->DelayedProtectionMode));
3832 assert_param(IS_HRTIM_TIMUPDATETRIGGER(pTimerCfg->UpdateTrigger));
3833 assert_param(IS_HRTIM_TIMRESETTRIGGER(pTimerCfg->ResetTrigger));
3834 assert_param(IS_HRTIM_TIMUPDATEONRESET(pTimerCfg->ResetUpdate));
3835
3836 /* Configure timing unit */
3837 HRTIM_TimingUnitWaveform_Config(hhrtim, TimerIdx, pTimerCfg);
3838 }
3839
3840 /* Update timer parameters */
3841 hhrtim->TimerParam[TimerIdx].InterruptRequests = pTimerCfg->InterruptRequests;
3842 hhrtim->TimerParam[TimerIdx].DMARequests = pTimerCfg->DMARequests;
3843 hhrtim->TimerParam[TimerIdx].DMASrcAddress = pTimerCfg->DMASrcAddress;
3844 hhrtim->TimerParam[TimerIdx].DMADstAddress = pTimerCfg->DMADstAddress;
3845 hhrtim->TimerParam[TimerIdx].DMASize = pTimerCfg->DMASize;
3846
3847 /* Force a software update */
3848 HRTIM_ForceRegistersUpdate(hhrtim, TimerIdx);
3849
3850 hhrtim->State = HAL_HRTIM_STATE_READY;
3851
3852 /* Process Unlocked */
3853 __HAL_UNLOCK(hhrtim);
3854
3855 return HAL_OK;
3856 }
3857
3858 /**
3859 * @brief Configures the event filtering capabilities of a timer (blanking, windowing)
3860 * @param hhrtim: pointer to HAL HRTIM handle
3861 * @param TimerIdx: Timer index
3862 * This parameter can be one of the following values:
3863 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3864 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3865 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3866 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3867 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3868 * @param Event: external event for which timer event filtering must be configured
3869 * This parameter can be one of the following values:
3870 * @arg HRTIM_EVENT_NONE: Reset timer event filtering configuration
3871 * @arg HRTIM_EVENT_1: External event 1
3872 * @arg HRTIM_EVENT_2: External event 2
3873 * @arg HRTIM_EVENT_3: External event 3
3874 * @arg HRTIM_EVENT_4: External event 4
3875 * @arg HRTIM_EVENT_5: External event 5
3876 * @arg HRTIM_EVENT_6: External event 6
3877 * @arg HRTIM_EVENT_7: External event 7
3878 * @arg HRTIM_EVENT_8: External event 8
3879 * @arg HRTIM_EVENT_9: External event 9
3880 * @arg HRTIM_EVENT_10: External event 10
3881 * @param pTimerEventFilteringCfg: pointer to the timer event filtering configuration structure
3882 * @note This function must be called before starting the timer
3883 * @retval HAL status
3884 */
3885 HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrtim,
3886 uint32_t TimerIdx,
3887 uint32_t Event,
3888 HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg)
3889 {
3890 uint32_t hrtim_eefr;
3891
3892 /* Check parameters */
3893 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
3894 assert_param(IS_HRTIM_EVENT(Event));
3895 assert_param(IS_HRTIM_TIMEVENTFILTER(pTimerEventFilteringCfg->Filter));
3896 assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch));
3897
3898 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3899 {
3900 return HAL_BUSY;
3901 }
3902
3903 /* Process Locked */
3904 __HAL_LOCK(hhrtim);
3905
3906 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3907
3908 /* Configure timer event filtering capabilities */
3909 switch (Event)
3910 {
3911 case HRTIM_EVENT_NONE:
3912 {
3913 hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = 0;
3914 hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = 0;
3915 }
3916 break;
3917 case HRTIM_EVENT_1:
3918 {
3919 hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
3920 hrtim_eefr &= ~(HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH);
3921 hrtim_eefr |= (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch);
3922 hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
3923 }
3924 break;
3925 case HRTIM_EVENT_2:
3926 {
3927 hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
3928 hrtim_eefr &= ~(HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH);
3929 hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6);
3930 hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
3931 }
3932 break;
3933 case HRTIM_EVENT_3:
3934 {
3935 hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
3936 hrtim_eefr &= ~(HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH);
3937 hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12);
3938 hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
3939 }
3940 break;
3941 case HRTIM_EVENT_4:
3942 {
3943 hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
3944 hrtim_eefr &= ~(HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH);
3945 hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18);
3946 hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
3947 }
3948 break;
3949 case HRTIM_EVENT_5:
3950 {
3951 hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
3952 hrtim_eefr &= ~(HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH);
3953 hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24);
3954 hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
3955 }
3956 break;
3957 case HRTIM_EVENT_6:
3958 {
3959 hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
3960 hrtim_eefr &= ~(HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH);
3961 hrtim_eefr |= (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch);
3962 hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
3963 }
3964 break;
3965 case HRTIM_EVENT_7:
3966 {
3967 hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
3968 hrtim_eefr &= ~(HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH);
3969 hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6);
3970 hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
3971 }
3972 break;
3973 case HRTIM_EVENT_8:
3974 {
3975 hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
3976 hrtim_eefr &= ~(HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH);
3977 hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12);
3978 hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
3979 }
3980 break;
3981 case HRTIM_EVENT_9:
3982 {
3983 hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
3984 hrtim_eefr &= ~(HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH);
3985 hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18);
3986 hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
3987 }
3988 break;
3989 case HRTIM_EVENT_10:
3990 {
3991 hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
3992 hrtim_eefr &= ~(HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH);
3993 hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24);
3994 hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
3995 }
3996 break;
3997 }
3998
3999 hhrtim->State = HAL_HRTIM_STATE_READY;
4000
4001 /* Process Unlocked */
4002 __HAL_UNLOCK(hhrtim);
4003
4004 return HAL_OK;
4005 }
4006
4007 /**
4008 * @brief Configures the deadtime insertion feature for a timer
4009 * @param hhrtim: pointer to HAL HRTIM handle
4010 * @param TimerIdx: Timer index
4011 * This parameter can be one of the following values:
4012 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4013 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4014 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4015 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4016 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4017 * @param pDeadTimeCfg: pointer to the deadtime insertion configuration structure
4018 * @retval HAL status
4019 * @note This function must be called before starting the timer
4020 */
4021 HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim,
4022 uint32_t TimerIdx,
4023 HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg)
4024 {
4025 uint32_t hrtim_dtr;
4026
4027 /* Check parameters */
4028 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
4029 assert_param(IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(pDeadTimeCfg->Prescaler));
4030 assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGN(pDeadTimeCfg->RisingSign));
4031 assert_param(IS_HRTIM_TIMDEADTIME_RISINGLOCK(pDeadTimeCfg->RisingLock));
4032 assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(pDeadTimeCfg->RisingSignLock));
4033 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGN(pDeadTimeCfg->FallingSign));
4034 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock));
4035 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock));
4036
4037 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4038 {
4039 return HAL_BUSY;
4040 }
4041
4042 /* Process Locked */
4043 __HAL_LOCK(hhrtim);
4044
4045 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4046
4047 hrtim_dtr = hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR;
4048
4049 /* Clear timer deadtime configuration */
4050 hrtim_dtr &= ~(HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC |
4051 HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_DTF |
4052 HRTIM_DTR_SDTF | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK);
4053
4054 /* Set timer deadtime configuration */
4055 hrtim_dtr |= pDeadTimeCfg->Prescaler;
4056 hrtim_dtr |= pDeadTimeCfg->RisingValue;
4057 hrtim_dtr |= pDeadTimeCfg->RisingSign;
4058 hrtim_dtr |= pDeadTimeCfg->RisingSignLock;
4059 hrtim_dtr |= pDeadTimeCfg->RisingLock;
4060 hrtim_dtr |= (pDeadTimeCfg->FallingValue << 16);
4061 hrtim_dtr |= pDeadTimeCfg->FallingSign;
4062 hrtim_dtr |= pDeadTimeCfg->FallingSignLock;
4063 hrtim_dtr |= pDeadTimeCfg->FallingLock;
4064
4065 /* Update the HRTIM registers */
4066 hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR = hrtim_dtr;
4067
4068 hhrtim->State = HAL_HRTIM_STATE_READY;
4069
4070 /* Process Unlocked */
4071 __HAL_UNLOCK(hhrtim);
4072
4073 return HAL_OK;
4074 }
4075
4076 /**
4077 * @brief Configures the chopper mode feature for a timer
4078 * @param hhrtim: pointer to HAL HRTIM handle
4079 * @param TimerIdx: Timer index
4080 * This parameter can be one of the following values:
4081 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4082 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4083 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4084 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4085 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4086 * @param pChopperModeCfg: pointer to the chopper mode configuration structure
4087 * @retval HAL status
4088 * @note This function must be called before configuring the timer output(s)
4089 */
4090 HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim,
4091 uint32_t TimerIdx,
4092 HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg)
4093 {
4094 uint32_t hrtim_chpr;
4095
4096 /* Check parameters */
4097 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
4098 assert_param(IS_HRTIM_CHOPPER_PRESCALERRATIO(pChopperModeCfg->CarrierFreq));
4099 assert_param(IS_HRTIM_CHOPPER_DUTYCYCLE(pChopperModeCfg->DutyCycle));
4100 assert_param(IS_HRTIM_CHOPPER_PULSEWIDTH(pChopperModeCfg->StartPulse));
4101
4102 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4103 {
4104 return HAL_BUSY;
4105 }
4106
4107 /* Process Locked */
4108 __HAL_LOCK(hhrtim);
4109
4110 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4111
4112 hrtim_chpr = hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR;
4113
4114 /* Clear timer chopper mode configuration */
4115 hrtim_chpr &= ~(HRTIM_CHPR_CARFRQ | HRTIM_CHPR_CARDTY | HRTIM_CHPR_STRPW);
4116
4117 /* Set timer choppe mode configuration */
4118 hrtim_chpr |= pChopperModeCfg->CarrierFreq;
4119 hrtim_chpr |= (pChopperModeCfg->DutyCycle);
4120 hrtim_chpr |= (pChopperModeCfg->StartPulse);
4121
4122 /* Update the HRTIM registers */
4123 hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR = hrtim_chpr;
4124
4125 hhrtim->State = HAL_HRTIM_STATE_READY;
4126
4127 /* Process Unlocked */
4128 __HAL_UNLOCK(hhrtim);
4129
4130 return HAL_OK;
4131 }
4132
4133 /**
4134 * @brief Configures the burst DMA controller for a timer
4135 * @param hhrtim: pointer to HAL HRTIM handle
4136 * @param TimerIdx: Timer index
4137 * This parameter can be one of the following values:
4138 * @arg HRTIM_TIMERINDEX_MASTER for master timer
4139 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4140 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4141 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4142 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4143 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4144 * @param RegistersToUpdate: registers to be written by DMA
4145 * This parameter can be any combination of the following values:
4146 * @arg HRTIM_BURSTDMA_CR: HRTIM_MCR or HRTIM_TIMxCR
4147 * @arg HRTIM_BURSTDMA_ICR: HRTIM_MICR or HRTIM_TIMxICR
4148 * @arg HRTIM_BURSTDMA_DIER: HRTIM_MDIER or HRTIM_TIMxDIER
4149 * @arg HRTIM_BURSTDMA_CNT: HRTIM_MCNT or HRTIM_TIMxCNT
4150 * @arg HRTIM_BURSTDMA_PER: HRTIM_MPER or HRTIM_TIMxPER
4151 * @arg HRTIM_BURSTDMA_REP: HRTIM_MREP or HRTIM_TIMxREP
4152 * @arg HRTIM_BURSTDMA_CMP1: HRTIM_MCMP1 or HRTIM_TIMxCMP1
4153 * @arg HRTIM_BURSTDMA_CMP2: HRTIM_MCMP2 or HRTIM_TIMxCMP2
4154 * @arg HRTIM_BURSTDMA_CMP3: HRTIM_MCMP3 or HRTIM_TIMxCMP3
4155 * @arg HRTIM_BURSTDMA_CMP4: HRTIM_MCMP4 or HRTIM_TIMxCMP4
4156 * @arg HRTIM_BURSTDMA_DTR: HRTIM_TIMxDTR
4157 * @arg HRTIM_BURSTDMA_SET1R: HRTIM_TIMxSET1R
4158 * @arg HRTIM_BURSTDMA_RST1R: HRTIM_TIMxRST1R
4159 * @arg HRTIM_BURSTDMA_SET2R: HRTIM_TIMxSET2R
4160 * @arg HRTIM_BURSTDMA_RST2R: HRTIM_TIMxRST2R
4161 * @arg HRTIM_BURSTDMA_EEFR1: HRTIM_TIMxEEFR1
4162 * @arg HRTIM_BURSTDMA_EEFR2: HRTIM_TIMxEEFR2
4163 * @arg HRTIM_BURSTDMA_RSTR: HRTIM_TIMxRSTR
4164 * @arg HRTIM_BURSTDMA_CHPR: HRTIM_TIMxCHPR
4165 * @arg HRTIM_BURSTDMA_OUTR: HRTIM_TIMxOUTR
4166 * @arg HRTIM_BURSTDMA_FLTR: HRTIM_TIMxFLTR
4167 * @retval HAL status
4168 * @note This function must be called before starting the timer
4169 */
4170 HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim,
4171 uint32_t TimerIdx,
4172 uint32_t RegistersToUpdate)
4173 {
4174 /* Check parameters */
4175 assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate));
4176
4177 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4178 {
4179 return HAL_BUSY;
4180 }
4181
4182 /* Process Locked */
4183 __HAL_LOCK(hhrtim);
4184
4185 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4186
4187 /* Set the burst DMA timer update register */
4188 switch (TimerIdx)
4189 {
4190 case HRTIM_TIMERINDEX_TIMER_A:
4191 {
4192 hhrtim->Instance->sCommonRegs.BDTAUPR = RegistersToUpdate;
4193 }
4194 break;
4195 case HRTIM_TIMERINDEX_TIMER_B:
4196 {
4197 hhrtim->Instance->sCommonRegs.BDTBUPR = RegistersToUpdate;
4198 }
4199 break;
4200 case HRTIM_TIMERINDEX_TIMER_C:
4201 {
4202 hhrtim->Instance->sCommonRegs.BDTCUPR = RegistersToUpdate;
4203 }
4204 break;
4205 case HRTIM_TIMERINDEX_TIMER_D:
4206 {
4207 hhrtim->Instance->sCommonRegs.BDTDUPR = RegistersToUpdate;
4208 }
4209 break;
4210 case HRTIM_TIMERINDEX_TIMER_E:
4211 {
4212 hhrtim->Instance->sCommonRegs.BDTEUPR = RegistersToUpdate;
4213 }
4214 break;
4215 case HRTIM_TIMERINDEX_MASTER:
4216 {
4217 hhrtim->Instance->sCommonRegs.BDMUPR = RegistersToUpdate;
4218 }
4219 break;
4220 }
4221
4222 hhrtim->State = HAL_HRTIM_STATE_READY;
4223
4224 /* Process Unlocked */
4225 __HAL_UNLOCK(hhrtim);
4226
4227 return HAL_OK;
4228 }
4229
4230 /**
4231 * @brief Configures the compare unit of a timer operating in waveform mode
4232 * @param hhrtim: pointer to HAL HRTIM handle
4233 * @param TimerIdx: Timer index
4234 * This parameter can be one of the following values:
4235 * @arg HRTIM_TIMERINDEX_MASTER for master timer
4236 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4237 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4238 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4239 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4240 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4241 * @param CompareUnit: Compare unit to configure
4242 * This parameter can be one of the following values:
4243 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
4244 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
4245 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
4246 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
4247 * @param pCompareCfg: pointer to the compare unit configuration structure
4248 * @note When auto delayed mode is required for compare unit 2 or compare unit 4,
4249 * application has to configure separately the capture unit. Capture unit
4250 * to configure in that case depends on the compare unit auto delayed mode
4251 * is applied to (see below):
4252 * Auto delayed on output compare 2: capture unit 1 must be configured
4253 * Auto delayed on output compare 4: capture unit 2 must be configured
4254 * @retval HAL status
4255 * @note This function must be called before starting the timer
4256 */
4257 HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim,
4258 uint32_t TimerIdx,
4259 uint32_t CompareUnit,
4260 HRTIM_CompareCfgTypeDef* pCompareCfg)
4261 {
4262 /* Check parameters */
4263 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
4264
4265 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4266 {
4267 return HAL_BUSY;
4268 }
4269
4270 /* Process Locked */
4271 __HAL_LOCK(hhrtim);
4272
4273 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4274
4275 /* Configure the compare unit */
4276 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
4277 {
4278 switch (CompareUnit)
4279 {
4280 case HRTIM_COMPAREUNIT_1:
4281 {
4282 hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue;
4283 }
4284 break;
4285 case HRTIM_COMPAREUNIT_2:
4286 {
4287 hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue;
4288 }
4289 break;
4290 case HRTIM_COMPAREUNIT_3:
4291 {
4292 hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue;
4293 }
4294 break;
4295 case HRTIM_COMPAREUNIT_4:
4296 {
4297 hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue;
4298 }
4299 break;
4300 }
4301 }
4302 else
4303 {
4304 switch (CompareUnit)
4305 {
4306 case HRTIM_COMPAREUNIT_1:
4307 {
4308 /* Set the compare value */
4309 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
4310 }
4311 break;
4312 case HRTIM_COMPAREUNIT_2:
4313 {
4314 /* Check parameters */
4315 assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
4316
4317 /* Set the compare value */
4318 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
4319
4320 if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
4321 {
4322 /* Configure auto-delayed mode */
4323 /* DELCMP2 bitfield must be reset when reprogrammed from one value */
4324 /* to the other to reinitialize properly the auto-delayed mechanism */
4325 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP2;
4326 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= pCompareCfg->AutoDelayedMode;
4327
4328 /* Set the compare value for timeout compare unit (if any) */
4329 if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
4330 {
4331 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
4332 }
4333 else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
4334 {
4335 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
4336 }
4337 }
4338 }
4339 break;
4340 case HRTIM_COMPAREUNIT_3:
4341 {
4342 /* Set the compare value */
4343 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
4344 }
4345 break;
4346 case HRTIM_COMPAREUNIT_4:
4347 {
4348 /* Check parameters */
4349 assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
4350
4351 /* Set the compare value */
4352 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
4353
4354 if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
4355 {
4356 /* Configure auto-delayed mode */
4357 /* DELCMP4 bitfield must be reset when reprogrammed from one value */
4358 /* to the other to reinitialize properly the auto-delayed mechanism */
4359 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP4;
4360 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= (pCompareCfg->AutoDelayedMode << 2);
4361
4362 /* Set the compare value for timeout compare unit (if any) */
4363 if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
4364 {
4365 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
4366 }
4367 else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
4368 {
4369 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
4370 }
4371 }
4372 }
4373 break;
4374 }
4375 }
4376 hhrtim->State = HAL_HRTIM_STATE_READY;
4377
4378 /* Process Unlocked */
4379 __HAL_UNLOCK(hhrtim);
4380
4381 return HAL_OK;
4382 }
4383
4384 /**
4385 * @brief Configures the cature unit of a timer operating in waveform mode
4386 * @param hhrtim: pointer to HAL HRTIM handle
4387 * @param TimerIdx: Timer index
4388 * This parameter can be one of the following values:
4389 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4390 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4391 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4392 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4393 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4394 * @param CaptureUnit: Capture unit to configure
4395 * This parameter can be one of the following values:
4396 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
4397 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
4398 * @param pCaptureCfg: pointer to the compare unit configuration structure
4399 * @retval HAL status
4400 * @note This function must be called before starting the timer
4401 */
4402 HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim,
4403 uint32_t TimerIdx,
4404 uint32_t CaptureUnit,
4405 HRTIM_CaptureCfgTypeDef* pCaptureCfg)
4406 {
4407 /* Check parameters */
4408 assert_param(IS_HRTIM_TIMER_CAPTURETRIGGER(TimerIdx, pCaptureCfg->Trigger));
4409
4410 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4411 {
4412 return HAL_BUSY;
4413 }
4414
4415 /* Process Locked */
4416 __HAL_LOCK(hhrtim);
4417
4418 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4419
4420 /* Configure the capture unit */
4421 switch (CaptureUnit)
4422 {
4423 case HRTIM_CAPTUREUNIT_1:
4424 {
4425 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = pCaptureCfg->Trigger;
4426 }
4427 break;
4428 case HRTIM_CAPTUREUNIT_2:
4429 {
4430 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = pCaptureCfg->Trigger;
4431 }
4432 break;
4433 }
4434
4435 hhrtim->State = HAL_HRTIM_STATE_READY;
4436
4437 /* Process Unlocked */
4438 __HAL_UNLOCK(hhrtim);
4439
4440 return HAL_OK;
4441 }
4442
4443 /**
4444 * @brief Configures the output of a timer operating in waveform mode
4445 * @param hhrtim: pointer to HAL HRTIM handle
4446 * @param TimerIdx: Timer index
4447 * This parameter can be one of the following values:
4448 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4449 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4450 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4451 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4452 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4453 * @param Output: Timer output
4454 * This parameter can be one of the following values:
4455 * @arg HRTIM_OUTPUT_TA1: Timer A - Ouput 1
4456 * @arg HRTIM_OUTPUT_TA2: Timer A - Ouput 2
4457 * @arg HRTIM_OUTPUT_TB1: Timer B - Ouput 1
4458 * @arg HRTIM_OUTPUT_TB2: Timer B - Ouput 2
4459 * @arg HRTIM_OUTPUT_TC1: Timer C - Ouput 1
4460 * @arg HRTIM_OUTPUT_TC2: Timer C - Ouput 2
4461 * @arg HRTIM_OUTPUT_TD1: Timer D - Ouput 1
4462 * @arg HRTIM_OUTPUT_TD2: Timer D - Ouput 2
4463 * @arg HRTIM_OUTPUT_TE1: Timer E - Ouput 1
4464 * @arg HRTIM_OUTPUT_TE2: Timer E - Ouput 2
4465 * @param pOutputCfg: pointer to the timer output configuration structure
4466 * @retval HAL status
4467 * @note This function must be called before configuring the timer and after
4468 * configuring the deadtime insertion feature (if required).
4469 */
4470 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim,
4471 uint32_t TimerIdx,
4472 uint32_t Output,
4473 HRTIM_OutputCfgTypeDef * pOutputCfg)
4474 {
4475 /* Check parameters */
4476 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
4477 assert_param(IS_HRTIM_OUTPUTPOLARITY(pOutputCfg->Polarity));
4478 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pOutputCfg->IdleLevel));
4479 assert_param(IS_HRTIM_OUTPUTIDLEMODE(pOutputCfg->IdleMode));
4480 assert_param(IS_HRTIM_OUTPUTFAULTLEVEL(pOutputCfg->FaultLevel));
4481 assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable));
4482 assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed));
4483
4484 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4485 {
4486 return HAL_BUSY;
4487 }
4488
4489 /* Process Locked */
4490 __HAL_LOCK(hhrtim);
4491
4492 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4493
4494 /* Configure the timer output */
4495 HRTIM_OutputConfig(hhrtim,
4496 TimerIdx,
4497 Output,
4498 pOutputCfg);
4499
4500 hhrtim->State = HAL_HRTIM_STATE_READY;
4501
4502 /* Process Unlocked */
4503 __HAL_UNLOCK(hhrtim);
4504
4505 return HAL_OK;
4506 }
4507
4508 /**
4509 * @brief Forces the timer output to its active or inactive state
4510 * @param hhrtim: pointer to HAL HRTIM handle
4511 * @param TimerIdx: Timer index
4512 * This parameter can be one of the following values:
4513 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4514 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4515 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4516 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4517 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4518 * @param Output: Timer output
4519 * This parameter can be one of the following values:
4520 * @arg HRTIM_OUTPUT_TA1: Timer A - Ouput 1
4521 * @arg HRTIM_OUTPUT_TA2: Timer A - Ouput 2
4522 * @arg HRTIM_OUTPUT_TB1: Timer B - Ouput 1
4523 * @arg HRTIM_OUTPUT_TB2: Timer B - Ouput 2
4524 * @arg HRTIM_OUTPUT_TC1: Timer C - Ouput 1
4525 * @arg HRTIM_OUTPUT_TC2: Timer C - Ouput 2
4526 * @arg HRTIM_OUTPUT_TD1: Timer D - Ouput 1
4527 * @arg HRTIM_OUTPUT_TD2: Timer D - Ouput 2
4528 * @arg HRTIM_OUTPUT_TE1: Timer E - Ouput 1
4529 * @arg HRTIM_OUTPUT_TE2: Timer E - Ouput 2
4530 * @param OutputLevel: indicates whether the output is forced to its active or inactive level
4531 * This parameter can be one of the following values:
4532 * @arg HRTIM_OUTPUTLEVEL_ACTIVE: output is forced to its active level
4533 * @arg HRTIM_OUTPUTLEVEL_INACTIVE: output is forced to its inactive level
4534 * @retval HAL status
4535 * @note The 'software set/reset trigger' bit in the output set/reset registers
4536 * is automatically reset by hardware
4537 */
4538 HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
4539 uint32_t TimerIdx,
4540 uint32_t Output,
4541 uint32_t OutputLevel)
4542 {
4543 /* Check parameters */
4544 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
4545 assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel));
4546
4547 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4548 {
4549 return HAL_BUSY;
4550 }
4551
4552 /* Process Locked */
4553 __HAL_LOCK(hhrtim);
4554
4555 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4556
4557 /* Force timer output level */
4558 switch (Output)
4559 {
4560 case HRTIM_OUTPUT_TA1:
4561 case HRTIM_OUTPUT_TB1:
4562 case HRTIM_OUTPUT_TC1:
4563 case HRTIM_OUTPUT_TD1:
4564 case HRTIM_OUTPUT_TE1:
4565 {
4566 if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
4567 {
4568 /* Force output to its active state */
4569 hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R |= HRTIM_SET1R_SST;
4570 }
4571 else
4572 {
4573 /* Force output to its inactive state */
4574 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R |= HRTIM_RST1R_SRT;
4575 }
4576 }
4577 break;
4578 case HRTIM_OUTPUT_TA2:
4579 case HRTIM_OUTPUT_TB2:
4580 case HRTIM_OUTPUT_TC2:
4581 case HRTIM_OUTPUT_TD2:
4582 case HRTIM_OUTPUT_TE2:
4583 {
4584 if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
4585 {
4586 /* Force output to its active state */
4587 hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R |= HRTIM_SET2R_SST;
4588 }
4589 else
4590 {
4591 /* Force output to its inactive state */
4592 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R |= HRTIM_RST2R_SRT;
4593 }
4594 }
4595 break;
4596 }
4597
4598 hhrtim->State = HAL_HRTIM_STATE_READY;
4599
4600 /* Process Unlocked */
4601 __HAL_UNLOCK(hhrtim);
4602
4603 return HAL_OK;
4604 }
4605
4606 /**
4607 * @brief Enables the generation of the waveform signal on the designated output(s)
4608 * Ouputs can becombined (ORed) to allow for simultaneous output enabling
4609 * @param hhrtim: pointer to HAL HRTIM handle
4610 * @param OutputsToStart: Timer output(s) to enable
4611 * This parameter can be any combination of the following values:
4612 * @arg HRTIM_OUTPUT_TA1: Timer A - Ouput 1
4613 * @arg HRTIM_OUTPUT_TA2: Timer A - Ouput 2
4614 * @arg HRTIM_OUTPUT_TB1: Timer B - Ouput 1
4615 * @arg HRTIM_OUTPUT_TB2: Timer B - Ouput 2
4616 * @arg HRTIM_OUTPUT_TC1: Timer C - Ouput 1
4617 * @arg HRTIM_OUTPUT_TC2: Timer C - Ouput 2
4618 * @arg HRTIM_OUTPUT_TD1: Timer D - Ouput 1
4619 * @arg HRTIM_OUTPUT_TD2: Timer D - Ouput 2
4620 * @arg HRTIM_OUTPUT_TE1: Timer E - Ouput 1
4621 * @arg HRTIM_OUTPUT_TE2: Timer E - Ouput 2
4622 * @retval HAL status
4623 */
4624 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim,
4625 uint32_t OutputsToStart)
4626 {
4627 /* Check the parameters */
4628 assert_param(IS_HRTIM_OUTPUT(OutputsToStart));
4629
4630 /* Process Locked */
4631 __HAL_LOCK(hhrtim);
4632
4633 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4634
4635 /* Enable the HRTIM outputs */
4636 hhrtim->Instance->sCommonRegs.OENR |= (OutputsToStart);
4637
4638 hhrtim->State = HAL_HRTIM_STATE_READY;
4639
4640 /* Process Unlocked */
4641 __HAL_UNLOCK(hhrtim);
4642
4643 return HAL_OK;
4644 }
4645
4646 /**
4647 * @brief Disables the generation of the waveform signal on the designated output(s)
4648 * Ouputs can becombined (ORed) to allow for simultaneous output disabling
4649 * @param hhrtim: pointer to HAL HRTIM handle
4650 * @param OutputsToStop: Timer output(s) to disable
4651 * This parameter can be any combination of the following values:
4652 * @arg HRTIM_OUTPUT_TA1: Timer A - Ouput 1
4653 * @arg HRTIM_OUTPUT_TA2: Timer A - Ouput 2
4654 * @arg HRTIM_OUTPUT_TB1: Timer B - Ouput 1
4655 * @arg HRTIM_OUTPUT_TB2: Timer B - Ouput 2
4656 * @arg HRTIM_OUTPUT_TC1: Timer C - Ouput 1
4657 * @arg HRTIM_OUTPUT_TC2: Timer C - Ouput 2
4658 * @arg HRTIM_OUTPUT_TD1: Timer D - Ouput 1
4659 * @arg HRTIM_OUTPUT_TD2: Timer D - Ouput 2
4660 * @arg HRTIM_OUTPUT_TE1: Timer E - Ouput 1
4661 * @arg HRTIM_OUTPUT_TE2: Timer E - Ouput 2
4662 * @retval HAL status
4663 */
4664 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim,
4665 uint32_t OutputsToStop)
4666 {
4667 /* Check the parameters */
4668 assert_param(IS_HRTIM_OUTPUT(OutputsToStop));
4669
4670 /* Process Locked */
4671 __HAL_LOCK(hhrtim);
4672
4673 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4674
4675 /* Enable the HRTIM outputs */
4676 hhrtim->Instance->sCommonRegs.ODISR |= (OutputsToStop);
4677
4678 hhrtim->State = HAL_HRTIM_STATE_READY;
4679
4680 /* Process Unlocked */
4681 __HAL_UNLOCK(hhrtim);
4682
4683 return HAL_OK;
4684 }
4685
4686 /**
4687 * @brief Starts the counter of the designated timer(s) operating in waveform mode
4688 * Timers can be combined (ORed) to allow for simultaneous counter start
4689 * @param hhrtim: pointer to HAL HRTIM handle
4690 * @param Timers: Timer counter(s) to start
4691 * This parameter can be any combination of the following values:
4692 * @arg HRTIM_TIMERID_MASTER
4693 * @arg HRTIM_TIMERID_TIMER_A
4694 * @arg HRTIM_TIMERID_TIMER_B
4695 * @arg HRTIM_TIMERID_TIMER_C
4696 * @arg HRTIM_TIMERID_TIMER_D
4697 * @arg HRTIM_TIMERID_TIMER_E
4698 * @retval HAL status
4699 */
4700 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart(HRTIM_HandleTypeDef * hhrtim,
4701 uint32_t Timers)
4702 {
4703 /* Check the parameters */
4704 assert_param(IS_HRTIM_TIMERID(Timers));
4705
4706 /* Process Locked */
4707 __HAL_LOCK(hhrtim);
4708
4709 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4710
4711 /* Enable timer(s) counter */
4712 hhrtim->Instance->sMasterRegs.MCR |= (Timers);
4713
4714 hhrtim->State = HAL_HRTIM_STATE_READY;
4715
4716 /* Process Unlocked */
4717 __HAL_UNLOCK(hhrtim);
4718
4719 return HAL_OK;
4720 }
4721
4722 /**
4723 * @brief Stops the counter of the designated timer(s) operating in waveform mode
4724 * Timers can be combined (ORed) to allow for simultaneous counter stop
4725 * @param hhrtim: pointer to HAL HRTIM handle
4726 * @param Timers: Timer counter(s) to stop
4727 * This parameter can be any combination of the following values:
4728 * @arg HRTIM_TIMER_MASTER
4729 * @arg HRTIM_TIMER_A
4730 * @arg HRTIM_TIMER_B
4731 * @arg HRTIM_TIMER_C
4732 * @arg HRTIM_TIMER_D
4733 * @arg HRTIM_TIMER_E
4734 * @retval HAL status
4735 * @note The counter of a timer is stopped only if all timer outputs are disabled
4736 */
4737 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop(HRTIM_HandleTypeDef * hhrtim,
4738 uint32_t Timers)
4739 {
4740 /* Check the parameters */
4741 assert_param(IS_HRTIM_TIMERID(Timers));
4742
4743 /* Process Locked */
4744 __HAL_LOCK(hhrtim);
4745
4746 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4747
4748 /* Disable timer(s) counter */
4749 hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
4750
4751 hhrtim->State = HAL_HRTIM_STATE_READY;
4752
4753 /* Process Unlocked */
4754 __HAL_UNLOCK(hhrtim);
4755
4756 return HAL_OK;
4757 }
4758
4759 /**
4760 * @brief Starts the counter of the designated timer(s) operating in waveform mode
4761 * Timers can be combined (ORed) to allow for simultaneous counter start
4762 * @param hhrtim: pointer to HAL HRTIM handle
4763 * @param Timers: Timer counter(s) to start
4764 * This parameter can be any combination of the following values:
4765 * @arg HRTIM_TIMERID_MASTER
4766 * @arg HRTIM_TIMERID_A
4767 * @arg HRTIM_TIMERID_B
4768 * @arg HRTIM_TIMERID_C
4769 * @arg HRTIM_TIMERID_D
4770 * @arg HRTIM_TIMERID_E
4771 * @note HRTIM interrupts (e.g. faults interrupts) and interrupts related
4772 * to the timers to start are enabled within this function.
4773 * Interrupts to enable are selected through HAL_HRTIM_WaveformTimerConfig
4774 * function.
4775 * @retval HAL status
4776 */
4777 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_IT(HRTIM_HandleTypeDef * hhrtim,
4778 uint32_t Timers)
4779 {
4780 uint8_t timer_idx;
4781
4782 /* Check the parameters */
4783 assert_param(IS_HRTIM_TIMERID(Timers));
4784
4785 /* Process Locked */
4786 __HAL_LOCK(hhrtim);
4787
4788 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4789
4790 /* Enable HRTIM interrupts (if required) */
4791 __HAL_HRTIM_ENABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
4792
4793 /* Enable master timer related interrupts (if required) */
4794 if ((Timers & HRTIM_TIMERID_MASTER) != RESET)
4795 {
4796 __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim,
4797 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
4798 }
4799
4800 /* Enable timing unit related interrupts (if required) */
4801 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
4802 timer_idx < HRTIM_TIMERINDEX_MASTER ;
4803 timer_idx++)
4804 {
4805 if ((Timers & TimerIdxToTimerId[timer_idx]) != RESET)
4806 {
4807 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim,
4808 timer_idx,
4809 hhrtim->TimerParam[timer_idx].InterruptRequests);
4810 }
4811 }
4812
4813 /* Enable timer(s) counter */
4814 hhrtim->Instance->sMasterRegs.MCR |= (Timers);
4815
4816 hhrtim->State = HAL_HRTIM_STATE_READY;
4817
4818 /* Process Unlocked */
4819 __HAL_UNLOCK(hhrtim);
4820
4821 return HAL_OK;}
4822
4823 /**
4824 * @brief Stops the counter of the designated timer(s) operating in waveform mode
4825 * Timers can be combined (ORed) to allow for simultaneous counter stop
4826 * @param hhrtim: pointer to HAL HRTIM handle
4827 * @param Timers: Timer counter(s) to stop
4828 * This parameter can be any combination of the following values:
4829 * @arg HRTIM_TIMER_MASTER
4830 * @arg HRTIM_TIMER_A
4831 * @arg HRTIM_TIMER_B
4832 * @arg HRTIM_TIMER_C
4833 * @arg HRTIM_TIMER_D
4834 * @arg HRTIM_TIMER_E
4835 * @retval HAL status
4836 * @note The counter of a timer is stopped only if all timer outputs are disabled
4837 * @note All enabled timer related interrupts are disabled.
4838 */
4839 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_IT(HRTIM_HandleTypeDef * hhrtim,
4840 uint32_t Timers)
4841 {
4842 /* ++ WA */
4843 __IO uint32_t delai = (uint32_t)(0x17F);
4844 /* -- WA */
4845
4846 uint8_t timer_idx;
4847
4848 /* Check the parameters */
4849 assert_param(IS_HRTIM_TIMERID(Timers));
4850
4851 /* Process Locked */
4852 __HAL_LOCK(hhrtim);
4853
4854 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4855
4856 /* Disable HRTIM interrupts (if required) */
4857 __HAL_HRTIM_DISABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
4858
4859 /* Disable master timer related interrupts (if required) */
4860 if ((Timers & HRTIM_TIMERID_MASTER) != RESET)
4861 {
4862 /* Interrupts enable flag must be cleared one by one */
4863 __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
4864 }
4865
4866 /* Disable timing unit related interrupts (if required) */
4867 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
4868 timer_idx < HRTIM_TIMERINDEX_MASTER ;
4869 timer_idx++)
4870 {
4871 if ((Timers & TimerIdxToTimerId[timer_idx]) != RESET)
4872 {
4873 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, timer_idx, hhrtim->TimerParam[timer_idx].InterruptRequests);
4874 }
4875 }
4876
4877 /* ++ WA */
4878 do { delai--; } while (delai != 0);
4879 /* -- WA */
4880
4881 /* Disable timer(s) counter */
4882 hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
4883
4884 hhrtim->State = HAL_HRTIM_STATE_READY;
4885
4886 /* Process Unlocked */
4887 __HAL_UNLOCK(hhrtim);
4888
4889 return HAL_OK;
4890 }
4891
4892 /**
4893 * @brief Starts the counter of the designated timer(s) operating in waveform mode
4894 * Timers can be combined (ORed) to allow for simultaneous counter start
4895 * @param hhrtim: pointer to HAL HRTIM handle
4896 * @param Timers: Timer counter(s) to start
4897 * This parameter can be any combination of the following values:
4898 * HRTIM_TIMER_MASTER
4899 * @arg HRTIM_TIMER_A
4900 * @arg HRTIM_TIMER_B
4901 * @arg HRTIM_TIMER_C
4902 * @arg HRTIM_TIMER_D
4903 * @arg HRTIM_TIMER_E
4904 * @retval HAL status
4905 * @note This function enables the dma request(s) mentionned in the timer
4906 * configuration data structure for every timers to start.
4907 * @note The source memory address, the destination memory address and the
4908 * size of each DMA transfer are specified at timer configuration time
4909 * (see HAL_HRTIM_WaveformTimerConfig)
4910 */
4911 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_DMA(HRTIM_HandleTypeDef * hhrtim,
4912 uint32_t Timers)
4913 {
4914 uint8_t timer_idx;
4915 DMA_HandleTypeDef * hdma;
4916
4917 /* Check the parameters */
4918 assert_param(IS_HRTIM_TIMERID(Timers));
4919
4920 if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
4921 {
4922 return HAL_BUSY;
4923 }
4924
4925 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4926
4927 /* Process Locked */
4928 __HAL_LOCK(hhrtim);
4929
4930 if (((Timers & HRTIM_TIMERID_MASTER) != RESET) &&
4931 (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0))
4932 {
4933 /* Set the DMA error callback */
4934 hhrtim->hdmaMaster->XferErrorCallback = HRTIM_DMAError ;
4935
4936 /* Set the DMA transfer completed callback */
4937 hhrtim->hdmaMaster->XferCpltCallback = HRTIM_DMAMasterCplt;
4938
4939 /* Enable the DMA channel */
4940 HAL_DMA_Start_IT(hhrtim->hdmaMaster,
4941 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASrcAddress,
4942 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMADstAddress,
4943 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASize);
4944
4945 /* Enable the timer DMA request */
4946 __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim,
4947 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
4948 }
4949
4950 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
4951 timer_idx < HRTIM_TIMERINDEX_MASTER ;
4952 timer_idx++)
4953 {
4954 if (((Timers & TimerIdxToTimerId[timer_idx]) != RESET) &&
4955 (hhrtim->TimerParam[timer_idx].DMARequests != 0))
4956 {
4957 /* Get the timer DMA handler */
4958 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx);
4959
4960 /* Set the DMA error callback */
4961 hdma->XferErrorCallback = HRTIM_DMAError ;
4962
4963 /* Set the DMA transfer completed callback */
4964 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
4965
4966 /* Enable the DMA channel */
4967 HAL_DMA_Start_IT(hdma,
4968 hhrtim->TimerParam[timer_idx].DMASrcAddress,
4969 hhrtim->TimerParam[timer_idx].DMADstAddress,
4970 hhrtim->TimerParam[timer_idx].DMASize);
4971
4972 /* Enable the timer DMA request */
4973 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim,
4974 timer_idx,
4975 hhrtim->TimerParam[timer_idx].DMARequests);
4976 }
4977 }
4978
4979 /* Enable the timer counter */
4980 __HAL_HRTIM_ENABLE(hhrtim, Timers);
4981
4982 hhrtim->State = HAL_HRTIM_STATE_READY;
4983
4984 /* Process Unlocked */
4985 __HAL_UNLOCK(hhrtim);
4986
4987 return HAL_OK;
4988 }
4989
4990 /**
4991 * @brief Stops the counter of the designated timer(s) operating in waveform mode
4992 * Timers can be combined (ORed) to allow for simultaneous counter stop
4993 * @param hhrtim: pointer to HAL HRTIM handle
4994 * @param Timers: Timer counter(s) to stop
4995 * This parameter can be any combination of the following values:
4996 * @arg HRTIM_TIMER_MASTER
4997 * @arg HRTIM_TIMER_A
4998 * @arg HRTIM_TIMER_B
4999 * @arg HRTIM_TIMER_C
5000 * @arg HRTIM_TIMER_D
5001 * @arg HRTIM_TIMER_E
5002 * @retval HAL status
5003 * @note The counter of a timer is stopped only if all timer outputs are disabled
5004 * @note All enabled timer related DMA requests are disabled.
5005 */
5006 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_DMA(HRTIM_HandleTypeDef * hhrtim,
5007 uint32_t Timers)
5008 {
5009 uint8_t timer_idx;
5010 DMA_HandleTypeDef * hdma;
5011
5012 /* Check the parameters */
5013 assert_param(IS_HRTIM_TIMERID(Timers));
5014
5015 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5016
5017 if (((Timers & HRTIM_TIMERID_MASTER) != RESET) &&
5018 (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0))
5019 {
5020 /* Disable the DMA */
5021 HAL_DMA_Abort(hhrtim->hdmaMaster);
5022
5023 /* Disable the DMA request(s) */
5024 __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim,
5025 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
5026 }
5027
5028 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
5029 timer_idx < HRTIM_TIMERINDEX_MASTER ;
5030 timer_idx++)
5031 {
5032 if (((Timers & TimerIdxToTimerId[timer_idx]) != RESET) &&
5033 (hhrtim->TimerParam[timer_idx].DMARequests != 0))
5034 {
5035 /* Get the timer DMA handler */
5036 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx);
5037
5038 /* Disable the DMA */
5039 HAL_DMA_Abort(hdma);
5040
5041 /* Disable the DMA request(s) */
5042 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim,
5043 timer_idx,
5044 hhrtim->TimerParam[timer_idx].DMARequests);
5045 }
5046 }
5047
5048 /* Disable the timer counter */
5049 __HAL_HRTIM_DISABLE(hhrtim, Timers);
5050
5051 hhrtim->State = HAL_HRTIM_STATE_READY;
5052
5053 return HAL_OK;
5054 }
5055
5056 /**
5057 * @brief Enables or disables the HRTIM burst mode controller.
5058 * @param hhrtim: pointer to HAL HRTIM handle
5059 * @param Enable: Burst mode controller enabling
5060 * This parameter can be one of the following values:
5061 * @arg HRTIM_BURSTMODECTL_ENABLED: Burst mode enabled
5062 * @arg HRTIM_BURSTMODECTL_DISABLED: Burst mode disabled
5063 * @retval HAL status
5064 * @note This function must be called after starting the timer(s)
5065 */
5066 HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim,
5067 uint32_t Enable)
5068 {
5069 uint32_t hrtim_bmcr;
5070
5071 /* Check parameters */
5072 assert_param(IS_HRTIM_BURSTMODECTL(Enable));
5073
5074 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5075 {
5076 return HAL_BUSY;
5077 }
5078
5079 /* Process Locked */
5080 __HAL_LOCK(hhrtim);
5081
5082 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5083
5084 /* Enable/Disable the burst mode controller */
5085 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
5086 hrtim_bmcr &= ~(HRTIM_BMCR_BME);
5087 hrtim_bmcr |= Enable;
5088
5089 /* Update the HRTIM registers */
5090 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
5091
5092 hhrtim->State = HAL_HRTIM_STATE_READY;
5093
5094 /* Process Unlocked */
5095 __HAL_UNLOCK(hhrtim);
5096
5097 return HAL_OK;
5098 }
5099
5100 /**
5101 * @brief Triggers the burst mode operation.
5102 * @param hhrtim: pointer to HAL HRTIM handle
5103 * @retval HAL status
5104 */
5105 HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim)
5106 {
5107 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5108 {
5109 return HAL_BUSY;
5110 }
5111
5112 /* Process Locked */
5113 __HAL_LOCK(hhrtim);
5114
5115 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5116
5117 /* Software trigger of the burst mode controller */
5118 hhrtim->Instance->sCommonRegs.BMTRGR |= HRTIM_BMTRGR_SW;
5119
5120 hhrtim->State = HAL_HRTIM_STATE_READY;
5121
5122 /* Process Unlocked */
5123 __HAL_UNLOCK(hhrtim);
5124
5125 return HAL_OK;
5126 }
5127
5128 /**
5129 * @brief Triggers a software capture on the designed capture unit
5130 * @param hhrtim: pointer to HAL HRTIM handle
5131 * @param TimerIdx: Timer index
5132 * This parameter can be one of the following values:
5133 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5134 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5135 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5136 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5137 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5138 * @param CaptureUnit: Capture unit to trig
5139 * This parameter can be one of the following values:
5140 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
5141 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
5142 * @retval HAL status
5143 * @note The 'software capture' bit in the capure configuration register is
5144 * automatically reset by hardware
5145 */
5146 HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim,
5147 uint32_t TimerIdx,
5148 uint32_t CaptureUnit)
5149 {
5150 /* Check parameters */
5151 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5152 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
5153
5154 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5155 {
5156 return HAL_BUSY;
5157 }
5158
5159 /* Process Locked */
5160 __HAL_LOCK(hhrtim);
5161
5162 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5163
5164 /* Force a software capture on concerned capture unit */
5165 switch (CaptureUnit)
5166 {
5167 case HRTIM_CAPTUREUNIT_1:
5168 {
5169 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR |= HRTIM_CPT1CR_SWCPT;
5170 }
5171 break;
5172 case HRTIM_CAPTUREUNIT_2:
5173 {
5174 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR |= HRTIM_CPT2CR_SWCPT;
5175 }
5176 break;
5177 }
5178
5179 hhrtim->State = HAL_HRTIM_STATE_READY;
5180
5181 /* Process Unlocked */
5182 __HAL_UNLOCK(hhrtim);
5183
5184 return HAL_OK;
5185 }
5186
5187 /**
5188 * @brief Triggers the update of the registers of one or several timers
5189 * @param hhrtim: pointer to HAL HRTIM handle
5190 * @param Timers: timers concerned with the software register update
5191 * This parameter can be any combination of the following values:
5192 * @arg HRTIM_TIMERUPDATE_MASTER
5193 * @arg HRTIM_TIMERUPDATE_A
5194 * @arg HRTIM_TIMERUPDATE_B
5195 * @arg HRTIM_TIMERUPDATE_C
5196 * @arg HRTIM_TIMERUPDATE_D
5197 * @arg HRTIM_TIMERUPDATE_E
5198 * @retval HAL status
5199 * @note The 'software update' bits in the HRTIM conrol register 2 register are
5200 * automatically reset by hardware
5201 */
5202 HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim,
5203 uint32_t Timers)
5204 {
5205 /* Check parameters */
5206 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
5207
5208 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5209 {
5210 return HAL_BUSY;
5211 }
5212
5213 /* Process Locked */
5214 __HAL_LOCK(hhrtim);
5215
5216 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5217
5218 /* Force timer(s) registers update */
5219 hhrtim->Instance->sCommonRegs.CR2 |= Timers;
5220
5221 hhrtim->State = HAL_HRTIM_STATE_READY;
5222
5223 /* Process Unlocked */
5224 __HAL_UNLOCK(hhrtim);
5225
5226 return HAL_OK;
5227 }
5228
5229 /**
5230 * @brief Triggers the reset of one or several timers
5231 * @param hhrtim: pointer to HAL HRTIM handle
5232 * @param Timers: timers concerned with the software counter reset
5233 * This parameter can be any combination of the following values:
5234 * @arg HRTIM_TIMERRESET_MASTER
5235 * @arg HRTIM_TIMERRESET_TIMER_A
5236 * @arg HRTIM_TIMERRESET_TIMER_B
5237 * @arg HRTIM_TIMERRESET_TIMER_C
5238 * @arg HRTIM_TIMERRESET_TIMER_D
5239 * @arg HRTIM_TIMERRESET_TIMER_E
5240 * @retval HAL status
5241 * @note The 'software reset' bits in the HRTIM conrol register 2 are
5242 * automatically reset by hardware
5243 */
5244 HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim,
5245 uint32_t Timers)
5246 {
5247 /* Check parameters */
5248 assert_param(IS_HRTIM_TIMERRESET(Timers));
5249
5250 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5251 {
5252 return HAL_BUSY;
5253 }
5254
5255 /* Process Locked */
5256 __HAL_LOCK(hhrtim);
5257
5258 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5259
5260 /* Force timer(s) registers reset */
5261 hhrtim->Instance->sCommonRegs.CR2 = Timers;
5262
5263 hhrtim->State = HAL_HRTIM_STATE_READY;
5264
5265 /* Process Unlocked */
5266 __HAL_UNLOCK(hhrtim);
5267
5268 return HAL_OK;
5269 }
5270
5271 /**
5272 * @brief Starts a burst DMA operation to update HRTIM control registers content
5273 * @param hhrtim: pointer to HAL HRTIM handle
5274 * @param TimerIdx: Timer index
5275 * This parameter can be one of the following values:
5276 * @arg HRTIM_TIMERINDEX_MASTER for master timer
5277 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5278 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5279 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5280 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5281 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5282 * @param BurstBufferAddress: address of the buffer the HRTIM control registers
5283 * content will be updated from.
5284 * @param BurstBufferLength: size (in WORDS) of the burst buffer.
5285 * @retval HAL status
5286 * @note The TimerIdx parameter determines the dma channel to be used by the
5287 * DMA burst controller (see below)
5288 * HRTIM_TIMERINDEX_MASTER: DMA channel 2 is used by the DMA burst controller
5289 * HRTIM_TIMERINDEX_TIMER_A: DMA channel 3 is used by the DMA burst controller
5290 * HRTIM_TIMERINDEX_TIMER_B: DMA channel 4 is used by the DMA burst controller
5291 * HRTIM_TIMERINDEX_TIMER_C: DMA channel 5 is used by the DMA burst controller
5292 * HRTIM_TIMERINDEX_TIMER_D: DMA channel 6 is used by the DMA burst controller
5293 * HRTIM_TIMERINDEX_TIMER_E: DMA channel 7 is used by the DMA burst controller
5294 */
5295 HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
5296 uint32_t TimerIdx,
5297 uint32_t BurstBufferAddress,
5298 uint32_t BurstBufferLength)
5299 {
5300 DMA_HandleTypeDef * hdma;
5301
5302 /* Check the parameters */
5303 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
5304
5305 if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
5306 {
5307 return HAL_BUSY;
5308 }
5309 if((hhrtim->State == HAL_HRTIM_STATE_READY))
5310 {
5311 if((BurstBufferAddress == 0 ) || (BurstBufferLength == 0))
5312 {
5313 return HAL_ERROR;
5314 }
5315 else
5316 {
5317 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5318 }
5319 }
5320
5321 /* Process Locked */
5322 __HAL_LOCK(hhrtim);
5323
5324 /* Get the timer DMA handler */
5325 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
5326
5327 /* Set the DMA transfer completed callback */
5328 hdma->XferCpltCallback = HRTIM_BurstDMACplt;
5329
5330 /* Set the DMA error callback */
5331 hdma->XferErrorCallback = HRTIM_DMAError ;
5332
5333 /* Enable the DMA channel */
5334 HAL_DMA_Start_IT(hdma,
5335 BurstBufferAddress,
5336 (uint32_t)&(hhrtim->Instance->sCommonRegs.BDMADR),
5337 BurstBufferLength);
5338
5339 hhrtim->State = HAL_HRTIM_STATE_READY;
5340
5341 /* Process Unlocked */
5342 __HAL_UNLOCK(hhrtim);
5343
5344 return HAL_OK;
5345 }
5346
5347 /**
5348 * @brief Enables the transfer from preload to active registers for one
5349 * or several timing units (including master timer)
5350 * @param hhrtim: pointer to HAL HRTIM handle
5351 * @param Timers: Timer(s) concerned by the register preload enabling command
5352 * This parameter can be any combination of the following values:
5353 * @arg HRTIM_TIMERUPDATE_MASTER
5354 * @arg HRTIM_TIMERUPDATE_A
5355 * @arg HRTIM_TIMERUPDATE_B
5356 * @arg HRTIM_TIMERUPDATE_C
5357 * @arg HRTIM_TIMERUPDATE_D
5358 * @arg HRTIM_TIMERUPDATE_E
5359 * @retval HAL status
5360 */
5361 HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
5362 uint32_t Timers)
5363 {
5364 /* Check the parameters */
5365 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
5366
5367 /* Process Locked */
5368 __HAL_LOCK(hhrtim);
5369
5370 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5371
5372 /* Enable timer(s) registers update */
5373 hhrtim->Instance->sCommonRegs.CR1 &= ~(Timers);
5374
5375 hhrtim->State = HAL_HRTIM_STATE_READY;
5376
5377 /* Process Unlocked */
5378 __HAL_UNLOCK(hhrtim);
5379
5380 return HAL_OK;
5381 }
5382
5383 /**
5384 * @brief Disables the transfer from preload to active registers for one
5385 * or several timing units (including master timer)
5386 * @param hhrtim: pointer to HAL HRTIM handle
5387 * @param Timers: Timer(s) concerned by the register preload disabling command
5388 * This parameter can be any combination of the following values:
5389 * @arg HRTIM_TIMERUPDATE_MASTER
5390 * @arg HRTIM_TIMERUPDATE_A
5391 * @arg HRTIM_TIMERUPDATE_B
5392 * @arg HRTIM_TIMERUPDATE_C
5393 * @arg HRTIM_TIMERUPDATE_D
5394 * @arg HRTIM_TIMERUPDATE_E
5395 * @retval HAL status
5396 */
5397 HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
5398 uint32_t Timers)
5399 {
5400 /* Check the parameters */
5401 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
5402
5403 /* Process Locked */
5404 __HAL_LOCK(hhrtim);
5405
5406 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5407
5408 /* Enable timer(s) registers update */
5409 hhrtim->Instance->sCommonRegs.CR1 |= (Timers);
5410
5411 hhrtim->State = HAL_HRTIM_STATE_READY;
5412
5413 /* Process Unlocked */
5414 __HAL_UNLOCK(hhrtim);
5415
5416 return HAL_OK;
5417 }
5418
5419 /**
5420 * @}
5421 */
5422
5423 /** @defgroup HRTIM_Exported_Functions_Group9 Peripheral state functions
5424 * @brief Functions used to get HRTIM or HRTIM timer specific
5425 * information.
5426 *
5427 @verbatim
5428 ===============================================================================
5429 ##### Peripheral State functions #####
5430 ===============================================================================
5431 [..] This section provides functions allowing to:
5432 (+) Get HRTIM HAL state
5433 (+) Get captured value
5434 (+) Get HRTIM timer output level
5435 (+) Get HRTIM timer output state
5436 (+) Get delayed protection status
5437 (+) Get burst status
5438 (+) Get current push-pull status
5439 (+) Get idle push-pull status
5440
5441 @endverbatim
5442 * @{
5443 */
5444
5445 /**
5446 * @brief return the HRTIM HAL state
5447 * @param hhrtim: pointer to HAL HRTIM handle
5448 * @retval HAL state
5449 */
5450 HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim)
5451 {
5452 /* Return ADC state */
5453 return hhrtim->State;
5454 }
5455
5456 /**
5457 * @brief Returns actual value of the capture register of the designated capture unit
5458 * @param hhrtim: pointer to HAL HRTIM handle
5459 * @param TimerIdx: Timer index
5460 * This parameter can be one of the following values:
5461 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5462 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5463 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5464 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5465 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5466 * @param CaptureUnit: Capture unit to trig
5467 * This parameter can be one of the following values:
5468 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
5469 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
5470 * @retval Captured value
5471 */
5472 uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim,
5473 uint32_t TimerIdx,
5474 uint32_t CaptureUnit)
5475 {
5476 uint32_t captured_value = 0;
5477
5478 /* Check parameters */
5479 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5480 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
5481
5482 /* Read captured value */
5483 switch (CaptureUnit)
5484 {
5485 case HRTIM_CAPTUREUNIT_1:
5486 {
5487 captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR;
5488 }
5489 break;
5490 case HRTIM_CAPTUREUNIT_2:
5491 {
5492 captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR;
5493 }
5494 break;
5495 }
5496
5497 return captured_value;
5498 }
5499
5500 /**
5501 * @brief Returns actual level (active or inactive) of the designated output
5502 * @param hhrtim: pointer to HAL HRTIM handle
5503 * @param TimerIdx: Timer index
5504 * This parameter can be one of the following values:
5505 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5506 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5507 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5508 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5509 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5510 * @param Output: Timer output
5511 * This parameter can be one of the following values:
5512 * @arg HRTIM_OUTPUT_TA1: Timer A - Ouput 1
5513 * @arg HRTIM_OUTPUT_TA2: Timer A - Ouput 2
5514 * @arg HRTIM_OUTPUT_TB1: Timer B - Ouput 1
5515 * @arg HRTIM_OUTPUT_TB2: Timer B - Ouput 2
5516 * @arg HRTIM_OUTPUT_TC1: Timer C - Ouput 1
5517 * @arg HRTIM_OUTPUT_TC2: Timer C - Ouput 2
5518 * @arg HRTIM_OUTPUT_TD1: Timer D - Ouput 1
5519 * @arg HRTIM_OUTPUT_TD2: Timer D - Ouput 2
5520 * @arg HRTIM_OUTPUT_TE1: Timer E - Ouput 1
5521 * @arg HRTIM_OUTPUT_TE2: Timer E - Ouput 2
5522 * @retval Output level
5523 * @note Returned output level is taken before the output stage (chopper,
5524 * polarity).
5525 */
5526 uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
5527 uint32_t TimerIdx,
5528 uint32_t Output)
5529 {
5530 uint32_t output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
5531
5532 /* Check parameters */
5533 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
5534
5535 /* Read the output level */
5536 switch (Output)
5537 {
5538 case HRTIM_OUTPUT_TA1:
5539 case HRTIM_OUTPUT_TB1:
5540 case HRTIM_OUTPUT_TC1:
5541 case HRTIM_OUTPUT_TD1:
5542 case HRTIM_OUTPUT_TE1:
5543 {
5544 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != RESET)
5545 {
5546 output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
5547 }
5548 else
5549 {
5550 output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
5551 }
5552 }
5553 break;
5554 case HRTIM_OUTPUT_TA2:
5555 case HRTIM_OUTPUT_TB2:
5556 case HRTIM_OUTPUT_TC2:
5557 case HRTIM_OUTPUT_TD2:
5558 case HRTIM_OUTPUT_TE2:
5559 {
5560 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != RESET)
5561 {
5562 output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
5563 }
5564 else
5565 {
5566 output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
5567 }
5568 }
5569 break;
5570 }
5571
5572 return output_level;
5573 }
5574
5575 /**
5576 * @brief Returns actual state (RUN, IDLE, FAULT) of the designated output
5577 * @param hhrtim: pointer to HAL HRTIM handle
5578 * @param TimerIdx: Timer index
5579 * This parameter can be one of the following values:
5580 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5581 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5582 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5583 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5584 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5585 * @param Output: Timer output
5586 * This parameter can be one of the following values:
5587 * @arg HRTIM_OUTPUT_TA1: Timer A - Ouput 1
5588 * @arg HRTIM_OUTPUT_TA2: Timer A - Ouput 2
5589 * @arg HRTIM_OUTPUT_TB1: Timer B - Ouput 1
5590 * @arg HRTIM_OUTPUT_TB2: Timer B - Ouput 2
5591 * @arg HRTIM_OUTPUT_TC1: Timer C - Ouput 1
5592 * @arg HRTIM_OUTPUT_TC2: Timer C - Ouput 2
5593 * @arg HRTIM_OUTPUT_TD1: Timer D - Ouput 1
5594 * @arg HRTIM_OUTPUT_TD2: Timer D - Ouput 2
5595 * @arg HRTIM_OUTPUT_TE1: Timer E - Ouput 1
5596 * @arg HRTIM_OUTPUT_TE2: Timer E - Ouput 2
5597 * @retval Output state
5598 */
5599 uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,
5600 uint32_t TimerIdx,
5601 uint32_t Output)
5602 {
5603 uint32_t output_bit = 0;
5604 uint32_t output_state = HRTIM_OUTPUTSTATE_IDLE;
5605
5606 /* Check parameters */
5607 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
5608
5609 /* Set output state according to output control status and output disable status */
5610 switch (Output)
5611 {
5612 case HRTIM_OUTPUT_TA1:
5613 {
5614 output_bit = HRTIM_OENR_TA1OEN;
5615 }
5616 break;
5617 case HRTIM_OUTPUT_TA2:
5618 {
5619 output_bit = HRTIM_OENR_TA2OEN;
5620 }
5621 break;
5622 case HRTIM_OUTPUT_TB1:
5623 {
5624 output_bit = HRTIM_OENR_TB1OEN;
5625 }
5626 break;
5627 case HRTIM_OUTPUT_TB2:
5628 {
5629 output_bit = HRTIM_OENR_TB2OEN;
5630 }
5631 break;
5632 case HRTIM_OUTPUT_TC1:
5633 {
5634 output_bit = HRTIM_OENR_TC1OEN;
5635 }
5636 break;
5637 case HRTIM_OUTPUT_TC2:
5638 {
5639 output_bit = HRTIM_OENR_TC2OEN;
5640 }
5641 break;
5642 case HRTIM_OUTPUT_TD1:
5643 {
5644 output_bit = HRTIM_OENR_TD1OEN;
5645 }
5646 break;
5647 case HRTIM_OUTPUT_TD2:
5648 {
5649 output_bit = HRTIM_OENR_TD2OEN;
5650 }
5651 break;
5652 case HRTIM_OUTPUT_TE1:
5653 {
5654 output_bit = HRTIM_OENR_TE1OEN;
5655 }
5656 break;
5657 case HRTIM_OUTPUT_TE2:
5658 {
5659 output_bit = HRTIM_OENR_TE2OEN;
5660 }
5661 break;
5662 }
5663
5664 if ((hhrtim->Instance->sCommonRegs.OENR & output_bit) != RESET)
5665 {
5666 /* Output is enabled: output in RUN state (whatever ouput disable status is)*/
5667 output_state = HRTIM_OUTPUTSTATE_RUN;
5668 }
5669 else
5670 {
5671 if ((hhrtim->Instance->sCommonRegs.ODSR & output_bit) != RESET)
5672 {
5673 /* Output is disabled: output in FAULT state */
5674 output_state = HRTIM_OUTPUTSTATE_FAULT;
5675 }
5676 else
5677 {
5678 /* Output is disabled: output in IDLE state */
5679 output_state = HRTIM_OUTPUTSTATE_IDLE;
5680 }
5681 }
5682
5683 return(output_state);
5684 }
5685
5686 /**
5687 * @brief Returns the level (active or inactive) of the designated output
5688 * when the delayed protection was triggered
5689 * @param hhrtim: pointer to HAL HRTIM handle
5690 * @param TimerIdx: Timer index
5691 * This parameter can be one of the following values:
5692 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5693 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5694 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5695 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5696 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5697 * @param Output: Timer output
5698 * This parameter can be one of the following values:
5699 * @arg HRTIM_OUTPUT_TA1: Timer A - Ouput 1
5700 * @arg HRTIM_OUTPUT_TA2: Timer A - Ouput 2
5701 * @arg HRTIM_OUTPUT_TB1: Timer B - Ouput 1
5702 * @arg HRTIM_OUTPUT_TB2: Timer B - Ouput 2
5703 * @arg HRTIM_OUTPUT_TC1: Timer C - Ouput 1
5704 * @arg HRTIM_OUTPUT_TC2: Timer C - Ouput 2
5705 * @arg HRTIM_OUTPUT_TD1: Timer D - Ouput 1
5706 * @arg HRTIM_OUTPUT_TD2: Timer D - Ouput 2
5707 * @arg HRTIM_OUTPUT_TD1: Timer E - Ouput 1
5708 * @arg HRTIM_OUTPUT_TD2: Timer E - Ouput 2
5709 * @retval Delayed protection status
5710 */
5711 uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef * hhrtim,
5712 uint32_t TimerIdx,
5713 uint32_t Output)
5714 {
5715 uint32_t delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
5716
5717 /* Check parameters */
5718 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
5719
5720 /* Read the delayed protection status */
5721 switch (Output)
5722 {
5723 case HRTIM_OUTPUT_TA1:
5724 case HRTIM_OUTPUT_TB1:
5725 case HRTIM_OUTPUT_TC1:
5726 case HRTIM_OUTPUT_TD1:
5727 case HRTIM_OUTPUT_TE1:
5728 {
5729 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != RESET)
5730 {
5731 /* Output 1 was active when the delayed idle protection was triggered */
5732 delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
5733 }
5734 else
5735 {
5736 /* Output 1 was inactive when the delayed idle protection was triggered */
5737 delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
5738 }
5739 }
5740 break;
5741 case HRTIM_OUTPUT_TA2:
5742 case HRTIM_OUTPUT_TB2:
5743 case HRTIM_OUTPUT_TC2:
5744 case HRTIM_OUTPUT_TD2:
5745 case HRTIM_OUTPUT_TE2:
5746 {
5747 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != RESET)
5748 {
5749 /* Output 2 was active when the delayed idle protection was triggered */
5750 delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
5751 }
5752 else
5753 {
5754 /* Output 2 was inactive when the delayed idle protection was triggered */
5755 delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
5756 }
5757 }
5758 break;
5759 }
5760
5761 return delayed_protection_status;
5762 }
5763
5764 /**
5765 * @brief Returns the actual status (active or inactive) of the burst mode controller
5766 * @param hhrtim: pointer to HAL HRTIM handle
5767 * @retval Burst mode controller status
5768 */
5769 uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef * hhrtim)
5770 {
5771 uint32_t burst_mode_status;
5772
5773 /* Read burst mode status */
5774 burst_mode_status = (hhrtim->Instance->sCommonRegs.BMCR & HRTIM_BMCR_BMSTAT);
5775
5776 return burst_mode_status;
5777 }
5778
5779 /**
5780 * @brief Indicates on which output the signal is currently active (when the
5781 * push pull mode is enabled)
5782 * @param hhrtim: pointer to HAL HRTIM handle
5783 * @param TimerIdx: Timer index
5784 * This parameter can be one of the following values:
5785 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5786 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5787 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5788 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5789 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5790 * @retval Burst mode controller status
5791 */
5792 uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef * hhrtim,
5793 uint32_t TimerIdx)
5794 {
5795 uint32_t current_pushpull_status;
5796
5797 /* Check the parameters */
5798 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5799
5800 /* Read current push pull status */
5801 current_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_CPPSTAT);
5802
5803 return current_pushpull_status;
5804 }
5805
5806
5807 /**
5808 * @brief Indicates on which output the signal was applied, in push-pull mode
5809 balanced fault mode or delayed idle mode, when the protection was triggered
5810 * @param hhrtim: pointer to HAL HRTIM handle
5811 * @param TimerIdx: Timer index
5812 * This parameter can be one of the following values:
5813 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5814 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5815 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5816 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5817 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5818 * @retval Idle Push Pull Status
5819 */
5820 uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef * hhrtim,
5821 uint32_t TimerIdx)
5822 {
5823 uint32_t idle_pushpull_status;
5824
5825 /* Check the parameters */
5826 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5827
5828 /* Read current push pull status */
5829 idle_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_IPPSTAT);
5830
5831 return idle_pushpull_status;
5832 }
5833
5834 /**
5835 * @}
5836 */
5837
5838 /** @defgroup HRTIM_Exported_Functions_Group10 Interrupts handling
5839 * @brief Functions called when HRTIM generates an interrupt
5840 * 7 interrupts can be generated by the master timer:
5841 * - Master timer registers update
5842 * - Synchronization event received
5843 * - Master timer repetition event
5844 * - Master Compare 1 to 4 event
5845 * 14 interrupts can be generated by each timing unit:
5846 * - Delayed protection triggered
5847 * - Counter reset or roll-over event
5848 * - Output 1 and output 2 reset (transition active to inactive)
5849 * - Output 1 and output 2 set (transition inactive to active)
5850 * - Capture 1 and 2 events
5851 * - Timing unit registers update
5852 * - Repetition event
5853 * - Compare 1 to 4 event
5854 * 8 global interrupts are generated for the whole HRTIM:
5855 * - System fault and Fault 1 to 5 (regardless of the timing unit attribution)
5856 * - DLL calibration done
5857 * - Burst mode period completed
5858 *
5859 @verbatim
5860 ===============================================================================
5861 ##### HRTIM interrupts handling #####
5862 ===============================================================================
5863 [..]
5864 This subsection provides a set of functions allowing to manage the HRTIM
5865 interrupts
5866 (+) HRTIM interrupt handler
5867 (+) Callback function called when Fault1 interrupt occurs
5868 (+) Callback function called when Fault2 interrupt occurs
5869 (+) Callback function called when Fault3 interrupt occurs
5870 (+) Callback function called when Fault4 interrupt occurs
5871 (+) Callback function called when Fault5 interrupt occurs
5872 (+) Callback function called when system Fault interrupt occurs
5873 (+) Callback function called when DLL ready interrupt occurs
5874 (+) Callback function called when burst mode period interrupt occurs
5875 (+) Callback function called when synchronization input interrupt occurs
5876 (+) Callback function called when a timer register update interrupt occurs
5877 (+) Callback function called when a timer repetition interrupt occurs
5878 (+) Callback function called when a compare 1 match interrupt occurs
5879 (+) Callback function called when a compare 2 match interrupt occurs
5880 (+) Callback function called when a compare 3 match interrupt occurs
5881 (+) Callback function called when a compare 4 match interrupt occurs
5882 (+) Callback function called when a capture 1 interrupt occurs
5883 (+) Callback function called when a capture 2 interrupt occurs
5884 (+) Callback function called when a delayed protection interrupt occurs
5885 (+) Callback function called when a timer counter reset interrupt occurs
5886 (+) Callback function called when a timer output 1 set interrupt occurs
5887 (+) Callback function called when a timer output 1 reset interrupt occurs
5888 (+) Callback function called when a timer output 2 set interrupt occurs
5889 (+) Callback function called when a timer output 2 reset interrupt occurs
5890 (+) Callback function called when a timer output 2 reset interrupt occurs
5891 (+) Callback function called upon completion of a burst DMA transfer
5892
5893 @endverbatim
5894 * @{
5895 */
5896
5897 /**
5898 * @brief This function handles HRTIM interrupt request.
5899 * @param hhrtim: pointer to HAL HRTIM handle
5900 * @param TimerIdx: Timer index
5901 * This parameter can be any value of @ref HRTIM_Timer_Index
5902 * @retval None
5903 */
5904 void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim,
5905 uint32_t TimerIdx)
5906 {
5907 /* HRTIM interrupts handling */
5908 if (TimerIdx == HRTIM_TIMERINDEX_COMMON)
5909 {
5910 HRTIM_HRTIM_ISR(hhrtim);
5911 }
5912 else if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
5913 {
5914 /* Master related interrupts handling */
5915 HRTIM_Master_ISR(hhrtim);
5916 }
5917 else
5918 {
5919 /* Timing unit related interrupts handling */
5920 HRTIM_Timer_ISR(hhrtim, TimerIdx);
5921 }
5922
5923 }
5924
5925 /**
5926 * @brief Callback function invoked when a fault 1 interrupt occured
5927 * @param hhrtim: pointer to HAL HRTIM handle * @retval None
5928 * @retval None
5929 */
5930 __weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim)
5931 {
5932 /* NOTE : This function should not be modified, when the callback is needed,
5933 the HAL_HRTIM_Fault1Callback could be implenetd in the user file
5934 */
5935 }
5936
5937 /**
5938 * @brief Callback function invoked when a fault 2 interrupt occured
5939 * @param hhrtim: pointer to HAL HRTIM handle
5940 * @retval None
5941 */
5942 __weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim)
5943 {
5944 /* NOTE : This function should not be modified, when the callback is needed,
5945 the HAL_HRTIM_Fault2Callback could be implenetd in the user file
5946 */
5947 }
5948
5949 /**
5950 * @brief Callback function invoked when a fault 3 interrupt occured
5951 * @param hhrtim: pointer to HAL HRTIM handle
5952 * @retval None
5953 */
5954 __weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim)
5955 {
5956 /* NOTE : This function should not be modified, when the callback is needed,
5957 the HAL_HRTIM_Fault3Callback could be implenetd in the user file
5958 */
5959 }
5960
5961 /**
5962 * @brief Callback function invoked when a fault 4 interrupt occured
5963 * @param hhrtim: pointer to HAL HRTIM handle
5964 * @retval None
5965 */
5966 __weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim)
5967 {
5968 /* NOTE : This function should not be modified, when the callback is needed,
5969 the HAL_HRTIM_Fault4Callback could be implenetd in the user file
5970 */
5971 }
5972
5973 /**
5974 * @brief Callback function invoked when a fault 5 interrupt occured
5975 * @param hhrtim: pointer to HAL HRTIM handle
5976 * @retval None
5977 */
5978 __weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim)
5979 {
5980 /* NOTE : This function should not be modified, when the callback is needed,
5981 the HAL_HRTIM_Fault5Callback could be implenetd in the user file
5982 */
5983 }
5984
5985 /**
5986 * @brief Callback function invoked when a system fault interrupt occured
5987 * @param hhrtim: pointer to HAL HRTIM handle
5988 * @retval None
5989 */
5990 __weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim)
5991 {
5992 /* NOTE : This function should not be modified, when the callback is needed,
5993 the HAL_HRTIM_SystemFaultCallback could be implenetd in the user file
5994 */
5995 }
5996
5997 /**
5998 * @brief Callback function invoked when a the DLL calibration is completed
5999 * @param hhrtim: pointer to HAL HRTIM handle
6000 * @retval None
6001 */
6002 __weak void HAL_HRTIM_DLLCalbrationReadyCallback(HRTIM_HandleTypeDef * hhrtim)
6003 {
6004 /* NOTE : This function should not be modified, when the callback is needed,
6005 the HAL_HRTIM_DLLCalbrationCallback could be implenetd in the user file
6006 */
6007 }
6008
6009 /**
6010 * @brief Callback function invoked when the end of the burst mode period is reached
6011 * @param hhrtim: pointer to HAL HRTIM handle
6012 * @retval None
6013 */
6014 __weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim)
6015 {
6016 /* NOTE : This function should not be modified, when the callback is needed,
6017 the HAL_HRTIM_BurstModeCallback could be implenetd in the user file
6018 */
6019 }
6020
6021 /**
6022 * @brief Callback function invoked when a synchronization input event is received
6023 * @param hhrtim: pointer to HAL HRTIM handle
6024 * @retval None
6025 */
6026 __weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim)
6027 {
6028 /* NOTE : This function should not be modified, when the callback is needed,
6029 the HAL_HRTIM_Master_SynchronizationEventCallback could be implenetd in the user file
6030 */
6031 }
6032
6033 /**
6034 * @brief Callback function invoked when timer registers are updated
6035 * @param hhrtim: pointer to HAL HRTIM handle
6036 * @param TimerIdx: Timer index
6037 * This parameter can be one of the following values:
6038 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6039 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6040 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6041 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6042 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6043 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6044 * @retval None
6045 */
6046 __weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim,
6047 uint32_t TimerIdx)
6048 {
6049 /* NOTE : This function should not be modified, when the callback is needed,
6050 the HAL_HRTIM_Master_RegistersUpdateCallback could be implenetd in the user file
6051 */
6052 }
6053
6054 /**
6055 * @brief Callback function invoked when timer repetition period has elapsed
6056 * @param hhrtim: pointer to HAL HRTIM handle
6057 * @param TimerIdx: Timer index
6058 * This parameter can be one of the following values:
6059 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6060 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6061 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6062 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6063 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6064 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6065 * @retval None
6066 */
6067 __weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim,
6068 uint32_t TimerIdx)
6069 {
6070 /* NOTE : This function should not be modified, when the callback is needed,
6071 the HAL_HRTIM_Master_RepetitionEventCallback could be implenetd in the user file
6072 */
6073 }
6074
6075 /**
6076 * @brief Callback function invoked when the timer counter matches the value
6077 * programmed in the compare 1 register
6078 * @param hhrtim: pointer to HAL HRTIM handle
6079 * @param TimerIdx: Timer index
6080 * This parameter can be one of the following values:
6081 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6082 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6083 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6084 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6085 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6086 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6087 * @retval None
6088 */
6089 __weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim,
6090 uint32_t TimerIdx)
6091 {
6092 /* NOTE : This function should not be modified, when the callback is needed,
6093 the HAL_HRTIM_Master_Compare1EventCallback could be implenetd in the user file
6094 */
6095 }
6096
6097 /**
6098 * @brief Callback function invoked when the timer counter matches the value
6099 * programmed in the compare 2 register
6100 * @param hhrtim: pointer to HAL HRTIM handle
6101 * @retval None
6102 * @param TimerIdx: Timer index
6103 * This parameter can be one of the following values:
6104 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6105 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6106 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6107 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6108 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6109 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6110 */
6111 __weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim,
6112 uint32_t TimerIdx)
6113 {
6114 /* NOTE : This function should not be modified, when the callback is needed,
6115 the HAL_HRTIM_Master_Compare2EventCallback could be implenetd in the user file
6116 */
6117 }
6118
6119 /**
6120 * @brief Callback function invoked when the timer counter matches the value
6121 * programmed in the compare 3 register
6122 * @param hhrtim: pointer to HAL HRTIM handle
6123 * @param TimerIdx: Timer index
6124 * This parameter can be one of the following values:
6125 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6126 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6127 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6128 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6129 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6130 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6131 * @retval None
6132 */
6133 __weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim,
6134 uint32_t TimerIdx)
6135 {
6136 /* NOTE : This function should not be modified, when the callback is needed,
6137 the HAL_HRTIM_Master_Compare3EventCallback could be implenetd in the user file
6138 */
6139 }
6140
6141 /**
6142 * @brief Callback function invoked when the timer counter matches the value
6143 * programmed in the compare 4 register
6144 * @param hhrtim: pointer to HAL HRTIM handle
6145 * @param TimerIdx: Timer index
6146 * This parameter can be one of the following values:
6147 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6148 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6149 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6150 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6151 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6152 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6153 * @retval None
6154 */
6155 __weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim,
6156 uint32_t TimerIdx)
6157 {
6158 /* NOTE : This function should not be modified, when the callback is needed,
6159 the HAL_HRTIM_Master_Compare4EventCallback could be implenetd in the user file
6160 */
6161 }
6162
6163 /**
6164 * @brief Callback function invoked when the timer x capture 1 event occurs
6165 * @param hhrtim: pointer to HAL HRTIM handle
6166 * @param TimerIdx: Timer index
6167 * This parameter can be one of the following values:
6168 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6169 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6170 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6171 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6172 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6173 * @retval None
6174 */
6175 __weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim,
6176 uint32_t TimerIdx)
6177 {
6178 /* NOTE : This function should not be modified, when the callback is needed,
6179 the HAL_HRTIM_Timer_Capture1EventCallback could be implenetd in the user file
6180 */
6181 }
6182
6183 /**
6184 * @brief Callback function invoked when the timer x capture 2 event occurs
6185 * @param hhrtim: pointer to HAL HRTIM handle
6186 * @param TimerIdx: Timer index
6187 * This parameter can be one of the following values:
6188 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6189 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6190 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6191 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6192 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6193 * @retval None
6194 */
6195 __weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim,
6196 uint32_t TimerIdx)
6197 {
6198 /* NOTE : This function should not be modified, when the callback is needed,
6199 the HAL_HRTIM_Timer_Capture2EventCallback could be implenetd in the user file
6200 */
6201 }
6202
6203 /**
6204 * @brief Callback function invoked when the delayed idle or balanced idle mode is
6205 * entered
6206 * @param hhrtim: pointer to HAL HRTIM handle
6207 * @param TimerIdx: Timer index
6208 * This parameter can be one of the following values:
6209 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6210 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6211 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6212 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6213 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6214 * @retval None
6215 */
6216 __weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim,
6217 uint32_t TimerIdx)
6218 {
6219 /* NOTE : This function should not be modified, when the callback is needed,
6220 the HAL_HRTIM_Timer_DelayedProtectionCallback could be implenetd in the user file
6221 */
6222 }
6223
6224 /**
6225 * @brief Callback function invoked when the timer x counter reset/roll-over
6226 * event occurs
6227 * @param hhrtim: pointer to HAL HRTIM handle
6228 * @param TimerIdx: Timer index
6229 * This parameter can be one of the following values:
6230 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6231 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6232 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6233 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6234 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6235 * @retval None
6236 */
6237 __weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim,
6238 uint32_t TimerIdx)
6239 {
6240 /* NOTE : This function should not be modified, when the callback is needed,
6241 the HAL_HRTIM_Timer_CounterResetCallback could be implenetd in the user file
6242 */
6243 }
6244
6245 /**
6246 * @brief Callback function invoked when the timer x output 1 is set
6247 * @param hhrtim: pointer to HAL HRTIM handle
6248 * @param TimerIdx: Timer index
6249 * This parameter can be one of the following values:
6250 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6251 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6252 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6253 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6254 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6255 * @retval None
6256 */
6257 __weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim,
6258 uint32_t TimerIdx)
6259 {
6260 /* NOTE : This function should not be modified, when the callback is needed,
6261 the HAL_HRTIM_Timer_Output1SetCallback could be implenetd in the user file
6262 */
6263 }
6264
6265 /**
6266 * @brief Callback function invoked when the timer x output 1 is reset
6267 * @param hhrtim: pointer to HAL HRTIM handle
6268 * @param TimerIdx: Timer index
6269 * This parameter can be one of the following values:
6270 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6271 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6272 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6273 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6274 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6275 * @retval None
6276 */
6277 __weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim,
6278 uint32_t TimerIdx)
6279 {
6280 /* NOTE : This function should not be modified, when the callback is needed,
6281 the HAL_HRTIM_Timer_Output1ResetCallback could be implenetd in the user file
6282 */
6283 }
6284
6285 /**
6286 * @brief Callback function invoked when the timer x output 2 is set
6287 * @param hhrtim: pointer to HAL HRTIM handle
6288 * @param TimerIdx: Timer index
6289 * This parameter can be one of the following values:
6290 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6291 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6292 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6293 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6294 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6295 * @retval None
6296 */
6297 __weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim,
6298 uint32_t TimerIdx)
6299 {
6300 /* NOTE : This function should not be modified, when the callback is needed,
6301 the HAL_HRTIM_Timer_Output2SetCallback could be implenetd in the user file
6302 */
6303 }
6304
6305 /**
6306 * @brief Callback function invoked when the timer x output 2 is reset
6307 * @param hhrtim: pointer to HAL HRTIM handle
6308 * @param TimerIdx: Timer index
6309 * This parameter can be one of the following values:
6310 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6311 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6312 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6313 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6314 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6315 * @retval None
6316 */
6317 __weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim,
6318 uint32_t TimerIdx)
6319 {
6320 /* NOTE : This function should not be modified, when the callback is needed,
6321 the HAL_HRTIM_Timer_Output2ResetCallback could be implenetd in the user file
6322 */
6323 }
6324
6325 /**
6326 * @brief Callback function invoked when a DMA burst transfer is completed
6327 * @param hhrtim: pointer to HAL HRTIM handle
6328 * @param TimerIdx: Timer index
6329 * This parameter can be one of the following values:
6330 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6331 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6332 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6333 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6334 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6335 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6336 * @retval None
6337 */
6338 __weak void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef * hhrtim,
6339 uint32_t TimerIdx)
6340 {
6341 /* NOTE : This function should not be modified, when the callback is needed,
6342 the HAL_HRTIM_BurstDMATransferCallback could be implenetd in the user file
6343 */
6344 }
6345
6346 /**
6347 * @brief Callback function invoked when a DMA error occurs
6348 * @param hhrtim: pointer to HAL HRTIM handle
6349 * @retval None
6350 */
6351 __weak void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim)
6352 {
6353 /* NOTE : This function should not be modified, when the callback is needed,
6354 the HAL_HRTIM_ErrorCallback could be implenetd in the user file
6355 */
6356 }
6357
6358 /**
6359 * @}
6360 */
6361
6362 /**
6363 * @}
6364 */
6365
6366 /** @addtogroup HRTIM_Private_Functions HRTIM Private Functions
6367 * @{
6368 */
6369
6370 /**
6371 * @brief Configures the master timer time base
6372 * @param hhrtim: pointer to HAL HRTIM handle
6373 * @param pTimeBaseCfg: pointer to the time base configuration structure
6374 * @retval None
6375 */
6376 static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
6377 HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
6378 {
6379 uint32_t hrtim_mcr;
6380
6381 /* Configure master timer */
6382 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
6383
6384 /* Set the prescaler ratio */
6385 hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CK_PSC);
6386 hrtim_mcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
6387
6388 /* Set the operating mode */
6389 hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CONT | HRTIM_MCR_RETRIG);
6390 hrtim_mcr |= (uint32_t)pTimeBaseCfg->Mode;
6391
6392 /* Update the HRTIM registers */
6393 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
6394 hhrtim->Instance->sMasterRegs.MPER = pTimeBaseCfg->Period;
6395 hhrtim->Instance->sMasterRegs.MREP = pTimeBaseCfg->RepetitionCounter;
6396 }
6397
6398 /**
6399 * @brief Configures timing unit (timer A to timer E) time base
6400 * @param hhrtim: pointer to HAL HRTIM handle
6401 * @param TimerIdx: Timer index
6402 * @param pTimeBaseCfg: pointer to the time base configuration structure
6403 * @retval None
6404 */
6405 static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
6406 uint32_t TimerIdx ,
6407 HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
6408 {
6409 uint32_t hrtim_timcr;
6410
6411 /* Configure master timing unit */
6412 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
6413
6414 /* Set the prescaler ratio */
6415 hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CK_PSC);
6416 hrtim_timcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
6417
6418 /* Set the operating mode */
6419 hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CONT | HRTIM_TIMCR_RETRIG);
6420 hrtim_timcr |= (uint32_t)pTimeBaseCfg->Mode;
6421
6422 /* Update the HRTIM registers */
6423 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
6424 hhrtim->Instance->sTimerxRegs[TimerIdx].PERxR = pTimeBaseCfg->Period;
6425 hhrtim->Instance->sTimerxRegs[TimerIdx].REPxR = pTimeBaseCfg->RepetitionCounter;
6426 }
6427
6428 /**
6429 * @brief Configures the master timer in waveform mode
6430 * @param hhrtim: pointer to HAL HRTIM handle
6431 * @param pTimerCfg: pointer to the timer configuration data structure
6432 * @retval None
6433 */
6434 static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
6435 HRTIM_TimerCfgTypeDef * pTimerCfg)
6436 {
6437 uint32_t hrtim_mcr;
6438 uint32_t hrtim_bmcr;
6439
6440 /* Configure master timer */
6441 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
6442 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
6443
6444 /* Enable/Disable the half mode */
6445 hrtim_mcr &= ~(HRTIM_MCR_HALF);
6446 hrtim_mcr |= pTimerCfg->HalfModeEnable;
6447
6448 /* Enable/Disable the timer start upon synchronization event reception */
6449 hrtim_mcr &= ~(HRTIM_MCR_SYNCSTRTM);
6450 hrtim_mcr |= pTimerCfg->StartOnSync;
6451
6452 /* Enable/Disable the timer reset upon synchronization event reception */
6453 hrtim_mcr &= ~(HRTIM_MCR_SYNCRSTM);
6454 hrtim_mcr |= pTimerCfg->ResetOnSync;
6455
6456 /* Enable/Disable the DAC synchronization event generation */
6457 hrtim_mcr &= ~(HRTIM_MCR_DACSYNC);
6458 hrtim_mcr |= pTimerCfg->DACSynchro;
6459
6460 /* Enable/Disable preload meachanism for timer registers */
6461 hrtim_mcr &= ~(HRTIM_MCR_PREEN);
6462 hrtim_mcr |= pTimerCfg->PreloadEnable;
6463
6464 /* Master timer registers update handling */
6465 hrtim_mcr &= ~(HRTIM_MCR_BRSTDMA);
6466 hrtim_mcr |= (pTimerCfg->UpdateGating << 2);
6467
6468 /* Enable/Disable registers update on repetition */
6469 hrtim_mcr &= ~(HRTIM_MCR_MREPU);
6470 hrtim_mcr |= pTimerCfg->RepetitionUpdate;
6471
6472 /* Set the timer burst mode */
6473 hrtim_bmcr &= ~(HRTIM_BMCR_MTBM);
6474 hrtim_bmcr |= pTimerCfg->BurstMode;
6475
6476 /* Update the HRTIM registers */
6477 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
6478 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
6479 }
6480
6481 /**
6482 * @brief Configures timing unit (timer A to timer E) in waveform mode
6483 * @param hhrtim: pointer to HAL HRTIM handle
6484 * @param TimerIdx: Timer index
6485 * @param pTimerCfg: pointer to the timer configuration data structure
6486 * @retval None
6487 */
6488 static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
6489 uint32_t TimerIdx,
6490 HRTIM_TimerCfgTypeDef * pTimerCfg)
6491 {
6492 uint32_t hrtim_timcr;
6493 uint32_t hrtim_timfltr;
6494 uint32_t hrtim_timoutr;
6495 uint32_t hrtim_timrstr;
6496 uint32_t hrtim_bmcr;
6497
6498 /* UPDGAT bitfield must be reset before programming a new value */
6499 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~(HRTIM_TIMCR_UPDGAT);
6500
6501 /* Configure timing unit (Timer A to Timer E) */
6502 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
6503 hrtim_timfltr = hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR;
6504 hrtim_timoutr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
6505 hrtim_timrstr = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR;
6506 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
6507
6508 /* Enable/Disable the half mode */
6509 hrtim_timcr &= ~(HRTIM_TIMCR_HALF);
6510 hrtim_timcr |= pTimerCfg->HalfModeEnable;
6511
6512 /* Enable/Disable the timer start upon synchronization event reception */
6513 hrtim_timcr &= ~(HRTIM_TIMCR_SYNCSTRT);
6514 hrtim_timcr |= pTimerCfg->StartOnSync;
6515
6516 /* Enable/Disable the timer reset upon synchronization event reception */
6517 hrtim_timcr &= ~(HRTIM_TIMCR_SYNCRST);
6518 hrtim_timcr |= pTimerCfg->ResetOnSync;
6519
6520 /* Enable/Disable the DAC synchronization event generation */
6521 hrtim_timcr &= ~(HRTIM_TIMCR_DACSYNC);
6522 hrtim_timcr |= pTimerCfg->DACSynchro;
6523
6524 /* Enable/Disable preload meachanism for timer registers */
6525 hrtim_timcr &= ~(HRTIM_TIMCR_PREEN);
6526 hrtim_timcr |= pTimerCfg->PreloadEnable;
6527
6528 /* Timing unit registers update handling */
6529 hrtim_timcr &= ~(HRTIM_TIMCR_UPDGAT);
6530 hrtim_timcr |= pTimerCfg->UpdateGating;
6531
6532 /* Enable/Disable registers update on repetition */
6533 hrtim_timcr &= ~(HRTIM_TIMCR_TREPU);
6534 if (pTimerCfg->RepetitionUpdate == HRTIM_UPDATEONREPETITION_ENABLED)
6535 {
6536 hrtim_timcr |= HRTIM_TIMCR_TREPU;
6537 }
6538
6539 /* Set the push-pull mode */
6540 hrtim_timcr &= ~(HRTIM_TIMCR_PSHPLL);
6541 hrtim_timcr |= pTimerCfg->PushPull;
6542
6543 /* Enable/Disable registers update on timer counter reset */
6544 hrtim_timcr &= ~(HRTIM_TIMCR_TRSTU);
6545 hrtim_timcr |= pTimerCfg->ResetUpdate;
6546
6547 /* Set the timer update trigger */
6548 hrtim_timcr &= ~(HRTIM_TIMCR_TIMUPDATETRIGGER);
6549 hrtim_timcr |= pTimerCfg->UpdateTrigger;
6550
6551
6552 /* Enable/Disable the fault channel at timer level */
6553 hrtim_timfltr &= ~(HRTIM_FLTR_FLTxEN);
6554 hrtim_timfltr |= (pTimerCfg->FaultEnable & HRTIM_FLTR_FLTxEN);
6555
6556 /* Lock/Unlock fault sources at timer level */
6557 hrtim_timfltr &= ~(HRTIM_FLTR_FLTLCK);
6558 hrtim_timfltr |= pTimerCfg->FaultLock;
6559
6560 /* The deadtime cannot be used simultaneously with the push-pull mode */
6561 if (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_DISABLED)
6562 {
6563 /* Enable/Disable dead time insertion at timer level */
6564 hrtim_timoutr &= ~(HRTIM_OUTR_DTEN);
6565 hrtim_timoutr |= pTimerCfg->DeadTimeInsertion;
6566 }
6567
6568 /* Enable/Disable delayed protection at timer level
6569 Delayed Idle is available whatever the timer operating mode (regular, push-pull)
6570 Balanced Idle is only available in push-pull mode
6571 */
6572 if ( ((pTimerCfg->DelayedProtectionMode != HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68)
6573 && (pTimerCfg->DelayedProtectionMode != HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79))
6574 || (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_ENABLED))
6575 {
6576 hrtim_timoutr &= ~(HRTIM_OUTR_DLYPRT| HRTIM_OUTR_DLYPRTEN);
6577 hrtim_timoutr |= pTimerCfg->DelayedProtectionMode;
6578 }
6579
6580 /* Set the timer counter reset trigger */
6581 hrtim_timrstr = pTimerCfg->ResetTrigger;
6582
6583 /* Set the timer burst mode */
6584 switch (TimerIdx)
6585 {
6586 case HRTIM_TIMERINDEX_TIMER_A:
6587 {
6588 hrtim_bmcr &= ~(HRTIM_BMCR_TABM);
6589 hrtim_bmcr |= ( pTimerCfg->BurstMode << 1);
6590 }
6591 break;
6592 case HRTIM_TIMERINDEX_TIMER_B:
6593 {
6594 hrtim_bmcr &= ~(HRTIM_BMCR_TBBM);
6595 hrtim_bmcr |= ( pTimerCfg->BurstMode << 2);
6596 }
6597 break;
6598 case HRTIM_TIMERINDEX_TIMER_C:
6599 {
6600 hrtim_bmcr &= ~(HRTIM_BMCR_TCBM);
6601 hrtim_bmcr |= ( pTimerCfg->BurstMode << 3);
6602 }
6603 break;
6604 case HRTIM_TIMERINDEX_TIMER_D:
6605 {
6606 hrtim_bmcr &= ~(HRTIM_BMCR_TDBM);
6607 hrtim_bmcr |= ( pTimerCfg->BurstMode << 4);
6608 }
6609 break;
6610 case HRTIM_TIMERINDEX_TIMER_E:
6611 {
6612 hrtim_bmcr &= ~(HRTIM_BMCR_TEBM);
6613 hrtim_bmcr |= ( pTimerCfg->BurstMode << 5);
6614 }
6615 break;
6616 }
6617
6618 /* Update the HRTIM registers */
6619 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
6620 hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR = hrtim_timfltr;
6621 hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_timoutr;
6622 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = hrtim_timrstr;
6623 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
6624 }
6625
6626 /**
6627 * @brief Configures a compare unit
6628 * @param hhrtim: pointer to HAL HRTIM handle
6629 * @param TimerIdx: Timer index
6630 * @param CompareUnit: Compare unit identifier
6631 * @param pCompareCfg: pointer to the compare unit configuration data structure
6632 * @retval None
6633 */
6634 static void HRTIM_CompareUnitConfig(HRTIM_HandleTypeDef * hhrtim,
6635 uint32_t TimerIdx,
6636 uint32_t CompareUnit,
6637 HRTIM_CompareCfgTypeDef * pCompareCfg)
6638 {
6639 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
6640 {
6641 /* Configure the compare unit of the master timer */
6642 switch (CompareUnit)
6643 {
6644 case HRTIM_COMPAREUNIT_1:
6645 {
6646 hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue;
6647 }
6648 break;
6649 case HRTIM_COMPAREUNIT_2:
6650 {
6651 hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue;
6652 }
6653 break;
6654 case HRTIM_COMPAREUNIT_3:
6655 {
6656 hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue;
6657 }
6658 break;
6659 case HRTIM_COMPAREUNIT_4:
6660 {
6661 hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue;
6662 }
6663 break;
6664 }
6665 }
6666 else
6667 {
6668 /* Configure the compare unit of the timing unit */
6669 switch (CompareUnit)
6670 {
6671 case HRTIM_COMPAREUNIT_1:
6672 {
6673 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
6674 }
6675 break;
6676 case HRTIM_COMPAREUNIT_2:
6677 {
6678 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
6679 }
6680 break;
6681 case HRTIM_COMPAREUNIT_3:
6682 {
6683 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
6684 }
6685 break;
6686 case HRTIM_COMPAREUNIT_4:
6687 {
6688 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
6689 }
6690 break;
6691 }
6692 }
6693 }
6694
6695 /**
6696 * @brief Configures a capture unit
6697 * @param hhrtim: pointer to HAL HRTIM handle
6698 * @param TimerIdx: Timer index
6699 * @param CaptureUnit: Capture unit identifier
6700 * @param Event: Event reference
6701 * @retval None
6702 */
6703 static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
6704 uint32_t TimerIdx,
6705 uint32_t CaptureUnit,
6706 uint32_t Event)
6707 {
6708 uint32_t CaptureTrigger = 0xFFFFFFFF;
6709
6710 switch (Event)
6711 {
6712 case HRTIM_EVENT_1:
6713 {
6714 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1;
6715 }
6716 break;
6717 case HRTIM_EVENT_2:
6718 {
6719 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2;
6720 }
6721 break;
6722 case HRTIM_EVENT_3:
6723 {
6724 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3;
6725 }
6726 break;
6727 case HRTIM_EVENT_4:
6728 {
6729 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4;
6730 }
6731 break;
6732 case HRTIM_EVENT_5:
6733 {
6734 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5;
6735 }
6736 break;
6737 case HRTIM_EVENT_6:
6738 {
6739 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6;
6740 }
6741 break;
6742 case HRTIM_EVENT_7:
6743 {
6744 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7;
6745 }
6746 break;
6747 case HRTIM_EVENT_8:
6748 {
6749 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8;
6750 }
6751 break;
6752 case HRTIM_EVENT_9:
6753 {
6754 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9;
6755 }
6756 break;
6757 case HRTIM_EVENT_10:
6758 {
6759 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10;
6760 }
6761 break;
6762 }
6763
6764 switch (CaptureUnit)
6765 {
6766 case HRTIM_CAPTUREUNIT_1:
6767 {
6768 hhrtim->TimerParam[TimerIdx].CaptureTrigger1 = CaptureTrigger;
6769 }
6770 break;
6771 case HRTIM_CAPTUREUNIT_2:
6772 {
6773 hhrtim->TimerParam[TimerIdx].CaptureTrigger2 = CaptureTrigger;
6774 }
6775 break;
6776 }
6777 }
6778
6779 /**
6780 * @brief Configures the output of a timing unit
6781 * @param hhrtim: pointer to HAL HRTIM handle
6782 * @param TimerIdx: Timer index
6783 * @param Output: timing unit output identifier
6784 * @param pOutputCfg: pointer to the output configuration data structure
6785 * @retval None
6786 */
6787 static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
6788 uint32_t TimerIdx,
6789 uint32_t Output,
6790 HRTIM_OutputCfgTypeDef * pOutputCfg)
6791 {
6792 uint32_t hrtim_outr;
6793 uint32_t hrtim_dtr;
6794
6795 uint32_t shift = 0xFFFFFFFF;
6796
6797 hrtim_outr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
6798 hrtim_dtr = hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR;
6799
6800 switch (Output)
6801 {
6802 case HRTIM_OUTPUT_TA1:
6803 case HRTIM_OUTPUT_TB1:
6804 case HRTIM_OUTPUT_TC1:
6805 case HRTIM_OUTPUT_TD1:
6806 case HRTIM_OUTPUT_TE1:
6807 {
6808 /* Set the output set/reset crossbar */
6809 hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R = pOutputCfg->SetSource;
6810 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R = pOutputCfg->ResetSource;
6811
6812 shift = 0;
6813 }
6814 break;
6815 case HRTIM_OUTPUT_TA2:
6816 case HRTIM_OUTPUT_TB2:
6817 case HRTIM_OUTPUT_TC2:
6818 case HRTIM_OUTPUT_TD2:
6819 case HRTIM_OUTPUT_TE2:
6820 {
6821 /* Set the output set/reset crossbar */
6822 hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R = pOutputCfg->SetSource;
6823 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R = pOutputCfg->ResetSource;
6824
6825 shift = 16;
6826 }
6827 break;
6828 }
6829
6830 /* Clear output config */
6831 hrtim_outr &= ~((HRTIM_OUTR_POL1 |
6832 HRTIM_OUTR_IDLM1 |
6833 HRTIM_OUTR_IDLES1|
6834 HRTIM_OUTR_FAULT1|
6835 HRTIM_OUTR_CHP1 |
6836 HRTIM_OUTR_DIDL1) << shift);
6837
6838 /* Set the polarity */
6839 hrtim_outr |= (pOutputCfg->Polarity << shift);
6840
6841 /* Set the IDLE mode */
6842 hrtim_outr |= (pOutputCfg->IdleMode << shift);
6843
6844 /* Set the IDLE state */
6845 hrtim_outr |= (pOutputCfg->IdleLevel << shift);
6846
6847 /* Set the FAULT state */
6848 hrtim_outr |= (pOutputCfg->FaultLevel << shift);
6849
6850 /* Set the chopper mode */
6851 hrtim_outr |= (pOutputCfg->ChopperModeEnable << shift);
6852
6853 /* Set the burst mode entry mode : deadtime insertion when entering the idle
6854 state during a burst mode operation is allowed only under the following
6855 conditions:
6856 - the outputs is active during the burst mode (IDLES=1)
6857 - positive deadtimes (SDTR/SDTF set to 0)
6858 */
6859 if ((pOutputCfg->IdleLevel == HRTIM_OUTPUTIDLELEVEL_ACTIVE) &&
6860 ((hrtim_dtr & HRTIM_DTR_SDTR) == RESET) &&
6861 ((hrtim_dtr & HRTIM_DTR_SDTF) == RESET))
6862 {
6863 hrtim_outr |= (pOutputCfg->BurstModeEntryDelayed << shift);
6864 }
6865
6866 /* Update HRTIM register */
6867 hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_outr;
6868 }
6869
6870 /**
6871 * @brief Configures an external event channel
6872 * @param hhrtim: pointer to HAL HRTIM handle
6873 * @param Event: Event channel identifier
6874 * @param pEventCfg: pointer to the event channel configuration data structure
6875 * @retval None
6876 */
6877 static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
6878 uint32_t Event,
6879 HRTIM_EventCfgTypeDef *pEventCfg)
6880 {
6881 uint32_t hrtim_eecr1;
6882 uint32_t hrtim_eecr2;
6883 uint32_t hrtim_eecr3;
6884
6885 /* Configure external event channel */
6886 hrtim_eecr1 = hhrtim->Instance->sCommonRegs.EECR1;
6887 hrtim_eecr2 = hhrtim->Instance->sCommonRegs.EECR2;
6888 hrtim_eecr3 = hhrtim->Instance->sCommonRegs.EECR3;
6889
6890 switch (Event)
6891 {
6892 case HRTIM_EVENT_1:
6893 {
6894 hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST);
6895 hrtim_eecr1 |= pEventCfg->Source;
6896 hrtim_eecr1 |= (pEventCfg->Polarity & HRTIM_EECR1_EE1POL);
6897 hrtim_eecr1 |= pEventCfg->Sensitivity;
6898 /* Update the HRTIM registers (all bitfields but EE1FAST bit) */
6899 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
6900 /* Update the HRTIM registers (EE1FAST bit) */
6901 hrtim_eecr1 |= pEventCfg->FastMode;
6902 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
6903 }
6904 break;
6905 case HRTIM_EVENT_2:
6906 {
6907 hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST);
6908 hrtim_eecr1 |= (pEventCfg->Source << 6);
6909 hrtim_eecr1 |= ((pEventCfg->Polarity << 6) & (HRTIM_EECR1_EE2POL));
6910 hrtim_eecr1 |= (pEventCfg->Sensitivity << 6);
6911 /* Update the HRTIM registers (all bitfields but EE2FAST bit) */
6912 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
6913 /* Update the HRTIM registers (EE2FAST bit) */
6914 hrtim_eecr1 |= (pEventCfg->FastMode << 6);
6915 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
6916 }
6917 break;
6918 case HRTIM_EVENT_3:
6919 {
6920 hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST);
6921 hrtim_eecr1 |= (pEventCfg->Source << 12);
6922 hrtim_eecr1 |= ((pEventCfg->Polarity << 12) & (HRTIM_EECR1_EE3POL));
6923 hrtim_eecr1 |= (pEventCfg->Sensitivity << 12);
6924 /* Update the HRTIM registers (all bitfields but EE3FAST bit) */
6925 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
6926 /* Update the HRTIM registers (EE3FAST bit) */
6927 hrtim_eecr1 |= (pEventCfg->FastMode << 12);
6928 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
6929 }
6930 break;
6931 case HRTIM_EVENT_4:
6932 {
6933 hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST);
6934 hrtim_eecr1 |= (pEventCfg->Source << 18);
6935 hrtim_eecr1 |= ((pEventCfg->Polarity << 18) & (HRTIM_EECR1_EE4POL));
6936 hrtim_eecr1 |= (pEventCfg->Sensitivity << 18);
6937 /* Update the HRTIM registers (all bitfields but EE4FAST bit) */
6938 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
6939 /* Update the HRTIM registers (EE4FAST bit) */
6940 hrtim_eecr1 |= (pEventCfg->FastMode << 18);
6941 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
6942 }
6943 break;
6944 case HRTIM_EVENT_5:
6945 {
6946 hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST);
6947 hrtim_eecr1 |= (pEventCfg->Source << 24);
6948 hrtim_eecr1 |= ((pEventCfg->Polarity << 24) & (HRTIM_EECR1_EE5POL));
6949 hrtim_eecr1 |= (pEventCfg->Sensitivity << 24);
6950 /* Update the HRTIM registers (all bitfields but EE5FAST bit) */
6951 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
6952 /* Update the HRTIM registers (EE5FAST bit) */
6953 hrtim_eecr1 |= (pEventCfg->FastMode << 24);
6954 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
6955 }
6956 break;
6957 case HRTIM_EVENT_6:
6958 {
6959 hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS);
6960 hrtim_eecr2 |= pEventCfg->Source;
6961 hrtim_eecr2 |= (pEventCfg->Polarity & HRTIM_EECR2_EE6POL);
6962 hrtim_eecr2 |= pEventCfg->Sensitivity;
6963 hrtim_eecr3 &= ~(HRTIM_EECR3_EE6F);
6964 hrtim_eecr3 |= pEventCfg->Filter;
6965 /* Update the HRTIM registers */
6966 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
6967 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
6968 }
6969 break;
6970 case HRTIM_EVENT_7:
6971 {
6972 hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS);
6973 hrtim_eecr2 |= (pEventCfg->Source << 6);
6974 hrtim_eecr2 |= ((pEventCfg->Polarity << 6) & (HRTIM_EECR2_EE7POL));
6975 hrtim_eecr2 |= (pEventCfg->Sensitivity << 6);
6976 hrtim_eecr3 &= ~(HRTIM_EECR3_EE7F);
6977 hrtim_eecr3 |= (pEventCfg->Filter << 6);
6978 /* Update the HRTIM registers */
6979 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
6980 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
6981 }
6982 break;
6983 case HRTIM_EVENT_8:
6984 {
6985 hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS);
6986 hrtim_eecr2 |= (pEventCfg->Source << 12);
6987 hrtim_eecr2 |= ((pEventCfg->Polarity << 12) & (HRTIM_EECR2_EE8POL));
6988 hrtim_eecr2 |= (pEventCfg->Sensitivity << 12);
6989 hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F);
6990 hrtim_eecr3 |= (pEventCfg->Filter << 12);
6991 /* Update the HRTIM registers */
6992 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
6993 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
6994 }
6995 break;
6996 case HRTIM_EVENT_9:
6997 {
6998 hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS);
6999 hrtim_eecr2 |= (pEventCfg->Source << 18);
7000 hrtim_eecr2 |= ((pEventCfg->Polarity << 18) & (HRTIM_EECR2_EE9POL));
7001 hrtim_eecr2 |= (pEventCfg->Sensitivity << 18);
7002 hrtim_eecr3 &= ~(HRTIM_EECR3_EE9F);
7003 hrtim_eecr3 |= (pEventCfg->Filter << 18);
7004 /* Update the HRTIM registers */
7005 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
7006 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
7007 }
7008 break;
7009 case HRTIM_EVENT_10:
7010 {
7011 hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS);
7012 hrtim_eecr2 |= (pEventCfg->Source << 24);
7013 hrtim_eecr2 |= ((pEventCfg->Polarity << 24) & (HRTIM_EECR2_EE10POL));
7014 hrtim_eecr2 |= (pEventCfg->Sensitivity << 24);
7015 hrtim_eecr3 &= ~(HRTIM_EECR3_EE10F);
7016 hrtim_eecr3 |= (pEventCfg->Filter << 24);
7017 /* Update the HRTIM registers */
7018 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
7019 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
7020 }
7021 break;
7022 default:
7023 break;
7024 }
7025 }
7026
7027 /**
7028 * @brief Configures the timer counter reset
7029 * @param hhrtim: pointer to HAL HRTIM handle
7030 * @param TimerIdx: Timer index
7031 * @param Event: Event channel identifier
7032 * @retval None
7033 */
7034 static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
7035 uint32_t TimerIdx,
7036 uint32_t Event)
7037 {
7038 switch (Event)
7039 {
7040 case HRTIM_EVENT_1:
7041 {
7042 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1;
7043 }
7044 break;
7045 case HRTIM_EVENT_2:
7046 {
7047 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2;
7048 }
7049 break;
7050 case HRTIM_EVENT_3:
7051 {
7052 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3;
7053 }
7054 break;
7055 case HRTIM_EVENT_4:
7056 {
7057 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4;
7058 }
7059 break;
7060 case HRTIM_EVENT_5:
7061 {
7062 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5;
7063 }
7064 break;
7065 case HRTIM_EVENT_6:
7066 {
7067 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6;
7068 }
7069 break;
7070 case HRTIM_EVENT_7:
7071 {
7072 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7;
7073 }
7074 break;
7075 case HRTIM_EVENT_8:
7076 {
7077 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8;
7078 }
7079 break;
7080 case HRTIM_EVENT_9:
7081 {
7082 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9;
7083 }
7084 break;
7085 case HRTIM_EVENT_10:
7086 {
7087 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10;
7088 }
7089 break;
7090 }
7091 }
7092
7093 /**
7094 * @brief Returns the interrupt to enable or disable according to the
7095 * OC mode.
7096 * @param hhrtim: pointer to HAL HRTIM handle
7097 * @param TimerIdx: Timer index
7098 * @param OCChannel: Timer output
7099 * This parameter can be one of the following values:
7100 * @arg HRTIM_OUTPUT_TA1: Timer A - Ouput 1
7101 * @arg HRTIM_OUTPUT_TA2: Timer A - Ouput 2
7102 * @arg HRTIM_OUTPUT_TB1: Timer B - Ouput 1
7103 * @arg HRTIM_OUTPUT_TB2: Timer B - Ouput 2
7104 * @arg HRTIM_OUTPUT_TC1: Timer C - Ouput 1
7105 * @arg HRTIM_OUTPUT_TC2: Timer C - Ouput 2
7106 * @arg HRTIM_OUTPUT_TD1: Timer D - Ouput 1
7107 * @arg HRTIM_OUTPUT_TD2: Timer D - Ouput 2
7108 * @arg HRTIM_OUTPUT_TE1: Timer E - Ouput 1
7109 * @arg HRTIM_OUTPUT_TE2: Timer E - Ouput 2
7110 * @retval Interrupt to enable or disable
7111 */
7112 static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim,
7113 uint32_t TimerIdx,
7114 uint32_t OCChannel)
7115 {
7116 uint32_t hrtim_set;
7117 uint32_t hrtim_reset;
7118 uint32_t interrupt = 0;
7119
7120 switch (OCChannel)
7121 {
7122 case HRTIM_OUTPUT_TA1:
7123 case HRTIM_OUTPUT_TB1:
7124 case HRTIM_OUTPUT_TC1:
7125 case HRTIM_OUTPUT_TD1:
7126 case HRTIM_OUTPUT_TE1:
7127 {
7128 /* Retreives actual OC mode and set interrupt accordingly */
7129 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
7130 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
7131
7132 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
7133 ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
7134 {
7135 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
7136 interrupt = HRTIM_TIM_IT_CMP1;
7137 }
7138 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
7139 (hrtim_reset == 0))
7140 {
7141 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
7142 interrupt = HRTIM_TIM_IT_SET1;
7143 }
7144 else if ((hrtim_set == 0) &&
7145 ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
7146 {
7147 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
7148 interrupt = HRTIM_TIM_IT_RST1;
7149 }
7150 }
7151 break;
7152 case HRTIM_OUTPUT_TA2:
7153 case HRTIM_OUTPUT_TB2:
7154 case HRTIM_OUTPUT_TC2:
7155 case HRTIM_OUTPUT_TD2:
7156 case HRTIM_OUTPUT_TE2:
7157 {
7158 /* Retreives actual OC mode and set interrupt accordingly */
7159 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
7160 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
7161
7162 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
7163 ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
7164 {
7165 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
7166 interrupt = HRTIM_TIM_IT_CMP2;
7167 }
7168 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
7169 (hrtim_reset == 0))
7170 {
7171 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
7172 interrupt = HRTIM_TIM_IT_SET2;
7173 }
7174 else if ((hrtim_set == 0) &&
7175 ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
7176 {
7177 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
7178 interrupt = HRTIM_TIM_IT_RST2;
7179 }
7180 }
7181 break;
7182 }
7183
7184 return interrupt;
7185 }
7186
7187 /**
7188 * @brief Returns the DMA request to enable or disable according to the
7189 * OC mode.
7190 * @param hhrtim: pointer to HAL HRTIM handle
7191 * @param TimerIdx: Timer index
7192 * @param OCChannel: Timer output
7193 * This parameter can be one of the following values:
7194 * @arg HRTIM_OUTPUT_TA1: Timer A - Ouput 1
7195 * @arg HRTIM_OUTPUT_TA2: Timer A - Ouput 2
7196 * @arg HRTIM_OUTPUT_TB1: Timer B - Ouput 1
7197 * @arg HRTIM_OUTPUT_TB2: Timer B - Ouput 2
7198 * @arg HRTIM_OUTPUT_TC1: Timer C - Ouput 1
7199 * @arg HRTIM_OUTPUT_TC2: Timer C - Ouput 2
7200 * @arg HRTIM_OUTPUT_TD1: Timer D - Ouput 1
7201 * @arg HRTIM_OUTPUT_TD2: Timer D - Ouput 2
7202 * @arg HRTIM_OUTPUT_TE1: Timer E - Ouput 1
7203 * @arg HRTIM_OUTPUT_TE2: Timer E - Ouput 2
7204 * @retval DMA request to enable or disable
7205 */
7206 static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim,
7207 uint32_t TimerIdx,
7208 uint32_t OCChannel)
7209 {
7210 uint32_t hrtim_set;
7211 uint32_t hrtim_reset;
7212 uint32_t dma_request = 0;
7213
7214 switch (OCChannel)
7215 {
7216 case HRTIM_OUTPUT_TA1:
7217 case HRTIM_OUTPUT_TB1:
7218 case HRTIM_OUTPUT_TC1:
7219 case HRTIM_OUTPUT_TD1:
7220 case HRTIM_OUTPUT_TE1:
7221 {
7222 /* Retreives actual OC mode and set dma_request accordingly */
7223 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
7224 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
7225
7226 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
7227 ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
7228 {
7229 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
7230 dma_request = HRTIM_TIM_DMA_CMP1;
7231 }
7232 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
7233 (hrtim_reset == 0))
7234 {
7235 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
7236 dma_request = HRTIM_TIM_DMA_SET1;
7237 }
7238 else if ((hrtim_set == 0) &&
7239 ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
7240 {
7241 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
7242 dma_request = HRTIM_TIM_DMA_RST1;
7243 }
7244 }
7245 break;
7246 case HRTIM_OUTPUT_TA2:
7247 case HRTIM_OUTPUT_TB2:
7248 case HRTIM_OUTPUT_TC2:
7249 case HRTIM_OUTPUT_TD2:
7250 case HRTIM_OUTPUT_TE2:
7251 {
7252 /* Retreives actual OC mode and set dma_request accordingly */
7253 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
7254 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
7255
7256 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
7257 ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
7258 {
7259 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
7260 dma_request = HRTIM_TIM_DMA_CMP2;
7261 }
7262 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
7263 (hrtim_reset == 0))
7264 {
7265 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
7266 dma_request = HRTIM_TIM_DMA_SET2;
7267 }
7268 else if ((hrtim_set == 0) &&
7269 ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
7270 {
7271 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
7272 dma_request = HRTIM_TIM_DMA_RST2;
7273 }
7274 }
7275 break;
7276 }
7277
7278 return dma_request;
7279 }
7280
7281 static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hhrtim,
7282 uint32_t TimerIdx)
7283 {
7284 DMA_HandleTypeDef * hdma = (DMA_HandleTypeDef *)HAL_NULL;
7285
7286 switch (TimerIdx)
7287 {
7288 case HRTIM_TIMERINDEX_MASTER:
7289 {
7290 hdma = hhrtim->hdmaMaster;
7291 }
7292 break;
7293 case HRTIM_TIMERINDEX_TIMER_A:
7294 {
7295 hdma = hhrtim->hdmaTimerA;
7296 }
7297 break;
7298 case HRTIM_TIMERINDEX_TIMER_B:
7299 {
7300 hdma = hhrtim->hdmaTimerB;
7301 }
7302 break;
7303 case HRTIM_TIMERINDEX_TIMER_C:
7304 {
7305 hdma = hhrtim->hdmaTimerC;
7306 }
7307 break;
7308 case HRTIM_TIMERINDEX_TIMER_D:
7309 {
7310 hdma = hhrtim->hdmaTimerD;
7311 }
7312 break;
7313 case HRTIM_TIMERINDEX_TIMER_E:
7314 {
7315 hdma = hhrtim->hdmaTimerE;
7316 }
7317 break;
7318 }
7319
7320 return hdma;
7321 }
7322
7323 static uint32_t GetTimerIdxFromDMAHandle(DMA_HandleTypeDef *hdma)
7324 {
7325 uint32_t timed_idx = 0xFFFFFFFF;
7326
7327 if (hdma->Instance == DMA1_Channel2)
7328 {
7329 timed_idx = HRTIM_TIMERINDEX_MASTER;
7330 }
7331 else if (hdma->Instance == DMA1_Channel3)
7332 {
7333 timed_idx = HRTIM_TIMERINDEX_TIMER_A;
7334 }
7335 else if (hdma->Instance == DMA1_Channel4)
7336 {
7337 timed_idx = HRTIM_TIMERINDEX_TIMER_B;
7338 }
7339 else if (hdma->Instance == DMA1_Channel5)
7340 {
7341 timed_idx = HRTIM_TIMERINDEX_TIMER_C;
7342 }
7343 else if (hdma->Instance == DMA1_Channel6)
7344 {
7345 timed_idx = HRTIM_TIMERINDEX_TIMER_D;
7346 }
7347 else if (hdma->Instance == DMA1_Channel7)
7348 {
7349 timed_idx = HRTIM_TIMERINDEX_TIMER_E;
7350 }
7351
7352 return timed_idx;
7353 }
7354
7355 /**
7356 * @brief Forces an immediate transfer from the preload to the active
7357 * registers.
7358 * @param hhrtim: pointer to HAL HRTIM handle
7359 * @param TimerIdx: Timer index
7360 * @retval None
7361 */
7362 static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
7363 uint32_t TimerIdx)
7364 {
7365 switch (TimerIdx)
7366 {
7367 case HRTIM_TIMERINDEX_MASTER:
7368 {
7369 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_MSWU;
7370 }
7371 break;
7372 case HRTIM_TIMERINDEX_TIMER_A:
7373 {
7374 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TASWU;
7375 }
7376 break;
7377 case HRTIM_TIMERINDEX_TIMER_B:
7378 {
7379 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TBSWU;
7380 }
7381 break;
7382 case HRTIM_TIMERINDEX_TIMER_C:
7383 {
7384 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TCSWU;
7385 }
7386 break;
7387 case HRTIM_TIMERINDEX_TIMER_D:
7388 {
7389 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TDSWU;
7390 }
7391 break;
7392 case HRTIM_TIMERINDEX_TIMER_E:
7393 {
7394 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TESWU;
7395 }
7396 break;
7397 }
7398 }
7399
7400
7401 /**
7402 * @brief HRTIM interrupts service routine
7403 * @param hhrtim: pointer to HAL HRTIM handle
7404 * @retval None
7405 */
7406 static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim)
7407 {
7408 /* Fault 1 event */
7409 if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT1) != RESET)
7410 {
7411 if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT1) != RESET)
7412 {
7413 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT1);
7414
7415 /* Invoke Fault 1 event callback */
7416 HAL_HRTIM_Fault1Callback(hhrtim);
7417 }
7418 }
7419
7420 /* Fault 2 event */
7421 if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT2) != RESET)
7422 {
7423 if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT2) != RESET)
7424 {
7425 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT2);
7426
7427 /* Invoke Fault 2 event callback */
7428 HAL_HRTIM_Fault2Callback(hhrtim);
7429 }
7430 }
7431
7432 /* Fault 3 event */
7433 if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT3) != RESET)
7434 {
7435 if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT3) != RESET)
7436 {
7437 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT3);
7438
7439 /* Invoke Fault 3 event callback */
7440 HAL_HRTIM_Fault3Callback(hhrtim);
7441 }
7442 }
7443
7444 /* Fault 4 event */
7445 if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT4) != RESET)
7446 {
7447 if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT4) != RESET)
7448 {
7449 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT4);
7450
7451 /* Invoke Fault 4 event callback */
7452 HAL_HRTIM_Fault4Callback(hhrtim);
7453 }
7454 }
7455
7456 /* Fault 5 event */
7457 if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT5) != RESET)
7458 {
7459 if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT5) != RESET)
7460 {
7461 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT5);
7462
7463 /* Invoke Fault 5 event callback */
7464 HAL_HRTIM_Fault5Callback(hhrtim);
7465 }
7466 }
7467
7468 /* System fault event */
7469 if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_SYSFLT) != RESET)
7470 {
7471 if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_SYSFLT) != RESET)
7472 {
7473 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_SYSFLT);
7474
7475 /* Invoke System fault event callback */
7476 HAL_HRTIM_SystemFaultCallback(hhrtim);
7477 }
7478 }
7479 }
7480
7481 /**
7482 * @brief Master timer interrupts service routine
7483 * @param hhrtim: pointer to HAL HRTIM handle
7484 * @retval None
7485 */
7486 static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim)
7487 {
7488 /* DLL calibration ready event */
7489 if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_DLLRDY) != RESET)
7490 {
7491 if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_DLLRDY) != RESET)
7492 {
7493 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_DLLRDY);
7494
7495 /* Set HRTIM State */
7496 hhrtim->State = HAL_HRTIM_STATE_READY;
7497
7498 /* Process unlocked */
7499 __HAL_UNLOCK(hhrtim);
7500
7501 /* Invoke System fault event callback */
7502 HAL_HRTIM_DLLCalbrationReadyCallback(hhrtim);
7503 }
7504 }
7505
7506 /* Burst mode period event */
7507 if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_BMPER) != RESET)
7508 {
7509 if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_BMPER) != RESET)
7510 {
7511 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_BMPER);
7512
7513 /* Invoke Burst mode period event callback */
7514 HAL_HRTIM_BurstModePeriodCallback(hhrtim);
7515 }
7516 }
7517
7518 /* Master timer compare 1 event */
7519 if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP1) != RESET)
7520 {
7521 if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP1) != RESET)
7522 {
7523 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP1);
7524
7525 /* Invoke compare 1 event callback */
7526 HAL_HRTIM_Compare1EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
7527 }
7528 }
7529
7530 /* Master timer compare 2 event */
7531 if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP2) != RESET)
7532 {
7533 if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP2) != RESET)
7534 {
7535 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP2);
7536
7537 /* Invoke compare 2 event callback */
7538 HAL_HRTIM_Compare2EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
7539 }
7540 }
7541
7542 /* Master timer compare 3 event */
7543 if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP3) != RESET)
7544 {
7545 if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP3) != RESET)
7546 {
7547 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP3);
7548
7549 /* Invoke compare 3 event callback */
7550 HAL_HRTIM_Compare3EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
7551 }
7552 }
7553
7554 /* Master timer compare 4 event */
7555 if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP4) != RESET)
7556 {
7557 if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP4) != RESET)
7558 {
7559 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP4);
7560
7561 /* Invoke compare 4 event callback */
7562 HAL_HRTIM_Compare4EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
7563 }
7564 }
7565
7566 /* Master timer repetition event */
7567 if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MREP) != RESET)
7568 {
7569 if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MREP) != RESET)
7570 {
7571 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MREP);
7572
7573 /* Invoke repetition event callback */
7574 HAL_HRTIM_RepetitionEventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
7575 }
7576 }
7577
7578 /* Synchronization input event */
7579 if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_SYNC) != RESET)
7580 {
7581 if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_SYNC) != RESET)
7582 {
7583 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_SYNC);
7584
7585 /* Invoke synchronization event callback */
7586 HAL_HRTIM_SynchronizationEventCallback(hhrtim);
7587 }
7588 }
7589
7590 /* Master timer registers update event */
7591 if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MUPD) != RESET)
7592 {
7593 if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MUPD) != RESET)
7594 {
7595 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MUPD);
7596
7597 /* Invoke registers update event callback */
7598 HAL_HRTIM_RegistersUpdateCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
7599 }
7600 }
7601 }
7602
7603 /**
7604 * @brief Timer interrupts service routine
7605 * @param hhrtim: pointer to HAL HRTIM handle
7606 * @param TimerIdx: Timer index
7607 * This parameter can be one of the following values:
7608 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7609 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7610 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7611 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7612 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7613 * @retval None
7614 */
7615 static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
7616 uint32_t TimerIdx)
7617 {
7618 /* Timer compare 1 event */
7619 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP1) != RESET)
7620 {
7621 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1) != RESET)
7622 {
7623 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
7624
7625 /* Invoke compare 1 event callback */
7626 HAL_HRTIM_Compare1EventCallback(hhrtim, TimerIdx);
7627 }
7628 }
7629
7630 /* Timer compare 2 event */
7631 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP2) != RESET)
7632 {
7633 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2) != RESET)
7634 {
7635 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
7636
7637 /* Invoke compare 2 event callback */
7638 HAL_HRTIM_Compare2EventCallback(hhrtim, TimerIdx);
7639 }
7640 }
7641
7642 /* Timer compare 3 event */
7643 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP3) != RESET)
7644 {
7645 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3) != RESET)
7646 {
7647 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3);
7648
7649 /* Invoke compare 3 event callback */
7650 HAL_HRTIM_Compare3EventCallback(hhrtim, TimerIdx);
7651 }
7652 }
7653
7654 /* Timer compare 4 event */
7655 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP4) != RESET)
7656 {
7657 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4) != RESET)
7658 {
7659 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4);
7660
7661 /* Invoke compare 4 event callback */
7662 HAL_HRTIM_Compare4EventCallback(hhrtim, TimerIdx);
7663 }
7664 }
7665
7666 /* Timer repetition event */
7667 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_REP) != RESET)
7668 {
7669 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_REP) != RESET)
7670 {
7671 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
7672
7673 /* Invoke repetition event callback */
7674 HAL_HRTIM_RepetitionEventCallback(hhrtim, TimerIdx);
7675 }
7676 }
7677
7678 /* Timer registers update event */
7679 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_UPD) != RESET)
7680 {
7681 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD) != RESET)
7682 {
7683 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD);
7684
7685 /* Invoke registers update event callback */
7686 HAL_HRTIM_RegistersUpdateCallback(hhrtim, TimerIdx);
7687 }
7688 }
7689
7690 /* Timer capture 1 event */
7691 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CPT1) != RESET)
7692 {
7693 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1) != RESET)
7694 {
7695 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
7696
7697 /* Invoke capture 1 event callback */
7698 HAL_HRTIM_Capture1EventCallback(hhrtim, TimerIdx);
7699 }
7700 }
7701
7702 /* Timer capture 2 event */
7703 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CPT2) != RESET)
7704 {
7705 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2) != RESET)
7706 {
7707 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
7708
7709 /* Invoke capture 2 event callback */
7710 HAL_HRTIM_Capture2EventCallback(hhrtim, TimerIdx);
7711 }
7712 }
7713
7714 /* Timer ouput 1 set event */
7715 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_SET1) != RESET)
7716 {
7717 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1) != RESET)
7718 {
7719 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1);
7720
7721 /* Invoke ouput 1 set event callback */
7722 HAL_HRTIM_Output1SetCallback(hhrtim, TimerIdx);
7723 }
7724 }
7725
7726 /* Timer ouput 1 reset event */
7727 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST1) != RESET)
7728 {
7729 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1) != RESET)
7730 {
7731 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1);
7732
7733 /* Invoke ouput 1 reset event callback */
7734 HAL_HRTIM_Output1ResetCallback(hhrtim, TimerIdx);
7735 }
7736 }
7737
7738 /* Timer ouput 2 set event */
7739 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_SET2) != RESET)
7740 {
7741 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2) != RESET)
7742 {
7743 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2);
7744
7745 /* Invoke ouput 2 set event callback */
7746 HAL_HRTIM_Output2SetCallback(hhrtim, TimerIdx);
7747 }
7748 }
7749
7750 /* Timer ouput 2 reset event */
7751 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST2) != RESET)
7752 {
7753 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2) != RESET)
7754 {
7755 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2);
7756
7757 /* Invoke ouput 2 reset event callback */
7758 HAL_HRTIM_Output2ResetCallback(hhrtim, TimerIdx);
7759 }
7760 }
7761
7762 /* Timer reset event */
7763 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST) != RESET)
7764 {
7765 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST) != RESET)
7766 {
7767 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST);
7768
7769 /* Invoke timer reset callback */
7770 HAL_HRTIM_CounterResetCallback(hhrtim, TimerIdx);
7771 }
7772 }
7773
7774 /* Delayed protection event */
7775 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_DLYPRT) != RESET)
7776 {
7777 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT) != RESET)
7778 {
7779 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT);
7780
7781 /* Invoke delayed protection callback */
7782 HAL_HRTIM_DelayedProtectionCallback(hhrtim, TimerIdx);
7783 }
7784 }
7785 }
7786
7787 /**
7788 * @brief DMA callback invoked upon master timer related DMA request completion
7789 * @param hdma: pointer to DMA handle.
7790 * @retval None
7791 */
7792 static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma)
7793 {
7794 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
7795
7796 if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP1) != RESET)
7797 {
7798 HAL_HRTIM_Compare1EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
7799 }
7800 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP2) != RESET)
7801 {
7802 HAL_HRTIM_Compare2EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
7803 }
7804 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP3) != RESET)
7805 {
7806 HAL_HRTIM_Compare3EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
7807 }
7808 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP4) != RESET)
7809 {
7810 HAL_HRTIM_Compare4EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
7811 }
7812 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MREP) != RESET)
7813 {
7814 HAL_HRTIM_RepetitionEventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
7815 }
7816 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_SYNC) != RESET)
7817 {
7818 HAL_HRTIM_SynchronizationEventCallback(hrtim);
7819 }
7820 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MUPD) != RESET)
7821 {
7822 HAL_HRTIM_RegistersUpdateCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
7823 }
7824 }
7825
7826 /**
7827 * @brief DMA callback invoked upon timer A..E related DMA request completion
7828 * @param hdma: pointer to DMA handle.
7829 * @retval None
7830 */
7831 static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma)
7832 {
7833 uint8_t timer_idx;
7834
7835 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
7836
7837 timer_idx = GetTimerIdxFromDMAHandle(hdma);
7838
7839 if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP1) != RESET)
7840 {
7841 HAL_HRTIM_Compare1EventCallback(hrtim, timer_idx);
7842 }
7843 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP2) != RESET)
7844 {
7845 HAL_HRTIM_Compare2EventCallback(hrtim, timer_idx);
7846 }
7847 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP3) != RESET)
7848 {
7849 HAL_HRTIM_Compare3EventCallback(hrtim, timer_idx);
7850 }
7851 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP4) != RESET)
7852 {
7853 HAL_HRTIM_Compare4EventCallback(hrtim, timer_idx);
7854 }
7855 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_REP) != RESET)
7856 {
7857 HAL_HRTIM_RepetitionEventCallback(hrtim, timer_idx);
7858 }
7859 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_UPD) != RESET)
7860 {
7861 HAL_HRTIM_RegistersUpdateCallback(hrtim, timer_idx);
7862 }
7863 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT1) != RESET)
7864 {
7865 HAL_HRTIM_Capture1EventCallback(hrtim, timer_idx);
7866 }
7867 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT2) != RESET)
7868 {
7869 HAL_HRTIM_Capture2EventCallback(hrtim, timer_idx);
7870 }
7871 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET1) != RESET)
7872 {
7873 HAL_HRTIM_Output1SetCallback(hrtim, timer_idx);
7874 }
7875 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST1) != RESET)
7876 {
7877 HAL_HRTIM_Output1ResetCallback(hrtim, timer_idx);
7878 }
7879 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET2) != RESET)
7880 {
7881 HAL_HRTIM_Output2SetCallback(hrtim, timer_idx);
7882 }
7883 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST2) != RESET)
7884 {
7885 HAL_HRTIM_Output2ResetCallback(hrtim, timer_idx);
7886 }
7887 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST) != RESET)
7888 {
7889 HAL_HRTIM_CounterResetCallback(hrtim, timer_idx);
7890 }
7891 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_DLYPRT) != RESET)
7892 {
7893 HAL_HRTIM_DelayedProtectionCallback(hrtim, timer_idx);
7894 }
7895 }
7896
7897 /**
7898 * @brief DMA error callback
7899 * @param hdma: pointer to DMA handle.
7900 * @retval None
7901 */
7902 static void HRTIM_DMAError(DMA_HandleTypeDef *hdma)
7903 {
7904 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
7905
7906 HAL_HRTIM_ErrorCallback(hrtim);
7907 }
7908
7909 /**
7910 * @brief DMA callback invoked upon burst DMA transfer completion
7911 * @param hdma: pointer to DMA handle.
7912 * @retval None
7913 */
7914 static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma)
7915 {
7916 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
7917
7918 HAL_HRTIM_BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hdma));
7919 }
7920
7921 /**
7922 * @}
7923 */
7924
7925 /**
7926 * @}
7927 */
7928 #endif /* STM32F334x8 */
7929
7930 #endif /* HAL_HRTIM_MODULE_ENABLED */
7931
7932 /**
7933 * @}
7934 */
7935
7936 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
7937
7938
7939
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