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[tmk_keyboard.git] / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_STM / TARGET_STM32F3 / stm32f3xx_hal_hrtim.h
1 /**
2 ******************************************************************************
3 * @file stm32f3xx_hal_hrtim.h
4 * @author MCD Application Team
5 * @version V1.1.0
6 * @date 12-Sept-2014
7 * @brief Header file of HRTIM HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F3xx_HAL_HRTIM_H
40 #define __STM32F3xx_HAL_HRTIM_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 #if defined(STM32F334x8)
47
48 /* Includes ------------------------------------------------------------------*/
49 #include "stm32f3xx_hal_def.h"
50
51 /** @addtogroup STM32F3xx_HAL_Driver
52 * @{
53 */
54
55 /** @addtogroup HRTIM HRTIM HAL module driver
56 * @{
57 */
58
59 /* Exported types ------------------------------------------------------------*/
60 /** @addtogroup HRTIM_Exported_Constants HRTIM Exported Constants
61 * @{
62 */
63 /** @defgroup HRTIM_Max_Timer HRTIM Max Timer
64 * @{
65 */
66 #define MAX_HRTIM_TIMER 6
67 /**
68 * @}
69 */
70 /**
71 * @}
72 */
73
74 /** @defgroup HRTIM_Exported_Types HRTIM Exported Types
75 * @{
76 */
77
78 /**
79 * @brief HRTIM Configuration Structure definition - Time base related parameters
80 */
81 typedef struct
82 {
83 uint32_t HRTIMInterruptResquests; /*!< Specifies which interrupts requests must enabled for the HRTIM instance
84 This parameter can be any combination of @ref HRTIM_Common_Interrupt_Enable */
85 uint32_t SyncOptions; /*!< Specifies how the HRTIM instance handles the external synchronization signals
86 This parameter can be a combination of @ref HRTIM_Synchronization_Options */
87 uint32_t SyncInputSource; /*!< Specifies the external synchronization input source
88 This parameter can be a value of @ref HRTIM_Synchronization_Input_Source */
89 uint32_t SyncOutputSource; /*!< Specifies the source and event to be sent on the external synchronization outputs
90 This parameter can be a value of @ref HRTIM_Synchronization_Output_Source */
91 uint32_t SyncOutputPolarity; /*!< Specifies the conditionning of the event to be sent on the external synchronization outputs
92 This parameter can be a value of @ref HRTIM_Synchronization_Output_Polarity */
93 } HRTIM_InitTypeDef;
94
95 /**
96 * @brief HAL State structures definition
97 */
98 typedef enum
99 {
100 HAL_HRTIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
101 HAL_HRTIM_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
102 HAL_HRTIM_STATE_TIMEOUT = 0x06, /*!< Timeout state */
103 HAL_HRTIM_STATE_ERROR = 0x07, /*!< Error state */
104 } HAL_HRTIM_StateTypeDef;
105
106 /**
107 * @brief HRTIM Timer Structure definition
108 */
109 typedef struct
110 {
111 uint32_t CaptureTrigger1; /*!< Event(s) triggering capture unit 1 */
112 uint32_t CaptureTrigger2; /*!< Event(s) triggering capture unit 2 */
113 uint32_t InterruptRequests; /*!< Interrupts requests enabled for the timer */
114 uint32_t DMARequests; /*!< DMA requests enabled for the timer */
115 uint32_t DMASrcAddress; /*!< Address of the source address of the DMA transfer */
116 uint32_t DMADstAddress; /*!< Address of the destination address of the DMA transfer */
117 uint32_t DMASize; /*!< Ssize of the DMA transfer */
118 } HRTIM_TimerParamTypeDef;
119
120 /**
121 * @brief HRTIM Handle Structure definition
122 */
123 typedef struct __HRTIM_HandleTypeDef
124 {
125 HRTIM_TypeDef * Instance; /*!< Register base address */
126
127 HRTIM_InitTypeDef Init; /*!< HRTIM required parameters */
128
129 HRTIM_TimerParamTypeDef TimerParam[MAX_HRTIM_TIMER]; /*!< HRTIM timers - including the master - parameters */
130
131 HAL_LockTypeDef Lock; /*!< Locking object */
132
133 __IO HAL_HRTIM_StateTypeDef State; /*!< HRTIM communication state */
134
135 DMA_HandleTypeDef * hdmaMaster; /*!< Master timer DMA handle parameters */
136 DMA_HandleTypeDef * hdmaTimerA; /*!< Timer A DMA handle parameters */
137 DMA_HandleTypeDef * hdmaTimerB; /*!< Timer B DMA handle parameters */
138 DMA_HandleTypeDef * hdmaTimerC; /*!< Timer C DMA handle parameters */
139 DMA_HandleTypeDef * hdmaTimerD; /*!< Timer D DMA handle parameters */
140 DMA_HandleTypeDef * hdmaTimerE; /*!< Timer E DMA handle parameters */
141 } HRTIM_HandleTypeDef;
142
143 /**
144 * @brief Simple output compare mode configuration definition
145 */
146 typedef struct {
147 uint32_t Period; /*!< Specifies the timer period
148 The period value must be above 3 periods of the fHRTIM clock.
149 Maximum value is = 0xFFDF */
150 uint32_t RepetitionCounter; /*!< Specifies the timer repetition period
151 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
152 uint32_t PrescalerRatio; /*!< Specifies the timer clock prescaler ratio.
153 This parameter can be any value of @ref HRTIM_Prescaler_Ratio */
154 uint32_t Mode; /*!< Specifies the counter operating mode
155 This parameter can be any value of @ref HRTIM_Mode */
156 } HRTIM_TimeBaseCfgTypeDef;
157
158 /**
159 * @brief Simple output compare mode configuration definition
160 */
161 typedef struct {
162 uint32_t Mode; /*!< Specifies the output compare mode (toggle, active, inactive)
163 This parameter can be any value of of @ref HRTIM_Simple_OC_Mode */
164 uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
165 The compare value must be above or equal to 3 periods of the fHRTIM clock */
166 uint32_t Polarity; /*!< Specifies the output polarity
167 This parameter can be any value of @ref HRTIM_Output_Polarity */
168 uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state
169 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
170 } HRTIM_SimpleOCChannelCfgTypeDef;
171
172 /**
173 * @brief Simple PWM output mode configuration definition
174 */
175 typedef struct {
176 uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
177 The compare value must be above or equal to 3 periods of the fHRTIM clock */
178 uint32_t Polarity; /*!< Specifies the output polarity
179 This parameter can be any value of @ref HRTIM_Output_Polarity */
180 uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state
181 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
182 } HRTIM_SimplePWMChannelCfgTypeDef;
183
184 /**
185 * @brief Simple capture mode configuration definition
186 */
187 typedef struct {
188 uint32_t Event; /*!< Specifies the external event triggering the capture
189 This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
190 uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity)
191 This parameter can be a value of @ref HRTIM_External_Event_Polarity */
192 uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event
193 This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
194 uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter
195 This parameter can be a value of @ref HRTIM_External_Event_Filter */
196 } HRTIM_SimpleCaptureChannelCfgTypeDef;
197
198 /**
199 * @brief Simple One Pulse mode configuration definition
200 */
201 typedef struct {
202 uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
203 The compare value must be above or equal to 3 periods of the fHRTIM clock */
204 uint32_t OutputPolarity; /*!< Specifies the output polarity
205 This parameter can be any value of @ref HRTIM_Output_Polarity */
206 uint32_t OutputIdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state
207 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
208 uint32_t Event; /*!< Specifies the external event triggering the pulse generation
209 This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
210 uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity)
211 This parameter can be a value of @ref HRTIM_External_Event_Polarity */
212 uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event
213 This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
214 uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter
215 This parameter can be a value of @ref HRTIM_External_Event_Filter */
216 } HRTIM_SimpleOnePulseChannelCfgTypeDef;
217
218 /**
219 * @brief Timer configuration definition
220 */
221 typedef struct {
222 uint32_t InterruptRequests; /*!< Relevant for all HRTIM timers, including the master
223 Specifies which interrupts requests must enabled for the timer
224 This parameter can be any combination of @ref HRTIM_Master_Interrupt_Enable
225 or HRTIM_Timing_Unit_Interrupt_Enable */
226 uint32_t DMARequests; /*!< Relevant for all HRTIM timers, including the master
227 Specifies which DMA requests must be enabled for the timer
228 This parameter can be any combination of @ref HRTIM_Master_DMA_Request_Enable
229 or HRTIM_Timing_Unit_DMA_Request_Enable */
230 uint32_t DMASrcAddress; /*!< Relevant for all HRTIM timers, including the master
231 Specifies the address of the source address of the DMA transfer */
232 uint32_t DMADstAddress; /*!< Relevant for all HRTIM timers, including the master
233 Specifies the address of the destination address of the DMA transfer */
234 uint32_t DMASize; /*!< Relevant for all HRTIM timers, including the master
235 Specifies the size of the DMA transfer */
236 uint32_t HalfModeEnable; /*!< Relevant for all HRTIM timers, including the master
237 Specifies whether or not hald mode is enabled
238 This parameter can be any value of @ref HRTIM_Half_Mode_Enable */
239 uint32_t StartOnSync; /*!< Relevant for all HRTIM timers, including the master
240 Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled)
241 This parameter can be any value of @ref HRTIM_Start_On_Sync_Input_Event */
242 uint32_t ResetOnSync; /*!< Relevant for all HRTIM timers, including the master
243 Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled)
244 This parameter can be any value of @ref HRTIM_Reset_On_Sync_Input_Event */
245 uint32_t DACSynchro; /*!< Relevant for all HRTIM timers, including the master
246 Indicates whether or not the a DAC synchronization event is generated
247 This parameter can be any value of @ref HRTIM_DAC_Synchronization */
248 uint32_t PreloadEnable; /*!< Relevant for all HRTIM timers, including the master
249 Specifies whether or not register preload is enabled
250 This parameter can be any value of @ref HRTIM_Register_Preload_Enable */
251 uint32_t UpdateGating; /*!< Relevant for all HRTIM timers, including the master
252 Specifies how the update occurs with respect to a burst DMA transaction or
253 update enable inputs (Slave timers only)
254 This parameter can be any value of @ref HRTIM_Update_Gating */
255 uint32_t BurstMode; /*!< Relevant for all HRTIM timers, including the master
256 Specifies how the timer behaves during a burst mode operation
257 This parameter can be any value of @ref HRTIM_Timer_Burst_Mode */
258 uint32_t RepetitionUpdate; /*!< Relevant for all HRTIM timers, including the master
259 Specifies whether or not registers update is triggered by the repetition event
260 This parameter can be any valuen of @ref HRTIM_Timer_Repetition_Update */
261 uint32_t PushPull; /*!< Relevant for Timer A to Timer E
262 Specifies whether or not the push-pull mode is enabled
263 This parameter can be any value of @ref HRTIM_Timer_Push_Pull_Mode */
264 uint32_t FaultEnable; /*!< Relevant for Timer A to Timer E
265 Specifies which fault channels are enabled for the timer
266 This parameter can be a combination of @ref HRTIM_Timer_Fault_Enabling */
267 uint32_t FaultLock; /*!< Relevant for Timer A to Timer E
268 Specifies whether or not fault enabling status is write protected
269 This parameter can be a value of @ref HRTIM_Timer_Fault_Lock */
270 uint32_t DeadTimeInsertion; /*!< Relevant for Timer A to Timer E
271 Specifies whether or not deadtime insertion is enabled for the timer
272 This parameter can be a value of @ref HRTIM_Timer_Deadtime_Insertion */
273 uint32_t DelayedProtectionMode; /*!< Relevant for Timer A to Timer E
274 Specifies the delayed protection mode
275 This parameter can be a value of @ref HRTIM_Timer_Delayed_Protection_Mode */
276 uint32_t UpdateTrigger; /*!< Relevant for Timer A to Timer E
277 Specifies source(s) triggering the timer registers update
278 This parameter can be a combination of @ref HRTIM_Timer_Update_Trigger */
279 uint32_t ResetTrigger; /*!< Relevant for Timer A to Timer E
280 Specifies source(s) triggering the timer counter reset
281 This parameter can be a combination of @ref HRTIM_Timer_Reset_Trigger */
282 uint32_t ResetUpdate; /*!< Relevant for Timer A to Timer E
283 Specifies whether or not registers update is triggered when the timer counter is reset
284 This parameter can be a value of @ref HRTIM_Timer_Reset_Update */
285 } HRTIM_TimerCfgTypeDef;
286
287 /**
288 * @brief Compare unit configuration definition
289 */
290 typedef struct {
291 uint32_t CompareValue; /*!< Specifies the compare value of the timer compare unit
292 the minimum value must be greater than or equal to 3 periods of the fHRTIM clock
293 the maximum value must be less than or equal to 0xFFFF - 1 periods of the fHRTIM clock */
294 uint32_t AutoDelayedMode; /*!< Specifies the auto delayed mode for compare unit 2 or 4
295 This parameter can be a value of @ref HRTIM_Compare_Unit_Auto_Delayed_Mode */
296 uint32_t AutoDelayedTimeout; /*!< Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected
297 CompareValue + AutoDelayedTimeout must be less than 0xFFFF */
298 } HRTIM_CompareCfgTypeDef;
299
300 /**
301 * @brief Capture unit configuration definition
302 */
303 typedef struct {
304 uint32_t Trigger; /*!< Specifies source(s) triggering the capture
305 This parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger */
306 } HRTIM_CaptureCfgTypeDef;
307
308 /**
309 * @brief Output configuration definition
310 */
311 typedef struct {
312 uint32_t Polarity; /*!< Specifies the output polarity
313 This parameter can be any value of @ref HRTIM_Output_Polarity */
314 uint32_t SetSource; /*!< Specifies the event(s) transitioning the output from its inactive level to its active level
315 This parameter can be a combination of @ref HRTIM_Output_Set_Source */
316 uint32_t ResetSource; /*!< Specifies the event(s) transitioning the output from its active level to its inactive level
317 This parameter can be a combination of @ref HRTIM_Output_Reset_Source */
318 uint32_t IdleMode; /*!< Specifies whether or not the output is affected by a burst mode operation
319 This parameter can be any value of @ref HRTIM_Output_Idle_Mode */
320 uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state
321 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
322 uint32_t FaultLevel; /*!< Specifies whether the output level is active or inactive when in FAULT state
323 This parameter can be any value of @ref HRTIM_Output_FAULT_Level */
324 uint32_t ChopperModeEnable; /*!< Indicates whether or not the chopper mode is enabled
325 This parameter can be any value of @ref HRTIM_Output_Chopper_Mode_Enable */
326 uint32_t BurstModeEntryDelayed; /* !<Indicates whether or not deadtime is inserted when entering the IDLE state
327 during a burst mode operation
328 This parameters can be any value of @ref HRTIM_Output_Burst_Mode_Entry_Delayed */
329 } HRTIM_OutputCfgTypeDef;
330
331 /**
332 * @brief External event filtering in timing units configuration definition
333 */
334 typedef struct {
335 uint32_t Filter; /*!< Specifies the type of event filtering within the timing unit
336 This parameter can be a value of @ref HRTIM_Timer_External_Event_Filter */
337 uint32_t Latch; /*!< Specifies whether or not the signal is latched
338 This parameter can be a value of @ref HRTIM_Timer_External_Event_Latch */
339 } HRTIM_TimerEventFilteringCfgTypeDef;
340
341 /**
342 * @brief Dead time feature configuration definition
343 */
344 typedef struct {
345 uint32_t Prescaler; /*!< Specifies the Deadtime Prescaler
346 This parameter can be a value of @ref HRTIM_Deadtime_Prescaler_Ratio */
347 uint32_t RisingValue; /*!< Specifies the Deadtime following a rising edge
348 This parameter can be a number between 0x0 and 0x1FF */
349 uint32_t RisingSign; /*!< Specifies whether the deadtime is positive or negative on rising edge
350 This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign */
351 uint32_t RisingLock; /*!< Specifies whether or not deadtime rising settings (value and sign) are write protected
352 This parameter can be a value of @ref HRTIM_Deadtime_Rising_Lock */
353 uint32_t RisingSignLock; /*!< Specifies whether or not deadtime rising sign is write protected
354 This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign_Lock */
355 uint32_t FallingValue; /*!< Specifies the Deadtime following a falling edge
356 This parameter can be a number between 0x0 and 0x1FF */
357 uint32_t FallingSign; /*!< Specifies whether the deadtime is positive or negative on falling edge
358 This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign */
359 uint32_t FallingLock; /*!< Specifies whether or not deadtime falling settings (value and sign) are write protected
360 This parameter can be a value of @ref HRTIM_Deadtime_Falling_Lock */
361 uint32_t FallingSignLock; /*!< Specifies whether or not deadtime falling sign is write protected
362 This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign_Lock */
363 } HRTIM_DeadTimeCfgTypeDef ;
364
365 /**
366 * @brief Chopper mode configuration definition
367 */
368 typedef struct {
369 uint32_t CarrierFreq; /*!< Specifies the Timer carrier frequency value.
370 This parameter can be a value of @ref HRTIM_Chopper_Frequency */
371 uint32_t DutyCycle; /*!< Specifies the Timer chopper duty cycle value.
372 This parameter can be a value of @ref HRTIM_Chopper_Duty_Cycle */
373 uint32_t StartPulse; /*!< Specifies the Timer pulse width value.
374 This parameter can be a value of @ref HRTIM_Chopper_Start_Pulse_Width */
375 } HRTIM_ChopperModeCfgTypeDef;
376
377 /**
378 * @brief External event channel configuration definition
379 */
380 typedef struct {
381 uint32_t Source; /*!< Identifies the source of the external event
382 This parameter can be a value of @ref HRTIM_External_Event_Sources */
383 uint32_t Polarity; /*!< Specifies the polarity of the external event (in case of level sensitivity)
384 This parameter can be a value of @ref HRTIM_External_Event_Polarity */
385 uint32_t Sensitivity; /*!< Specifies the sensitivity of the external event
386 This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
387 uint32_t Filter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter
388 This parameter can be a value of @ref HRTIM_External_Event_Filter */
389 uint32_t FastMode; /*!< Indicates whether or not low latency mode is enabled for the external event
390 This parameter can be a value of @ref HRTIM_External_Event_Fast_Mode */
391 } HRTIM_EventCfgTypeDef;
392
393 /**
394 * @brief Fault channel configuration definition
395 */
396 typedef struct {
397 uint32_t Source; /*!< Identifies the source of the fault
398 This parameter can be a value of @ref HRTIM_Fault_Sources */
399 uint32_t Polarity; /*!< Specifies the polarity of the fault event
400 This parameter can be a value of @ref HRTIM_Fault_Polarity */
401 uint32_t Filter; /*!< Defines the frequency used to sample the Fault input and the length of the digital filter
402 This parameter can be a value of @ref HRTIM_Fault_Filter */
403 uint32_t Lock; /*!< Indicates whether or not fault programming bits are write protected
404 This parameter can be a value of @ref HRTIM_Fault_Lock */
405 } HRTIM_FaultCfgTypeDef;
406
407 /**
408 * @brief Burst mode configuration definition
409 */
410 typedef struct {
411 uint32_t Mode; /*!< Specifies the burst mode operating mode
412 This parameter can be a value of @ref HRTIM_Burst_Mode_Operating_Mode */
413 uint32_t ClockSource; /*!< Specifies the burst mode clock source
414 This parameter can be a value of @ref HRTIM_Burst_Mode_Clock_Source */
415 uint32_t Prescaler; /*!< Specifies the burst mode prescaler
416 This parameter can be a value of @ref HRTIM_Burst_Mode_Prescaler */
417 uint32_t PreloadEnable; /*!< Specifies whether or not preload is enabled for burst mode related registers (HRTIM_BMCMPR and HRTIM_BMPER)
418 This parameter can be a combination of @ref HRTIM_Burst_Mode_Register_Preload_Enable */
419 uint32_t Trigger; /*!< Specifies the event(s) trigering the burst operation
420 This parameter can be a combination of @ref HRTIM_Burst_Mode_Trigger */
421 uint32_t IdleDuration; /*!< Specifies number of periods during which the selected timers are in idle state
422 This parameter can be a number between 0x0 and 0xFFFF */
423 uint32_t Period; /*!< Specifies burst mode repetition period
424 This parameter can be a number between 0x1 and 0xFFFF */
425 } HRTIM_BurstModeCfgTypeDef;
426
427 /**
428 * @brief ADC trigger configuration definition
429 */
430 typedef struct {
431 uint32_t UpdateSource; /*!< Specifies the ADC trigger update source
432 This parameter can be a combination of @ref HRTIM_ADC_Trigger_Update_Source */
433 uint32_t Trigger; /*!< Specifies the event(s) triggering the ADC conversion
434 This parameter can be a value of @ref HRTIM_ADC_Trigger_Event */
435 } HRTIM_ADCTriggerCfgTypeDef;
436
437 /**
438 * @}
439 */
440
441 /* Exported constants --------------------------------------------------------*/
442 /** @defgroup HRTIM_Exported_Constants HRTIM Exported Constants
443 * @{
444 */
445
446 /** @defgroup HRTIM_Timer_Index HRTIM Timer Index
447 * @{
448 * @brief Constants defining the timer indexes
449 */
450 #define HRTIM_TIMERINDEX_TIMER_A (uint32_t)0x0 /*!< Index used to access timer A registers */
451 #define HRTIM_TIMERINDEX_TIMER_B (uint32_t)0x1 /*!< Index used to access timer B registers */
452 #define HRTIM_TIMERINDEX_TIMER_C (uint32_t)0x2 /*!< Index used to access timer C registers */
453 #define HRTIM_TIMERINDEX_TIMER_D (uint32_t)0x3 /*!< Index used to access timer D registers */
454 #define HRTIM_TIMERINDEX_TIMER_E (uint32_t)0x4 /*!< Index used to access timer E registers */
455 #define HRTIM_TIMERINDEX_MASTER (uint32_t)0x5 /*!< Index used to access master registers */
456 #define HRTIM_TIMERINDEX_COMMON (uint32_t)0xFF /*!< Index used to access HRTIM common registers */
457
458 #define IS_HRTIM_TIMERINDEX(TIMERINDEX)\
459 (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) || \
460 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \
461 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \
462 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \
463 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \
464 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
465
466 #define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\
467 (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \
468 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \
469 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \
470 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \
471 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
472 /**
473 * @}
474 */
475
476 /** @defgroup HRTIM_Timer_identifier HRTIM Timer identifier
477 * @{
478 * @brief Constants defining timer identifiers
479 */
480 #define HRTIM_TIMERID_MASTER (HRTIM_MCR_MCEN) /*!< Master identifier*/
481 #define HRTIM_TIMERID_TIMER_A (HRTIM_MCR_TACEN) /*!< Timer A identifier */
482 #define HRTIM_TIMERID_TIMER_B (HRTIM_MCR_TBCEN) /*!< Timer B identifier */
483 #define HRTIM_TIMERID_TIMER_C (HRTIM_MCR_TCCEN) /*!< Timer C identifier */
484 #define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN) /*!< Timer D identifier */
485 #define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN) /*!< Timer E identifier */
486
487 #define IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFFC0FFFF) == 0x00000000)
488
489 /**
490 * @}
491 */
492
493 /** @defgroup HRTIM_Compare_Unit HRTIM Compare Unit
494 * @{
495 * @brief Constants defining compare unit identifiers
496 */
497 #define HRTIM_COMPAREUNIT_1 (uint32_t)0x00000001 /*!< Compare unit 1 identifier */
498 #define HRTIM_COMPAREUNIT_2 (uint32_t)0x00000002 /*!< Compare unit 2 identifier */
499 #define HRTIM_COMPAREUNIT_3 (uint32_t)0x00000004 /*!< Compare unit 3 identifier */
500 #define HRTIM_COMPAREUNIT_4 (uint32_t)0x00000008 /*!< Compare unit 4 identifier */
501
502 #define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\
503 (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) || \
504 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) || \
505 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) || \
506 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4))
507 /**
508 * @}
509 */
510
511 /** @defgroup HRTIM_Capture_Unit HRTIM Capture Unit
512 * @{
513 * @brief Constants defining capture unit identifiers
514 */
515 #define HRTIM_CAPTUREUNIT_1 (uint32_t)0x00000001 /*!< Capture unit 1 identifier */
516 #define HRTIM_CAPTUREUNIT_2 (uint32_t)0x00000002 /*!< Capture unit 2 identifier */
517
518 #define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\
519 (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) || \
520 ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2))
521 /**
522 * @}
523 */
524
525 /** @defgroup HRTIM_Timer_Output HRTIM Timer Output
526 * @{
527 * @brief Constants defining timer output identifiers
528 */
529 #define HRTIM_OUTPUT_TA1 (uint32_t)0x00000001 /*!< Timer A - Ouput 1 identifier */
530 #define HRTIM_OUTPUT_TA2 (uint32_t)0x00000002 /*!< Timer A - Ouput 2 identifier */
531 #define HRTIM_OUTPUT_TB1 (uint32_t)0x00000004 /*!< Timer B - Ouput 1 identifier */
532 #define HRTIM_OUTPUT_TB2 (uint32_t)0x00000008 /*!< Timer B - Ouput 2 identifier */
533 #define HRTIM_OUTPUT_TC1 (uint32_t)0x00000010 /*!< Timer C - Ouput 1 identifier */
534 #define HRTIM_OUTPUT_TC2 (uint32_t)0x00000020 /*!< Timer C - Ouput 2 identifier */
535 #define HRTIM_OUTPUT_TD1 (uint32_t)0x00000040 /*!< Timer D - Ouput 1 identifier */
536 #define HRTIM_OUTPUT_TD2 (uint32_t)0x00000080 /*!< Timer D - Ouput 2 identifier */
537 #define HRTIM_OUTPUT_TE1 (uint32_t)0x00000100 /*!< Timer E - Ouput 1 identifier */
538 #define HRTIM_OUTPUT_TE2 (uint32_t)0x00000200 /*!< Timer E - Ouput 2 identifier */
539
540 #define IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFFC00) == 0x00000000)
541
542 #define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\
543 ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
544 (((OUTPUT) == HRTIM_OUTPUT_TA1) || \
545 ((OUTPUT) == HRTIM_OUTPUT_TA2))) \
546 || \
547 (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
548 (((OUTPUT) == HRTIM_OUTPUT_TB1) || \
549 ((OUTPUT) == HRTIM_OUTPUT_TB2))) \
550 || \
551 (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
552 (((OUTPUT) == HRTIM_OUTPUT_TC1) || \
553 ((OUTPUT) == HRTIM_OUTPUT_TC2))) \
554 || \
555 (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
556 (((OUTPUT) == HRTIM_OUTPUT_TD1) || \
557 ((OUTPUT) == HRTIM_OUTPUT_TD2))) \
558 || \
559 (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
560 (((OUTPUT) == HRTIM_OUTPUT_TE1) || \
561 ((OUTPUT) == HRTIM_OUTPUT_TE2))))
562 /**
563 * @}
564 */
565
566 /** @defgroup HRTIM_ADC_Trigger HRTIM ADC Trigger
567 * @{
568 * @brief Constants defining ADC triggers identifiers
569 */
570 #define HRTIM_ADCTRIGGER_1 (uint32_t)0x00000001 /*!< ADC trigger 1 identifier */
571 #define HRTIM_ADCTRIGGER_2 (uint32_t)0x00000002 /*!< ADC trigger 2 identifier */
572 #define HRTIM_ADCTRIGGER_3 (uint32_t)0x00000004 /*!< ADC trigger 3 identifier */
573 #define HRTIM_ADCTRIGGER_4 (uint32_t)0x00000008 /*!< ADC trigger 4 identifier */
574
575 #define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\
576 (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \
577 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) || \
578 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) || \
579 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4))
580 /**
581 * @}
582 */
583
584 /** @defgroup HRTIM_External_Event_Channels HRTIM External Event Channels
585 * @{
586 * @brief Constants defining external event channel identifiers
587 */
588 #define HRTIM_EVENT_NONE ((uint32_t)0x00000000) /*!< Undefined event channel */
589 #define HRTIM_EVENT_1 ((uint32_t)0x00000001) /*!< External event channel 1 identifier */
590 #define HRTIM_EVENT_2 ((uint32_t)0x00000002) /*!< External event channel 2 identifier */
591 #define HRTIM_EVENT_3 ((uint32_t)0x00000004) /*!< External event channel 3 identifier */
592 #define HRTIM_EVENT_4 ((uint32_t)0x00000008) /*!< External event channel 4 identifier */
593 #define HRTIM_EVENT_5 ((uint32_t)0x00000010) /*!< External event channel 5 identifier */
594 #define HRTIM_EVENT_6 ((uint32_t)0x00000020) /*!< External event channel 6 identifier */
595 #define HRTIM_EVENT_7 ((uint32_t)0x00000040) /*!< External event channel 7 identifier */
596 #define HRTIM_EVENT_8 ((uint32_t)0x00000080) /*!< External event channel 8 identifier */
597 #define HRTIM_EVENT_9 ((uint32_t)0x00000100) /*!< External event channel 9 identifier */
598 #define HRTIM_EVENT_10 ((uint32_t)0x00000200) /*!< External event channel 10 identifier */
599
600 #define IS_HRTIM_EVENT(EVENT)\
601 (((EVENT) == HRTIM_EVENT_1) || \
602 ((EVENT) == HRTIM_EVENT_2) || \
603 ((EVENT) == HRTIM_EVENT_3) || \
604 ((EVENT) == HRTIM_EVENT_4) || \
605 ((EVENT) == HRTIM_EVENT_5) || \
606 ((EVENT) == HRTIM_EVENT_6) || \
607 ((EVENT) == HRTIM_EVENT_7) || \
608 ((EVENT) == HRTIM_EVENT_8) || \
609 ((EVENT) == HRTIM_EVENT_9) || \
610 ((EVENT) == HRTIM_EVENT_10))
611 /**
612 * @}
613 */
614
615 /** @defgroup HRTIM_Fault_Channel HRTIM Fault Channel
616 * @{
617 * @brief Constants defining fault channel identifiers
618 */
619 #define HRTIM_FAULT_1 ((uint32_t)0x01) /*!< Fault channel 1 identifier */
620 #define HRTIM_FAULT_2 ((uint32_t)0x02) /*!< Fault channel 2 identifier */
621 #define HRTIM_FAULT_3 ((uint32_t)0x04) /*!< Fault channel 3 identifier */
622 #define HRTIM_FAULT_4 ((uint32_t)0x08) /*!< Fault channel 4 identifier */
623 #define HRTIM_FAULT_5 ((uint32_t)0x10) /*!< Fault channel 5 identifier */
624
625 #define IS_HRTIM_FAULT(FAULT)\
626 (((FAULT) == HRTIM_FAULT_1) || \
627 ((FAULT) == HRTIM_FAULT_2) || \
628 ((FAULT) == HRTIM_FAULT_3) || \
629 ((FAULT) == HRTIM_FAULT_4) || \
630 ((FAULT) == HRTIM_FAULT_5))
631 /**
632 * @}
633 */
634
635
636 /** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio
637 * @{
638 * @brief Constants defining timer high-resolution clock prescaler ratio.
639 */
640 #define HRTIM_PRESCALERRATIO_MUL32 ((uint32_t)0x00000000) /*!< fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */
641 #define HRTIM_PRESCALERRATIO_MUL16 ((uint32_t)0x00000001) /*!< fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */
642 #define HRTIM_PRESCALERRATIO_MUL8 ((uint32_t)0x00000002) /*!< fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */
643 #define HRTIM_PRESCALERRATIO_MUL4 ((uint32_t)0x00000003) /*!< fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */
644 #define HRTIM_PRESCALERRATIO_MUL2 ((uint32_t)0x00000004) /*!< fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */
645 #define HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005) /*!< fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */
646 #define HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006) /*!< fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */
647 #define HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007) /*!< fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */
648
649 #define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\
650 (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) || \
651 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) || \
652 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8) || \
653 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4) || \
654 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2) || \
655 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \
656 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \
657 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4))
658 /**
659 * @}
660 */
661
662 /** @defgroup HRTIM_Mode HRTIM Mode
663 * @{
664 * @brief Constants defining timer counter operating mode.
665 */
666 #define HRTIM_MODE_CONTINUOUS ((uint32_t)0x00000008) /*!< The timer operates in continuous (free-running) mode */
667 #define HRTIM_MODE_SINGLESHOT ((uint32_t)0x00000000) /*!< The timer operates in non retriggerable single-shot mode */
668 #define HRTIM_MODE_SINGLESHOT_RETRIGGERABLE ((uint32_t)0x00000010) /*!< The timer operates in retriggerable single-shot mode */
669
670 #define IS_HRTIM_MODE(MODE)\
671 (((MODE) == HRTIM_MODE_CONTINUOUS) || \
672 ((MODE) == HRTIM_MODE_SINGLESHOT) || \
673 ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
674
675 #define IS_HRTIM_MODE_ONEPULSE(MODE)\
676 (((MODE) == HRTIM_MODE_SINGLESHOT) || \
677 ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
678
679 /**
680 * @}
681 */
682
683 /** @defgroup HRTIM_Half_Mode_Enable HRTIM Half Mode Enable
684 * @{
685 * @brief Constants defining half mode enabling status.
686 */
687 #define HRTIM_HALFMODE_DISABLED ((uint32_t)0x00000000) /*!< Half mode is disabled */
688 #define HRTIM_HALFMODE_ENABLED ((uint32_t)0x00000020) /*!< Half mode is enabled */
689
690 #define IS_HRTIM_HALFMODE(HALFMODE)\
691 (((HALFMODE) == HRTIM_HALFMODE_DISABLED) || \
692 ((HALFMODE) == HRTIM_HALFMODE_ENABLED))
693 /**
694 * @}
695 */
696
697 /** @defgroup HRTIM_Start_On_Sync_Input_Event HRTIM Start On Sync Input Event
698 * @{
699 * @brief Constants defining the timer behavior following the synchronization event
700 */
701 #define HRTIM_SYNCSTART_DISABLED ((uint32_t)0x00000000) /*!< Synchronization input event has effect on the timer */
702 #define HRTIM_SYNCSTART_ENABLED (HRTIM_MCR_SYNCSTRTM) /*!< Synchronization input event starts the timer */
703
704 #define IS_HRTIM_SYNCSTART(SYNCSTART)\
705 (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) || \
706 ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED))
707 /**
708 * @}
709 */
710
711 /** @defgroup HRTIM_Reset_On_Sync_Input_Event HRTIM Reset On Sync Input Event
712 * @{
713 * @brief Constants defining the timer behavior following the synchronization event
714 */
715 #define HRTIM_SYNCRESET_DISABLED ((uint32_t)0x00000000) /*!< Synchronization input event has effect on the timer */
716 #define HRTIM_SYNCRESET_ENABLED (HRTIM_MCR_SYNCRSTM) /*!< Synchronization input event resets the timer */
717
718 #define IS_HRTIM_SYNCRESET(SYNCRESET)\
719 (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) || \
720 ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED))
721 /**
722 * @}
723 */
724
725 /** @defgroup HRTIM_DAC_Synchronization HRTIM DAC Synchronization
726 * @{
727 * @brief Constants defining on which output the DAC synchronization event is sent
728 */
729 #define HRTIM_DACSYNC_NONE (uint32_t)0x00000000 /*!< No DAC synchronization event generated */
730 #define HRTIM_DACSYNC_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */
731 #define HRTIM_DACSYNC_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */
732 #define HRTIM_DACSYNC_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC update generated on DACTrigOut3 output upon timer update */
733
734 #define IS_HHRTIM_DACSYNC(DACSYNC)\
735 (((DACSYNC) == HRTIM_DACSYNC_NONE) || \
736 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) || \
737 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) || \
738 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3))
739 /**
740 * @}
741 */
742
743 /** @defgroup HRTIM_Register_Preload_Enable HRTIM Register Preload Enable
744 * @{
745 * @brief Constants defining whether a write access into a preloadable
746 * register is done into the active or the preload register.
747 */
748 #define HRTIM_PRELOAD_DISABLED ((uint32_t)0x00000000) /*!< Preload disabled: the write access is directly done into the active register */
749 #define HRTIM_PRELOAD_ENABLED (HRTIM_MCR_PREEN) /*!< Preload enabled: the write access is done into the preload register */
750
751 #define IS_HRTIM_PRELOAD(PRELOAD)\
752 (((PRELOAD) == HRTIM_PRELOAD_DISABLED) || \
753 ((PRELOAD) == HRTIM_PRELOAD_ENABLED))
754 /**
755 * @}
756 */
757
758 /** @defgroup HRTIM_Update_Gating HRTIM Update Gating
759 * @{
760 * @brief Constants defining how the update occurs relatively to the burst DMA
761 * transaction and the external update request on update enable inputs 1 to 3.
762 */
763 #define HRTIM_UPDATEGATING_INDEPENDENT (uint32_t)0x00000000 /*!< Update done independently from the DMA burst transfer completion */
764 #define HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /*!< Update done when the DMA burst transfer is completed */
765 #define HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /*!< Update done on timer roll-over following a DMA burst transfer completion*/
766 #define HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1 */
767 #define HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2 */
768 #define HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3 */
769 #define HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1 */
770 #define HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2 */
771 #define HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3 */
772
773 #define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\
774 (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \
775 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \
776 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE))
777
778 #define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\
779 (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \
780 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \
781 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) || \
782 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) || \
783 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) || \
784 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) || \
785 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) || \
786 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) || \
787 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE))
788 /**
789 * @}
790 */
791
792 /** @defgroup HRTIM_Timer_Burst_Mode HRTIM Timer Burst Mode
793 * @{
794 * @brief Constants defining how the timer behaves during a burst
795 mode operation.
796 */
797 #define HRTIM_TIMERBURSTMODE_MAINTAINCLOCK (uint32_t)0x000000 /*!< Timer counter clock is maintained and the timer operates normally */
798 #define HRTIM_TIMERBURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /*!< Timer counter clock is stopped and the counter is reset */
799
800 #define IS_HRTIM_TIMERBURSTMODE(TIMERBURSTMODE) \
801 (((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) || \
802 ((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER))
803 /**
804 * @}
805 */
806
807 /** @defgroup HRTIM_Timer_Repetition_Update HRTIM Timer Repetition Update
808 * @{
809 * @brief Constants defining whether registers are updated when the timer
810 * repetition period is completed (either due to roll-over or
811 * reset events)
812 */
813 #define HRTIM_UPDATEONREPETITION_DISABLED (uint32_t)0x00000000 /*!< Update on repetition disabled */
814 #define HRTIM_UPDATEONREPETITION_ENABLED (HRTIM_MCR_MREPU) /*!< Update on repetition enabled */
815
816 #define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION) \
817 (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) || \
818 ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED))
819 /**
820 * @}
821 */
822
823
824 /** @defgroup HRTIM_Timer_Push_Pull_Mode HRTIM Timer Push Pull Mode
825 * @{
826 * @brief Constants defining whether or not the puhs-pull mode is enabled for
827 * a timer.
828 */
829 #define HRTIM_TIMPUSHPULLMODE_DISABLED ((uint32_t)0x00000000) /*!< Push-Pull mode disabled */
830 #define HRTIM_TIMPUSHPULLMODE_ENABLED ((uint32_t)HRTIM_TIMCR_PSHPLL) /*!< Push-Pull mode enabled */
831
832 #define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\
833 (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \
834 ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED))
835 /**
836 * @}
837 */
838
839 /** @defgroup HRTIM_Timer_Fault_Enabling HRTIM Timer Fault Enabling
840 * @{
841 * @brief Constants defining whether a faut channel is enabled for a timer
842 */
843 #define HRTIM_TIMFAULTENABLE_NONE (uint32_t)0x00000000 /*!< No fault enabled */
844 #define HRTIM_TIMFAULTENABLE_FAULT1 (HRTIM_FLTR_FLT1EN) /*!< Fault 1 enabled */
845 #define HRTIM_TIMFAULTENABLE_FAULT2 (HRTIM_FLTR_FLT2EN) /*!< Fault 2 enabled */
846 #define HRTIM_TIMFAULTENABLE_FAULT3 (HRTIM_FLTR_FLT3EN) /*!< Fault 3 enabled */
847 #define HRTIM_TIMFAULTENABLE_FAULT4 (HRTIM_FLTR_FLT4EN) /*!< Fault 4 enabled */
848 #define HRTIM_TIMFAULTENABLE_FAULT5 (HRTIM_FLTR_FLT5EN) /*!< Fault 5 enabled */
849
850 #define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0) == 0x00000000)
851
852 /**
853 * @}
854 */
855
856 /** @defgroup HRTIM_Timer_Fault_Lock HRTIM Timer Fault Lock
857 * @{
858 * @brief Constants defining whether or not fault enabling bits are write
859 * protected for a timer
860 */
861 #define HRTIM_TIMFAULTLOCK_READWRITE ((uint32_t)0x00000000) /*!< Timer fault enabling bits are read/write */
862 #define HRTIM_TIMFAULTLOCK_READONLY (HRTIM_FLTR_FLTLCK) /*!< Timer fault enabling bits are read only */
863
864 #define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\
865 (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \
866 ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY))
867 /**
868 * @}
869 */
870
871 /** @defgroup HRTIM_Timer_Deadtime_Insertion HRTIM Timer Deadtime Insertion
872 * @{
873 * @brief Constants defining whether or not fault the dead time insertion
874 * feature is enabled for a timer
875 */
876 #define HRTIM_TIMDEADTIMEINSERTION_DISABLED ((uint32_t)0x00000000) /*!< Output 1 and output 2 signals are independent */
877 #define HRTIM_TIMDEADTIMEINSERTION_ENABLED HRTIM_OUTR_DTEN /*!< Deadtime is inserted between output 1 and output 2 */
878
879 #define IS_HRTIM_TIMDEADTIMEINSERTION(TIMPUSHPULLMODE, TIMDEADTIMEINSERTION)\
880 ((((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) && \
881 ((((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \
882 ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED)))) \
883 || \
884 (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \
885 ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED)))
886 /**
887 * @}
888 */
889
890 /** @defgroup HRTIM_Timer_Delayed_Protection_Mode HRTIM Timer Delayed Protection Mode
891 * @{
892 * @brief Constants defining all possible delayed protection modes
893 * for a timer. Also definethe source and outputs on which the delayed
894 * protection schemes are applied
895 */
896 #define HRTIM_TIMDELAYEDPROTECTION_DISABLED ((uint32_t)0x00000000) /*!< No action */
897 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 (HRTIM_OUTR_DLYPRTEN) /*!< Output 1 delayed Idle on external Event 6 or 8 */
898 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Output 2 delayed Idle on external Event 6 or 8 */
899 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Output 1 and output 2 delayed Idle on external Event 6 or 8 */
900 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Balanced Idle on external Event 6 or 8 */
901 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Output 1 delayed Idle on external Event 7 or 9 */
902 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Output 2 delayed Idle on external Event 7 or 9 */
903 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Output 1 and output2 delayed Idle on external Event 7 or 9 */
904 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Balanced Idle on external Event 7 or 9 */
905
906 #define IS_HRTIM_TIMDELAYEDPROTECTION(TIMPUSHPULLMODE, TIMDELAYEDPROTECTION)\
907 ((((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DISABLED) || \
908 ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68) || \
909 ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68) || \
910 ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68) || \
911 ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79) || \
912 ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79) || \
913 ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79)) \
914 || \
915 (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \
916 ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68) || \
917 ((TIMDELAYEDPROTECTION) == HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79)))
918 /**
919 * @}
920 */
921
922 /** @defgroup HRTIM_Timer_Update_Trigger HRTIM Timer Update Trigger
923 * @{
924 * @brief Constants defining whether the registers update is done synchronously
925 * with any other timer or master update
926 */
927 #define HRTIM_TIMUPDATETRIGGER_NONE (uint32_t)0x00000000 /*!< Register update is disabled */
928 #define HRTIM_TIMUPDATETRIGGER_MASTER (HRTIM_TIMCR_MSTU) /*!< Register update is triggered by the master timer update */
929 #define HRTIM_TIMUPDATETRIGGER_TIMER_A (HRTIM_TIMCR_TAU) /*!< Register update is triggered by the timer A update */
930 #define HRTIM_TIMUPDATETRIGGER_TIMER_B (HRTIM_TIMCR_TBU) /*!< Register update is triggered by the timer B update */
931 #define HRTIM_TIMUPDATETRIGGER_TIMER_C (HRTIM_TIMCR_TCU) /*!< Register update is triggered by the timer C update*/
932 #define HRTIM_TIMUPDATETRIGGER_TIMER_D (HRTIM_TIMCR_TDU) /*!< Register update is triggered by the timer D update */
933 #define HRTIM_TIMUPDATETRIGGER_TIMER_E (HRTIM_TIMCR_TEU) /*!< Register update is triggered by the timer E update */
934
935 #define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFF) == 0x00000000)
936 /**
937 * @}
938 */
939
940 /** @defgroup HRTIM_Timer_Reset_Trigger HRTIM Timer Reset Trigger
941 * @{
942 * @brief Constants defining the events that can be selected to trigger the reset
943 * of the timer counter
944 */
945 #define HRTIM_TIMRESETTRIGGER_NONE (uint32_t)0x00000000 /*!< No counter reset trigger */
946 #define HRTIM_TIMRESETTRIGGER_UPDATE (HRTIM_RSTR_UPDATE) /*!< The timer counter is reset upon update event */
947 #define HRTIM_TIMRESETTRIGGER_CMP2 (HRTIM_RSTR_CMP2) /*!< The timer counter is reset upon Timer Compare 2 event */
948 #define HRTIM_TIMRESETTRIGGER_CMP4 (HRTIM_RSTR_CMP4) /*!< The timer counter is reset upon Timer Compare 4 event */
949 #define HRTIM_TIMRESETTRIGGER_MASTER_PER (HRTIM_RSTR_MSTPER) /*!< The timercounter is reset upon master timer period event */
950 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1) /*!< The timer counter is reset upon master timer Compare 1 event */
951 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2) /*!< The timer counter is reset upon master timer Compare 2 event */
952 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3) /*!< The timer counter is reset upon master timer Compare 3 event */
953 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4) /*!< The timer counter is reset upon master timer Compare 4 event */
954 #define HRTIM_TIMRESETTRIGGER_EEV_1 (HRTIM_RSTR_EXTEVNT1) /*!< The timer counter is reset upon external event 1 */
955 #define HRTIM_TIMRESETTRIGGER_EEV_2 (HRTIM_RSTR_EXTEVNT2) /*!< The timer counter is reset upon external event 2 */
956 #define HRTIM_TIMRESETTRIGGER_EEV_3 (HRTIM_RSTR_EXTEVNT3) /*!< The timer counter is reset upon external event 3 */
957 #define HRTIM_TIMRESETTRIGGER_EEV_4 (HRTIM_RSTR_EXTEVNT4) /*!< The timer counter is reset upon external event 4 */
958 #define HRTIM_TIMRESETTRIGGER_EEV_5 (HRTIM_RSTR_EXTEVNT5) /*!< The timer counter is reset upon external event 5 */
959 #define HRTIM_TIMRESETTRIGGER_EEV_6 (HRTIM_RSTR_EXTEVNT6) /*!< The timer counter is reset upon external event 6 */
960 #define HRTIM_TIMRESETTRIGGER_EEV_7 (HRTIM_RSTR_EXTEVNT7) /*!< The timer counter is reset upon external event 7 */
961 #define HRTIM_TIMRESETTRIGGER_EEV_8 (HRTIM_RSTR_EXTEVNT8) /*!< The timer counter is reset upon external event 8 */
962 #define HRTIM_TIMRESETTRIGGER_EEV_9 (HRTIM_RSTR_EXTEVNT9) /*!< The timer counter is reset upon external event 9 */
963 #define HRTIM_TIMRESETTRIGGER_EEV_10 (HRTIM_RSTR_EXTEVNT10) /*!< The timer counter is reset upon external event 10 */
964 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
965 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
966 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
967 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
968 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
969 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
970 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
971 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
972 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
973 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
974 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
975 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
976
977 #define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x800000001) == 0x00000000)
978
979 /**
980 * @}
981 */
982
983 /** @defgroup HRTIM_Timer_Reset_Update HRTIM Timer Reset Update
984 * @{
985 * @brief Constants defining whether the register are updated upon Timerx
986 * counter reset or roll-over to 0 after reaching the period value
987 * in continuous mode
988 */
989 #define HRTIM_TIMUPDATEONRESET_DISABLED (uint32_t)0x00000000 /*!< Update by timer x reset / roll-over disabled */
990 #define HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU) /*!< Update by timer x reset / roll-over enabled */
991
992 #define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET) \
993 (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \
994 ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED))
995 /**
996 * @}
997 */
998
999 /** @defgroup HRTIM_Compare_Unit_Auto_Delayed_Mode HRTIM Compare Unit Auto Delayed Mode
1000 * @{
1001 * @brief Constants defining whether the compare register is behaving in
1002 * regular mode (compare match issued as soon as counter equal compare),
1003 * or in auto-delayed mode
1004 */
1005 #define HRTIM_AUTODELAYEDMODE_REGULAR ((uint32_t)0x00000000) /*!< standard compare mode */
1006 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated only if a capture has occured */
1007 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1) /*!< Compare event generated if a capture has occured or after a Compare 1 match (timeout if capture event is missing) */
1008 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occured or after a Compare 3 match (timeout if capture event is missing) */
1009
1010 #define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\
1011 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
1012 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
1013 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
1014 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))
1015
1016 /* Auto delayed mode is only available for compare units 2 and 4 */
1017 #define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE) \
1018 ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \
1019 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
1020 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
1021 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
1022 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \
1023 || \
1024 (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \
1025 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
1026 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
1027 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
1028 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))))
1029 /**
1030 * @}
1031 */
1032
1033 /** @defgroup HRTIM_Simple_OC_Mode HRTIM Simple OC Mode
1034 * @{
1035 * @brief Constants defining the behavior of the output signal when the timer
1036 operates in basic output compare mode
1037 */
1038 #define HRTIM_BASICOCMODE_TOGGLE ((uint32_t)0x00000001) /*!< Ouput toggles when the timer counter reaches the compare value */
1039 #define HRTIM_BASICOCMODE_INACTIVE ((uint32_t)0x00000002) /*!< Ouput forced to active level when the timer counter reaches the compare value */
1040 #define HRTIM_BASICOCMODE_ACTIVE ((uint32_t)0x00000003) /*!< Ouput forced to inactive level when the timer counter reaches the compare value */
1041
1042 #define IS_HRTIM_BASICOCMODE(BASICOCMODE)\
1043 (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) || \
1044 ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \
1045 ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE))
1046 /**
1047 * @}
1048 */
1049
1050 /** @defgroup HRTIM_Output_Polarity HRTIM Output Polarity
1051 * @{
1052 * @brief Constants defining the polarity of a timer output
1053 */
1054 #define HRTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000) /*!< Output is acitve HIGH */
1055 #define HRTIM_OUTPUTPOLARITY_LOW (HRTIM_OUTR_POL1) /*!< Output is active LOW */
1056
1057 #define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\
1058 (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \
1059 ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW))
1060 /**
1061 * @}
1062 */
1063
1064 /** @defgroup HRTIM_Output_Set_Source HRTIM Output Set Source
1065 * @{
1066 * @brief Constants defining the events that can be selected to configure the
1067 * set crossbar of a timer output
1068 */
1069 #define HRTIM_OUTPUTSET_NONE (uint32_t)0x00000000 /*!< Reset the output set crossbar */
1070 #define HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its active state */
1071 #define HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces the output to its active state */
1072 #define HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces the output to its active state */
1073 #define HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces the output to its active state */
1074 #define HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces the output to its active state */
1075 #define HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces the output to its active state */
1076 #define HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces the output to its active state */
1077 #define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its active state */
1078 #define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its active state */
1079 #define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its active state */
1080 #define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its active state */
1081 #define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
1082 #define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
1083 #define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
1084 #define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
1085 #define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
1086 #define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
1087 #define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
1088 #define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
1089 #define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
1090 #define HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces the output to its active state */
1091 #define HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces the output to its active state */
1092 #define HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces the output to its active state */
1093 #define HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces the output to its active state */
1094 #define HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces the output to its active state */
1095 #define HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces the output to its active state */
1096 #define HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces the output to its active state */
1097 #define HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces the output to its active state */
1098 #define HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces the output to its active state */
1099 #define HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces the output to its active state */
1100 #define HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces the output to its active state */
1101
1102 #define IS_HRTIM_OUTPUTSET(OUTPUTSET)\
1103 (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \
1104 ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \
1105 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \
1106 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \
1107 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \
1108 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \
1109 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \
1110 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \
1111 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \
1112 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \
1113 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \
1114 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \
1115 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1) || \
1116 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2) || \
1117 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3) || \
1118 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4) || \
1119 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5) || \
1120 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6) || \
1121 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7) || \
1122 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8) || \
1123 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9) || \
1124 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \
1125 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \
1126 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \
1127 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \
1128 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \
1129 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \
1130 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \
1131 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \
1132 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \
1133 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \
1134 ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE))
1135 /**
1136 * @}
1137 */
1138
1139 /** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source
1140 * @{
1141 * @brief Constants defining the events that can be selected to configure the
1142 * set crossbar of a timer output
1143 */
1144 #define HRTIM_OUTPUTRESET_NONE (uint32_t)0x00000000 /*!< Reset the output reset crossbar */
1145 #define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
1146 #define HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /*!< Timer period event forces the output to its inactive state */
1147 #define HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /*!< Timer compare 1 event forces the output to its inactive state */
1148 #define HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /*!< Timer compare 2 event forces the output to its inactive state */
1149 #define HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /*!< Timer compare 3 event forces the output to its inactive state */
1150 #define HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /*!< Timer compare 4 event forces the output to its inactive state */
1151 #define HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /*!< The master timer period event forces the output to its inactive state */
1152 #define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its inactive state */
1153 #define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */
1154 #define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */
1155 #define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */
1156 #define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
1157 #define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
1158 #define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
1159 #define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
1160 #define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
1161 #define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
1162 #define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
1163 #define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
1164 #define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
1165 #define HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */
1166 #define HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */
1167 #define HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */
1168 #define HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /*!< External event 4 forces the output to its inactive state */
1169 #define HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /*!< External event 5 forces the output to its inactive state */
1170 #define HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /*!< External event 6 forces the output to its inactive state */
1171 #define HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /*!< External event 7 forces the output to its inactive state */
1172 #define HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /*!< External event 8 forces the output to its inactive state */
1173 #define HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /*!< External event 9 forces the output to its inactive state */
1174 #define HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /*!< External event 10 forces the output to its inactive state */
1175 #define HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /*!< Timer register update event forces the output to its inactive state */
1176
1177 #define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\
1178 (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \
1179 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \
1180 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \
1181 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \
1182 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \
1183 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \
1184 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \
1185 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \
1186 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \
1187 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \
1188 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \
1189 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \
1190 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1) || \
1191 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2) || \
1192 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3) || \
1193 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4) || \
1194 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5) || \
1195 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6) || \
1196 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7) || \
1197 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8) || \
1198 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9) || \
1199 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \
1200 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \
1201 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \
1202 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \
1203 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \
1204 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \
1205 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \
1206 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \
1207 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \
1208 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \
1209 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE))
1210 /**
1211 * @}
1212 */
1213
1214 /** @defgroup HRTIM_Output_Idle_Mode HRTIM Output Idle Mode
1215 * @{
1216 * @brief Constants defining whether or not the timer output transition to its
1217 IDLE state when burst mode is entered
1218 */
1219 #define HRTIM_OUTPUTIDLEMODE_NONE (uint32_t)0x00000000 /*!< The output is not affected by the burst mode operation */
1220 #define HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */
1221
1222 #define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\
1223 (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \
1224 ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE))
1225 /**
1226 * @}
1227 */
1228
1229 /** @defgroup HRTIM_Output_IDLE_Level HRTIM Output IDLE Level
1230 * @{
1231 * @brief Constants defining the output level when output is in IDLE state
1232 */
1233 #define HRTIM_OUTPUTIDLELEVEL_INACTIVE (uint32_t)0x00000000 /*!< Output at inactive level when in IDLE state */
1234 #define HRTIM_OUTPUTIDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1) /*!< Output at active level when in IDLE state */
1235
1236 #define IS_HRTIM_OUTPUTIDLELEVEL(OUTPUTIDLELEVEL)\
1237 (((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \
1238 ((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE))
1239 /**
1240 * @}
1241 */
1242
1243 /** @defgroup HRTIM_Output_FAULT_Level HRTIM Output FAULT Level
1244 * @{
1245 * @brief Constants defining the output level when output is in FAULT state
1246 */
1247 #define HRTIM_OUTPUTFAULTLEVEL_NONE (uint32_t)0x00000000 /*!< The output is not affected by the fault input */
1248 #define HRTIM_OUTPUTFAULTLEVEL_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */
1249 #define HRTIM_OUTPUTFAULTLEVEL_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */
1250 #define HRTIM_OUTPUTFAULTLEVEL_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) /*!< Output is tri-stated when in FAULT state */
1251
1252 #define IS_HRTIM_OUTPUTFAULTLEVEL(OUTPUTFAULTLEVEL)\
1253 (((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE) || \
1254 ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE) || \
1255 ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \
1256 ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ))
1257 /**
1258 * @}
1259 */
1260
1261 /** @defgroup HRTIM_Output_Chopper_Mode_Enable HRTIM Output Chopper Mode Enable
1262 * @{
1263 * @brief Constants defining whether or not chopper mode is enabled for a timer
1264 output
1265 */
1266 #define HRTIM_OUTPUTCHOPPERMODE_DISABLED (uint32_t)0x00000000 /*!< Output signal is not altered */
1267 #define HRTIM_OUTPUTCHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /*!< Output signal is chopped by a carrier signal */
1268
1269 #define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\
1270 (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) || \
1271 ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED))
1272 /**
1273 * @}
1274 */
1275
1276 /** @defgroup HRTIM_Output_Burst_Mode_Entry_Delayed HRTIM Output Burst Mode Entry Delayed
1277 * @{
1278 * @brief Constants defining the idle mode entry is delayed by forcing a
1279 deadtime insertion before switching the outputs to their idle state
1280 */
1281 #define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR (uint32_t)0x00000000 /*!< The programmed Idle state is applied immediately to the Output */
1282 #define HRTIM_OUTPUTBURSTMODEENTRY_DELAYED (HRTIM_OUTR_DIDL1) /*!< Deadtime is inserted on output before entering the idle mode */
1283
1284 #define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\
1285 (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) || \
1286 ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED))
1287 /**
1288 * @}
1289 */
1290
1291 /** @defgroup HRTIM_Capture_Unit_Trigger HRTIM Capture Unit Trigger
1292 * @{
1293 * @brief Constants defining the events that can be selected to trigger the
1294 * capture of the timing unit counter
1295 */
1296 #define HRTIM_CAPTURETRIGGER_NONE (uint32_t)0x00000000 /*!< Capture trigger is disabled */
1297 #define HRTIM_CAPTURETRIGGER_UPDATE (HRTIM_CPT1CR_UPDCPT) /*!< The update event triggers the Capture */
1298 #define HRTIM_CAPTURETRIGGER_EEV_1 (HRTIM_CPT1CR_EXEV1CPT) /*!< The External event 1 triggers the Capture */
1299 #define HRTIM_CAPTURETRIGGER_EEV_2 (HRTIM_CPT1CR_EXEV2CPT) /*!< The External event 2 triggers the Capture */
1300 #define HRTIM_CAPTURETRIGGER_EEV_3 (HRTIM_CPT1CR_EXEV3CPT) /*!< The External event 3 triggers the Capture */
1301 #define HRTIM_CAPTURETRIGGER_EEV_4 (HRTIM_CPT1CR_EXEV4CPT) /*!< The External event 4 triggers the Capture */
1302 #define HRTIM_CAPTURETRIGGER_EEV_5 (HRTIM_CPT1CR_EXEV5CPT) /*!< The External event 5 triggers the Capture */
1303 #define HRTIM_CAPTURETRIGGER_EEV_6 (HRTIM_CPT1CR_EXEV6CPT) /*!< The External event 6 triggers the Capture */
1304 #define HRTIM_CAPTURETRIGGER_EEV_7 (HRTIM_CPT1CR_EXEV7CPT) /*!< The External event 7 triggers the Capture */
1305 #define HRTIM_CAPTURETRIGGER_EEV_8 (HRTIM_CPT1CR_EXEV8CPT) /*!< The External event 8 triggers the Capture */
1306 #define HRTIM_CAPTURETRIGGER_EEV_9 (HRTIM_CPT1CR_EXEV9CPT) /*!< The External event 9 triggers the Capture */
1307 #define HRTIM_CAPTURETRIGGER_EEV_10 (HRTIM_CPT1CR_EXEV10CPT) /*!< The External event 10 triggers the Capture */
1308 #define HRTIM_CAPTURETRIGGER_TA1_SET (HRTIM_CPT1CR_TA1SET) /*!< Capture is triggered by TA1 output inactive to active transition */
1309 #define HRTIM_CAPTURETRIGGER_TA1_RESET (HRTIM_CPT1CR_TA1RST) /*!< Capture is triggered by TA1 output active to inactive transition */
1310 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP1 (HRTIM_CPT1CR_TIMACMP1) /*!< Timer A Compare 1 triggers Capture */
1311 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP2 (HRTIM_CPT1CR_TIMACMP2) /*!< Timer A Compare 2 triggers Capture */
1312 #define HRTIM_CAPTURETRIGGER_TB1_SET (HRTIM_CPT1CR_TB1SET) /*!< Capture is triggered by TB1 output inactive to active transition */
1313 #define HRTIM_CAPTURETRIGGER_TB1_RESET (HRTIM_CPT1CR_TB1RST) /*!< Capture is triggered by TB1 output active to inactive transition */
1314 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP1 (HRTIM_CPT1CR_TIMBCMP1) /*!< Timer B Compare 1 triggers Capture */
1315 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP2 (HRTIM_CPT1CR_TIMBCMP2) /*!< Timer B Compare 2 triggers Capture */
1316 #define HRTIM_CAPTURETRIGGER_TC1_SET (HRTIM_CPT1CR_TC1SET) /*!< Capture is triggered by TC1 output inactive to active transition */
1317 #define HRTIM_CAPTURETRIGGER_TC1_RESET (HRTIM_CPT1CR_TC1RST) /*!< Capture is triggered by TC1 output active to inactive transition */
1318 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP1 (HRTIM_CPT1CR_TIMCCMP1) /*!< Timer C Compare 1 triggers Capture */
1319 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP2 (HRTIM_CPT1CR_TIMCCMP2) /*!< Timer C Compare 2 triggers Capture */
1320 #define HRTIM_CAPTURETRIGGER_TD1_SET (HRTIM_CPT1CR_TD1SET) /*!< Capture is triggered by TD1 output inactive to active transition */
1321 #define HRTIM_CAPTURETRIGGER_TD1_RESET (HRTIM_CPT1CR_TD1RST) /*!< Capture is triggered by TD1 output active to inactive transition */
1322 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP1 (HRTIM_CPT1CR_TIMDCMP1) /*!< Timer D Compare 1 triggers Capture */
1323 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP2 (HRTIM_CPT1CR_TIMDCMP2) /*!< Timer D Compare 2 triggers Capture */
1324 #define HRTIM_CAPTURETRIGGER_TE1_SET (HRTIM_CPT1CR_TE1SET) /*!< Capture is triggered by TE1 output inactive to active transition */
1325 #define HRTIM_CAPTURETRIGGER_TE1_RESET (HRTIM_CPT1CR_TE1RST) /*!< Capture is triggered by TE1 output active to inactive transition */
1326 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP1 (HRTIM_CPT1CR_TIMECMP1) /*!< Timer E Compare 1 triggers Capture */
1327 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP2 (HRTIM_CPT1CR_TIMECMP2) /*!< Timer E Compare 2 triggers Capture */
1328
1329 #define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER) \
1330 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) || \
1331 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE) || \
1332 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1) || \
1333 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2) || \
1334 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_3) || \
1335 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_4) || \
1336 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_5) || \
1337 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_6) || \
1338 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_7) || \
1339 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_8) || \
1340 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_9) || \
1341 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10) \
1342 || \
1343 (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
1344 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
1345 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
1346 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
1347 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
1348 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
1349 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
1350 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
1351 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
1352 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
1353 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
1354 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
1355 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
1356 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
1357 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
1358 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
1359 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
1360 || \
1361 (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
1362 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
1363 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
1364 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
1365 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
1366 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
1367 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
1368 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
1369 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
1370 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
1371 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
1372 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
1373 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
1374 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
1375 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
1376 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
1377 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
1378 || \
1379 (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
1380 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
1381 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
1382 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
1383 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
1384 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
1385 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
1386 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
1387 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
1388 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
1389 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
1390 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
1391 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
1392 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
1393 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
1394 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
1395 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
1396 || \
1397 (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
1398 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
1399 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
1400 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
1401 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
1402 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
1403 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
1404 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
1405 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
1406 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
1407 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
1408 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
1409 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
1410 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
1411 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
1412 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
1413 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
1414 || \
1415 (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
1416 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
1417 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
1418 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
1419 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
1420 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
1421 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
1422 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
1423 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
1424 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
1425 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
1426 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
1427 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
1428 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
1429 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
1430 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
1431 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2))))
1432 /**
1433 * @}
1434 */
1435
1436 /** @defgroup HRTIM_Timer_External_Event_Filter HRTIM Timer External Event Filter
1437 * @{
1438 * @brief Constants defining the event filtering apploed to external events
1439 * by a timer
1440 */
1441 #define HRTIM_TIMEVENTFILTER_NONE (0x00000000)
1442 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1 */
1443 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2 */
1444 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3 */
1445 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4 */
1446 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
1447 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
1448 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
1449 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
1450 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
1451 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
1452 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
1453 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
1454 #define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2 */
1455 #define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3 */
1456 #define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */
1457
1458 #define IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER)\
1459 (((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE) || \
1460 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1) || \
1461 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2) || \
1462 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3) || \
1463 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4) || \
1464 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1) || \
1465 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2) || \
1466 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3) || \
1467 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4) || \
1468 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5) || \
1469 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6) || \
1470 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7) || \
1471 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8) || \
1472 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2) || \
1473 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3) || \
1474 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM))
1475 /**
1476 * @}
1477 */
1478
1479 /** @defgroup HRTIM_Timer_External_Event_Latch HRTIM Timer External Event Latch
1480 * @{
1481 * @brief Constants defining whether or not the external event is
1482 * memorized (latched) and generated as soon as the blanking period
1483 * is completed or the window ends
1484 */
1485 #define HRTIM_TIMEVENTLATCH_DISABLED ((uint32_t)0x00000000) /*!< Event is ignored if it happens during a blank, or passed through during a window */
1486 #define HRTIM_TIMEVENTLATCH_ENABLED HRTIM_EEFR1_EE1LTCH /*!< Event is latched and delayed till the end of the blanking or windowing period */
1487
1488 #define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\
1489 (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \
1490 ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED))
1491 /**
1492 * @}
1493 */
1494
1495 /** @defgroup HRTIM_Deadtime_Prescaler_Ratio HRTIM Deadtime Prescaler Ratio
1496 * @{
1497 * @brief Constants defining division ratio between the timer clock frequency
1498 * (fHRTIM) and the deadtime generator clock (fDTG)
1499 */
1500 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8 ((uint32_t)0x00000000) /*!< fDTG = fHRTIM * 8 */
1501 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4 (HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM * 4 */
1502 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2 (HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM * 2 */
1503 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM */
1504 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2 (HRTIM_DTR_DTPRSC_2) /*!< fDTG = fHRTIM / 2 */
1505 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 4 */
1506 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM / 8 */
1507 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 16 */
1508
1509 #define IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)\
1510 (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8) || \
1511 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4) || \
1512 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2) || \
1513 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \
1514 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \
1515 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \
1516 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \
1517 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16))
1518 /**
1519 * @}
1520 */
1521
1522 /** @defgroup HRTIM_Deadtime_Rising_Sign HRTIM Deadtime Rising Sign
1523 * @{
1524 * @brief Constants defining whether the deadtime is positive or negative
1525 * (overlapping signal) on rising edge
1526 */
1527 #define HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE ((uint32_t)0x00000000) /*!< Positive deadtime on rising edge */
1528 #define HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE (HRTIM_DTR_SDTR) /*!< Negative deadtime on rising edge */
1529
1530 #define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\
1531 (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) || \
1532 ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE))
1533 /**
1534 * @}
1535 */
1536
1537 /** @defgroup HRTIM_Deadtime_Rising_Lock HRTIM Deadtime Rising Lock
1538 * @{
1539 * @brief Constants defining whether or not the deadtime (rising sign and
1540 * value) is write protected
1541 */
1542 #define HRTIM_TIMDEADTIME_RISINGLOCK_WRITE ((uint32_t)0x00000000) /*!< Deadtime rising value and sign is writable */
1543 #define HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK) /*!< Deadtime rising value and sign is read-only */
1544
1545 #define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\
1546 (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) || \
1547 ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY))
1548 /**
1549 * @}
1550 */
1551
1552 /** @defgroup HRTIM_Deadtime_Rising_Sign_Lock HRTIM Deadtime Rising Sign Lock
1553 * @{
1554 * @brief Constants defining whether or not the deadtime rising sign is write
1555 * protected
1556 */
1557 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE ((uint32_t)0x00000000) /*!< Deadtime rising sign is writable */
1558 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK) /*!< Deadtime rising sign is read-only */
1559
1560 #define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\
1561 (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) || \
1562 ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY))
1563 /**
1564 * @}
1565 */
1566
1567 /** @defgroup HRTIM_Deadtime_Falling_Sign HRTIM Deadtime Falling Sign
1568 * @{
1569 * @brief Constants defining whether the deadtime is positive or negative
1570 * (overlapping signal) on falling edge
1571 */
1572 #define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE ((uint32_t)0x00000000) /*!< Positive deadtime on falling edge */
1573 #define HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE (HRTIM_DTR_SDTF) /*!< Negative deadtime on falling edge */
1574
1575 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\
1576 (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) || \
1577 ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE))
1578 /**
1579 * @}
1580 */
1581
1582 /** @defgroup HRTIM_Deadtime_Falling_Lock HRTIM Deadtime Falling Lock
1583 * @{
1584 * @brief Constants defining whether or not the deadtime (falling sign and
1585 * value) is write protected
1586 */
1587 #define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE ((uint32_t)0x00000000) /*!< Deadtime falling value and sign is writable */
1588 #define HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK) /*!< Deadtime falling value and sign is read-only */
1589
1590 #define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\
1591 (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) || \
1592 ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY))
1593 /**
1594 * @}
1595 */
1596
1597 /** @defgroup HRTIM_Deadtime_Falling_Sign_Lock HRTIM Deadtime Falling Sign Lock
1598 * @{
1599 * @brief Constants defining whether or not the deadtime falling sign is write
1600 * protected
1601 */
1602 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE ((uint32_t)0x00000000) /*!< Deadtime falling sign is writable */
1603 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK) /*!< Deadtime falling sign is read-only */
1604
1605 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\
1606 (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) || \
1607 ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY))
1608 /**
1609 * @}
1610 */
1611
1612 /** @defgroup HRTIM_Chopper_Frequency HRTIM Chopper Frequency
1613 * @{
1614 * @brief Constants defining the frequency of the generated high frequency carrier
1615 */
1616 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV16 ((uint32_t)0x000000) /*!< fCHPFRQ = fHRTIM / 16 */
1617 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV32 (HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 32 */
1618 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV48 (HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 48 */
1619 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV64 (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 64 */
1620 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV80 (HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 80 */
1621 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV96 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 96 */
1622 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 112 */
1623 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 128 */
1624 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV144 (HRTIM_CHPR_CARFRQ_3) /*!< fCHPFRQ = fHRTIM / 144 */
1625 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 160 */
1626 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 176 */
1627 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 192 */
1628 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 208 */
1629 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 224 */
1630 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */
1631 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */
1632
1633 #define IS_HRTIM_CHOPPER_PRESCALERRATIO(PRESCALERRATIO)\
1634 (((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16) || \
1635 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32) || \
1636 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48) || \
1637 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64) || \
1638 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80) || \
1639 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96) || \
1640 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112) || \
1641 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128) || \
1642 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144) || \
1643 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160) || \
1644 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176) || \
1645 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192) || \
1646 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208) || \
1647 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224) || \
1648 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240) || \
1649 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256))
1650 /**
1651 * @}
1652 */
1653
1654 /** @defgroup HRTIM_Chopper_Duty_Cycle HRTIM Chopper Duty Cycle
1655 * @{
1656 * @brief Constants defining the duty cycle of the generated high frequency carrier
1657 * Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
1658 */
1659 #define HRTIM_CHOPPER_DUTYCYCLE_0 ((uint32_t)0x000000) /*!< 0/8 (i.e. only 1st pulse is present) */ /*!< fCHPFRQ = fHRTIM / 16 */
1660 #define HRTIM_CHOPPER_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /*!< 1/8 (12.5 %)*/ /*!< fCHPFRQ = fHRTIM / 16 */
1661 #define HRTIM_CHOPPER_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /*!< 2/8 (25 %) */ /*!< fCHPFRQ = fHRTIM / 16 */
1662 #define HRTIM_CHOPPER_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< 3/8 (37.5 %) */ /*!< fCHPFRQ = fHRTIM / 16 */
1663 #define HRTIM_CHOPPER_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2) /*!< 4/8 (50 %) */ /*!< fCHPFRQ = fHRTIM / 16 */
1664 #define HRTIM_CHOPPER_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0) /*!< 5/8 (62.5 %) */ /*!< fCHPFRQ = fHRTIM / 16 */
1665 #define HRTIM_CHOPPER_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1) /*!< 6/8 (75 %) */ /*!< fCHPFRQ = fHRTIM / 16 */
1666 #define HRTIM_CHOPPER_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< 7/8 (87.5 %) */ /*!< fCHPFRQ = fHRTIM / 16 */
1667
1668 #define IS_HRTIM_CHOPPER_DUTYCYCLE(DUTYCYCLE)\
1669 (((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0) || \
1670 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125) || \
1671 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250) || \
1672 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375) || \
1673 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500) || \
1674 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625) || \
1675 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750) || \
1676 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875))
1677 /**
1678 * @}
1679 */
1680
1681 /** @defgroup HRTIM_Chopper_Start_Pulse_Width HRTIM Chopper Start Pulse Width
1682 * @{
1683 * @brief Constants defining the pulse width of the first pulse of the generated
1684 * high frequency carrier
1685 */
1686 #define HRTIM_CHOPPER_PULSEWIDTH_16 ((uint32_t)0x000000) /*!< tSTPW = tHRTIM x 16 */
1687 #define HRTIM_CHOPPER_PULSEWIDTH_32 (HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 32 */
1688 #define HRTIM_CHOPPER_PULSEWIDTH_48 (HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 48 */
1689 #define HRTIM_CHOPPER_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 64 */
1690 #define HRTIM_CHOPPER_PULSEWIDTH_80 (HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 80 */
1691 #define HRTIM_CHOPPER_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 96 */
1692 #define HRTIM_CHOPPER_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 112 */
1693 #define HRTIM_CHOPPER_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 128 */
1694 #define HRTIM_CHOPPER_PULSEWIDTH_144 (HRTIM_CHPR_STRPW_3) /*!< tSTPW = tHRTIM x 144 */
1695 #define HRTIM_CHOPPER_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 160 */
1696 #define HRTIM_CHOPPER_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 176 */
1697 #define HRTIM_CHOPPER_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 192 */
1698 #define HRTIM_CHOPPER_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 208 */
1699 #define HRTIM_CHOPPER_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 224 */
1700 #define HRTIM_CHOPPER_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 240 */
1701 #define HRTIM_CHOPPER_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 256 */
1702
1703 #define IS_HRTIM_CHOPPER_PULSEWIDTH(PULSEWIDTH)\
1704 (((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16) || \
1705 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32) || \
1706 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48) || \
1707 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64) || \
1708 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80) || \
1709 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96) || \
1710 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112) || \
1711 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128) || \
1712 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144) || \
1713 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160) || \
1714 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176) || \
1715 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192) || \
1716 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208) || \
1717 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224) || \
1718 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240) || \
1719 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256))
1720 /**
1721 * @}
1722 */
1723
1724 /** @defgroup HRTIM_Synchronization_Options HRTIM Synchronization Options
1725 * @{
1726 * @brief Constants defining the options for synchronizing multiple HRTIM
1727 * instances, as a master unit (generating a synchronization signal)
1728 * or as a slave (waiting for a trigger to be synchronized)
1729 */
1730 #define HRTIM_SYNCOPTION_NONE (uint32_t)0x00000000 /*!< HRTIM instance doesn't handle external synchronization signals (SYNCIN, SYNCOUT) */
1731 #define HRTIM_SYNCOPTION_MASTER (uint32_t)0x00000001 /*!< HRTIM instance acts as a MASTER, i.e. generates external synchronization output (SYNCOUT)*/
1732 #define HRTIM_SYNCOPTION_SLAVE (uint32_t)0x00000002 /*!< HRTIM instance acts as a SLAVE, i.e. it is synchronized by external sources (SYNCIN) */
1733 /**
1734 * @}
1735 */
1736
1737 /** @defgroup HRTIM_Synchronization_Input_Source HRTIM Synchronization Input Source
1738 * @{
1739 * @brief Constants defining defining the synchronization input source
1740 */
1741 #define HRTIM_SYNCINPUTSOURCE_NONE (uint32_t)0x00000000 /*!< disabled. HRTIM is not synchronized and runs in standalone mode */
1742 #define HRTIM_SYNCINPUTSOURCE_INTERNALEVENT HRTIM_MCR_SYNC_IN_1 /*!< The HRTIM is synchronized with the on-chip timer */
1743 #define HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */
1744
1745 #define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\
1746 (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) || \
1747 ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) || \
1748 ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT))
1749 /**
1750 * @}
1751 */
1752
1753 /** @defgroup HRTIM_Synchronization_Output_Source HRTIM Synchronization Output Source
1754 * @{
1755 * @brief Constants defining the source and event to be sent on the
1756 * synchronization outputs
1757 */
1758 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_START (uint32_t)0x00000000 /*!< A pulse is sent on the SYNCOUT output (16x fHRTIM clock cycles) upon master timer start event */
1759 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output (16x fHRTIM clock cycles) upon master timer compare 1 event*/
1760 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on the SYNCOUT output (16x fHRTIM clock cycles) upon timer A start or reset events */
1761 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output (16x fHRTIM clock cycles) upon timer A compare 1 event */
1762
1763 #define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\
1764 (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) || \
1765 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) || \
1766 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) || \
1767 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1))
1768 /**
1769 * @}
1770 */
1771
1772 /** @defgroup HRTIM_Synchronization_Output_Polarity HRTIM Synchronization Output Polarity
1773 * @{
1774 * @brief Constants defining the routing and conditioning of the synchronization output event
1775 */
1776 #define HRTIM_SYNCOUTPUTPOLARITY_NONE (uint32_t)0x00000000 /*!< Synchronization output event is disabled */
1777 #define HRTIM_SYNCOUTPUTPOLARITY_POSITIVE (HRTIM_MCR_SYNC_OUT_1) /*!< Positive pulse on SCOUT output (16x fHRTIM clock cycles) */
1778 #define HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< Positive pulse on SCOUT output (16x fHRTIM clock cycles) */
1779
1780 #define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\
1781 (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) || \
1782 ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \
1783 ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE))
1784 /**
1785 * @}
1786 */
1787
1788 /** @defgroup HRTIM_External_Event_Sources HRTIM External Event Sources
1789 * @{
1790 * @brief Constants defining available sources associated to external events
1791 */
1792 #define HRTIM_EVENTSRC_1 ((uint32_t)0x00000000) /*!< External event source 1 */
1793 #define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 */
1794 #define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 */
1795 #define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 */
1796
1797 #define IS_HRTIM_EVENTSRC(EVENTSRC)\
1798 (((EVENTSRC) == HRTIM_EVENTSRC_1) || \
1799 ((EVENTSRC) == HRTIM_EVENTSRC_2) || \
1800 ((EVENTSRC) == HRTIM_EVENTSRC_3) || \
1801 ((EVENTSRC) == HRTIM_EVENTSRC_4))
1802 /**
1803 * @}
1804 */
1805
1806 /** @defgroup HRTIM_External_Event_Polarity HRTIM External Event Polarity
1807 * @{
1808 * @brief Constants defining the polarity of an external event
1809 */
1810 #define HRTIM_EVENTPOLARITY_HIGH ((uint32_t)0x00000000) /*!< External event is active high */
1811 #define HRTIM_EVENTPOLARITY_LOW (HRTIM_EECR1_EE1POL) /*!< External event is active low */
1812
1813 #define IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)\
1814 ((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) && \
1815 (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) || \
1816 ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))) \
1817 || \
1818 (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \
1819 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \
1820 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)))
1821 /**
1822 * @}
1823 */
1824
1825 /** @defgroup HRTIM_External_Event_Sensitivity HRTIM External Event Sensitivity
1826 * @{
1827 * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive)
1828 * of an external event
1829 */
1830 #define HRTIM_EVENTSENSITIVITY_LEVEL ((uint32_t)0x00000000) /*!< External event is active on level */
1831 #define HRTIM_EVENTSENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising edge */
1832 #define HRTIM_EVENTSENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /*!< External event is active on Falling edge */
1833 #define HRTIM_EVENTSENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising and Falling edges */
1834
1835 #define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\
1836 (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) || \
1837 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \
1838 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \
1839 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))
1840 /**
1841 * @}
1842 */
1843
1844 /** @defgroup HRTIM_External_Event_Fast_Mode HRTIM External Event Fast Mode
1845 * @{
1846 * @brief Constants defining whether or not an external event is programmed in
1847 fast mode
1848 */
1849 #define HRTIM_EVENTFASTMODE_DISABLE ((uint32_t)0x00000000) /*!< External Event is acting asynchronously on outputs (low latency mode) */
1850 #define HRTIM_EVENTFASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
1851
1852 #define IS_HRTIM_EVENTFASTMODE(EVENT, FASTMODE)\
1853 (((((EVENT) == HRTIM_EVENT_1) || \
1854 ((EVENT) == HRTIM_EVENT_2) || \
1855 ((EVENT) == HRTIM_EVENT_3) || \
1856 ((EVENT) == HRTIM_EVENT_4) || \
1857 ((EVENT) == HRTIM_EVENT_5)) && \
1858 (((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \
1859 ((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \
1860 || \
1861 (((EVENT) == HRTIM_EVENT_6) || \
1862 ((EVENT) == HRTIM_EVENT_7) || \
1863 ((EVENT) == HRTIM_EVENT_8) || \
1864 ((EVENT) == HRTIM_EVENT_9) || \
1865 ((EVENT) == HRTIM_EVENT_10)))
1866
1867 /**
1868 * @}
1869 */
1870
1871 /** @defgroup HRTIM_External_Event_Filter HRTIM External Event Filter
1872 * @{
1873 * @brief Constants defining the frequency used to sample an external event 6
1874 * input and the length (N) of the digital filter applied
1875 */
1876 #define HRTIM_EVENTFILTER_NONE ((uint32_t)0x00000000) /*!< Filter disabled */
1877 #define HRTIM_EVENTFILTER_1 (HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=2 */
1878 #define HRTIM_EVENTFILTER_2 (HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fHRTIM, N=4 */
1879 #define HRTIM_EVENTFILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=8 */
1880 #define HRTIM_EVENTFILTER_4 (HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/2, N=6 */
1881 #define HRTIM_EVENTFILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/2, N=8 */
1882 #define HRTIM_EVENTFILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/4, N=6 */
1883 #define HRTIM_EVENTFILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/4, N=8 */
1884 #define HRTIM_EVENTFILTER_8 (HRTIM_EECR3_EE6F_3) /*!< fSAMPLING= fEEVS/8, N=6 */
1885 #define HRTIM_EVENTFILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/8, N=8 */
1886 #define HRTIM_EVENTFILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/16, N=5 */
1887 #define HRTIM_EVENTFILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/16, N=6 */
1888 #define HRTIM_EVENTFILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/16, N=8 */
1889 #define HRTIM_EVENTFILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32, N=5 */
1890 #define HRTIM_EVENTFILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/32, N=6 */
1891 #define HRTIM_EVENTFILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32, N=8 */
1892
1893 #define IS_HRTIM_EVENTFILTER(EVENT, FILTER)\
1894 ((((EVENT) == HRTIM_EVENT_1) || \
1895 ((EVENT) == HRTIM_EVENT_2) || \
1896 ((EVENT) == HRTIM_EVENT_3) || \
1897 ((EVENT) == HRTIM_EVENT_4) || \
1898 ((EVENT) == HRTIM_EVENT_5)) \
1899 || \
1900 ((((EVENT) == HRTIM_EVENT_6) || \
1901 ((EVENT) == HRTIM_EVENT_7) || \
1902 ((EVENT) == HRTIM_EVENT_8) || \
1903 ((EVENT) == HRTIM_EVENT_9) || \
1904 ((EVENT) == HRTIM_EVENT_10)) && \
1905 (((FILTER) == HRTIM_EVENTFILTER_NONE) || \
1906 ((FILTER) == HRTIM_EVENTFILTER_1) || \
1907 ((FILTER) == HRTIM_EVENTFILTER_2) || \
1908 ((FILTER) == HRTIM_EVENTFILTER_3) || \
1909 ((FILTER) == HRTIM_EVENTFILTER_4) || \
1910 ((FILTER) == HRTIM_EVENTFILTER_5) || \
1911 ((FILTER) == HRTIM_EVENTFILTER_6) || \
1912 ((FILTER) == HRTIM_EVENTFILTER_7) || \
1913 ((FILTER) == HRTIM_EVENTFILTER_8) || \
1914 ((FILTER) == HRTIM_EVENTFILTER_9) || \
1915 ((FILTER) == HRTIM_EVENTFILTER_10) || \
1916 ((FILTER) == HRTIM_EVENTFILTER_11) || \
1917 ((FILTER) == HRTIM_EVENTFILTER_12) || \
1918 ((FILTER) == HRTIM_EVENTFILTER_13) || \
1919 ((FILTER) == HRTIM_EVENTFILTER_14) || \
1920 ((FILTER) == HRTIM_EVENTFILTER_15))))
1921 /**
1922 * @}
1923 */
1924
1925 /** @defgroup HRTIM_External_Event_Prescaler HRTIM External Event Prescaler
1926 * @{
1927 * @brief Constants defining division ratio between the timer clock frequency
1928 * fHRTIM) and the external event signal sampling clock (fEEVS)
1929 * used by the digital filters
1930 */
1931 #define HRTIM_EVENTPRESCALER_DIV1 ((uint32_t)0x00000000) /*!< fEEVS=fHRTIM */
1932 #define HRTIM_EVENTPRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 2 */
1933 #define HRTIM_EVENTPRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /*!< fEEVS=fHRTIM / 4 */
1934 #define HRTIM_EVENTPRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 8 */
1935
1936 #define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\
1937 (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) || \
1938 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) || \
1939 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) || \
1940 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8))
1941 /**
1942 * @}
1943 */
1944
1945 /** @defgroup HRTIM_Fault_Sources HRTIM Fault Sources
1946 * @{
1947 * @brief Constants defining whether a faults is be triggered by any external
1948 * or internal fault source
1949 */
1950 #define HRTIM_FAULTSOURCE_DIGITALINPUT ((uint32_t)0x00000000) /*!< Fault input is FLT input pin */
1951 #define HRTIM_FAULTSOURCE_INTERNAL (HRTIM_FLTINR1_FLT1SRC) /*!< Fault input is FLT_Int signal (e.g. internal comparator) */
1952
1953
1954 #define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\
1955 (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \
1956 ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL))
1957 /**
1958 * @}
1959 */
1960
1961 /** @defgroup HRTIM_Fault_Polarity HRTIM Fault Polarity
1962 * @{
1963 * @brief Constants defining the polarity of a fault event
1964 */
1965 #define HRTIM_FAULTPOLARITY_LOW ((uint32_t)0x00000000) /*!< Fault input is active low */
1966 #define HRTIM_FAULTPOLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /*!< Fault input is active high */
1967
1968 #define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\
1969 (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \
1970 ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH))
1971 /**
1972 * @}
1973 */
1974
1975 /** @defgroup HRTIM_Fault_Filter HRTIM Fault Filter
1976 * @{
1977 * @ brief Constants defining the frequency used to sample the fault input and
1978 * the length (N) of the digital filter applied
1979 */
1980 #define HRTIM_FAULTFILTER_NONE ((uint32_t)0x00000000) /*!< Filter disabled */
1981 #define HRTIM_FAULTFILTER_1 (HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=2 */
1982 #define HRTIM_FAULTFILTER_2 (HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fHRTIM, N=4 */
1983 #define HRTIM_FAULTFILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=8 */
1984 #define HRTIM_FAULTFILTER_4 (HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/2, N=6 */
1985 #define HRTIM_FAULTFILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/2, N=8 */
1986 #define HRTIM_FAULTFILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/4, N=6 */
1987 #define HRTIM_FAULTFILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/4, N=8 */
1988 #define HRTIM_FAULTFILTER_8 (HRTIM_FLTINR1_FLT1F_3) /*!< fSAMPLING= fFLTS/8, N=6 */
1989 #define HRTIM_FAULTFILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/8, N=8 */
1990 #define HRTIM_FAULTFILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/16, N=5 */
1991 #define HRTIM_FAULTFILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/16, N=6 */
1992 #define HRTIM_FAULTFILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/16, N=8 */
1993 #define HRTIM_FAULTFILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=5 */
1994 #define HRTIM_FAULTFILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/32, N=6 */
1995 #define HRTIM_FAULTFILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=8 */
1996
1997 #define IS_HRTIM_FAULTFILTER(FAULTFILTER)\
1998 (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \
1999 ((FAULTFILTER) == HRTIM_FAULTFILTER_1) || \
2000 ((FAULTFILTER) == HRTIM_FAULTFILTER_2) || \
2001 ((FAULTFILTER) == HRTIM_FAULTFILTER_3) || \
2002 ((FAULTFILTER) == HRTIM_FAULTFILTER_4) || \
2003 ((FAULTFILTER) == HRTIM_FAULTFILTER_5) || \
2004 ((FAULTFILTER) == HRTIM_FAULTFILTER_6) || \
2005 ((FAULTFILTER) == HRTIM_FAULTFILTER_7) || \
2006 ((FAULTFILTER) == HRTIM_FAULTFILTER_8) || \
2007 ((FAULTFILTER) == HRTIM_FAULTFILTER_9) || \
2008 ((FAULTFILTER) == HRTIM_FAULTFILTER_10) || \
2009 ((FAULTFILTER) == HRTIM_FAULTFILTER_11) || \
2010 ((FAULTFILTER) == HRTIM_FAULTFILTER_12) || \
2011 ((FAULTFILTER) == HRTIM_FAULTFILTER_13) || \
2012 ((FAULTFILTER) == HRTIM_FAULTFILTER_14) || \
2013 ((FAULTFILTER) == HRTIM_FAULTFILTER_15))
2014 /**
2015 * @}
2016 */
2017
2018 /** @defgroup HRTIM_Fault_Lock HRTIM Fault Lock
2019 * @{
2020 * @brief Constants defining whether or not the fault programming bits are
2021 write protected
2022 */
2023 #define HRTIM_FAULTLOCK_READWRITE ((uint32_t)0x00000000) /*!< Fault settings bits are read/write */
2024 #define HRTIM_FAULTLOCK_READONLY (HRTIM_FLTINR1_FLT1LCK) /*!< Fault settings bits are read only */
2025
2026 #define IS_HRTIM_FAULTLOCK(FAULTLOCK)\
2027 (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \
2028 ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY))
2029 /**
2030 * @}
2031 */
2032
2033 /** @defgroup HRTIM_External_Fault_Prescaler HRTIM External Fault Prescaler
2034 * @{
2035 * @brief Constants defining the division ratio between the timer clock
2036 * frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used
2037 * by the digital filters.
2038 */
2039 #define HRTIM_FAULTPRESCALER_DIV1 ((uint32_t)0x00000000) /*!< fFLTS=fHRTIM */
2040 #define HRTIM_FAULTPRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 2 */
2041 #define HRTIM_FAULTPRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /*!< fFLTS=fHRTIM / 4 */
2042 #define HRTIM_FAULTPRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 8 */
2043
2044 #define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\
2045 (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) || \
2046 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) || \
2047 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) || \
2048 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8))
2049 /**
2050 * @}
2051 */
2052
2053 /** @defgroup HRTIM_Burst_Mode_Operating_Mode HRTIM Burst Mode Operating Mode
2054 * @{
2055 * @brief Constants defining if the burst mode is entered once or if it is
2056 * continuously operating
2057 */
2058 #define HRTIM_BURSTMODE_SINGLESHOT ((uint32_t)0x00000000) /*!< Burst mode operates in single shot mode */
2059 #define HRTIM_BURSTMODE_CONTINOUS (HRTIM_BMCR_BMOM) /*!< Burst mode operates in continuous mode */
2060
2061 #define IS_HRTIM_BURSTMODE(BURSTMODE)\
2062 (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) || \
2063 ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS))
2064 /**
2065 * @}
2066 */
2067
2068 /** @defgroup HRTIM_Burst_Mode_Clock_Source HRTIM Burst Mode Clock Source
2069 * @{
2070 * @brief Constants defining the clock source for the burst mode counter
2071 */
2072 #define HRTIM_BURSTMODECLOCKSOURCE_MASTER ((uint32_t)0x00000000) /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
2073 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_A (HRTIM_BMCR_BMCLK_0) /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */
2074 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_B (HRTIM_BMCR_BMCLK_1) /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */
2075 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */
2076 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_D (HRTIM_BMCR_BMCLK_2) /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */
2077 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */
2078 #define HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1) /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */
2079 #define HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */
2080 #define HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO (HRTIM_BMCR_BMCLK_3) /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */
2081 #define HRTIM_BURSTMODECLOCKSOURCE_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1) /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */
2082
2083 #define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\
2084 (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) || \
2085 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) || \
2086 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) || \
2087 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) || \
2088 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) || \
2089 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) || \
2090 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC) || \
2091 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC) || \
2092 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO) || \
2093 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM))
2094 /**
2095 * @}
2096 */
2097
2098 /** @defgroup HRTIM_Burst_Mode_Prescaler HRTIM Burst Mode Prescaler
2099 * @{
2100 * @brief Constants defining the prescaling ratio of the fHRTIM clock
2101 * for the burst mode controller
2102 */
2103 #define HRTIM_BURSTMODEPRESCALER_DIV1 ((uint32_t)0x00000000) /*!< fBRST = fHRTIM */
2104 #define HRTIM_BURSTMODEPRESCALER_DIV2 (HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2 */
2105 #define HRTIM_BURSTMODEPRESCALER_DIV4 (HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/4 */
2106 #define HRTIM_BURSTMODEPRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8 */
2107 #define HRTIM_BURSTMODEPRESCALER_DIV16 (HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/16 */
2108 #define HRTIM_BURSTMODEPRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32 */
2109 #define HRTIM_BURSTMODEPRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/64 */
2110 #define HRTIM_BURSTMODEPRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/128 */
2111 #define HRTIM_BURSTMODEPRESCALER_DIV256 (HRTIM_BMCR_BMPRSC_3) /*!< fBRST = fHRTIM/256 */
2112 #define HRTIM_BURSTMODEPRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/512 */
2113 #define HRTIM_BURSTMODEPRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/1024 */
2114 #define HRTIM_BURSTMODEPRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2048*/
2115 #define HRTIM_BURSTMODEPRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/4096 */
2116 #define HRTIM_BURSTMODEPRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8192 */
2117 #define HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/16384 */
2118 #define HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768 */
2119
2120 #define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\
2121 (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) || \
2122 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) || \
2123 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) || \
2124 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) || \
2125 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) || \
2126 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) || \
2127 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) || \
2128 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) || \
2129 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) || \
2130 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) || \
2131 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) || \
2132 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) || \
2133 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) || \
2134 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) || \
2135 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \
2136 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768))
2137 /**
2138 * @}
2139 */
2140
2141 /** @defgroup HRTIM_Burst_Mode_Register_Preload_Enable HRTIM Burst Mode Register Preload Enable
2142 * @{
2143 * @brief Constants defining whether or not burst mode registers preload
2144 mechanism is enabled, i.e. a write access into a preloadable register
2145 (HRTIM_BMCMPR, HRTIM_BMPER) is done into the active or the preload register
2146 */
2147 #define HRIM_BURSTMODEPRELOAD_DISABLED ((uint32_t)0x00000000) /*!< Preload disabled: the write access is directly done into active registers */
2148 #define HRIM_BURSTMODEPRELOAD_ENABLED (HRTIM_BMCR_BMPREN) /*!< Preload enabled: the write access is done into preload registers */
2149
2150 #define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\
2151 (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) || \
2152 ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED))
2153 /**
2154 * @}
2155 */
2156
2157 /** @defgroup HRTIM_Burst_Mode_Trigger HRTIM Burst Mode Trigger
2158 * @{
2159 * @brief Constants defining the events that can be used tor trig the burst
2160 * mode operation
2161 */
2162 #define HRTIM_BURSTMODETRIGGER_NONE (uint32_t)0x00000000 /*!< No trigger */
2163 #define HRTIM_BURSTMODETRIGGER_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /*!< Master reset */
2164 #define HRTIM_BURSTMODETRIGGER_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /*!< Master repetition */
2165 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /*!< Master compare 1 */
2166 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /*!< Master compare 2 */
2167 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /*!< Master compare 3 */
2168 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /*!< Master compare 4 */
2169 #define HRTIM_BURSTMODETRIGGER_TIMERA_RESET (HRTIM_BMTRGR_TARST) /*!< Timer A reset */
2170 #define HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION (HRTIM_BMTRGR_TAREP) /*!< Timer A repetition */
2171 #define HRTIM_BURSTMODETRIGGER_TIMERA_CMP1 (HRTIM_BMTRGR_TACMP1) /*!< Timer A compare 1 */
2172 #define HRTIM_BURSTMODETRIGGER_TIMERA_CMP2 (HRTIM_BMTRGR_TACMP2) /*!< Timer A compare 2 */
2173 #define HRTIM_BURSTMODETRIGGER_TIMERB_RESET (HRTIM_BMTRGR_TBRST) /*!< Timer B reset */
2174 #define HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION (HRTIM_BMTRGR_TBREP) /*!< Timer B repetition */
2175 #define HRTIM_BURSTMODETRIGGER_TIMERB_CMP1 (HRTIM_BMTRGR_TBCMP1) /*!< Timer B compare 1 */
2176 #define HRTIM_BURSTMODETRIGGER_TIMERB_CMP2 (HRTIM_BMTRGR_TBCMP2) /*!< Timer B compare 2 */
2177 #define HRTIM_BURSTMODETRIGGER_TIMERC_RESET (HRTIM_BMTRGR_TCRST) /*!< Timer C reset */
2178 #define HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION (HRTIM_BMTRGR_TCREP) /*!< Timer C repetition */
2179 #define HRTIM_BURSTMODETRIGGER_TIMERC_CMP1 (HRTIM_BMTRGR_TCCMP1) /*!< Timer C compare 1 */
2180 #define HRTIM_BURSTMODETRIGGER_TIMERC_CMP2 (HRTIM_BMTRGR_TCCMP2) /*!< Timer C compare 2 */
2181 #define HRTIM_BURSTMODETRIGGER_TIMERD_RESET (HRTIM_BMTRGR_TDRST) /*!< Timer D reset */
2182 #define HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION (HRTIM_BMTRGR_TDREP) /*!< Timer D repetition */
2183 #define HRTIM_BURSTMODETRIGGER_TIMERD_CMP1 (HRTIM_BMTRGR_TDCMP1) /*!< Timer D compare 1 */
2184 #define HRTIM_BURSTMODETRIGGER_TIMERD_CMP2 (HRTIM_BMTRGR_TDCMP2) /*!< Timer D compare 2 */
2185 #define HRTIM_BURSTMODETRIGGER_TIMERE_RESET (HRTIM_BMTRGR_TERST) /*!< Timer E reset */
2186 #define HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION (HRTIM_BMTRGR_TEREP) /*!< Timer E repetition */
2187 #define HRTIM_BURSTMODETRIGGER_TIMERE_CMP1 (HRTIM_BMTRGR_TECMP1) /*!< Timer E compare 1 */
2188 #define HRTIM_BURSTMODETRIGGER_TIMERE_CMP2 (HRTIM_BMTRGR_TECMP2) /*!< Timer E compare 2 */
2189 #define HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /*!< Timer A period following External Event 7 */
2190 #define HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /*!< Timer D period following External Event 8 */
2191 #define HRTIM_BURSTMODETRIGGER_EVENT_7 (HRTIM_BMTRGR_EEV7) /*!< External Event 7 (timer A filters applied) */
2192 #define HRTIM_BURSTMODETRIGGER_EVENT_8 (HRTIM_BMTRGR_EEV8) /*!< External Event 8 (timer D filters applied)*/
2193 #define HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /*!< On-chip Event */
2194
2195 #define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\
2196 (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) || \
2197 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) || \
2198 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) || \
2199 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) || \
2200 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) || \
2201 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) || \
2202 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) || \
2203 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) || \
2204 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \
2205 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) || \
2206 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) || \
2207 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) || \
2208 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \
2209 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) || \
2210 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) || \
2211 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) || \
2212 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \
2213 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) || \
2214 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP2) || \
2215 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) || \
2216 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \
2217 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP1) || \
2218 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) || \
2219 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_RESET) || \
2220 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \
2221 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) || \
2222 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) || \
2223 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) || \
2224 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) || \
2225 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) || \
2226 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) || \
2227 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP))
2228 /**
2229 * @}
2230 */
2231
2232 /** @defgroup HRTIM_ADC_Trigger_Update_Source HRTIM ADC Trigger Update Source
2233 * @{
2234 * @brief constants defining the source triggering the update of the
2235 HRTIM_ADCxR register (transfer from preload to active register).
2236 */
2237 #define HRTIM_ADCTRIGGERUPDATE_MASTER (uint32_t)0x00000000 /*!< Master timer */
2238 #define HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0) /*!< Timer A */
2239 #define HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1) /*!< Timer B */
2240 #define HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< Timer C */
2241 #define HRTIM_ADCTRIGGERUPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2) /*!< Timer D */
2242 #define HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< Timer E */
2243
2244 #define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\
2245 (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) || \
2246 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) || \
2247 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) || \
2248 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) || \
2249 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) || \
2250 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E))
2251 /**
2252 * @}
2253 */
2254
2255 /** @defgroup HRTIM_ADC_Trigger_Event HRTIM ADC Trigger Event
2256 * @{
2257 * @brief constants defining the events triggering ADC conversion.
2258 * HRTIM_ADCTRIGGEREVENT13_*: ADC Triggers 1 and 3
2259 * HRTIM_ADCTRIGGEREVENT24_*: ADC Triggers 2 and 4
2260 */
2261 #define HRTIM_ADCTRIGGEREVENT13_NONE (uint32_t)0x00000000 /*!< No ADC trigger event */
2262 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1 (HRTIM_ADC1R_AD1MC1) /*!< ADC Trigger on master compare 1 */
2263 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2 (HRTIM_ADC1R_AD1MC2) /*!< ADC Trigger on master compare 2 */
2264 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3 (HRTIM_ADC1R_AD1MC3) /*!< ADC Trigger on master compare 3 */
2265 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4 (HRTIM_ADC1R_AD1MC4) /*!< ADC Trigger on master compare 4 */
2266 #define HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD (HRTIM_ADC1R_AD1MPER) /*!< ADC Trigger on master period */
2267 #define HRTIM_ADCTRIGGEREVENT13_EVENT_1 (HRTIM_ADC1R_AD1EEV1) /*!< ADC Trigger on external event 1 */
2268 #define HRTIM_ADCTRIGGEREVENT13_EVENT_2 (HRTIM_ADC1R_AD1EEV2) /*!< ADC Trigger on external event 2 */
2269 #define HRTIM_ADCTRIGGEREVENT13_EVENT_3 (HRTIM_ADC1R_AD1EEV3) /*!< ADC Trigger on external event 3 */
2270 #define HRTIM_ADCTRIGGEREVENT13_EVENT_4 (HRTIM_ADC1R_AD1EEV4) /*!< ADC Trigger on external event 4 */
2271 #define HRTIM_ADCTRIGGEREVENT13_EVENT_5 (HRTIM_ADC1R_AD1EEV5) /*!< ADC Trigger on external event 5 */
2272 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP2 (HRTIM_ADC1R_AD1TAC2) /*!< ADC Trigger on Timer A compare 2 */
2273 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3 (HRTIM_ADC1R_AD1TAC3) /*!< ADC Trigger on Timer A compare 3 */
2274 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4 (HRTIM_ADC1R_AD1TAC4) /*!< ADC Trigger on Timer A compare 4 */
2275 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD (HRTIM_ADC1R_AD1TAPER) /*!< ADC Trigger on Timer A period */
2276 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET (HRTIM_ADC1R_AD1TARST) /*!< ADC Trigger on Timer A reset */
2277 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP2 (HRTIM_ADC1R_AD1TBC2) /*!< ADC Trigger on Timer B compare 2 */
2278 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3 (HRTIM_ADC1R_AD1TBC3) /*!< ADC Trigger on Timer B compare 3 */
2279 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4 (HRTIM_ADC1R_AD1TBC4) /*!< ADC Trigger on Timer B compare 4 */
2280 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD (HRTIM_ADC1R_AD1TBPER) /*!< ADC Trigger on Timer B period */
2281 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET (HRTIM_ADC1R_AD1TBRST) /*!< ADC Trigger on Timer B reset */
2282 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP2 (HRTIM_ADC1R_AD1TCC2) /*!< ADC Trigger on Timer C compare 2 */
2283 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3 (HRTIM_ADC1R_AD1TCC3) /*!< ADC Trigger on Timer C compare 3 */
2284 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4 (HRTIM_ADC1R_AD1TCC4) /*!< ADC Trigger on Timer C compare 4 */
2285 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD (HRTIM_ADC1R_AD1TCPER) /*!< ADC Trigger on Timer C period */
2286 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP2 (HRTIM_ADC1R_AD1TDC2) /*!< ADC Trigger on Timer D compare 2 */
2287 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3 (HRTIM_ADC1R_AD1TDC3) /*!< ADC Trigger on Timer D compare 3 */
2288 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4 (HRTIM_ADC1R_AD1TDC4) /*!< ADC Trigger on Timer D compare 4 */
2289 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD (HRTIM_ADC1R_AD1TDPER) /*!< ADC Trigger on Timer D period */
2290 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP2 (HRTIM_ADC1R_AD1TEC2) /*!< ADC Trigger on Timer E compare 2 */
2291 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3 (HRTIM_ADC1R_AD1TEC3) /*!< ADC Trigger on Timer E compare 3 */
2292 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4 (HRTIM_ADC1R_AD1TEC4) /*!< ADC Trigger on Timer E compare 4 */
2293 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD (HRTIM_ADC1R_AD1TEPER) /*!< ADC Trigger on Timer E period */
2294
2295 #define HRTIM_ADCTRIGGEREVENT24_NONE (uint32_t)0x00000000 /*!< No ADC trigger event */
2296 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1 (HRTIM_ADC2R_AD2MC1) /*!< ADC Trigger on master compare 1 */
2297 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2 (HRTIM_ADC2R_AD2MC2) /*!< ADC Trigger on master compare 2 */
2298 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3 (HRTIM_ADC2R_AD2MC3) /*!< ADC Trigger on master compare 3 */
2299 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4 (HRTIM_ADC2R_AD2MC4) /*!< ADC Trigger on master compare 4 */
2300 #define HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD (HRTIM_ADC2R_AD2MPER) /*!< ADC Trigger on master period */
2301 #define HRTIM_ADCTRIGGEREVENT24_EVENT_6 (HRTIM_ADC2R_AD2EEV6) /*!< ADC Trigger on external event 6 */
2302 #define HRTIM_ADCTRIGGEREVENT24_EVENT_7 (HRTIM_ADC2R_AD2EEV7) /*!< ADC Trigger on external event 7 */
2303 #define HRTIM_ADCTRIGGEREVENT24_EVENT_8 (HRTIM_ADC2R_AD2EEV8) /*!< ADC Trigger on external event 8 */
2304 #define HRTIM_ADCTRIGGEREVENT24_EVENT_9 (HRTIM_ADC2R_AD2EEV9) /*!< ADC Trigger on external event 9 */
2305 #define HRTIM_ADCTRIGGEREVENT24_EVENT_10 (HRTIM_ADC2R_AD2EEV10) /*!< ADC Trigger on external event 10 */
2306 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2 (HRTIM_ADC2R_AD2TAC2) /*!< ADC Trigger on Timer A compare 2 */
2307 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP3 (HRTIM_ADC2R_AD2TAC3) /*!< ADC Trigger on Timer A compare 3 */
2308 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4 (HRTIM_ADC2R_AD2TAC4) /*!< ADC Trigger on Timer A compare 4 */
2309 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD (HRTIM_ADC2R_AD2TAPER) /*!< ADC Trigger on Timer A period */
2310 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2 (HRTIM_ADC2R_AD2TBC2) /*!< ADC Trigger on Timer B compare 2 */
2311 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP3 (HRTIM_ADC2R_AD2TBC3) /*!< ADC Trigger on Timer B compare 3 */
2312 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4 (HRTIM_ADC2R_AD2TBC4) /*!< ADC Trigger on Timer B compare 4 */
2313 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD (HRTIM_ADC2R_AD2TBPER) /*!< ADC Trigger on Timer B period */
2314 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2 (HRTIM_ADC2R_AD2TCC2) /*!< ADC Trigger on Timer C compare 2 */
2315 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP3 (HRTIM_ADC2R_AD2TCC3) /*!< ADC Trigger on Timer C compare 3 */
2316 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4 (HRTIM_ADC2R_AD2TCC4) /*!< ADC Trigger on Timer C compare 4 */
2317 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD (HRTIM_ADC2R_AD2TCPER) /*!< ADC Trigger on Timer C period */
2318 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET (HRTIM_ADC2R_AD2TCRST) /*!< ADC Trigger on Timer C reset */
2319 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2 (HRTIM_ADC2R_AD2TDC2) /*!< ADC Trigger on Timer D compare 2 */
2320 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP3 (HRTIM_ADC2R_AD2TDC3) /*!< ADC Trigger on Timer D compare 3 */
2321 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4 (HRTIM_ADC2R_AD2TDC4) /*!< ADC Trigger on Timer D compare 4 */
2322 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD (HRTIM_ADC2R_AD2TDPER) /*!< ADC Trigger on Timer D period */
2323 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET (HRTIM_ADC2R_AD2TDRST) /*!< ADC Trigger on Timer D reset */
2324 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2 (HRTIM_ADC2R_AD2TEC2) /*!< ADC Trigger on Timer E compare 2 */
2325 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3 (HRTIM_ADC2R_AD2TEC3) /*!< ADC Trigger on Timer E compare 3 */
2326 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4 (HRTIM_ADC2R_AD2TEC4) /*!< ADC Trigger on Timer E compare 4 */
2327 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET (HRTIM_ADC2R_AD2TERST) /*!< ADC Trigger on Timer E reset */
2328
2329 /**
2330 * @}
2331 */
2332
2333 /** @defgroup HRTIM_DLL_Calibration_Rate HRTIM DLL Calibration Rate
2334 * @{
2335 * @brief Constants defining the DLL calibration periods (in micro seconds)
2336 */
2337 #define HRTIM_SINGLE_CALIBRATION (uint32_t)0xFFFFFFFF /*!< Non periodic DLL calibration */
2338 #define HRTIM_CALIBRATIONRATE_7300 (uint32_t)0x00000000 /*!< Periodic DLL calibration: T = 1048576 * tHRTIM (7.3 ms) */
2339 #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 131072 * tHRTIM (910 µs) */
2340 #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) /*!< Periodic DLL calibration: T = 16384 * tHRTIM (114 µs) */
2341 #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 2048 * tHRTIM (14 µs) */
2342
2343 #define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\
2344 (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \
2345 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) || \
2346 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910) || \
2347 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114) || \
2348 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14))
2349 /**
2350 * @}
2351 */
2352
2353 /** @defgroup HRTIM_Burst_DMA_Registers_Update HRTIM Burst DMA Registers Update
2354 * @{
2355 * @brief Constants defining the registers that can be written during a burst
2356 * DMA operation
2357 */
2358 #define HRTIM_BURSTDMA_NONE (uint32_t)0x00000000 /*!< No register is updated by Burst DMA accesses */
2359 #define HRTIM_BURSTDMA_CR (HRTIM_BDTUPR_TIMCR) /*!< MCR or TIMxCR register is updated by Burst DMA accesses */
2360 #define HRTIM_BURSTDMA_ICR (HRTIM_BDTUPR_TIMICR) /*!< MICR or TIMxICR register is updated by Burst DMA accesses */
2361 #define HRTIM_BURSTDMA_DIER (HRTIM_BDTUPR_TIMDIER) /*!< MDIER or TIMxDIER register is updated by Burst DMA accesses */
2362 #define HRTIM_BURSTDMA_CNT (HRTIM_BDTUPR_TIMCNT) /*!< MCNTR or CNTxCR register is updated by Burst DMA accesses */
2363 #define HRTIM_BURSTDMA_PER (HRTIM_BDTUPR_TIMPER) /*!< MPER or PERxR register is updated by Burst DMA accesses */
2364 #define HRTIM_BURSTDMA_REP (HRTIM_BDTUPR_TIMREP) /*!< MREPR or REPxR register is updated by Burst DMA accesses */
2365 #define HRTIM_BURSTDMA_CMP1 (HRTIM_BDTUPR_TIMCMP1) /*!< MCMP1R or CMP1xR register is updated by Burst DMA accesses */
2366 #define HRTIM_BURSTDMA_CMP2 (HRTIM_BDTUPR_TIMCMP2) /*!< MCMP2R or CMP2xR register is updated by Burst DMA accesses */
2367 #define HRTIM_BURSTDMA_CMP3 (HRTIM_BDTUPR_TIMCMP3) /*!< MCMP3R or CMP3xR register is updated by Burst DMA accesses */
2368 #define HRTIM_BURSTDMA_CMP4 (HRTIM_BDTUPR_TIMCMP4) /*!< MCMP4R or CMP4xR register is updated by Burst DMA accesses */
2369 #define HRTIM_BURSTDMA_DTR (HRTIM_BDTUPR_TIMDTR) /*!< TDxR register is updated by Burst DMA accesses */
2370 #define HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R) /*!< SET1R register is updated by Burst DMA accesses */
2371 #define HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R) /*!< RST1R register is updated by Burst DMA accesses */
2372 #define HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R) /*!< SET2R register is updated by Burst DMA accesses */
2373 #define HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R) /*!< RST1R register is updated by Burst DMA accesses */
2374 #define HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1) /*!< EEFxR1 register is updated by Burst DMA accesses */
2375 #define HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2) /*!< EEFxR2 register is updated by Burst DMA accesses */
2376 #define HRTIM_BURSTDMA_RSTR (HRTIM_BDTUPR_TIMRSTR) /*!< RSTxR register is updated by Burst DMA accesses */
2377 #define HRTIM_BURSTDMA_CHPR (HRTIM_BDTUPR_TIMCHPR) /*!< CHPxR register is updated by Burst DMA accesses */
2378 #define HRTIM_BURSTDMA_OUTR (HRTIM_BDTUPR_TIMOUTR) /*!< OUTxR register is updated by Burst DMA accesses */
2379 #define HRTIM_BURSTDMA_FLTR (HRTIM_BDTUPR_TIMFLTR) /*!< FLTxR register is updated by Burst DMA accesses */
2380
2381 #define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \
2382 ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFFC000) == 0x00000000)) \
2383 || \
2384 (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
2385 || \
2386 (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
2387 || \
2388 (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
2389 || \
2390 (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)) \
2391 || \
2392 (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000) == 0x00000000)))
2393 /**
2394 * @}
2395 */
2396
2397 /** @defgroup HRTIM_Burst_Mode_Control HRTIM Burst Mode Control
2398 * @{
2399 * @brief Constants used to enable or disable the burst mode controller
2400 */
2401 #define HRTIM_BURSTMODECTL_DISABLED (uint32_t)0x00000000 /*!< Burst mode disabled */
2402 #define HRTIM_BURSTMODECTL_ENABLED (HRTIM_BMCR_BME) /*!< Burst mode enabled */
2403
2404 #define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\
2405 (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \
2406 ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED))
2407 /**
2408 * @}
2409 */
2410
2411 /** @defgroup HRTIM_Fault_Mode_Control HRTIM Fault Mode Control
2412 * @{
2413 * @brief Constants used to enable or disable a fault channel
2414 */
2415 #define HRTIM_FAULTMODECTL_DISABLED (uint32_t)0x00000000 /*!< Fault channel is disabled */
2416 #define HRTIM_FAULTMODECTL_ENABLED (uint32_t)0x00000001 /*!< Fault channel is enabled */
2417
2418 #define IS_HRTIM_FAULTMODECTL(FAULTMODECTL)\
2419 (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED) || \
2420 ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED))
2421 /**
2422 * @}
2423 */
2424
2425 /** @defgroup HRTIM_Software_Timer_Update HRTIM Software Timer Update
2426 * @{
2427 * @brief Constants used to force timer registers update
2428 */
2429 #define HRTIM_TIMERUPDATE_MASTER (HRTIM_CR2_MSWU) /*!< Forces an immediate transfer from the preload to the active register in the master timer */
2430 #define HRTIM_TIMERUPDATE_A (HRTIM_CR2_TASWU) /*!< Forces an immediate transfer from the preload to the active register in the timer A */
2431 #define HRTIM_TIMERUPDATE_B (HRTIM_CR2_TBSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer B */
2432 #define HRTIM_TIMERUPDATE_C (HRTIM_CR2_TCSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer C */
2433 #define HRTIM_TIMERUPDATE_D (HRTIM_CR2_TDSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer D */
2434 #define HRTIM_TIMERUPDATE_E (HRTIM_CR2_TESWU) /*!< Forces an immediate transfer from the preload to the active register in the timer E */
2435
2436 #define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0) == 0x00000000)
2437 /**
2438 * @}
2439 */
2440
2441 /** @defgroup HRTIM_Software_Timer_Reset HRTIM Software Timer Reset
2442 * @{
2443 * @brief Constants used to force timer counter reset
2444 */
2445 #define HRTIM_TIMERRESET_MASTER (HRTIM_CR2_MRST) /*!< Resets the master timer counter */
2446 #define HRTIM_TIMERRESET_TIMER_A (HRTIM_CR2_TARST) /*!< Resets the timer A counter */
2447 #define HRTIM_TIMERRESET_TIMER_B (HRTIM_CR2_TBRST) /*!< Resets the timer B counter */
2448 #define HRTIM_TIMERRESET_TIMER_C (HRTIM_CR2_TCRST) /*!< Resets the timer C counter */
2449 #define HRTIM_TIMERRESET_TIMER_D (HRTIM_CR2_TDRST) /*!< Resets the timer D counter */
2450 #define HRTIM_TIMERRESET_TIMER_E (HRTIM_CR2_TERST) /*!< Resets the timer E counter */
2451
2452 #define IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFFC0FF) == 0x00000000)
2453 /**
2454 * @}
2455 */
2456
2457 /** @defgroup HRTIM_Output_Level HRTIM Output Level
2458 * @{
2459 * @brief Constants defining the level of a timer output
2460 */
2461 #define HRTIM_OUTPUTLEVEL_ACTIVE (uint32_t)0x00000001 /*!< Forces the output to its active state */
2462 #define HRTIM_OUTPUTLEVEL_INACTIVE (uint32_t)0x00000002 /*!< Forces the output to its inactive state */
2463
2464 #define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\
2465 (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) || \
2466 ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE))
2467 /**
2468 * @}
2469 */
2470
2471 /** @defgroup HRTIM_Output_State HRTIM Output State
2472 * @{
2473 * @brief Constants defining the state of a timer output
2474 */
2475 #define HRTIM_OUTPUTSTATE_IDLE (uint32_t)0x00000001 /*!< Main operating mode, where the output can take the active or
2476 inactive level as programmed in the crossbar unit */
2477 #define HRTIM_OUTPUTSTATE_RUN (uint32_t)0x00000002 /*!< Default operating state (e.g. after an HRTIM reset, when the
2478 outputs are disabled by software or during a burst mode operation */
2479 #define HRTIM_OUTPUTSTATE_FAULT (uint32_t)0x00000003 /*!< Safety state, entered in case of a shut-down request on
2480 FAULTx inputs */
2481 /**
2482 * @}
2483 */
2484
2485 /** @defgroup HRTIM_Burst_Mode_Status HRTIM Burst Mode Status
2486 * @{
2487 * @brief Constants defining the operating state of the burst mode controller
2488 */
2489 #define HRTIM_BURSTMODESTATUS_NORMAL (uint32_t) 0x00000000 /*!< Normal operation */
2490 #define HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT) /*!< Burst operation on-going */
2491 /**
2492 * @}
2493 */
2494
2495 /** @defgroup HRTIM_Current_Push_Pull_Status HRTIM Current Push Pull Status
2496 * @{
2497 * @brief Constants defining on which output the signal is currently applied
2498 * in push-pull mode
2499 */
2500 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1 (uint32_t) 0x00000000 /*!< Signal applied on output 1 and output 2 forced inactive */
2501 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /*!< Signal applied on output 2 and output 1 forced inactive */
2502 /**
2503 * @}
2504 */
2505
2506 /** @defgroup HRTIM_Idle_Push_Pull_Status HRTIM Idle Push Pull Status
2507 * @{
2508 * @brief Constants defining on which output the signal was applied, in
2509 * push-pull mode balanced fault mode or delayed idle mode, when the
2510 * protection was triggered
2511 */
2512 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1 (uint32_t) 0x00000000 /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
2513 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /*!< Protection occurred when the output 2 was active and output 1 forced inactive */
2514 /**
2515 * @}
2516 */
2517
2518 /** @defgroup HRTIM_Common_Interrupt_Enable HRTIM Common Interrupt Enable
2519 * @{
2520 */
2521 #define HRTIM_IT_NONE (uint32_t)0x00000000 /*!< No interrupt enabled */
2522 #define HRTIM_IT_FLT1 HRTIM_IER_FLT1 /*!< Fault 1 interrupt enable */
2523 #define HRTIM_IT_FLT2 HRTIM_IER_FLT2 /*!< Fault 2 interrupt enable */
2524 #define HRTIM_IT_FLT3 HRTIM_IER_FLT3 /*!< Fault 3 interrupt enable */
2525 #define HRTIM_IT_FLT4 HRTIM_IER_FLT4 /*!< Fault 4 interrupt enable */
2526 #define HRTIM_IT_FLT5 HRTIM_IER_FLT5 /*!< Fault 5 interrupt enable */
2527 #define HRTIM_IT_SYSFLT HRTIM_IER_SYSFLT /*!< System Fault interrupt enable */
2528 #define HRTIM_IT_DLLRDY HRTIM_IER_DLLRDY /*!< DLL ready interrupt enable */
2529 #define HRTIM_IT_BMPER HRTIM_IER_BMPER /*!< Burst mode period interrupt enable */
2530
2531 #define IS_HRTIM_IT(IT) (((IT) & 0xFFFCFFC0) == 0x00000000)
2532
2533 /**
2534 * @}
2535 */
2536
2537 /** @defgroup HRTIM_Master_Interrupt_Enable HRTIM Master Interrupt Enable
2538 * @{
2539 */
2540 #define HRTIM_MASTER_IT_NONE (uint32_t)0x00000000 /*!< No interrupt enabled */
2541 #define HRTIM_MASTER_IT_MCMP1 HRTIM_MDIER_MCMP1IE /*!< Master compare 1 interrupt enable */
2542 #define HRTIM_MASTER_IT_MCMP2 HRTIM_MDIER_MCMP2IE /*!< Master compare 2 interrupt enable */
2543 #define HRTIM_MASTER_IT_MCMP3 HRTIM_MDIER_MCMP3IE /*!< Master compare 3 interrupt enable */
2544 #define HRTIM_MASTER_IT_MCMP4 HRTIM_MDIER_MCMP4IE /*!< Master compare 4 interrupt enable */
2545 #define HRTIM_MASTER_IT_MREP HRTIM_MDIER_MREPIE /*!< Master Repetition interrupt enable */
2546 #define HRTIM_MASTER_IT_SYNC HRTIM_MDIER_SYNCIE /*!< Synchronization input interrupt enable */
2547 #define HRTIM_MASTER_IT_MUPD HRTIM_MDIER_MUPDIE /*!< Master update interrupt enable */
2548
2549 #define IS_HRTIM_MASTER_IT(MASTER_IT) (((MASTER_IT) & 0xFFFFFF80) == 0x00000000)
2550
2551 /**
2552 * @}
2553 */
2554
2555 /** @defgroup HRTIM_Timing_Unit_Interrupt_Enable HRTIM Timing Unit Interrupt Enable
2556 * @{
2557 */
2558 #define HRTIM_TIM_IT_NONE (uint32_t)0x00000000 /*!< No interrupt enabled */
2559 #define HRTIM_TIM_IT_CMP1 HRTIM_TIMDIER_CMP1IE /*!< Timer compare 1 interrupt enable */
2560 #define HRTIM_TIM_IT_CMP2 HRTIM_TIMDIER_CMP2IE /*!< Timer compare 2 interrupt enable */
2561 #define HRTIM_TIM_IT_CMP3 HRTIM_TIMDIER_CMP3IE /*!< Timer compare 3 interrupt enable */
2562 #define HRTIM_TIM_IT_CMP4 HRTIM_TIMDIER_CMP4IE /*!< Timer compare 4 interrupt enable */
2563 #define HRTIM_TIM_IT_REP HRTIM_TIMDIER_REPIE /*!< Timer repetition interrupt enable */
2564 #define HRTIM_TIM_IT_UPD HRTIM_TIMDIER_UPDIE /*!< Timer update interrupt enable */
2565 #define HRTIM_TIM_IT_CPT1 HRTIM_TIMDIER_CPT1IE /*!< Timer capture 1 interrupt enable */
2566 #define HRTIM_TIM_IT_CPT2 HRTIM_TIMDIER_CPT2IE /*!< Timer capture 2 interrupt enable */
2567 #define HRTIM_TIM_IT_SET1 HRTIM_TIMDIER_SET1IE /*!< Timer output 1 set interrupt enable */
2568 #define HRTIM_TIM_IT_RST1 HRTIM_TIMDIER_RST1IE /*!< Timer output 1 reset interrupt enable */
2569 #define HRTIM_TIM_IT_SET2 HRTIM_TIMDIER_SET2IE /*!< Timer output 2 set interrupt enable */
2570 #define HRTIM_TIM_IT_RST2 HRTIM_TIMDIER_RST2IE /*!< Timer output 2 reset interrupt enable */
2571 #define HRTIM_TIM_IT_RST HRTIM_TIMDIER_RSTIE /*!< Timer reset interrupt enable */
2572 #define HRTIM_TIM_IT_DLYPRT HRTIM_TIMDIER_DLYPRTIE /*!< Timer delay protection interrupt enable */
2573
2574 #define IS_HRTIM_TIM_IT(IS_HRTIM_TIM_IT) (((IS_HRTIM_TIM_IT) & 0xFFFF8020) == 0x00000000)
2575
2576 /**
2577 * @}
2578 */
2579
2580 /** @defgroup HRTIM_Common_Interrupt_Flag HRTIM Common Interrupt Flag
2581 * @{
2582 */
2583 #define HRTIM_FLAG_FLT1 HRTIM_ISR_FLT1 /*!< Fault 1 interrupt flag */
2584 #define HRTIM_FLAG_FLT2 HRTIM_ISR_FLT2 /*!< Fault 2 interrupt flag */
2585 #define HRTIM_FLAG_FLT3 HRTIM_ISR_FLT3 /*!< Fault 3 interrupt flag */
2586 #define HRTIM_FLAG_FLT4 HRTIM_ISR_FLT4 /*!< Fault 4 interrupt flag */
2587 #define HRTIM_FLAG_FLT5 HRTIM_ISR_FLT5 /*!< Fault 5 interrupt flag */
2588 #define HRTIM_FLAG_SYSFLT HRTIM_ISR_SYSFLT /*!< System Fault interrupt flag */
2589 #define HRTIM_FLAG_DLLRDY HRTIM_ISR_DLLRDY /*!< DLL ready interrupt flag */
2590 #define HRTIM_FLAG_BMPER HRTIM_ISR_BMPER /*!< Burst mode period interrupt flag */
2591
2592 /**
2593 * @}
2594 */
2595
2596 /** @defgroup HRTIM_Master_Interrupt_Flag HRTIM Master Interrupt Flag
2597 * @{
2598 */
2599 #define HRTIM_MASTER_FLAG_MCMP1 HRTIM_MISR_MCMP1 /*!< Master compare 1 interrupt flag */
2600 #define HRTIM_MASTER_FLAG_MCMP2 HRTIM_MISR_MCMP2 /*!< Master compare 2 interrupt flag */
2601 #define HRTIM_MASTER_FLAG_MCMP3 HRTIM_MISR_MCMP3 /*!< Master compare 3 interrupt flag */
2602 #define HRTIM_MASTER_FLAG_MCMP4 HRTIM_MISR_MCMP4 /*!< Master compare 4 interrupt flag */
2603 #define HRTIM_MASTER_FLAG_MREP HRTIM_MISR_MREP /*!< Master Repetition interrupt flag */
2604 #define HRTIM_MASTER_FLAG_SYNC HRTIM_MISR_SYNC /*!< Synchronization input interrupt flag */
2605 #define HRTIM_MASTER_FLAG_MUPD HRTIM_MISR_MUPD /*!< Master update interrupt flag */
2606
2607 /**
2608 * @}
2609 */
2610
2611 /** @defgroup HRTIM_Timing_Unit_Interrupt_Flag HRTIM Timing Unit Interrupt Flag
2612 * @{
2613 */
2614 #define HRTIM_TIM_FLAG_CMP1 HRTIM_TIMISR_CMP1 /*!< Timer compare 1 interrupt flag */
2615 #define HRTIM_TIM_FLAG_CMP2 HRTIM_TIMISR_CMP2 /*!< Timer compare 2 interrupt flag */
2616 #define HRTIM_TIM_FLAG_CMP3 HRTIM_TIMISR_CMP3 /*!< Timer compare 3 interrupt flag */
2617 #define HRTIM_TIM_FLAG_CMP4 HRTIM_TIMISR_CMP4 /*!< Timer compare 4 interrupt flag */
2618 #define HRTIM_TIM_FLAG_REP HRTIM_TIMISR_REP /*!< Timer repetition interrupt flag */
2619 #define HRTIM_TIM_FLAG_UPD HRTIM_TIMISR_UPD /*!< Timer update interrupt flag */
2620 #define HRTIM_TIM_FLAG_CPT1 HRTIM_TIMISR_CPT1 /*!< Timer capture 1 interrupt flag */
2621 #define HRTIM_TIM_FLAG_CPT2 HRTIM_TIMISR_CPT2 /*!< Timer capture 2 interrupt flag */
2622 #define HRTIM_TIM_FLAG_SET1 HRTIM_TIMISR_SET1 /*!< Timer output 1 set interrupt flag */
2623 #define HRTIM_TIM_FLAG_RST1 HRTIM_TIMISR_RST1 /*!< Timer output 1 reset interrupt flag */
2624 #define HRTIM_TIM_FLAG_SET2 HRTIM_TIMISR_SET2 /*!< Timer output 2 set interrupt flag */
2625 #define HRTIM_TIM_FLAG_RST2 HRTIM_TIMISR_RST2 /*!< Timer output 2 reset interrupt flag */
2626 #define HRTIM_TIM_FLAG_RST HRTIM_TIMISR_RST /*!< Timer reset interrupt flag */
2627 #define HRTIM_TIM_FLAG_DLYPRT HRTIM_TIMISR_DLYPRT /*!< Timer delay protection interrupt flag */
2628
2629 /**
2630 * @}
2631 */
2632
2633 /** @defgroup HRTIM_Master_DMA_Request_Enable HRTIM Master DMA Request Enable
2634 * @{
2635 */
2636 #define HRTIM_MASTER_DMA_NONE (uint32_t)0x00000000 /*!< No DMA request enable */
2637 #define HRTIM_MASTER_DMA_MCMP1 HRTIM_MDIER_MCMP1DE /*!< Master compare 1 DMA request enable */
2638 #define HRTIM_MASTER_DMA_MCMP2 HRTIM_MDIER_MCMP2DE /*!< Master compare 2 DMA request enable */
2639 #define HRTIM_MASTER_DMA_MCMP3 HRTIM_MDIER_MCMP3DE /*!< Master compare 3 DMA request enable */
2640 #define HRTIM_MASTER_DMA_MCMP4 HRTIM_MDIER_MCMP4DE /*!< Master compare 4 DMA request enable */
2641 #define HRTIM_MASTER_DMA_MREP HRTIM_MDIER_MREPDE /*!< Master Repetition DMA request enable */
2642 #define HRTIM_MASTER_DMA_SYNC HRTIM_MDIER_SYNCDE /*!< Synchronization input DMA request enable */
2643 #define HRTIM_MASTER_DMA_MUPD HRTIM_MDIER_MUPDDE /*!< Master update DMA request enable */
2644
2645 #define IS_HRTIM_MASTER_DMA(MASTER_DMA) (((MASTER_DMA) & 0xFF80FFFF) == 0x00000000)
2646 /**
2647 * @}
2648 */
2649
2650 /** @defgroup HRTIM_Timing_Unit_DMA_Request_Enable HRTIM Timing Unit DMA Request Enable
2651 * @{
2652 */
2653 #define HRTIM_TIM_DMA_NONE (uint32_t)0x00000000 /*!< No DMA request enable */
2654 #define HRTIM_TIM_DMA_CMP1 HRTIM_TIMDIER_CMP1DE /*!< Timer compare 1 DMA request enable */
2655 #define HRTIM_TIM_DMA_CMP2 HRTIM_TIMDIER_CMP2DE /*!< Timer compare 2 DMA request enable */
2656 #define HRTIM_TIM_DMA_CMP3 HRTIM_TIMDIER_CMP3DE /*!< Timer compare 3 DMA request enable */
2657 #define HRTIM_TIM_DMA_CMP4 HRTIM_TIMDIER_CMP4DE /*!< Timer compare 4 DMA request enable */
2658 #define HRTIM_TIM_DMA_REP HRTIM_TIMDIER_REPDE /*!< Timer repetition DMA request enable */
2659 #define HRTIM_TIM_DMA_UPD HRTIM_TIMDIER_UPDDE /*!< Timer update DMA request enable */
2660 #define HRTIM_TIM_DMA_CPT1 HRTIM_TIMDIER_CPT1DE /*!< Timer capture 1 DMA request enable */
2661 #define HRTIM_TIM_DMA_CPT2 HRTIM_TIMDIER_CPT2DE /*!< Timer capture 2 DMA request enable */
2662 #define HRTIM_TIM_DMA_SET1 HRTIM_TIMDIER_SET1DE /*!< Timer output 1 set DMA request enable */
2663 #define HRTIM_TIM_DMA_RST1 HRTIM_TIMDIER_RST1DE /*!< Timer output 1 reset DMA request enable */
2664 #define HRTIM_TIM_DMA_SET2 HRTIM_TIMDIER_SET2DE /*!< Timer output 2 set DMA request enable */
2665 #define HRTIM_TIM_DMA_RST2 HRTIM_TIMDIER_RST2DE /*!< Timer output 2 reset DMA request enable */
2666 #define HRTIM_TIM_DMA_RST HRTIM_TIMDIER_RSTDE /*!< Timer reset DMA request enable */
2667 #define HRTIM_TIM_DMA_DLYPRT HRTIM_TIMDIER_DLYPRTDE /*!< Timer delay protection DMA request enable */
2668
2669 #define IS_HRTIM_TIM_DMA(TIM_DMA) (((TIM_DMA) & 0x8020FFFF) == 0x00000000)
2670
2671 /**
2672 * @}
2673 */
2674
2675 /**
2676 * @}
2677 */
2678
2679 /* Exported macros -----------------------------------------------------------*/
2680 /** @defgroup HRTIM_Exported_Macros HRTIM Exported Macros
2681 * @{
2682 */
2683
2684 /** @brief Reset HRTIM handle state
2685 * @param __HANDLE__: HRTIM handle.
2686 * @retval None
2687 */
2688 #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET)
2689
2690 /** @brief Enables or disables the timer counter(s)
2691 * @param __HANDLE__: specifies the HRTIM Handle.
2692 * @param __TIMERS__: timersto enable/disable
2693 * This parameter can be any combinations of the following values:
2694 * @arg HRTIM_TIMERID_MASTER: Master timer identifier
2695 * @arg HRTIM_TIMERID_TIMER_A: Timer A identifier
2696 * @arg HRTIM_TIMERID_TIMER_B: Timer B identifier
2697 * @arg HRTIM_TIMERID_TIMER_C: Timer C identifier
2698 * @arg HRTIM_TIMERID_TIMER_D: Timer D identifier
2699 * @arg HRTIM_TIMERID_TIMER_E: Timer E identifier
2700 * @retval None
2701 */
2702 #define __HAL_HRTIM_ENABLE(__HANDLE__, __TIMERS__) ((__HANDLE__)->Instance->sMasterRegs.MCR |= (__TIMERS__))
2703
2704 /* The counter of a timing unit is disabled only if all the timer outputs */
2705 /* are disabled and no capture is configured */
2706 #define HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN | HRTIM_OENR_TA1OEN)
2707 #define HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN | HRTIM_OENR_TB1OEN)
2708 #define HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN | HRTIM_OENR_TC1OEN)
2709 #define HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN | HRTIM_OENR_TD1OEN)
2710 #define HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN | HRTIM_OENR_TE1OEN)
2711 #define __HAL_HRTIM_DISABLE(__HANDLE__, __TIMERS__)\
2712 do {\
2713 if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\
2714 {\
2715 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\
2716 }\
2717 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\
2718 {\
2719 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == RESET)\
2720 {\
2721 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\
2722 }\
2723 }\
2724 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\
2725 {\
2726 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == RESET)\
2727 {\
2728 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\
2729 }\
2730 }\
2731 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\
2732 {\
2733 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == RESET)\
2734 {\
2735 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\
2736 }\
2737 }\
2738 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\
2739 {\
2740 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == RESET)\
2741 {\
2742 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\
2743 }\
2744 }\
2745 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\
2746 {\
2747 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == RESET)\
2748 {\
2749 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\
2750 }\
2751 }\
2752 } while(0)
2753
2754 /** @brief Enables or disables the specified HRTIM common interrupts.
2755 * @param __HANDLE__: specifies the HRTIM Handle.
2756 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
2757 * This parameter can be one of the following values:
2758 * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
2759 * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
2760 * @arg HRTIM_IT_FLT3: Fault 3 interrupt enable
2761 * @arg HRTIM_IT_FLT4: Fault 4 interrupt enable
2762 * @arg HRTIM_IT_FLT5: Fault 5 interrupt enable
2763 * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
2764 * @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
2765 * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
2766 * @retval None
2767 */
2768 #define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__))
2769 #define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
2770
2771 /** @brief Enables or disables the specified HRTIM Master timer interrupts.
2772 * @param __HANDLE__: specifies the HRTIM Handle.
2773 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
2774 * This parameter can be one of the following values:
2775 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
2776 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
2777 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
2778 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
2779 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
2780 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
2781 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
2782 * @retval None
2783 */
2784 #define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__INTERRUPT__))
2785 #define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__INTERRUPT__))
2786
2787 /** @brief Enables or disables the specified HRTIM Timerx interrupts.
2788 * @param __HANDLE__: specifies the HRTIM Handle.
2789 * @param __TIMER__: specified the timing unit (Timer A to E)
2790 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
2791 * This parameter can be one of the following values:
2792 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
2793 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
2794 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
2795 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
2796 * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
2797 * @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
2798 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
2799 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
2800 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
2801 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
2802 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
2803 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
2804 * @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
2805 * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
2806 * @retval None
2807 */
2808 #define __HAL_HRTIM_TIMER_ENABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__INTERRUPT__))
2809 #define __HAL_HRTIM_TIMER_DISABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__INTERRUPT__))
2810
2811 /** @brief Checks if the specified HRTIM common interrupt source is enabled or disabled.
2812 * @param __HANDLE__: specifies the HRTIM Handle.
2813 * @param __INTERRUPT__: specifies the interrupt source to check.
2814 * This parameter can be one of the following values:
2815 * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
2816 * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
2817 * @arg HRTIM_IT_FLT3: Fault 3 enable
2818 * @arg HRTIM_IT_FLT4: Fault 4 enable
2819 * @arg HRTIM_IT_FLT5: Fault 5 enable
2820 * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
2821 * @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
2822 * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
2823 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
2824 */
2825 #define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sCommonRegs.IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
2826
2827 /** @brief Checks if the specified HRTIM Master interrupt source is enabled or disabled.
2828 * @param __HANDLE__: specifies the HRTIM Handle.
2829 * @param __INTERRUPT__: specifies the interrupt source to check.
2830 * This parameter can be one of the following values:
2831 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
2832 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
2833 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
2834 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
2835 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
2836 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
2837 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
2838 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
2839 */
2840 #define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
2841
2842 /** @brief Checks if the specified HRTIM Timerx interrupt source is enabled or disabled.
2843 * @param __HANDLE__: specifies the HRTIM Handle.
2844 * @param __TIMER__: specified the timing unit (Timer A to E)
2845 * @param __INTERRUPT__: specifies the interrupt source to check.
2846 * This parameter can be one of the following values:
2847 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
2848 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
2849 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
2850 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
2851 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
2852 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
2853 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
2854 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
2855 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
2856 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
2857 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
2858 * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
2859 * @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
2860 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
2861 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
2862 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
2863 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
2864 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
2865 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
2866 * @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
2867 * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
2868 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
2869 */
2870 #define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__) ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
2871
2872 /** @brief Clears the specified HRTIM common pending flag.
2873 * @param __HANDLE__: specifies the HRTIM Handle.
2874 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
2875 * This parameter can be one of the following values:
2876 * @arg HRTIM_IT_FLT1: Fault 1 interrupt clear flag
2877 * @arg HRTIM_IT_FLT2: Fault 2 interrupt clear flag
2878 * @arg HRTIM_IT_FLT3: Fault 3 clear flag
2879 * @arg HRTIM_IT_FLT4: Fault 4 clear flag
2880 * @arg HRTIM_IT_FLT5: Fault 5 clear flag
2881 * @arg HRTIM_IT_SYSFLT: System Fault interrupt clear flag
2882 * @arg HRTIM_IT_DLLRDY: DLL ready interrupt clear flag
2883 * @arg HRTIM_IT_BMPER: Burst mode period interrupt clear flag
2884 * @retval None
2885 */
2886 #define __HAL_HRTIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__INTERRUPT__))
2887
2888 /** @brief Clears the specified HRTIM Master pending flag.
2889 * @param __HANDLE__: specifies the HRTIM Handle.
2890 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
2891 * This parameter can be one of the following values:
2892 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt clear flag
2893 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt clear flag
2894 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt clear flag
2895 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt clear flag
2896 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt clear flag
2897 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt clear flag
2898 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt clear flag
2899 * @retval None
2900 */
2901 #define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__INTERRUPT__))
2902
2903 /** @brief Clears the specified HRTIM Timerx pending flag.
2904 * @param __HANDLE__: specifies the HRTIM Handle.
2905 * @param __TIMER__: specified the timing unit (Timer A to E)
2906 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
2907 * This parameter can be one of the following values:
2908 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt clear flag
2909 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt clear flag
2910 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt clear flag
2911 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt clear flag
2912 * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt clear flag
2913 * @arg HRTIM_TIM_IT_UPD: Timer update interrupt clear flag
2914 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt clear flag
2915 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt clear flag
2916 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt clear flag
2917 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt clear flag
2918 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt clear flag
2919 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt clear flag
2920 * @arg HRTIM_TIM_IT_RST: Timer reset interrupt clear flag
2921 * @arg HRTIM_TIM_IT_DLYPRT: Timer output 1 delay protection interrupt clear flag
2922 * @retval None
2923 */
2924 #define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__INTERRUPT__))
2925
2926 /* DMA HANDLING */
2927 /** @brief Enables or disables the specified HRTIM common interrupts.
2928 * @param __HANDLE__: specifies the HRTIM Handle.
2929 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
2930 * This parameter can be one of the following values:
2931 * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
2932 * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
2933 * @arg HRTIM_IT_FLT3: Fault 3 interrupt enable
2934 * @arg HRTIM_IT_FLT4: Fault 4 interrupt enable
2935 * @arg HRTIM_IT_FLT5: Fault 5 interrupt enable
2936 * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
2937 * @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
2938 * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
2939 * @retval None
2940 */
2941 #define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__))
2942 #define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
2943
2944 /** @brief Enables or disables the specified HRTIM Master timer DMA requets.
2945 * @param __HANDLE__: specifies the HRTIM Handle.
2946 * @param __DMA__: specifies the DMA request to enable or disable.
2947 * This parameter can be one of the following values:
2948 * @arg HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA resquest enable
2949 * @arg HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA resquest enable
2950 * @arg HRTIM_MASTER_DMA_MCMP3: Master compare 3 DMA resquest enable
2951 * @arg HRTIM_MASTER_DMA_MCMP4: Master compare 4 DMA resquest enable
2952 * @arg HRTIM_MASTER_DMA_MREP: Master Repetition DMA resquest enable
2953 * @arg HRTIM_MASTER_DMA_SYNC: Synchronization input DMA resquest enable
2954 * @arg HRTIM_MASTER_DMA_MUPD: Master update DMA resquest enable
2955 * @retval None
2956 */
2957 #define __HAL_HRTIM_MASTER_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__DMA__))
2958 #define __HAL_HRTIM_MASTER_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__DMA__))
2959
2960 /** @brief Enables or disables the specified HRTIM Timerx DMA requests.
2961 * @param __HANDLE__: specifies the HRTIM Handle.
2962 * @param __TIMER__: specified the timing unit (Timer A to E)
2963 * @param __DMA__: specifies the DMA request to enable or disable.
2964 * This parameter can be one of the following values:
2965 * @arg HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA resquest enable
2966 * @arg HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA resquest enable
2967 * @arg HRTIM_TIM_DMA_CMP3: Timer compare 3 DMA resquest enable
2968 * @arg HRTIM_TIM_DMA_CMP4: Timer compare 4 DMA resquest enable
2969 * @arg HRTIM_TIM_DMA_REP: Timer repetition DMA resquest enable
2970 * @arg HRTIM_TIM_DMA_UPD: Timer update DMA resquest enable
2971 * @arg HRTIM_TIM_DMA_CPT1: Timer capture 1 DMA resquest enable
2972 * @arg HRTIM_TIM_DMA_CPT2: Timer capture 2 DMA resquest enable
2973 * @arg HRTIM_TIM_DMA_SET1: Timer output 1 set DMA resquest enable
2974 * @arg HRTIM_TIM_DMA_RST1: Timer output 1 reset DMA resquest enable
2975 * @arg HRTIM_TIM_DMA_SET2: Timer output 2 set DMA resquest enable
2976 * @arg HRTIM_TIM_DMA_RST2: Timer output 2 reset DMA resquest enable
2977 * @arg HRTIM_TIM_DMA_RST: Timer reset DMA resquest enable
2978 * @arg HRTIM_TIM_DMA_DLYPRT: Timer delay protection DMA resquest enable
2979 * @retval None
2980 */
2981 #define __HAL_HRTIM_TIMER_ENABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__DMA__))
2982 #define __HAL_HRTIM_TIMER_DISABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__))
2983
2984 #define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sCommonRegs.ISR & (__FLAG__)) == (__FLAG__))
2985 #define __HAL_HRTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__))
2986
2987 #define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sMasterRegs.MISR & (__FLAG__)) == (__FLAG__))
2988 #define __HAL_HRTIM_MASTER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__))
2989
2990 #define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__, __TIMER__, __FLAG__) (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR & (__FLAG__)) == (__FLAG__))
2991 #define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__, __TIMER__, __FLAG__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__FLAG__))
2992
2993 /** @brief Sets the HRTIM timer Counter Register value on runtime
2994 * @param __HANDLE__: HRTIM Handle.
2995 * @param __TIMER__: HRTIM timer
2996 * This parameter can be one of the following values:
2997 * @arg 0x5 for master timer
2998 * @arg 0x0 to 0x4 for timers A to E
2999 * @param __COUNTER__: specifies the Counter Register new value.
3000 * @retval None
3001 */
3002 #define __HAL_HRTIM_SetCounter(__HANDLE__, __TIMER__, __COUNTER__) \
3003 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR = (__COUNTER__)) :\
3004 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR = (__COUNTER__)))
3005
3006 /** @brief Gets the HRTIM timer Counter Register value on runtime
3007 * @param __HANDLE__: HRTIM Handle.
3008 * @param __TIMER__: HRTIM timer
3009 * This parameter can be one of the following values:
3010 * @arg 0x5 for master timer
3011 * @arg 0x0 to 0x4 for timers A to E
3012 * @retval HRTIM timer Counter Register value
3013 */
3014 #define __HAL_HRTIM_GetCounter(__HANDLE__, __TIMER__) \
3015 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR) :\
3016 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR))
3017
3018 /** @brief Sets the HRTIM timer Period value on runtime
3019 * @param __HANDLE__: HRTIM Handle.
3020 * @param __TIMER__: HRTIM timer
3021 * This parameter can be one of the following values:
3022 * @arg 0x5 for master timer
3023 * @arg 0x0 to 0x4 for timers A to E
3024 * @param __PERIOD__: specifies the Period Register new value.
3025 * @retval None
3026 */
3027 #define __HAL_HRTIM_SetPeriod(__HANDLE__, __TIMER__, __PERIOD__) \
3028 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER = (__PERIOD__)) :\
3029 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR = (__PERIOD__)))
3030
3031 /** @brief Gets the HRTIM timer Period Register value on runtime
3032 * @param __HANDLE__: HRTIM Handle.
3033 * @param __TIMER__: HRTIM timer
3034 * This parameter can be one of the following values:
3035 * @arg 0x5 for master timer
3036 * @arg 0x0 to 0x4 for timers A to E
3037 * @retval timer Period Register
3038 */
3039 #define __HAL_HRTIM_GetPeriod(__HANDLE__, __TIMER__) \
3040 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER) :\
3041 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR))
3042
3043 /** @brief Sets the HRTIM timer clock prescaler value on runtime
3044 * @param __HANDLE__: HRTIM Handle.
3045 * @param __TIMER__: HRTIM timer
3046 * This parameter can be one of the following values:
3047 * @arg 0x5 for master timer
3048 * @arg 0x0 to 0x4 for timers A to E
3049 * @param __PRESCALER__: specifies the clock prescaler new value.
3050 * This parameter can be one of the following values:
3051 * @arg HRTIM_PRESCALERRATIO_MUL32: fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz)
3052 * @arg HRTIM_PRESCALERRATIO_MUL16: fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz)
3053 * @arg HRTIM_PRESCALERRATIO_MUL8: fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz)
3054 * @arg HRTIM_PRESCALERRATIO_MUL4: fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz)
3055 * @arg HRTIM_PRESCALERRATIO_MUL2: fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz)
3056 * @arg HRTIM_PRESCALERRATIO_DIV1: fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)
3057 * @arg HRTIM_PRESCALERRATIO_DIV2: fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)
3058 * @arg HRTIM_PRESCALERRATIO_DIV4: fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)
3059 * @retval None
3060 */
3061 #define __HAL_HRTIM_SetClockPrescaler(__HANDLE__, __TIMER__, __PRESCALER__) \
3062 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR |= (__PRESCALER__)) :\
3063 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR |= (__PRESCALER__)))
3064
3065 /** @brief Gets the HRTIM timer clock prescaler value on runtime
3066 * @param __HANDLE__: HRTIM Handle.
3067 * @param __TIMER__: HRTIM timer
3068 * This parameter can be one of the following values:
3069 * @arg 0x5 for master timer
3070 * @arg 0x0 to 0x4 for timers A to E
3071 * @retval timer clock prescaler value
3072 */
3073 #define __HAL_HRTIM_GetClockPrescaler(__HANDLE__, __TIMER__) \
3074 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR & HRTIM_MCR_CK_PSC) :\
3075 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR & HRTIM_TIMCR_CK_PSC))
3076
3077 /** @brief Sets the HRTIM timer Compare Register value on runtime
3078 * @param __HANDLE__: HRTIM Handle.
3079 * @param __TIMER__: HRTIM timer
3080 * This parameter can be one of the following values:
3081 * @arg 0x0 to 0x4 for timers A to E
3082 * @param __COMPAREUNIT__: timer compare unit
3083 * This parameter can be one of the following values:
3084 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
3085 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
3086 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
3087 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
3088 * @param __COMPARE__: specifies the Compare new value.
3089 * @retval None
3090 */
3091 #define __HAL_HRTIM_SetCompare(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__) \
3092 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
3093 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\
3094 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\
3095 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\
3096 ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \
3097 : \
3098 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\
3099 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\
3100 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\
3101 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__))))
3102
3103 /** @brief Gets the HRTIM timer Compare Register value on runtime
3104 * @param __HANDLE__: HRTIM Handle.
3105 * @param __TIMER__: HRTIM timer
3106 * This parameter can be one of the following values:
3107 * @arg 0x0 to 0x4 for timers A to E
3108 * @param __COMPAREUNIT__: timer compare unit
3109 * This parameter can be one of the following values:
3110 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
3111 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
3112 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
3113 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
3114 * @retval Compare value
3115 */
3116 #define __HAL_HRTIM_GetCompare(__HANDLE__, __TIMER__, __COMPAREUNIT__) \
3117 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
3118 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\
3119 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\
3120 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\
3121 ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \
3122 : \
3123 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\
3124 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\
3125 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\
3126 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR)))
3127
3128 /**
3129 * @}
3130 */
3131
3132 /* Exported functions --------------------------------------------------------*/
3133 /** @addtogroup HRTIM_Exported_Functions HRTIM Exported Functions
3134 * @{
3135 */
3136
3137 /** @addtogroup HRTIM_Exported_Functions_Group1 Initialization and de-initialization functions
3138 * @{
3139 */
3140
3141 /* Initialization and Configuration functions ********************************/
3142 HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim);
3143
3144 HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef *hhrtim);
3145
3146 void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim);
3147
3148 void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim);
3149
3150 HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
3151 uint32_t TimerIdx,
3152 HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
3153
3154 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef *hhrtim,
3155 uint32_t CalibrationRate);
3156
3157 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef *hhrtim,
3158 uint32_t CalibrationRate);
3159
3160 HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef *hhrtim,
3161 uint32_t Timeout);
3162
3163 /**
3164 * @}
3165 */
3166
3167 /** @addtogroup HRTIM_Exported_Functions_Group2 Simple time base mode functions
3168 * @{
3169 */
3170
3171 /* Simple time base related functions *****************************************/
3172 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim,
3173 uint32_t TimerIdx);
3174
3175 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim,
3176 uint32_t TimerIdx);
3177
3178 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim,
3179 uint32_t TimerIdx);
3180
3181 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim,
3182 uint32_t TimerIdx);
3183
3184 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim,
3185 uint32_t TimerIdx,
3186 uint32_t SrcAddr,
3187 uint32_t DestAddr,
3188 uint32_t Length);
3189
3190 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim,
3191 uint32_t TimerIdx);
3192
3193 /**
3194 * @}
3195 */
3196
3197 /** @addtogroup HRTIM_Exported_Functions_Group3 Simple output compare mode functions
3198 * @{
3199 */
3200 /* Simple output compare related functions ************************************/
3201 HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim,
3202 uint32_t TimerIdx,
3203 uint32_t OCChannel,
3204 HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg);
3205
3206 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim,
3207 uint32_t TimerIdx,
3208 uint32_t OCChannel);
3209
3210 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim,
3211 uint32_t TimerIdx,
3212 uint32_t OCChannel);
3213
3214 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim,
3215 uint32_t TimerIdx,
3216 uint32_t OCChannel);
3217
3218 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim,
3219 uint32_t TimerIdx,
3220 uint32_t OCChannel);
3221
3222 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim,
3223 uint32_t TimerIdx,
3224 uint32_t OCChannel,
3225 uint32_t SrcAddr,
3226 uint32_t DestAddr,
3227 uint32_t Length);
3228
3229 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim,
3230 uint32_t TimerIdx,
3231 uint32_t OCChannel);
3232
3233 /**
3234 * @}
3235 */
3236
3237 /** @addtogroup HRTIM_Exported_Functions_Group4 Simple PWM output mode functions
3238 * @{
3239 */
3240 /* Simple PWM output related functions ****************************************/
3241 HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim,
3242 uint32_t TimerIdx,
3243 uint32_t PWMChannel,
3244 HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg);
3245
3246 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim,
3247 uint32_t TimerIdx,
3248 uint32_t PWMChannel);
3249
3250 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim,
3251 uint32_t TimerIdx,
3252 uint32_t PWMChannel);
3253
3254 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim,
3255 uint32_t TimerIdx,
3256 uint32_t PWMChannel);
3257
3258 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim,
3259 uint32_t TimerIdx,
3260 uint32_t PWMChannel);
3261
3262 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim,
3263 uint32_t TimerIdx,
3264 uint32_t PWMChannel,
3265 uint32_t SrcAddr,
3266 uint32_t DestAddr,
3267 uint32_t Length);
3268
3269 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim,
3270 uint32_t TimerIdx,
3271 uint32_t PWMChannel);
3272
3273 /**
3274 * @}
3275 */
3276
3277 /** @addtogroup HRTIM_Exported_Functions_Group5 Simple input capture functions
3278 * @{
3279 */
3280 /* Simple capture related functions *******************************************/
3281 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim,
3282 uint32_t TimerIdx,
3283 uint32_t CaptureChannel,
3284 HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg);
3285
3286 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim,
3287 uint32_t TimerIdx,
3288 uint32_t CaptureChannel);
3289
3290 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim,
3291 uint32_t TimerIdx,
3292 uint32_t CaptureChannel);
3293
3294 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim,
3295 uint32_t TimerIdx,
3296 uint32_t CaptureChannel);
3297
3298 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim,
3299 uint32_t TimerIdx,
3300 uint32_t CaptureChannel);
3301
3302 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim,
3303 uint32_t TimerIdx,
3304 uint32_t CaptureChannel,
3305 uint32_t SrcAddr,
3306 uint32_t DestAddr,
3307 uint32_t Length);
3308
3309 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim,
3310 uint32_t TimerIdx,
3311 uint32_t CaptureChannel);
3312
3313 /**
3314 * @}
3315 */
3316
3317 /** @addtogroup HRTIM_Exported_Functions_Group6 Simple one pulse functions
3318 * @{
3319 */
3320 /* Simple one pulse related functions *****************************************/
3321 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim,
3322 uint32_t TimerIdx,
3323 uint32_t OnePulseChannel,
3324 HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg);
3325
3326 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim,
3327 uint32_t TimerIdx,
3328 uint32_t OnePulseChannel);
3329
3330 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim,
3331 uint32_t TimerIdx,
3332 uint32_t OnePulseChannel);
3333
3334 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim,
3335 uint32_t TimerIdx,
3336 uint32_t OnePulseChannel);
3337
3338 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim,
3339 uint32_t TimerIdx,
3340 uint32_t OnePulseChannel);
3341
3342 /**
3343 * @}
3344 */
3345
3346 /** @addtogroup HRTIM_Exported_Functions_Group7 Configuration functions
3347 * @{
3348 */
3349 HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim,
3350 HRTIM_BurstModeCfgTypeDef* pBurstModeCfg);
3351
3352 HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim,
3353 uint32_t Event,
3354 HRTIM_EventCfgTypeDef* pEventCfg);
3355
3356 HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
3357 uint32_t Prescaler);
3358
3359 HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim,
3360 uint32_t Fault,
3361 HRTIM_FaultCfgTypeDef* pFaultCfg);
3362
3363 HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
3364 uint32_t Prescaler);
3365
3366 void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
3367 uint32_t Faults,
3368 uint32_t Enable);
3369
3370 HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim,
3371 uint32_t ADCTrigger,
3372 HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg);
3373
3374 /**
3375 * @}
3376 */
3377
3378 /** @addtogroup HRTIM_Exported_Functions_Group8 Timer waveform configuration and functions
3379 * @{
3380 */
3381 /* Waveform related functions *************************************************/
3382 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim,
3383 uint32_t TimerIdx,
3384 HRTIM_TimerCfgTypeDef * pTimerCfg);
3385
3386 HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim,
3387 uint32_t TimerIdx,
3388 uint32_t CompareUnit,
3389 HRTIM_CompareCfgTypeDef* pCompareCfg);
3390
3391 HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim,
3392 uint32_t TimerIdx,
3393 uint32_t CaptureUnit,
3394 HRTIM_CaptureCfgTypeDef* pCaptureCfg);
3395
3396 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim,
3397 uint32_t TimerIdx,
3398 uint32_t Output,
3399 HRTIM_OutputCfgTypeDef * pOutputCfg);
3400
3401 HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
3402 uint32_t TimerIdx,
3403 uint32_t Output,
3404 uint32_t OutputLevel);
3405
3406 HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim,
3407 uint32_t TimerIdx,
3408 uint32_t Event,
3409 HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg);
3410
3411 HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim,
3412 uint32_t TimerIdx,
3413 HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg);
3414
3415 HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim,
3416 uint32_t TimerIdx,
3417 HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg);
3418
3419 HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim,
3420 uint32_t TimerIdx,
3421 uint32_t RegistersToUpdate);
3422
3423
3424 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart(HRTIM_HandleTypeDef *hhrtim,
3425 uint32_t Timers);
3426
3427 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop(HRTIM_HandleTypeDef *hhrtim,
3428 uint32_t Timers);
3429
3430
3431 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_IT(HRTIM_HandleTypeDef *hhrtim,
3432 uint32_t Timers);
3433
3434 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_IT(HRTIM_HandleTypeDef *hhrtim,
3435 uint32_t Timers);
3436
3437
3438 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_DMA(HRTIM_HandleTypeDef *hhrtim,
3439 uint32_t Timers);
3440
3441 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_DMA(HRTIM_HandleTypeDef *hhrtim,
3442 uint32_t Timers);
3443
3444 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim,
3445 uint32_t OutputsToStart);
3446
3447 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim,
3448 uint32_t OutputsToStop);
3449
3450 HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef *hhrtim,
3451 uint32_t Enable);
3452
3453 HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim);
3454
3455 HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef *hhrtim,
3456 uint32_t TimerIdx,
3457 uint32_t CaptureUnit);
3458
3459 HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef *hhrtim,
3460 uint32_t Timers);
3461
3462 HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef *hhrtim,
3463 uint32_t Timers);
3464
3465 HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
3466 uint32_t TimerIdx,
3467 uint32_t BurstBufferAddress,
3468 uint32_t BurstBufferLength);
3469
3470 HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
3471 uint32_t Timers);
3472
3473 HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
3474 uint32_t Timers);
3475
3476 /**
3477 * @}
3478 */
3479
3480 /** @addtogroup HRTIM_Exported_Functions_Group9 Peripheral state functions
3481 * @{
3482 */
3483 /* HRTIM peripheral state functions */
3484 HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim);
3485
3486 uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef *hhrtim,
3487 uint32_t TimerIdx,
3488 uint32_t CaptureUnit);
3489
3490 uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
3491 uint32_t TimerIdx,
3492 uint32_t Output);
3493
3494 uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,
3495 uint32_t TimerIdx,
3496 uint32_t Output);
3497
3498 uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef *hhrtim,
3499 uint32_t TimerIdx,
3500 uint32_t Output);
3501
3502 uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef *hhrtim);
3503
3504 uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef *hhrtim,
3505 uint32_t TimerIdx);
3506
3507 uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef *hhrtim,
3508 uint32_t TimerIdx);
3509
3510 /**
3511 * @}
3512 */
3513
3514 /** @addtogroup HRTIM_Exported_Functions_Group10 Interrupts handling
3515 * @{
3516 */
3517 /* IRQ handler */
3518 void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim,
3519 uint32_t TimerIdx);
3520
3521 /* HRTIM events related callback functions */
3522 void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef *hhrtim);
3523 void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef *hhrtim);
3524 void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef *hhrtim);
3525 void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef *hhrtim);
3526 void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef *hhrtim);
3527 void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef *hhrtim);
3528 void HAL_HRTIM_DLLCalbrationReadyCallback(HRTIM_HandleTypeDef *hhrtim);
3529 void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef *hhrtim);
3530 void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim);
3531
3532 /* Timer events related callback functions */
3533 void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim,
3534 uint32_t TimerIdx);
3535 void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim,
3536 uint32_t TimerIdx);
3537 void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim,
3538 uint32_t TimerIdx);
3539 void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim,
3540 uint32_t TimerIdx);
3541 void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim,
3542 uint32_t TimerIdx);
3543 void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim,
3544 uint32_t TimerIdx);
3545 void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim,
3546 uint32_t TimerIdx);
3547 void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim,
3548 uint32_t TimerIdx);
3549 void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim,
3550 uint32_t TimerIdx);
3551 void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim,
3552 uint32_t TimerIdx);
3553 void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim,
3554 uint32_t TimerIdx);
3555 void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim,
3556 uint32_t TimerIdx);
3557 void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim,
3558 uint32_t TimerIdx);
3559 void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim,
3560 uint32_t TimerIdx);
3561 void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim,
3562 uint32_t TimerIdx);
3563 void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim);
3564
3565 /**
3566 * @}
3567 */
3568
3569 /**
3570 * @}
3571 */
3572
3573 /**
3574 * @}
3575 */
3576
3577 /**
3578 * @}
3579 */
3580
3581 #endif /* defined(STM32F334x8) */
3582
3583 #ifdef __cplusplus
3584 }
3585 #endif
3586
3587 #endif /* __STM32F3xx_HAL_HRTIM_H */
3588
3589 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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