tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_nand.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f3xx_hal_nand.h
   4   * @author  MCD Application Team
   5   * @version V1.1.0
   6   * @date    12-Sept-2014
   7   * @brief   Header file of NAND HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32F3xx_HAL_NAND_H
  40 #define __STM32F3xx_HAL_NAND_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
  48   #include "stm32f3xx_ll_fmc.h"
  49 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
  50
  51 /** @addtogroup STM32F3xx_HAL_Driver
  52   * @{
  53   */
  54
  55 /** @addtogroup NAND
  56   * @{
  57   */
  58
  59 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
  60
  61 /* Exported typedef ----------------------------------------------------------*/
  62 /* Exported types ------------------------------------------------------------*/
  63 /** @defgroup NAND_Exported_Types NAND Exported Types
  64   * @{
  65   */
  66
  67 /**
  68   * @brief  HAL NAND State structures definition
  69   */
  70 typedef enum
  71 {
  72   HAL_NAND_STATE_RESET     = 0x00,  /*!< NAND not yet initialized or disabled */
  73   HAL_NAND_STATE_READY     = 0x01,  /*!< NAND initialized and ready for use   */
  74   HAL_NAND_STATE_BUSY      = 0x02,  /*!< NAND internal process is ongoing     */
  75   HAL_NAND_STATE_ERROR     = 0x03   /*!< NAND error state                     */
  76 }HAL_NAND_StateTypeDef;
  77
  78 /**
  79   * @brief  NAND Memory electronic signature Structure definition
  80   */
  81 typedef struct
  82 {
  83   /*<! NAND memory electronic signature maker and device IDs */
  84
  85   uint8_t Maker_Id;
  86
  87   uint8_t Device_Id;
  88
  89   uint8_t Third_Id;
  90
  91   uint8_t Fourth_Id;
  92 }NAND_IDTypeDef;
  93
  94 /**
  95   * @brief  NAND Memory address Structure definition
  96   */
  97 typedef struct
  98 {
  99   uint16_t Page;   /*!< NAND memory Page address  */
 100
 101   uint16_t Zone;   /*!< NAND memory Zone address  */
 102
 103   uint16_t Block;  /*!< NAND memory Block address */
 104
 105 }NAND_AddressTypedef;
 106
 107 /**
 108   * @brief  NAND Memory info Structure definition
 109   */
 110 typedef struct
 111 {
 112   uint32_t PageSize;       /*!< NAND memory page (without spare area) size measured in K. bytes */
 113
 114   uint32_t SpareAreaSize;  /*!< NAND memory spare area size measured in K. bytes                */
 115
 116   uint32_t BlockSize;      /*!< NAND memory block size number of pages                          */
 117
 118   uint32_t BlockNbr;       /*!< NAND memory number of blocks                                    */
 119
 120   uint32_t ZoneSize;       /*!< NAND memory zone size measured in number of blocks              */
 121 }NAND_InfoTypeDef;
 122
 123 /**
 124   * @brief  NAND handle Structure definition
 125   */
 126 typedef struct
 127 {
 128   FMC_NAND_TypeDef             *Instance;  /*!< Register base address                        */
 129
 130   FMC_NAND_InitTypeDef         Init;       /*!< NAND device control configuration parameters */
 131
 132   HAL_LockTypeDef              Lock;       /*!< NAND locking object                          */
 133
 134   __IO HAL_NAND_StateTypeDef   State;      /*!< NAND device access state                     */
 135
 136   NAND_InfoTypeDef             Info;       /*!< NAND characteristic information structure    */
 137 }NAND_HandleTypeDef;
 138
 139 /**
 140   * @}
 141   */
 142
 143 /* Exported constants --------------------------------------------------------*/
 144 /** @defgroup NAND_Exported_Constants NAND Exported Constants
 145  * @{
 146  */
 147 #define NAND_DEVICE1               ((uint32_t)0x70000000)
 148 #define NAND_DEVICE2               ((uint32_t)0x80000000)
 149 #define NAND_WRITE_TIMEOUT         ((uint32_t)0x01000000)
 150
 151 #define CMD_AREA                   ((uint32_t)(1<<16))  /* A16 = CLE high */
 152 #define ADDR_AREA                  ((uint32_t)(1<<17))  /* A17 = ALE high */
 153
 154 #define NAND_CMD_AREA_A            ((uint8_t)0x00)
 155 #define NAND_CMD_AREA_B            ((uint8_t)0x01)
 156 #define NAND_CMD_AREA_C            ((uint8_t)0x50)
 157
 158 /* NAND memory status */
 159 #define NAND_VALID_ADDRESS         ((uint32_t)0x00000100)
 160 #define NAND_INVALID_ADDRESS       ((uint32_t)0x00000200)
 161 #define NAND_TIMEOUT_ERROR         ((uint32_t)0x00000400)
 162 #define NAND_BUSY                  ((uint32_t)0x00000000)
 163 #define NAND_ERROR                 ((uint32_t)0x00000001)
 164 #define NAND_READY                 ((uint32_t)0x00000040)
 165
 166 /**
 167   * @}
 168   */
 169
 170 /* Exported macro ------------------------------------------------------------*/
 171 /** @defgroup NAND_Exported_Macros NAND Exported Macros
 172  * @{
 173  */
 174
 175 /** @brief Reset NAND handle state
 176   * @param  __HANDLE__: specifies the NAND handle.
 177   * @retval None
 178   */
 179 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
 180
 181 /**
 182   * @brief  NAND memory address computation.
 183   * @param  __ADDRESS__: NAND memory address.
 184   * @param  __HANDLE__ : NAND handle.
 185   * @retval NAND Raw address value
 186   */
 187 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize)))
 188
 189 /**
 190   * @brief  NAND memory address cycling.
 191   * @param  __ADDRESS__: NAND memory address.
 192   * @retval NAND address cycling value.
 193   */
 194 #define ADDR_1st_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__)& 0xFF)               /* 1st addressing cycle */
 195 #define ADDR_2nd_CYCLE(__ADDRESS__)       (uint8_t)(((__ADDRESS__)& 0xFF00) >> 8)      /* 2nd addressing cycle */
 196 #define ADDR_3rd_CYCLE(__ADDRESS__)       (uint8_t)(((__ADDRESS__)& 0xFF0000) >> 16)   /* 3rd addressing cycle */
 197 #define ADDR_4th_CYCLE(__ADDRESS__)       (uint8_t)(((__ADDRESS__)& 0xFF000000) >> 24) /* 4th addressing cycle */
 198 /**
 199   * @}
 200   */
 201
 202 /* Exported functions --------------------------------------------------------*/
 203 /** @addtogroup NAND_Exported_Functions NAND Exported Functions
 204   * @{
 205   */
 206
 207 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
 208   * @{
 209   */
 210
 211 /* Initialization/de-initialization functions  ********************************/
 212 HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
 213 HAL_StatusTypeDef  HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
 214 void        HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
 215 void        HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
 216 void               HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
 217 void        HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
 218
 219 /**
 220   * @}
 221   */
 222
 223 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
 224   * @{
 225   */
 226
 227 /* IO operation functions  ****************************************************/
 228 HAL_StatusTypeDef  HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
 229 HAL_StatusTypeDef  HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
 230 HAL_StatusTypeDef  HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
 231 HAL_StatusTypeDef  HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
 232 HAL_StatusTypeDef  HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
 233 HAL_StatusTypeDef  HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
 234 HAL_StatusTypeDef  HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress);
 235 uint32_t           HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
 236 uint32_t           HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress);
 237
 238 /**
 239   * @}
 240   */
 241
 242 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
 243   * @{
 244   */
 245
 246 /* NAND Control functions  ****************************************************/
 247 HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
 248 HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
 249 HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
 250
 251 /**
 252   * @}
 253   */
 254
 255 /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
 256   * @{
 257   */
 258
 259 /* NAND State functions *******************************************************/
 260 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
 261 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
 262
 263 /**
 264   * @}
 265   */
 266
 267 /**
 268   * @}
 269   */
 270
 271 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
 272 /**
 273   * @}
 274   */
 275
 276 /**
 277   * @}
 278   */
 279
 280 #ifdef __cplusplus
 281 }
 282 #endif
 283
 284 #endif /* __STM32F3xx_HAL_NAND_H */
 285
 286 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/