tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_nor.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f3xx_hal_nor.h
   4   * @author  MCD Application Team
   5   * @version V1.1.0
   6   * @date    12-Sept-2014
   7   * @brief   Header file of NOR HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32F3xx_HAL_NOR_H
  40 #define __STM32F3xx_HAL_NOR_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
  48   #include "stm32f3xx_ll_fmc.h"
  49 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
  50
  51 /** @addtogroup STM32F3xx_HAL_Driver
  52   * @{
  53   */
  54
  55 /** @addtogroup NOR
  56   * @{
  57   */
  58
  59 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
  60
  61 /* Exported typedef ----------------------------------------------------------*/
  62 /** @defgroup NOR_Exported_Types NOR Exported Types
  63   * @{
  64   */
  65
  66 /**
  67   * @brief  HAL SRAM State structures definition
  68   */
  69 typedef enum
  70 {
  71   HAL_NOR_STATE_RESET             = 0x00,  /*!< NOR not yet initialized or disabled  */
  72   HAL_NOR_STATE_READY             = 0x01,  /*!< NOR initialized and ready for use    */
  73   HAL_NOR_STATE_BUSY              = 0x02,  /*!< NOR internal processing is ongoing   */
  74   HAL_NOR_STATE_ERROR             = 0x03,  /*!< NOR error state                      */
  75   HAL_NOR_STATE_PROTECTED         = 0x04   /*!< NOR NORSRAM device write protected  */
  76
  77 }HAL_NOR_StateTypeDef;
  78
  79 /**
  80   * @brief  FMC NOR Status typedef
  81   */
  82 typedef enum
  83 {
  84   NOR_SUCCESS = 0,
  85   NOR_ONGOING,
  86   NOR_ERROR,
  87   NOR_TIMEOUT
  88
  89 }NOR_StatusTypedef;
  90
  91 /**
  92   * @brief  FMC NOR ID typedef
  93   */
  94 typedef struct
  95 {
  96   uint16_t Manufacturer_Code;  /*!< Defines the device's manufacturer code used to identify the memory       */
  97
  98   uint16_t Device_Code1;
  99
 100   uint16_t Device_Code2;
 101
 102   uint16_t Device_Code3;       /*!< Defines the device's codes used to identify the memory.
 103                                     These codes can be accessed by performing read operations with specific
 104                                     control signals and addresses set.They can also be accessed by issuing
 105                                     an Auto Select command                                                   */
 106 }NOR_IDTypeDef;
 107
 108 /**
 109   * @brief  FMC NOR CFI typedef
 110   */
 111 typedef struct
 112 {
 113   /*!< Defines the information stored in the memory's Common flash interface
 114        which contains a description of various electrical and timing parameters,
 115        density information and functions supported by the memory                   */
 116
 117   uint16_t CFI_1;
 118
 119   uint16_t CFI_2;
 120
 121   uint16_t CFI_3;
 122
 123   uint16_t CFI_4;
 124
 125 }NOR_CFITypeDef;
 126
 127 /**
 128   * @brief  NOR handle Structure definition
 129   */
 130 typedef struct
 131 {
 132   FMC_NORSRAM_TypeDef           *Instance;    /*!< Register base address                        */
 133
 134   FMC_NORSRAM_EXTENDED_TypeDef  *Extended;    /*!< Extended mode register base address          */
 135
 136   FMC_NORSRAM_InitTypeDef       Init;         /*!< NOR device control configuration parameters  */
 137
 138   HAL_LockTypeDef               Lock;         /*!< NOR locking object                           */
 139
 140   __IO HAL_NOR_StateTypeDef     State;        /*!< NOR device access state                      */
 141
 142 }NOR_HandleTypeDef;
 143
 144 /**
 145   * @}
 146   */
 147
 148 /* Exported constants --------------------------------------------------------*/
 149 /** @defgroup NOR_Exported_Constants NOR Exported Constants
 150   * @{
 151   */
 152 /* NOR device IDs addresses */
 153 #define MC_ADDRESS               ((uint16_t)0x0000)
 154 #define DEVICE_CODE1_ADDR        ((uint16_t)0x0001)
 155 #define DEVICE_CODE2_ADDR        ((uint16_t)0x000E)
 156 #define DEVICE_CODE3_ADDR        ((uint16_t)0x000F)
 157
 158 /* NOR CFI IDs addresses */
 159 #define CFI1_ADDRESS             ((uint16_t)0x61)
 160 #define CFI2_ADDRESS             ((uint16_t)0x62)
 161 #define CFI3_ADDRESS             ((uint16_t)0x63)
 162 #define CFI4_ADDRESS             ((uint16_t)0x64)
 163
 164 /* NOR operation wait timeout */
 165 #define NOR_TMEOUT               ((uint16_t)0xFFFF)
 166
 167 /* NOR memory data width */
 168 #define NOR_MEMORY_8B            ((uint8_t)0x0)
 169 #define NOR_MEMORY_16B           ((uint8_t)0x1)
 170
 171 /* NOR memory device read/write start address */
 172 #define NOR_MEMORY_ADRESS1       ((uint32_t)0x60000000)
 173 #define NOR_MEMORY_ADRESS2       ((uint32_t)0x64000000)
 174 #define NOR_MEMORY_ADRESS3       ((uint32_t)0x68000000)
 175 #define NOR_MEMORY_ADRESS4       ((uint32_t)0x6C000000)
 176
 177 /**
 178   * @}
 179   */
 180
 181 /* Exported macro ------------------------------------------------------------*/
 182 /** @defgroup NOR_Exported_Macros NOR Exported Macros
 183   * @{
 184   */
 185
 186 /** @brief Reset NOR handle state
 187   * @param  __HANDLE__: specifies the NOR handle.
 188   * @retval None
 189   */
 190 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
 191
 192 /**
 193   * @brief  NOR memory address shifting.
 194   * @param  __NOR_ADDRESS: NOR base address
 195   * @param  __NOR_MEMORY_WIDTH_: NOR memory width
 196   * @param  __ADDRESS__: NOR memory address
 197   * @retval NOR shifted address value
 198   */
 199 #define __NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)       \
 200             ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)?              \
 201               ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))):              \
 202               ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
 203
 204 /**
 205   * @brief  NOR memory write data to specified address.
 206   * @param  __ADDRESS__: NOR memory address
 207   * @param  __DATA__: Data to write
 208   * @retval None
 209   */
 210 #define __NOR_WRITE(__ADDRESS__, __DATA__)  (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
 211
 212 /**
 213   * @}
 214   */
 215
 216 /* Exported functions --------------------------------------------------------*/
 217 /** @addtogroup NOR_Exported_Functions NOR Exported Functions
 218   * @{
 219   */
 220
 221 /** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
 222   * @{
 223   */
 224
 225 /* Initialization/de-initialization functions  **********************************/
 226 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
 227 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
 228 void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
 229 void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
 230 void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
 231
 232 /**
 233   * @}
 234   */
 235
 236 /** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
 237   * @{
 238   */
 239
 240 /* I/O operation functions  *****************************************************/
 241 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
 242 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
 243 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
 244 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
 245
 246 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
 247 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
 248
 249 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
 250 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
 251 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
 252
 253 /**
 254   * @}
 255   */
 256
 257 /** @addtogroup NOR_Exported_Functions_Group3 Peripheral Control functions
 258   * @{
 259   */
 260
 261 /* NOR Control functions  *******************************************************/
 262 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
 263 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
 264
 265 /**
 266   * @}
 267   */
 268
 269 /** @addtogroup NOR_Exported_Functions_Group4 Peripheral State functions
 270   * @{
 271   */
 272
 273 /* NOR State functions **********************************************************/
 274 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
 275 NOR_StatusTypedef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
 276
 277 /**
 278   * @}
 279   */
 280
 281 /**
 282   * @}
 283   */
 284
 285 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
 286 /**
 287   * @}
 288   */
 289
 290 /**
 291   * @}
 292   */
 293
 294 #ifdef __cplusplus
 295 }
 296 #endif
 297
 298 #endif /* __STM32F3xx_HAL_NOR_H */
 299
 300 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/