tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f3xx_hal_rcc.c
   4   * @author  MCD Application Team
   5   * @version V1.1.0
   6   * @date    12-Sept-2014
   7   * @brief   RCC HAL module driver.
   8   *          This file provides firmware functions to manage the following
   9   *          functionalities of the Reset and Clock Control (RCC) peripheral:
  10   *           + Initialization and de-initialization functions
  11   *           + Peripheral Control functions
  12   *
  13   @verbatim
  14   ==============================================================================
  15                       ##### RCC specific features #####
  16   ==============================================================================
  17     [..]
  18       After reset the device is running from Internal High Speed oscillator
  19       (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is disabled,
  20       and all peripherals are off except internal SRAM, Flash and JTAG.
  21       (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
  22           all peripherals mapped on these busses are running at HSI speed.
  23       (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
  24       (+) All GPIOs are in input floating state, except the JTAG pins which
  25           are assigned to be used for debug purpose.
  26
  27     [..]
  28       Once the device started from reset, the user application has to:
  29       (+) Configure the clock source to be used to drive the System clock
  30           (if the application needs higher frequency/performance)
  31       (+) Configure the System clock frequency and Flash settings
  32       (+) Configure the AHB and APB busses prescalers
  33       (+) Enable the clock for the peripheral(s) to be used
  34       (+) Configure the clock source(s) for peripherals which clocks are not
  35           derived from the System clock (RTC, ADC, I2C, I2S, TIM, USB FS)
  36   @endverbatim
  37   ******************************************************************************
  38   * @attention
  39   *
  40   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  41   *
  42   * Redistribution and use in source and binary forms, with or without modification,
  43   * are permitted provided that the following conditions are met:
  44   *   1. Redistributions of source code must retain the above copyright notice,
  45   *      this list of conditions and the following disclaimer.
  46   *   2. Redistributions in binary form must reproduce the above copyright notice,
  47   *      this list of conditions and the following disclaimer in the documentation
  48   *      and/or other materials provided with the distribution.
  49   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  50   *      may be used to endorse or promote products derived from this software
  51   *      without specific prior written permission.
  52   *
  53   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  54   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  55   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  56   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  57   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  58   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  59   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  60   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  61   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  62   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  63   *
  64   ******************************************************************************
  65   */
  66
  67 /* Includes ------------------------------------------------------------------*/
  68 #include "stm32f3xx_hal.h"
  69
  70 /** @addtogroup STM32F3xx_HAL_Driver
  71   * @{
  72   */
  73
  74 /** @defgroup RCC RCC HAL module driver
  75   * @brief RCC HAL module driver
  76   * @{
  77   */
  78
  79 #ifdef HAL_RCC_MODULE_ENABLED
  80
  81 /* Private typedef -----------------------------------------------------------*/
  82 /* Private define ------------------------------------------------------------*/
  83 /** @defgroup RCC_Private_Define RCC Private Define
  84   * @{
  85   */
  86 #define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
  87 #define HSI_TIMEOUT_VALUE          ((uint32_t)100)  /* 100 ms */
  88 #define LSI_TIMEOUT_VALUE          ((uint32_t)100)  /* 100 ms */
  89 #define PLL_TIMEOUT_VALUE          ((uint32_t)100)  /* 100 ms */
  90 #define CLOCKSWITCH_TIMEOUT_VALUE  ((uint32_t)5000) /* 5 s    */
  91 /**
  92   * @}
  93   */
  94
  95 /* Private macro -------------------------------------------------------------*/
  96 /** @defgroup RCC_Private_Macros RCC Private Macros
  97   * @{
  98   */
  99 #define __MCO_CLK_ENABLE()   __GPIOA_CLK_ENABLE()
 100 #define MCO_GPIO_PORT        GPIOA
 101 #define MCO_PIN              GPIO_PIN_8
 102 /**
 103   * @}
 104   */
 105
 106 /* Private variables ---------------------------------------------------------*/
 107 /** @defgroup RCC_Private_Variables RCC Private Variables
 108   * @{
 109   */
 110 const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
 111 /**
 112   * @}
 113   */
 114
 115 /* Private function prototypes -----------------------------------------------*/
 116 /* Exported functions ---------------------------------------------------------*/
 117
 118 /** @defgroup RCC_Exported_Functions RCC Exported Functions
 119   * @{
 120   */
 121
 122 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
 123  *  @brief    Initialization and Configuration functions
 124  *
 125 @verbatim
 126  ===============================================================================
 127            ##### Initialization and de-initialization functions #####
 128  ===============================================================================
 129     [..]
 130       This section provide functions allowing to configure the internal/external oscillators
 131       (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
 132        and APB2).
 133
 134     [..] Internal/external clock and PLL configuration
 135          (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
 136              the PLL as System clock source.
 137              The HSI clock can be used also to clock the USART and I2C peripherals.
 138
 139          (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC
 140              clock source.
 141
 142          (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or
 143              through the PLL as System clock source. Can be used also as RTC clock source.
 144
 145          (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
 146
 147          (#) PLL (clocked by HSI or HSE), featuring different output clocks:
 148            (+@) The first output is used to generate the high speed system clock (up to 72 MHz)
 149            (+@) The second output is used to generate the clock for the USB FS (48 MHz)
 150            (+@) The third output may be used to generate the clock for the ADC peripherals (up to 72 MHz)
 151            (+@) The fourth output may be used to generate the clock for the TIM peripherals (144 MHz)
 152
 153          (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
 154              and if a HSE clock failure occurs(HSE used directly or through PLL as System
 155              clock source), the System clockis automatically switched to HSI and an interrupt
 156              is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
 157              (Non-Maskable Interrupt) exception vector.
 158
 159          (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL
 160              clock (divided by 2) output on pin (such as PA8 pin).
 161
 162     [..] System, AHB and APB busses clocks configuration
 163          (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
 164              HSE and PLL.
 165              The AHB clock (HCLK) is derived from System clock through configurable
 166              prescaler and used to clock the CPU, memory and peripherals mapped
 167              on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
 168              from AHB clock through configurable prescalers and used to clock
 169              the peripherals mapped on these busses. You can use
 170              "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
 171
 172          (#) All the peripheral clocks are derived from the System clock (SYSCLK) except:
 173            (+@) The FLASH program/erase clock  which is always HSI 8MHz clock.
 174            (+@) The USB 48 MHz clock which is derived from the PLL VCO clock.
 175            (+@) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE.
 176            (+@) The I2C clock which can be derived as well from HSI 8MHz clock.
 177            (+@) The ADC clock which is derived from PLL output.
 178            (+@) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC
 179                 (HSE divided by a programmable prescaler). The System clock (SYSCLK)
 180                 frequency must be higher or equal to the RTC clock frequency.
 181            (+@) IWDG clock which is always the LSI clock.
 182
 183          (#) For the STM32F3xx devices, the maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 72 MHz,
 184              Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
 185         +-----------------------------------------------+
 186         | Latency       | SYSCLK clock frequency (MHz)  |
 187         |---------------|-------------------------------|
 188         |0WS(1CPU cycle)|       0 < SYSCLK <= 24        |
 189         |---------------|-------------------------------|
 190         |1WS(2CPU cycle)|      24 < SYSCLK <= 48        |
 191         |---------------|-------------------------------|
 192         |2WS(3CPU cycle)|      48 < SYSCLK <= 72        |
 193         +-----------------------------------------------+
 194
 195          (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
 196              prefetch is disabled.
 197
 198 @endverbatim
 199   * @{
 200   */
 201
 202 /**
 203   * @brief  Resets the RCC clock configuration to the default reset state.
 204   * @note   The default reset state of the clock configuration is given below:
 205   *            - HSI ON and used as system clock source
 206   *            - HSE and PLL OFF
 207   *            - AHB, APB1 and APB2 prescaler set to 1.
 208   *            - CSS, MCO OFF
 209   *            - All interrupts disabled
 210   * @note   This function doesn't modify the configuration of the
 211   *            - Peripheral clocks
 212   *            - LSI, LSE and RTC clocks
 213   * @retval None
 214   */
 215 void HAL_RCC_DeInit(void)
 216 {
 217   /* Set HSION bit, HSITRIM[4:0] bits to the reset value*/
 218   SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
 219
 220   /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0] and MCOSEL[2:0] bits */
 221   CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCO);
 222
 223   /* Reset HSEON, CSSON, PLLON bits */
 224   CLEAR_BIT(RCC->CR, RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON);
 225
 226   /* Reset HSEBYP bit */
 227   CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
 228
 229   /* Reset CFGR register */
 230   CLEAR_REG(RCC->CFGR);
 231
 232   /* Reset CFGR2 register */
 233   CLEAR_REG(RCC->CFGR2);
 234
 235   /* Reset CFGR3 register */
 236   CLEAR_REG(RCC->CFGR3);
 237
 238   /* Disable all interrupts */
 239   CLEAR_REG(RCC->CIR);
 240 }
 241
 242 /**
 243   * @brief  Initializes the RCC Oscillators according to the specified parameters in the
 244   *         RCC_OscInitTypeDef.
 245   * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
 246   *         contains the configuration information for the RCC Oscillators.
 247   * @note   The PLL is not disabled when used as system clock.
 248   * @retval HAL status
 249   */
 250 __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
 251 {
 252         return HAL_ERROR;
 253 }
 254
 255 /**
 256   * @brief  Initializes the CPU, AHB and APB busses clocks according to the specified
 257   *         parameters in the RCC_ClkInitStruct.
 258   * @param  RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
 259   *         contains the configuration information for the RCC peripheral.
 260   * @param  FLatency: FLASH Latency
 261   *          This parameter can be one of the following values:
 262   *            @arg FLASH_LATENCY_0:  FLASH 0 Latency cycle
 263   *            @arg FLASH_LATENCY_1:  FLASH 1 Latency cycle
 264   *            @arg FLASH_LATENCY_2:  FLASH 2 Latency cycle
 265   *
 266   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
 267   *         and updated by HAL_RCC_GetHCLKFreq() function called within this function
 268   *
 269   * @note   The HSI is used (enabled by hardware) as system clock source after
 270   *         startup from Reset, wake-up from STOP and STANDBY mode, or in case
 271   *         of failure of the HSE used directly or indirectly as system clock
 272   *         (if the Clock Security System CSS is enabled).
 273   *
 274   * @note   A switch from one clock source to another occurs only if the target
 275   *         clock source is ready (clock stable after startup delay or PLL locked).
 276   *         If a clock source which is not yet ready is selected, the switch will
 277   *         occur when the clock source will be ready.
 278   * @retval HAL status
 279   */
 280 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
 281 {
 282   uint32_t tickstart = 0;
 283
 284   /* Check the parameters */
 285   assert_param(RCC_ClkInitStruct != HAL_NULL);
 286   assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
 287   assert_param(IS_FLASH_LATENCY(FLatency));
 288
 289   /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
 290     must be correctly programmed according to the frequency of the CPU clock
 291     (HCLK) of the device. */
 292
 293   /* Increasing the CPU frequency */
 294   if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
 295   {
 296     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
 297     __HAL_FLASH_SET_LATENCY(FLatency);
 298
 299     /* Check that the new number of wait states is taken into account to access the Flash
 300     memory by reading the FLASH_ACR register */
 301     if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
 302     {
 303       return HAL_ERROR;
 304     }
 305
 306     /*-------------------------- HCLK Configuration ----------------------------*/
 307     if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 308     {
 309       assert_param(IS_RCC_SYSCLK_DIV(RCC_ClkInitStruct->AHBCLKDivider));
 310       MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 311     }
 312
 313     /*------------------------- SYSCLK Configuration ---------------------------*/
 314     if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
 315     {
 316       assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
 317
 318       /* HSE is selected as System Clock Source */
 319       if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 320       {
 321         /* Check the HSE ready flag */
 322         if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 323         {
 324           return HAL_ERROR;
 325         }
 326       }
 327       /* PLL is selected as System Clock Source */
 328       else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 329       {
 330         /* Check the PLL ready flag */
 331         if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
 332         {
 333           return HAL_ERROR;
 334         }
 335       }
 336       /* HSI is selected as System Clock Source */
 337       else
 338       {
 339         /* Check the HSI ready flag */
 340         if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 341         {
 342           return HAL_ERROR;
 343         }
 344       }
 345       MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
 346
 347       /* Get timeout */
 348       tickstart = HAL_GetTick();
 349
 350       if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 351       {
 352         while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
 353         {
 354           if((HAL_GetTick()-tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
 355           {
 356             return HAL_TIMEOUT;
 357           }
 358         }
 359       }
 360       else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 361       {
 362         while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 363         {
 364           if((HAL_GetTick()-tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
 365           {
 366             return HAL_TIMEOUT;
 367           }
 368         }
 369       }
 370       else
 371       {
 372         while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
 373         {
 374           if((HAL_GetTick()-tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
 375           {
 376             return HAL_TIMEOUT;
 377           }
 378         }
 379       }
 380     }
 381   }
 382   /* Decreasing the CPU frequency */
 383   else
 384   {
 385     /*-------------------------- HCLK Configuration ----------------------------*/
 386     if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 387     {
 388       assert_param(IS_RCC_SYSCLK_DIV(RCC_ClkInitStruct->AHBCLKDivider));
 389       MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 390     }
 391
 392     /*------------------------- SYSCLK Configuration ---------------------------*/
 393     if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
 394     {
 395       assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
 396
 397       /* HSE is selected as System Clock Source */
 398       if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 399       {
 400         /* Check the HSE ready flag */
 401         if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 402         {
 403           return HAL_ERROR;
 404         }
 405       }
 406       /* PLL is selected as System Clock Source */
 407       else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 408       {
 409         /* Check the PLL ready flag */
 410         if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
 411         {
 412           return HAL_ERROR;
 413         }
 414       }
 415       /* HSI is selected as System Clock Source */
 416       else
 417       {
 418         /* Check the HSI ready flag */
 419         if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 420         {
 421           return HAL_ERROR;
 422         }
 423       }
 424       MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
 425
 426       /* Get timeout */
 427       tickstart = HAL_GetTick();
 428
 429       if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 430       {
 431         while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
 432         {
 433           if((HAL_GetTick()-tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
 434           {
 435             return HAL_TIMEOUT;
 436           }
 437         }
 438       }
 439       else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 440       {
 441         while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 442         {
 443           if((HAL_GetTick()-tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
 444           {
 445             return HAL_TIMEOUT;
 446           }
 447         }
 448       }
 449       else
 450       {
 451         while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
 452         {
 453           if((HAL_GetTick()-tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
 454           {
 455             return HAL_TIMEOUT;
 456           }
 457         }
 458       }
 459     }
 460
 461     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
 462     __HAL_FLASH_SET_LATENCY(FLatency);
 463
 464     /* Check that the new number of wait states is taken into account to access the Flash
 465     memory by reading the FLASH_ACR register */
 466     if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
 467     {
 468       return HAL_ERROR;
 469     }
 470  }
 471
 472   /*-------------------------- PCLK1 Configuration ---------------------------*/
 473   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 474   {
 475     assert_param(IS_RCC_HCLK_DIV(RCC_ClkInitStruct->APB1CLKDivider));
 476     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
 477   }
 478
 479   /*-------------------------- PCLK2 Configuration ---------------------------*/
 480   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 481   {
 482     assert_param(IS_RCC_HCLK_DIV(RCC_ClkInitStruct->APB2CLKDivider));
 483     MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
 484   }
 485
 486   /* Configure the source of time base considering new system clocks settings*/
 487   HAL_InitTick (TICK_INT_PRIORITY);
 488
 489   return HAL_OK;
 490 }
 491
 492 /**
 493   * @}
 494   */
 495
 496 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
 497  *  @brief   RCC clocks control functions
 498  *
 499 @verbatim
 500  ===============================================================================
 501                       ##### Peripheral Control functions #####
 502  ===============================================================================
 503     [..]
 504     This subsection provides a set of functions allowing to control the RCC Clocks
 505     frequencies.
 506
 507 @endverbatim
 508   * @{
 509   */
 510
 511 /**
 512   * @brief  Selects the clock source to output on MCO pin(such as PA8).
 513   * @note   MCO pin (such as PA8) should be configured in alternate function mode.
 514   * @param  RCC_MCOx: specifies the output direction for the clock source.
 515   *          This parameter can be one of the following values:
 516   *            @arg RCC_MCO: Clock source to output on MCO pin(such as PA8).
 517   * @param  RCC_MCOSource: specifies the clock source to output.
 518   *          This parameter can be one of the following values:
 519   *            @arg RCC_MCOSOURCE_LSI: LSI clock selected as MCO source
 520   *            @arg RCC_MCOSOURCE_HSI: HSI clock selected as MCO source
 521   *            @arg RCC_MCOSOURCE_LSE: LSE clock selected as MCO source
 522   *            @arg RCC_MCOSOURCE_HSE: HSE clock selected as MCO source
 523   *            @arg RCC_MCOSOURCE_PLLCLK_DIV2: main PLL clock divided by 2 selected as MCO source
 524   *            @arg RCC_MCOSOURCE_SYSCLK: System clock (SYSCLK) selected as MCO source
 525   * @param  RCC_MCODiv: specifies the MCOx prescaler.
 526   *          This parameter can be one of the following values:
 527   *            @arg RCC_MCO_NODIV: no division applied to MCO clock
 528   * @retval None
 529   */
 530 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
 531 {
 532   GPIO_InitTypeDef gpio;
 533   /* Check the parameters */
 534   assert_param(IS_RCC_MCO(RCC_MCOx));
 535   assert_param(IS_RCC_MCODIV(RCC_MCODiv));
 536   /* RCC_MCO */
 537   assert_param(IS_RCC_MCOSOURCE(RCC_MCOSource));
 538
 539   /* MCO Clock Enable */
 540   __MCO_CLK_ENABLE();
 541
 542   /* Configue the MCO pin in alternate function mode */
 543   gpio.Pin = MCO_PIN;
 544   gpio.Mode = GPIO_MODE_AF_PP;
 545   gpio.Speed = GPIO_SPEED_HIGH;
 546   gpio.Pull = GPIO_NOPULL;
 547   gpio.Alternate = GPIO_AF0_MCO;
 548   HAL_GPIO_Init(MCO_GPIO_PORT, &gpio);
 549
 550   /* Configure the MCO clock source */
 551   __HAL_RCC_MCO_CONFIG(RCC_MCOSource, RCC_MCODiv);
 552 }
 553
 554 /**
 555   * @brief  Enables the Clock Security System.
 556   * @note   If a failure is detected on the HSE oscillator clock, this oscillator
 557   *         is automatically disabled and an interrupt is generated to inform the
 558   *         software about the failure (Clock Security System Interrupt, CSSI),
 559   *         allowing the MCU to perform rescue operations. The CSSI is linked to
 560   *         the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
 561   * @retval None
 562   */
 563 void HAL_RCC_EnableCSS(void)
 564 {
 565   *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)ENABLE;
 566 }
 567
 568 /**
 569   * @brief  Disables the Clock Security System.
 570   * @retval None
 571   */
 572 void HAL_RCC_DisableCSS(void)
 573 {
 574   *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)DISABLE;
 575 }
 576
 577 /**
 578   * @brief  Returns the SYSCLK frequency
 579   * @note   The system frequency computed by this function is not the real
 580   *         frequency in the chip. It is calculated based on the predefined
 581   *         constant and the selected clock source:
 582   * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
 583   * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE
 584   *           divided by PREDIV factor(**)
 585   * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE
 586   *           divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
 587   * @note     (*) HSI_VALUE is a constant defined in stm32f3xx.h file (default value
 588   *               8 MHz).
 589   * @note     (**) HSE_VALUE is a constant defined in stm32f3xx.h file (default value
 590   *                8 MHz), user has to ensure that HSE_VALUE is same as the real
 591   *                frequency of the crystal used. Otherwise, this function may
 592   *                have wrong result.
 593   *
 594   * @note   The result of this function could be not correct when using fractional
 595   *         value for HSE crystal.
 596   *
 597   * @note   This function can be used by the user application to compute the
 598   *         baudrate for the communication peripherals or configure other parameters.
 599   *
 600   * @note   Each time SYSCLK changes, this function must be called to update the
 601   *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
 602   *
 603   * @retval SYSCLK frequency
 604   */
 605 __weak uint32_t HAL_RCC_GetSysClockFreq(void)
 606 {
 607   return 0;
 608 }
 609
 610 /**
 611   * @brief  Returns the HCLK frequency
 612   * @note   Each time HCLK changes, this function must be called to update the
 613   *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
 614   *
 615   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
 616   *         and updated within this function
 617   *
 618   * @retval HCLK frequency
 619   */
 620 uint32_t HAL_RCC_GetHCLKFreq(void)
 621 {
 622   SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
 623   return SystemCoreClock;
 624 }
 625
 626 /**
 627   * @brief  Returns the PCLK1 frequency
 628   * @note   Each time PCLK1 changes, this function must be called to update the
 629   *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
 630   * @retval PCLK1 frequency
 631   */
 632 uint32_t HAL_RCC_GetPCLK1Freq(void)
 633 {
 634   /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
 635   return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
 636 }
 637
 638 /**
 639   * @brief  Returns the PCLK2 frequency
 640   * @note   Each time PCLK2 changes, this function must be called to update the
 641   *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
 642   * @retval PCLK2 frequency
 643   */
 644 uint32_t HAL_RCC_GetPCLK2Freq(void)
 645 {
 646   /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
 647   return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
 648 }
 649
 650 /**
 651   * @brief  Configures the RCC_OscInitStruct according to the internal
 652   * RCC configuration registers.
 653   * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
 654   * will be configured.
 655   * @retval None
 656   */
 657 __weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
 658 {
 659 }
 660
 661 /**
 662   * @brief  Get the RCC_ClkInitStruct according to the internal
 663   * RCC configuration registers.
 664   * @param  RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
 665   * contains the current clock configuration.
 666   * @param  pFLatency: Pointer on the Flash Latency.
 667   * @retval None
 668   */
 669 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
 670 {
 671   /* Check the parameters */
 672   assert_param(RCC_ClkInitStruct != HAL_NULL);
 673   assert_param(pFLatency != HAL_NULL);
 674
 675   /* Set all possible values for the Clock type parameter --------------------*/
 676   RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
 677
 678   /* Get the SYSCLK configuration --------------------------------------------*/
 679   RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
 680
 681   /* Get the HCLK configuration ----------------------------------------------*/
 682   RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
 683
 684   /* Get the APB1 configuration ----------------------------------------------*/
 685   RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
 686
 687   /* Get the APB2 configuration ----------------------------------------------*/
 688   RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
 689
 690   /* Get the Flash Wait State (Latency) configuration ------------------------*/
 691   *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
 692 }
 693
 694 /**
 695   * @brief This function handles the RCC CSS interrupt request.
 696   * @note This API should be called under the NMI_Handler().
 697   * @retval None
 698   */
 699 void HAL_RCC_NMI_IRQHandler(void)
 700 {
 701   /* Check RCC CSSF flag  */
 702   if(__HAL_RCC_GET_IT(RCC_IT_CSS))
 703   {
 704     /* RCC Clock Security System interrupt user callback */
 705     HAL_RCC_CCSCallback();
 706
 707     /* Clear RCC CSS pending bit */
 708     __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
 709   }
 710 }
 711
 712 /**
 713   * @brief  RCC Clock Security System interrupt callback
 714   * @retval None
 715   */
 716 __weak void HAL_RCC_CCSCallback(void)
 717 {
 718   /* NOTE : This function Should not be modified, when the callback is needed,
 719             the HAL_RCC_CCSCallback could be implemented in the user file
 720    */
 721 }
 722
 723 /**
 724   * @}
 725   */
 726
 727 /**
 728   * @}
 729   */
 730
 731 #endif /* HAL_RCC_MODULE_ENABLED */
 732 /**
 733   * @}
 734   */
 735
 736 /**
 737   * @}
 738   */
 739
 740 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/