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[tmk_keyboard.git] / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_STM / TARGET_STM32F3 / stm32f3xx_hal_rcc_ex.h
1 /**
2 ******************************************************************************
3 * @file stm32f3xx_hal_rcc_ex.h
4 * @author MCD Application Team
5 * @version V1.1.0
6 * @date 12-Sept-2014
7 * @brief Header file of RCC HAL Extended module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F3xx_HAL_RCC_EX_H
40 #define __STM32F3xx_HAL_RCC_EX_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f3xx_hal_def.h"
48
49 /** @addtogroup STM32F3xx_HAL_Driver
50 * @{
51 */
52
53 /** @addtogroup RCCEx
54 * @{
55 */
56
57 /* Exported types ------------------------------------------------------------*/
58
59 /** @defgroup RCCEx_Exported_Types RCC Extended Exported Types
60 * @{
61 */
62 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
63 /**
64 * @brief RCC PLL configuration structure definition
65 */
66 typedef struct
67 {
68 uint32_t PLLState; /*!< PLLState: The new state of the PLL.
69 This parameter can be a value of @ref RCC_PLL_Config */
70
71 uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
72 This parameter must be a value of @ref RCCEx_PLL_Clock_Source */
73
74 uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
75 This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
76
77 uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
78 This parameter must be a value of @ref RCCEx_PLL_Prediv_Factor */
79
80 }RCC_PLLInitTypeDef;
81
82 /**
83 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
84 */
85 typedef struct
86 {
87 uint32_t OscillatorType; /*!< The oscillators to be configured.
88 This parameter can be a value of @ref RCC_Oscillator_Type */
89
90 uint32_t HSEState; /*!< The new state of the HSE.
91 This parameter can be a value of @ref RCC_HSE_Config */
92
93 uint32_t LSEState; /*!< The new state of the LSE.
94 This parameter can be a value of @ref RCC_LSE_Config */
95
96 uint32_t HSIState; /*!< The new state of the HSI.
97 This parameter can be a value of @ref RCC_HSI_Config */
98
99 uint32_t HSICalibrationValue; /*!< The calibration trimming value.
100 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
101
102 uint32_t LSIState; /*!< The new state of the LSI.
103 This parameter can be a value of @ref RCC_LSI_Config */
104
105 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
106
107 }RCC_OscInitTypeDef;
108
109 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
110
111 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
112 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
113 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
114 defined(STM32F373xC) || defined(STM32F378xx)
115 /**
116 * @brief RCC PLL configuration structure definition
117 */
118 typedef struct
119 {
120 uint32_t PLLState; /*!< PLLState: The new state of the PLL.
121 This parameter can be a value of @ref RCC_PLL_Config */
122
123 uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
124 This parameter must be a value of @ref RCCEx_PLL_Clock_Source */
125
126 uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
127 This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
128
129 }RCC_PLLInitTypeDef;
130
131 /**
132 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
133 */
134 typedef struct
135 {
136 uint32_t OscillatorType; /*!< The oscillators to be configured.
137 This parameter can be a value of @ref RCC_Oscillator_Type */
138
139 uint32_t HSEState; /*!< The new state of the HSE.
140 This parameter can be a value of @ref RCC_HSE_Config */
141
142 uint32_t HSEPredivValue; /*!< The HSE predivision factor value.
143 This parameter can be a value of @ref RCCEx_HSE_Predivision_Factor */
144
145 uint32_t LSEState; /*!< The new state of the LSE.
146 This parameter can be a value of @ref RCC_LSE_Config */
147
148 uint32_t HSIState; /*!< The new state of the HSI.
149 This parameter can be a value of @ref RCC_HSI_Config */
150
151 uint32_t HSICalibrationValue; /*!< The calibration trimming value.
152 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
153
154 uint32_t LSIState; /*!< The new state of the LSI.
155 This parameter can be a value of @ref RCC_LSI_Config */
156
157 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
158
159 }RCC_OscInitTypeDef;
160 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
161 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
162 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
163 /* STM32F373xC || STM32F378xx */
164
165 /**
166 * @brief RCC extended clocks structure definition
167 */
168 #if defined(STM32F301x8) || defined(STM32F318xx)
169 typedef struct
170 {
171 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
172 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
173
174 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
175 This parameter can be a value of @ref RCC_RTC_Clock_Source */
176
177 uint32_t Usart1ClockSelection; /*!< USART1 clock source
178 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
179
180 uint32_t Usart2ClockSelection; /*!< USART2 clock source
181 This parameter can be a value of @ref RCC_USART2_Clock_Source */
182
183 uint32_t Usart3ClockSelection; /*!< USART3 clock source
184 This parameter can be a value of @ref RCC_USART3_Clock_Source */
185
186 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
187 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
188
189 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
190 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
191
192 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
193 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
194
195 uint32_t Adc1ClockSelection; /*!< ADC1 clock source
196 This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
197
198 uint32_t I2sClockSelection; /*!< I2S clock source
199 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
200
201 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
202 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
203
204 uint32_t Tim15ClockSelection; /*!< TIM15 clock source
205 This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
206
207 uint32_t Tim16ClockSelection; /*!< TIM16 clock source
208 This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
209
210 uint32_t Tim17ClockSelection; /*!< TIM17 clock source
211 This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
212 }RCC_PeriphCLKInitTypeDef;
213 #endif /* STM32F301x8 || STM32F318xx */
214
215 #if defined(STM32F302x8)
216 typedef struct
217 {
218 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
219 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
220
221 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
222 This parameter can be a value of @ref RCC_RTC_Clock_Source */
223
224 uint32_t Usart1ClockSelection; /*!< USART1 clock source
225 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
226
227 uint32_t Usart2ClockSelection; /*!< USART2 clock source
228 This parameter can be a value of @ref RCC_USART2_Clock_Source */
229
230 uint32_t Usart3ClockSelection; /*!< USART3 clock source
231 This parameter can be a value of @ref RCC_USART3_Clock_Source */
232
233 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
234 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
235
236 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
237 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
238
239 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
240 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
241
242 uint32_t Adc1ClockSelection; /*!< ADC1 clock source
243 This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
244
245 uint32_t I2sClockSelection; /*!< I2S clock source
246 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
247
248 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
249 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
250
251 uint32_t Tim15ClockSelection; /*!< TIM15 clock source
252 This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
253
254 uint32_t Tim16ClockSelection; /*!< TIM16 clock source
255 This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
256
257 uint32_t Tim17ClockSelection; /*!< TIM17 clock source
258 This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
259
260 uint32_t USBClockSelection; /*!< USB clock source
261 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
262
263 }RCC_PeriphCLKInitTypeDef;
264 #endif /* STM32F302x8 */
265
266 #if defined(STM32F302xC)
267 typedef struct
268 {
269 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
270 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
271
272 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
273 This parameter can be a value of @ref RCC_RTC_Clock_Source */
274
275 uint32_t Usart1ClockSelection; /*!< USART1 clock source
276 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
277
278 uint32_t Usart2ClockSelection; /*!< USART2 clock source
279 This parameter can be a value of @ref RCC_USART2_Clock_Source */
280
281 uint32_t Usart3ClockSelection; /*!< USART3 clock source
282 This parameter can be a value of @ref RCC_USART3_Clock_Source */
283
284 uint32_t Uart4ClockSelection; /*!< UART4 clock source
285 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
286
287 uint32_t Uart5ClockSelection; /*!< UART5 clock source
288 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
289
290 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
291 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
292
293 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
294 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
295
296 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
297 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
298
299 uint32_t I2sClockSelection; /*!< I2S clock source
300 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
301
302 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
303 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
304
305 uint32_t USBClockSelection; /*!< USB clock source
306 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
307
308 }RCC_PeriphCLKInitTypeDef;
309 #endif /* STM32F302xC */
310
311 #if defined(STM32F303xC)
312 typedef struct
313 {
314 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
315 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
316
317 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
318 This parameter can be a value of @ref RCC_RTC_Clock_Source */
319
320 uint32_t Usart1ClockSelection; /*!< USART1 clock source
321 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
322
323 uint32_t Usart2ClockSelection; /*!< USART2 clock source
324 This parameter can be a value of @ref RCC_USART2_Clock_Source */
325
326 uint32_t Usart3ClockSelection; /*!< USART3 clock source
327 This parameter can be a value of @ref RCC_USART3_Clock_Source */
328
329 uint32_t Uart4ClockSelection; /*!< UART4 clock source
330 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
331
332 uint32_t Uart5ClockSelection; /*!< UART5 clock source
333 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
334
335 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
336 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
337
338 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
339 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
340
341 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
342 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
343
344 uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
345 This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
346
347 uint32_t I2sClockSelection; /*!< I2S clock source
348 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
349
350 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
351 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
352
353 uint32_t Tim8ClockSelection; /*!< TIM8 clock source
354 This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
355
356 uint32_t USBClockSelection; /*!< USB clock source
357 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
358
359 }RCC_PeriphCLKInitTypeDef;
360 #endif /* STM32F303xC */
361
362 #if defined(STM32F302xE)
363 typedef struct
364 {
365 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
366 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
367
368 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
369 This parameter can be a value of @ref RCC_RTC_Clock_Source */
370
371 uint32_t Usart1ClockSelection; /*!< USART1 clock source
372 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
373
374 uint32_t Usart2ClockSelection; /*!< USART2 clock source
375 This parameter can be a value of @ref RCC_USART2_Clock_Source */
376
377 uint32_t Usart3ClockSelection; /*!< USART3 clock source
378 This parameter can be a value of @ref RCC_USART3_Clock_Source */
379
380 uint32_t Uart4ClockSelection; /*!< UART4 clock source
381 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
382
383 uint32_t Uart5ClockSelection; /*!< UART5 clock source
384 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
385
386 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
387 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
388
389 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
390 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
391
392 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
393 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
394
395 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
396 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
397
398 uint32_t I2sClockSelection; /*!< I2S clock source
399 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
400
401 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
402 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
403
404 uint32_t Tim2ClockSelection; /*!< TIM2 clock source
405 This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
406
407 uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
408 This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
409
410 uint32_t Tim15ClockSelection; /*!< TIM15 clock source
411 This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
412
413 uint32_t Tim16ClockSelection; /*!< TIM16 clock source
414 This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
415
416 uint32_t Tim17ClockSelection; /*!< TIM17 clock source
417 This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
418
419 uint32_t USBClockSelection; /*!< USB clock source
420 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
421
422 }RCC_PeriphCLKInitTypeDef;
423 #endif /* STM32F302xE */
424
425 #if defined(STM32F303xE)
426 typedef struct
427 {
428 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
429 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
430
431 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
432 This parameter can be a value of @ref RCC_RTC_Clock_Source */
433
434 uint32_t Usart1ClockSelection; /*!< USART1 clock source
435 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
436
437 uint32_t Usart2ClockSelection; /*!< USART2 clock source
438 This parameter can be a value of @ref RCC_USART2_Clock_Source */
439
440 uint32_t Usart3ClockSelection; /*!< USART3 clock source
441 This parameter can be a value of @ref RCC_USART3_Clock_Source */
442
443 uint32_t Uart4ClockSelection; /*!< UART4 clock source
444 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
445
446 uint32_t Uart5ClockSelection; /*!< UART5 clock source
447 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
448
449 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
450 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
451
452 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
453 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
454
455 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
456 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
457
458 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
459 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
460
461 uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
462 This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
463
464 uint32_t I2sClockSelection; /*!< I2S clock source
465 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
466
467 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
468 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
469
470 uint32_t Tim2ClockSelection; /*!< TIM2 clock source
471 This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
472
473 uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
474 This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
475
476 uint32_t Tim8ClockSelection; /*!< TIM8 clock source
477 This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
478
479 uint32_t Tim15ClockSelection; /*!< TIM15 clock source
480 This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
481
482 uint32_t Tim16ClockSelection; /*!< TIM16 clock source
483 This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
484
485 uint32_t Tim17ClockSelection; /*!< TIM17 clock source
486 This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
487
488 uint32_t Tim20ClockSelection; /*!< TIM20 clock source
489 This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */
490
491 uint32_t USBClockSelection; /*!< USB clock source
492 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
493
494 }RCC_PeriphCLKInitTypeDef;
495 #endif /* STM32F303xE */
496
497 #if defined(STM32F398xx)
498 typedef struct
499 {
500 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
501 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
502
503 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
504 This parameter can be a value of @ref RCC_RTC_Clock_Source */
505
506 uint32_t Usart1ClockSelection; /*!< USART1 clock source
507 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
508
509 uint32_t Usart2ClockSelection; /*!< USART2 clock source
510 This parameter can be a value of @ref RCC_USART2_Clock_Source */
511
512 uint32_t Usart3ClockSelection; /*!< USART3 clock source
513 This parameter can be a value of @ref RCC_USART3_Clock_Source */
514
515 uint32_t Uart4ClockSelection; /*!< UART4 clock source
516 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
517
518 uint32_t Uart5ClockSelection; /*!< UART5 clock source
519 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
520
521 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
522 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
523
524 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
525 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
526
527 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
528 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
529
530 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
531 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
532
533 uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
534 This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
535
536 uint32_t I2sClockSelection; /*!< I2S clock source
537 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
538
539 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
540 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
541
542 uint32_t Tim2ClockSelection; /*!< TIM2 clock source
543 This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
544
545 uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
546 This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
547
548 uint32_t Tim8ClockSelection; /*!< TIM8 clock source
549 This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
550
551 uint32_t Tim15ClockSelection; /*!< TIM15 clock source
552 This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
553
554 uint32_t Tim16ClockSelection; /*!< TIM16 clock source
555 This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
556
557 uint32_t Tim17ClockSelection; /*!< TIM17 clock source
558 This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
559
560 uint32_t Tim20ClockSelection; /*!< TIM20 clock source
561 This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */
562
563 }RCC_PeriphCLKInitTypeDef;
564 #endif /* STM32F398xx */
565
566 #if defined(STM32F358xx)
567 typedef struct
568 {
569 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
570 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
571
572 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
573 This parameter can be a value of @ref RCC_RTC_Clock_Source */
574
575 uint32_t Usart1ClockSelection; /*!< USART1 clock source
576 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
577
578 uint32_t Usart2ClockSelection; /*!< USART2 clock source
579 This parameter can be a value of @ref RCC_USART2_Clock_Source */
580
581 uint32_t Usart3ClockSelection; /*!< USART3 clock source
582 This parameter can be a value of @ref RCC_USART3_Clock_Source */
583
584 uint32_t Uart4ClockSelection; /*!< UART4 clock source
585 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
586
587 uint32_t Uart5ClockSelection; /*!< UART5 clock source
588 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
589
590 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
591 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
592
593 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
594 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
595
596 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
597 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
598
599 uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
600 This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
601
602 uint32_t I2sClockSelection; /*!< I2S clock source
603 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
604
605 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
606 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
607
608 uint32_t Tim8ClockSelection; /*!< TIM8 clock source
609 This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
610
611 }RCC_PeriphCLKInitTypeDef;
612 #endif /* STM32F358xx */
613
614 #if defined(STM32F303x8)
615 typedef struct
616 {
617 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
618 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
619
620 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
621 This parameter can be a value of @ref RCC_RTC_Clock_Source */
622
623 uint32_t Usart1ClockSelection; /*!< USART1 clock source
624 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
625
626 uint32_t Usart2ClockSelection; /*!< USART2 clock source
627 This parameter can be a value of @ref RCC_USART2_Clock_Source */
628
629 uint32_t Usart3ClockSelection; /*!< USART3 clock source
630 This parameter can be a value of @ref RCC_USART3_Clock_Source */
631
632 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
633 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
634
635 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
636 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
637
638 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
639 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
640
641 }RCC_PeriphCLKInitTypeDef;
642 #endif /* STM32F303x8 */
643
644 #if defined(STM32F334x8)
645 typedef struct
646 {
647 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
648 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
649
650 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
651 This parameter can be a value of @ref RCC_RTC_Clock_Source */
652
653 uint32_t Usart1ClockSelection; /*!< USART1 clock source
654 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
655
656 uint32_t Usart2ClockSelection; /*!< USART2 clock source
657 This parameter can be a value of @ref RCC_USART2_Clock_Source */
658
659 uint32_t Usart3ClockSelection; /*!< USART3 clock source
660 This parameter can be a value of @ref RCC_USART3_Clock_Source */
661
662 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
663 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
664
665 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
666 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
667
668 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
669 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
670
671 uint32_t Hrtim1ClockSelection; /*!< HRTIM1 clock source
672 This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source */
673
674 }RCC_PeriphCLKInitTypeDef;
675 #endif /* STM32F334x8 */
676
677 #if defined(STM32F328xx)
678 typedef struct
679 {
680 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
681 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
682
683 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
684 This parameter can be a value of @ref RCC_RTC_Clock_Source */
685
686 uint32_t Usart1ClockSelection; /*!< USART1 clock source
687 This parameter can be a value of @ref RCC_USART1_Clock_Source */
688
689 uint32_t Usart2ClockSelection; /*!< USART2 clock source
690 This parameter can be a value of @ref RCC_USART2_Clock_Source */
691
692 uint32_t Usart3ClockSelection; /*!< USART3 clock source
693 This parameter can be a value of @ref RCC_USART3_Clock_Source */
694
695 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
696 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
697
698 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
699 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
700
701 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
702 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
703
704 }RCC_PeriphCLKInitTypeDef;
705 #endif /* STM32F328xx */
706
707 #if defined(STM32F373xC)
708 typedef struct
709 {
710 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
711 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
712
713 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
714 This parameter can be a value of @ref RCC_RTC_Clock_Source */
715
716 uint32_t Usart1ClockSelection; /*!< USART1 clock source
717 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
718
719 uint32_t Usart2ClockSelection; /*!< USART2 clock source
720 This parameter can be a value of @ref RCC_USART2_Clock_Source */
721
722 uint32_t Usart3ClockSelection; /*!< USART3 clock source
723 This parameter can be a value of @ref RCC_USART3_Clock_Source */
724
725 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
726 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
727
728 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
729 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
730
731 uint32_t Adc1ClockSelection; /*!< ADC1 clock source
732 This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
733
734 uint32_t SdadcClockSelection; /*!< SDADC clock prescaler
735 This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */
736
737 uint32_t CecClockSelection; /*!< HDMI CEC clock source
738 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
739
740 uint32_t USBClockSelection; /*!< USB clock source
741 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
742
743 }RCC_PeriphCLKInitTypeDef;
744 #endif /* STM32F373xC */
745
746 #if defined(STM32F378xx)
747 typedef struct
748 {
749 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
750 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
751
752 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
753 This parameter can be a value of @ref RCC_RTC_Clock_Source */
754
755 uint32_t Usart1ClockSelection; /*!< USART1 clock source
756 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
757
758 uint32_t Usart2ClockSelection; /*!< USART2 clock source
759 This parameter can be a value of @ref RCC_USART2_Clock_Source */
760
761 uint32_t Usart3ClockSelection; /*!< USART3 clock source
762 This parameter can be a value of @ref RCC_USART3_Clock_Source */
763
764 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
765 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
766
767 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
768 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
769
770 uint32_t Adc1ClockSelection; /*!< ADC1 clock source
771 This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
772
773 uint32_t SdadcClockSelection; /*!< SDADC clock prescaler
774 This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */
775
776 uint32_t CecClockSelection; /*!< HDMI CEC clock source
777 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
778
779 }RCC_PeriphCLKInitTypeDef;
780 #endif /* STM32F378xx */
781
782 /**
783 * @}
784 */
785
786 /* Exported constants --------------------------------------------------------*/
787 /** @defgroup RCCEx_Exported_Constants RCC Extended Exported Constants
788 * @{
789 */
790 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
791 defined(STM32F334x8) || \
792 defined(STM32F373xC) || defined(STM32F378xx)
793 /** @defgroup RCCEx_MCO_Clock_Source RCC Extended MCO Clock Source
794 * @{
795 */
796 #define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK
797 #define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI
798 #define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE
799 #define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
800 #define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI
801 #define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE
802 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
803
804 #define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
805 ((SOURCE) == RCC_MCOSOURCE_LSI) || \
806 ((SOURCE) == RCC_MCOSOURCE_LSE) || \
807 ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
808 ((SOURCE) == RCC_MCOSOURCE_HSI) || \
809 ((SOURCE) == RCC_MCOSOURCE_HSE) || \
810 ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2))
811 /**
812 * @}
813 */
814 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
815 /* STM32F334x8 */
816 /* STM32F373xC || STM32F378xx */
817
818 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
819 defined(STM32F303x8) || defined(STM32F328xx) || \
820 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
821 /** @defgroup RCCEx_MCO_Clock_Source RCC Extended MCO Clock Source
822 * @{
823 */
824 #define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK
825 #define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI
826 #define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE
827 #define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
828 #define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI
829 #define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE
830 #define RCC_MCOSOURCE_PLLCLK_DIV1 (RCC_CFGR_PLLNODIV | RCC_CFGR_MCO_PLL)
831 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
832
833 #define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
834 ((SOURCE) == RCC_MCOSOURCE_LSI) || \
835 ((SOURCE) == RCC_MCOSOURCE_LSE) || \
836 ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
837 ((SOURCE) == RCC_MCOSOURCE_HSI) || \
838 ((SOURCE) == RCC_MCOSOURCE_HSE) || \
839 ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV1) || \
840 ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2))
841 /**
842 * @}
843 */
844 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
845 /* STM32F303x8 || STM32F328xx || */
846 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
847
848 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
849 /** @defgroup RCCEx_PLL_Clock_Source RCC Extended PLL Clock Source
850 * @{
851 */
852 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
853 #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV
854
855 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
856 ((SOURCE) == RCC_PLLSOURCE_HSE))
857 /**
858 * @}
859 */
860
861 /** @defgroup RCCEx_PLL_Prediv_Factor RCC Extended PLL Prediv Factor
862 * @{
863 */
864 #define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
865 #define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
866 #define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
867 #define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
868 #define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
869 #define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
870 #define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
871 #define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
872 #define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
873 #define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
874 #define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
875 #define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
876 #define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
877 #define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
878 #define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
879 #define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
880
881 #define IS_RCC_PREDIV(PREDIV) (((PREDIV) == RCC_PREDIV_DIV1) || ((PREDIV) == RCC_PREDIV_DIV2) || \
882 ((PREDIV) == RCC_PREDIV_DIV3) || ((PREDIV) == RCC_PREDIV_DIV4) || \
883 ((PREDIV) == RCC_PREDIV_DIV5) || ((PREDIV) == RCC_PREDIV_DIV6) || \
884 ((PREDIV) == RCC_PREDIV_DIV7) || ((PREDIV) == RCC_PREDIV_DIV8) || \
885 ((PREDIV) == RCC_PREDIV_DIV9) || ((PREDIV) == RCC_PREDIV_DIV10) || \
886 ((PREDIV) == RCC_PREDIV_DIV11) || ((PREDIV) == RCC_PREDIV_DIV12) || \
887 ((PREDIV) == RCC_PREDIV_DIV13) || ((PREDIV) == RCC_PREDIV_DIV14) || \
888 ((PREDIV) == RCC_PREDIV_DIV15) || ((PREDIV) == RCC_PREDIV_DIV16))
889 /**
890 * @}
891 */
892 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
893
894 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
895 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
896 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
897 defined(STM32F373xC) || defined(STM32F378xx)
898 /** @defgroup RCCEx_PLL_Clock_Source RCC Extended PLL Clock Source
899 * @{
900 */
901 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
902 #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV
903
904 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
905 ((SOURCE) == RCC_PLLSOURCE_HSE))
906 /**
907 * @}
908 */
909
910 /** @defgroup RCCEx_HSE_Predivision_Factor RCC Extended HSE Predivision Factor
911 * @{
912 */
913
914 #define RCC_HSE_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
915 #define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
916 #define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
917 #define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
918 #define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
919 #define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
920 #define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
921 #define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
922 #define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
923 #define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
924 #define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
925 #define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
926 #define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
927 #define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
928 #define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
929 #define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
930
931 #define IS_RCC_HSE_PREDIV(DIV) (((DIV) == RCC_HSE_PREDIV_DIV1) || ((DIV) == RCC_HSE_PREDIV_DIV2) || \
932 ((DIV) == RCC_HSE_PREDIV_DIV3) || ((DIV) == RCC_HSE_PREDIV_DIV4) || \
933 ((DIV) == RCC_HSE_PREDIV_DIV5) || ((DIV) == RCC_HSE_PREDIV_DIV6) || \
934 ((DIV) == RCC_HSE_PREDIV_DIV7) || ((DIV) == RCC_HSE_PREDIV_DIV8) || \
935 ((DIV) == RCC_HSE_PREDIV_DIV9) || ((DIV) == RCC_HSE_PREDIV_DIV10) || \
936 ((DIV) == RCC_HSE_PREDIV_DIV11) || ((DIV) == RCC_HSE_PREDIV_DIV12) || \
937 ((DIV) == RCC_HSE_PREDIV_DIV13) || ((DIV) == RCC_HSE_PREDIV_DIV14) || \
938 ((DIV) == RCC_HSE_PREDIV_DIV15) || ((DIV) == RCC_HSE_PREDIV_DIV16))
939 /**
940 * @}
941 */
942 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
943 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
944 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
945 /* STM32F373xC || STM32F378xx */
946
947 /** @defgroup RCCEx_Periph_Clock_Selection RCC Extended Periph Clock Selection
948 * @{
949 */
950 #if defined(STM32F301x8) || defined(STM32F318xx)
951 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
952 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
953 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
954 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
955 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
956 #define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
957 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
958 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
959 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00008000)
960 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
961 #define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00040000)
962 #define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00080000)
963 #define RCC_PERIPHCLK_TIM17 ((uint32_t)0x00100000)
964
965 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
966 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
967 RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_I2S | \
968 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM1 | \
969 RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
970 RCC_PERIPHCLK_TIM17 | RCC_PERIPHCLK_RTC))
971 #endif /* STM32F301x8 || STM32F318xx */
972
973 #if defined(STM32F302x8)
974 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
975 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
976 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
977 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
978 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
979 #define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
980 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
981 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
982 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00008000)
983 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
984 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
985 #define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00040000)
986 #define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00080000)
987 #define RCC_PERIPHCLK_TIM17 ((uint32_t)0x00100000)
988
989 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
990 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
991 RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_I2S | \
992 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM1 | \
993 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB | \
994 RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
995 RCC_PERIPHCLK_TIM17))
996 #endif /* STM32F302x8 */
997
998 #if defined(STM32F302xC)
999 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
1000 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
1001 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
1002 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
1003 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
1004 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
1005 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
1006 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
1007 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
1008 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
1009 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
1010 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
1011
1012 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
1013 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
1014 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
1015 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_I2S | \
1016 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC | \
1017 RCC_PERIPHCLK_USB))
1018 #endif /* STM32F302xC */
1019
1020 #if defined(STM32F303xC)
1021 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
1022 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
1023 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
1024 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
1025 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
1026 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
1027 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
1028 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
1029 #define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
1030 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
1031 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
1032 #define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
1033 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
1034 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
1035
1036 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
1037 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
1038 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
1039 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
1040 RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
1041 RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \
1042 RCC_PERIPHCLK_USB))
1043 #endif /* STM32F303xC */
1044
1045 #if defined(STM32F302xE)
1046 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
1047 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
1048 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
1049 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
1050 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
1051 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
1052 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
1053 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
1054 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
1055 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
1056 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
1057 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
1058 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000)
1059 #define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000)
1060 #define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000)
1061 #define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000)
1062 #define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000)
1063 #define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000)
1064
1065 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
1066 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
1067 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
1068 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_I2S | \
1069 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC | \
1070 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_I2C3 | \
1071 RCC_PERIPHCLK_TIM2 | RCC_PERIPHCLK_TIM34 | \
1072 RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
1073 RCC_PERIPHCLK_TIM17))
1074 #endif /* STM32F302xE */
1075
1076 #if defined(STM32F303xE)
1077 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
1078 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
1079 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
1080 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
1081 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
1082 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
1083 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
1084 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
1085 #define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
1086 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
1087 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
1088 #define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
1089 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
1090 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
1091 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000)
1092 #define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000)
1093 #define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000)
1094 #define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000)
1095 #define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000)
1096 #define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000)
1097 #define RCC_PERIPHCLK_TIM20 ((uint32_t)0x02000000)
1098
1099 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
1100 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
1101 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
1102 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
1103 RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
1104 RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \
1105 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_I2C3 | \
1106 RCC_PERIPHCLK_TIM2 | RCC_PERIPHCLK_TIM34 | \
1107 RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
1108 RCC_PERIPHCLK_TIM17 | RCC_PERIPHCLK_TIM20))
1109 #endif /* STM32F303xE */
1110
1111 #if defined(STM32F398xx)
1112 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
1113 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
1114 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
1115 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
1116 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
1117 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
1118 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
1119 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
1120 #define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
1121 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
1122 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
1123 #define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
1124 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
1125 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000)
1126 #define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000)
1127 #define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000)
1128 #define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000)
1129 #define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000)
1130 #define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000)
1131 #define RCC_PERIPHCLK_TIM20 ((uint32_t)0x02000000)
1132
1133 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
1134 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
1135 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
1136 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
1137 RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
1138 RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \
1139 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM2 | \
1140 RCC_PERIPHCLK_TIM34 | RCC_PERIPHCLK_TIM15 | \
1141 RCC_PERIPHCLK_TIM16 | RCC_PERIPHCLK_TIM17 | \
1142 RCC_PERIPHCLK_TIM20))
1143 #endif /* STM32F398xx */
1144
1145 #if defined(STM32F358xx)
1146 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
1147 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
1148 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
1149 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
1150 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
1151 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
1152 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
1153 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
1154 #define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
1155 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
1156 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
1157 #define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
1158 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
1159
1160 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
1161 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
1162 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
1163 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
1164 RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
1165 RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC))
1166 #endif /* STM32F358xx */
1167
1168 #if defined(STM32F303x8)
1169 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
1170 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
1171 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
1172 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
1173 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
1174 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
1175 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
1176
1177 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
1178 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \
1179 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC))
1180 #endif /* STM32F303x8 */
1181
1182 #if defined(STM32F334x8)
1183 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
1184 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
1185 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
1186 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
1187 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
1188 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
1189 #define RCC_PERIPHCLK_HRTIM1 ((uint32_t)0x00004000)
1190 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
1191
1192 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
1193 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \
1194 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_HRTIM1 | \
1195 RCC_PERIPHCLK_RTC))
1196 #endif /* STM32F334x8 */
1197
1198 #if defined(STM32F328xx)
1199 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
1200 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
1201 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
1202 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
1203 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
1204 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
1205 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
1206
1207 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
1208 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \
1209 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC))
1210 #endif /* STM32F328xx */
1211
1212 #if defined(STM32F373xC)
1213 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
1214 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
1215 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
1216 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
1217 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
1218 #define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
1219 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
1220 #define RCC_PERIPHCLK_SDADC ((uint32_t)0x00000800)
1221 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
1222 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
1223
1224 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
1225 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
1226 RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_SDADC | \
1227 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \
1228 RCC_PERIPHCLK_USB))
1229 #endif /* STM32F373xC */
1230
1231 #if defined(STM32F378xx)
1232 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
1233 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
1234 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
1235 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
1236 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
1237 #define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
1238 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
1239 #define RCC_PERIPHCLK_SDADC ((uint32_t)0x00000800)
1240 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
1241
1242 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
1243 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
1244 RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_SDADC | \
1245 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC))
1246 #endif /* STM32F378xx */
1247 /**
1248 * @}
1249 */
1250
1251 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
1252
1253 /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
1254 * @{
1255 */
1256 #define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
1257 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
1258 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
1259 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
1260
1261 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
1262 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
1263 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
1264 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
1265 /**
1266 * @}
1267 */
1268
1269 /** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
1270 * @{
1271 */
1272 #define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
1273 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
1274
1275 #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
1276 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
1277 /**
1278 * @}
1279 */
1280
1281 /** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source
1282 * @{
1283 */
1284 #define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI
1285 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK
1286
1287 #define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \
1288 ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK))
1289 /**
1290 * @}
1291 */
1292
1293 /** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source
1294 * @{
1295 */
1296 #define RCC_ADC1PLLCLK_OFF RCC_CFGR2_ADC1PRES_NO
1297 #define RCC_ADC1PLLCLK_DIV1 RCC_CFGR2_ADC1PRES_DIV1
1298 #define RCC_ADC1PLLCLK_DIV2 RCC_CFGR2_ADC1PRES_DIV2
1299 #define RCC_ADC1PLLCLK_DIV4 RCC_CFGR2_ADC1PRES_DIV4
1300 #define RCC_ADC1PLLCLK_DIV6 RCC_CFGR2_ADC1PRES_DIV6
1301 #define RCC_ADC1PLLCLK_DIV8 RCC_CFGR2_ADC1PRES_DIV8
1302 #define RCC_ADC1PLLCLK_DIV10 RCC_CFGR2_ADC1PRES_DIV10
1303 #define RCC_ADC1PLLCLK_DIV12 RCC_CFGR2_ADC1PRES_DIV12
1304 #define RCC_ADC1PLLCLK_DIV16 RCC_CFGR2_ADC1PRES_DIV16
1305 #define RCC_ADC1PLLCLK_DIV32 RCC_CFGR2_ADC1PRES_DIV32
1306 #define RCC_ADC1PLLCLK_DIV64 RCC_CFGR2_ADC1PRES_DIV64
1307 #define RCC_ADC1PLLCLK_DIV128 RCC_CFGR2_ADC1PRES_DIV128
1308 #define RCC_ADC1PLLCLK_DIV256 RCC_CFGR2_ADC1PRES_DIV256
1309
1310 #define IS_RCC_ADC1PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PLLCLK_OFF) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV1) || \
1311 ((ADCCLK) == RCC_ADC1PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV4) || \
1312 ((ADCCLK) == RCC_ADC1PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV8) || \
1313 ((ADCCLK) == RCC_ADC1PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV12) || \
1314 ((ADCCLK) == RCC_ADC1PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV32) || \
1315 ((ADCCLK) == RCC_ADC1PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV128) || \
1316 ((ADCCLK) == RCC_ADC1PLLCLK_DIV256))
1317 /**
1318 * @}
1319 */
1320
1321 /** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
1322 * @{
1323 */
1324 #define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
1325 #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
1326
1327 #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \
1328 ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
1329 /**
1330 * @}
1331 */
1332
1333 /** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
1334 * @{
1335 */
1336 #define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
1337 #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
1338
1339 #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
1340 ((SOURCE) == RCC_TIM1CLK_PLLCLK))
1341 /**
1342 * @}
1343 */
1344
1345 /** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source
1346 * @{
1347 */
1348 #define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK
1349 #define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL
1350
1351 #define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) || \
1352 ((SOURCE) == RCC_TIM15CLK_PLLCLK))
1353 /**
1354 * @}
1355 */
1356
1357 /** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source
1358 * @{
1359 */
1360 #define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK
1361 #define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL
1362
1363 #define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) || \
1364 ((SOURCE) == RCC_TIM16CLK_PLLCLK))
1365 /**
1366 * @}
1367 */
1368
1369 /** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source
1370 * @{
1371 */
1372 #define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK
1373 #define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL
1374
1375 #define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) || \
1376 ((SOURCE) == RCC_TIM17CLK_PLLCLK))
1377 /**
1378 * @}
1379 */
1380
1381 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
1382
1383 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
1384
1385 /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
1386 * @{
1387 */
1388 #define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
1389 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
1390 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
1391 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
1392
1393 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
1394 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
1395 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
1396 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
1397 /**
1398 * @}
1399 */
1400
1401 /** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
1402 * @{
1403 */
1404 #define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
1405 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
1406
1407 #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
1408 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
1409 /**
1410 * @}
1411 */
1412
1413 /** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
1414 * @{
1415 */
1416
1417 /* ADC1 & ADC2 */
1418 #define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
1419 #define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
1420 #define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
1421 #define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
1422 #define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
1423 #define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
1424 #define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
1425 #define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
1426 #define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
1427 #define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
1428 #define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
1429 #define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
1430 #define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
1431
1432 #define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \
1433 ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \
1434 ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \
1435 ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \
1436 ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \
1437 ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \
1438 ((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
1439 /**
1440 * @}
1441 */
1442
1443 /** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
1444 * @{
1445 */
1446 #define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
1447 #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
1448
1449 #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \
1450 ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
1451 /**
1452 * @}
1453 */
1454 /** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
1455 * @{
1456 */
1457 #define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
1458 #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
1459
1460 #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
1461 ((SOURCE) == RCC_TIM1CLK_PLLCLK))
1462 /**
1463 * @}
1464 */
1465
1466 /** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source
1467 * @{
1468 */
1469 #define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK
1470 #define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK
1471 #define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE
1472 #define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI
1473
1474 #define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \
1475 ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
1476 ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \
1477 ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
1478 /**
1479 * @}
1480 */
1481
1482 /** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source
1483 * @{
1484 */
1485 #define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK
1486 #define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK
1487 #define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE
1488 #define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI
1489
1490 #define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \
1491 ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
1492 ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \
1493 ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
1494 /**
1495 * @}
1496 */
1497
1498 #endif /* STM32F302xC || STM32F303xC || STM32F358xx */
1499
1500 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
1501
1502 /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
1503 * @{
1504 */
1505 #define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
1506 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
1507 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
1508 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
1509
1510 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
1511 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
1512 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
1513 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
1514 /**
1515 * @}
1516 */
1517
1518 /** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
1519 * @{
1520 */
1521 #define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
1522 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
1523
1524 #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
1525 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
1526 /**
1527 * @}
1528 */
1529
1530 /** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source
1531 * @{
1532 */
1533 #define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI
1534 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK
1535
1536 #define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \
1537 ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK))
1538 /**
1539 * @}
1540 */
1541
1542 /** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
1543 * @{
1544 */
1545
1546 /* ADC1 & ADC2 */
1547 #define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
1548 #define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
1549 #define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
1550 #define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
1551 #define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
1552 #define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
1553 #define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
1554 #define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
1555 #define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
1556 #define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
1557 #define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
1558 #define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
1559 #define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
1560
1561 #define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \
1562 ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \
1563 ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \
1564 ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \
1565 ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \
1566 ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \
1567 ((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
1568 /**
1569 * @}
1570 */
1571
1572 /** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
1573 * @{
1574 */
1575 #define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
1576 #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
1577
1578 #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \
1579 ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
1580 /**
1581 * @}
1582 */
1583
1584 /** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
1585 * @{
1586 */
1587 #define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
1588 #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
1589
1590 #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
1591 ((SOURCE) == RCC_TIM1CLK_PLLCLK))
1592 /**
1593 * @}
1594 */
1595
1596 /** @defgroup RCCEx_TIM2_Clock_Source RCC Extended TIM2 Clock Source
1597 * @{
1598 */
1599 #define RCC_TIM2CLK_HCLK RCC_CFGR3_TIM2SW_HCLK
1600 #define RCC_TIM2CLK_PLLCLK RCC_CFGR3_TIM2SW_PLL
1601
1602 #define IS_RCC_TIM2CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM2CLK_HCLK) || \
1603 ((SOURCE) == RCC_TIM2CLK_PLLCLK))
1604 /**
1605 * @}
1606 */
1607
1608 /** @defgroup RCCEx_TIM34_Clock_Source RCC Extended TIM3 & TIM4 Clock Source
1609 * @{
1610 */
1611 #define RCC_TIM34CLK_HCLK RCC_CFGR3_TIM34SW_HCLK
1612 #define RCC_TIM34CLK_PLLCLK RCC_CFGR3_TIM34SW_PLL
1613
1614 #define IS_RCC_TIM3CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM34CLK_HCLK) || \
1615 ((SOURCE) == RCC_TIM34CLK_PLLCLK))
1616 /**
1617 * @}
1618 */
1619
1620 /** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source
1621 * @{
1622 */
1623 #define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK
1624 #define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL
1625
1626 #define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) || \
1627 ((SOURCE) == RCC_TIM15CLK_PLLCLK))
1628 /**
1629 * @}
1630 */
1631
1632 /** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source
1633 * @{
1634 */
1635 #define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK
1636 #define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL
1637
1638 #define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) || \
1639 ((SOURCE) == RCC_TIM16CLK_PLLCLK))
1640 /**
1641 * @}
1642 */
1643
1644 /** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source
1645 * @{
1646 */
1647 #define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK
1648 #define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL
1649
1650 #define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) || \
1651 ((SOURCE) == RCC_TIM17CLK_PLLCLK))
1652 /**
1653 * @}
1654 */
1655
1656 /** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source
1657 * @{
1658 */
1659 #define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK
1660 #define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK
1661 #define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE
1662 #define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI
1663
1664 #define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \
1665 ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
1666 ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \
1667 ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
1668 /**
1669 * @}
1670 */
1671
1672 /** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source
1673 * @{
1674 */
1675 #define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK
1676 #define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK
1677 #define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE
1678 #define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI
1679
1680 #define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \
1681 ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
1682 ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \
1683 ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
1684 /**
1685 * @}
1686 */
1687
1688 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
1689
1690 #if defined(STM32F303xE) || defined(STM32F398xx)
1691 /** @defgroup RCCEx_TIM20_Clock_Source RCC Extended TIM20 Clock Source
1692 * @{
1693 */
1694 #define RCC_TIM20CLK_HCLK RCC_CFGR3_TIM20SW_HCLK
1695 #define RCC_TIM20CLK_PLLCLK RCC_CFGR3_TIM20SW_PLL
1696
1697 #define IS_RCC_TIM20CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM20CLK_HCLK) || \
1698 ((SOURCE) == RCC_TIM20CLK_PLLCLK))
1699 /**
1700 * @}
1701 */
1702 #endif /* STM32F303xE || STM32F398xx */
1703
1704 #if defined(STM32F303xE) || defined(STM32F398xx) || \
1705 defined(STM32F303xC) || defined(STM32F358xx)
1706
1707 /** @defgroup RCCEx_ADC34_Clock_Source RCC Extended ADC34 Clock Source
1708 * @{
1709 */
1710
1711 /* ADC3 & ADC4 */
1712 #define RCC_ADC34PLLCLK_OFF RCC_CFGR2_ADCPRE34_NO
1713 #define RCC_ADC34PLLCLK_DIV1 RCC_CFGR2_ADCPRE34_DIV1
1714 #define RCC_ADC34PLLCLK_DIV2 RCC_CFGR2_ADCPRE34_DIV2
1715 #define RCC_ADC34PLLCLK_DIV4 RCC_CFGR2_ADCPRE34_DIV4
1716 #define RCC_ADC34PLLCLK_DIV6 RCC_CFGR2_ADCPRE34_DIV6
1717 #define RCC_ADC34PLLCLK_DIV8 RCC_CFGR2_ADCPRE34_DIV8
1718 #define RCC_ADC34PLLCLK_DIV10 RCC_CFGR2_ADCPRE34_DIV10
1719 #define RCC_ADC34PLLCLK_DIV12 RCC_CFGR2_ADCPRE34_DIV12
1720 #define RCC_ADC34PLLCLK_DIV16 RCC_CFGR2_ADCPRE34_DIV16
1721 #define RCC_ADC34PLLCLK_DIV32 RCC_CFGR2_ADCPRE34_DIV32
1722 #define RCC_ADC34PLLCLK_DIV64 RCC_CFGR2_ADCPRE34_DIV64
1723 #define RCC_ADC34PLLCLK_DIV128 RCC_CFGR2_ADCPRE34_DIV128
1724 #define RCC_ADC34PLLCLK_DIV256 RCC_CFGR2_ADCPRE34_DIV256
1725
1726 #define IS_RCC_ADC34PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC34PLLCLK_OFF) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV1) || \
1727 ((ADCCLK) == RCC_ADC34PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV4) || \
1728 ((ADCCLK) == RCC_ADC34PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV8) || \
1729 ((ADCCLK) == RCC_ADC34PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV12) || \
1730 ((ADCCLK) == RCC_ADC34PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV32) || \
1731 ((ADCCLK) == RCC_ADC34PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV128) || \
1732 ((ADCCLK) == RCC_ADC34PLLCLK_DIV256))
1733 /**
1734 * @}
1735 */
1736
1737 /** @defgroup RCCEx_TIM8_Clock_Source RCC Extended TIM8 Clock Source
1738 * @{
1739 */
1740 #define RCC_TIM8CLK_HCLK RCC_CFGR3_TIM8SW_HCLK
1741 #define RCC_TIM8CLK_PLLCLK RCC_CFGR3_TIM8SW_PLL
1742
1743 #define IS_RCC_TIM8CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM8CLK_HCLK) || \
1744 ((SOURCE) == RCC_TIM8CLK_PLLCLK))
1745 /**
1746 * @}
1747 */
1748
1749 #endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */
1750
1751 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
1752
1753 /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
1754 * @{
1755 */
1756 #define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK
1757 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
1758 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
1759 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
1760
1761 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \
1762 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
1763 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
1764 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
1765 /**
1766 * @}
1767 */
1768
1769 /** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
1770 * @{
1771 */
1772 /* ADC1 & ADC2 */
1773 #define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
1774 #define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
1775 #define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
1776 #define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
1777 #define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
1778 #define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
1779 #define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
1780 #define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
1781 #define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
1782 #define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
1783 #define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
1784 #define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
1785 #define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
1786
1787 #define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \
1788 ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \
1789 ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \
1790 ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \
1791 ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \
1792 ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \
1793 ((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
1794 /**
1795 * @}
1796 */
1797
1798 /** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
1799 * @{
1800 */
1801 #define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
1802 #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
1803
1804 #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
1805 ((SOURCE) == RCC_TIM1CLK_PLLCLK))
1806 /**
1807 * @}
1808 */
1809
1810 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
1811
1812 #if defined(STM32F334x8)
1813
1814 /** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source
1815 * @{
1816 */
1817 #define RCC_HRTIM1CLK_HCLK RCC_CFGR3_HRTIM1SW_HCLK
1818 #define RCC_HRTIM1CLK_PLLCLK RCC_CFGR3_HRTIM1SW_PLL
1819
1820 #define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_HCLK) || \
1821 ((SOURCE) == RCC_HRTIM1CLK_PLLCLK))
1822 /**
1823 * @}
1824 */
1825
1826 #endif /* STM32F334x8 */
1827
1828 #if defined(STM32F373xC) || defined(STM32F378xx)
1829
1830 /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
1831 * @{
1832 */
1833 #define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
1834 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
1835 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
1836 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
1837
1838 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
1839 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
1840 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
1841 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
1842 /**
1843 * @}
1844 */
1845
1846 /** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
1847 * @{
1848 */
1849 #define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
1850 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
1851
1852 #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
1853 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
1854 /**
1855 * @}
1856 */
1857
1858 /** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source
1859 * @{
1860 */
1861
1862 /* ADC1 */
1863 #define RCC_ADC1PCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
1864 #define RCC_ADC1PCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
1865 #define RCC_ADC1PCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
1866 #define RCC_ADC1PCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8
1867
1868 #define IS_RCC_ADC1PCLK2_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PCLK2_DIV2) || ((ADCCLK) == RCC_ADC1PCLK2_DIV4) || \
1869 ((ADCCLK) == RCC_ADC1PCLK2_DIV6) || ((ADCCLK) == RCC_ADC1PCLK2_DIV8))
1870 /**
1871 * @}
1872 */
1873
1874 /** @defgroup RCCEx_CEC_Clock_Source RCC Extended CEC Clock Source
1875 * @{
1876 */
1877 #define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
1878 #define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
1879
1880 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
1881 ((SOURCE) == RCC_CECCLKSOURCE_LSE))
1882 /**
1883 * @}
1884 */
1885
1886 /** @defgroup RCCEx_SDADC_Clock_Prescaler RCC Extended SDADC Clock Prescaler
1887 * @{
1888 */
1889 #define RCC_SDADCSYSCLK_DIV1 RCC_CFGR_SDADCPRE_DIV1
1890 #define RCC_SDADCSYSCLK_DIV2 RCC_CFGR_SDADCPRE_DIV2
1891 #define RCC_SDADCSYSCLK_DIV4 RCC_CFGR_SDADCPRE_DIV4
1892 #define RCC_SDADCSYSCLK_DIV6 RCC_CFGR_SDADCPRE_DIV6
1893 #define RCC_SDADCSYSCLK_DIV8 RCC_CFGR_SDADCPRE_DIV8
1894 #define RCC_SDADCSYSCLK_DIV10 RCC_CFGR_SDADCPRE_DIV10
1895 #define RCC_SDADCSYSCLK_DIV12 RCC_CFGR_SDADCPRE_DIV12
1896 #define RCC_SDADCSYSCLK_DIV14 RCC_CFGR_SDADCPRE_DIV14
1897 #define RCC_SDADCSYSCLK_DIV16 RCC_CFGR_SDADCPRE_DIV16
1898 #define RCC_SDADCSYSCLK_DIV20 RCC_CFGR_SDADCPRE_DIV20
1899 #define RCC_SDADCSYSCLK_DIV24 RCC_CFGR_SDADCPRE_DIV24
1900 #define RCC_SDADCSYSCLK_DIV28 RCC_CFGR_SDADCPRE_DIV28
1901 #define RCC_SDADCSYSCLK_DIV32 RCC_CFGR_SDADCPRE_DIV32
1902 #define RCC_SDADCSYSCLK_DIV36 RCC_CFGR_SDADCPRE_DIV36
1903 #define RCC_SDADCSYSCLK_DIV40 RCC_CFGR_SDADCPRE_DIV40
1904 #define RCC_SDADCSYSCLK_DIV44 RCC_CFGR_SDADCPRE_DIV44
1905 #define RCC_SDADCSYSCLK_DIV48 RCC_CFGR_SDADCPRE_DIV48
1906
1907 #define IS_RCC_SDADCSYSCLK_DIV(DIV) (((DIV) == RCC_SDADCSYSCLK_DIV1) || ((DIV) == RCC_SDADCSYSCLK_DIV2) || \
1908 ((DIV) == RCC_SDADCSYSCLK_DIV4) || ((DIV) == RCC_SDADCSYSCLK_DIV6) || \
1909 ((DIV) == RCC_SDADCSYSCLK_DIV8) || ((DIV) == RCC_SDADCSYSCLK_DIV10) || \
1910 ((DIV) == RCC_SDADCSYSCLK_DIV12) || ((DIV) == RCC_SDADCSYSCLK_DIV14) || \
1911 ((DIV) == RCC_SDADCSYSCLK_DIV16) || ((DIV) == RCC_SDADCSYSCLK_DIV20) || \
1912 ((DIV) == RCC_SDADCSYSCLK_DIV24) || ((DIV) == RCC_SDADCSYSCLK_DIV28) || \
1913 ((DIV) == RCC_SDADCSYSCLK_DIV32) || ((DIV) == RCC_SDADCSYSCLK_DIV36) || \
1914 ((DIV) == RCC_SDADCSYSCLK_DIV40) || ((DIV) == RCC_SDADCSYSCLK_DIV44) || \
1915 ((DIV) == RCC_SDADCSYSCLK_DIV48))
1916 /**
1917 * @}
1918 */
1919
1920 #endif /* STM32F373xC || STM32F378xx */
1921
1922 #if defined(STM32F302xE) || defined(STM32F303xE) || \
1923 defined(STM32F302xC) || defined(STM32F303xC) || \
1924 defined(STM32F302x8) || \
1925 defined(STM32F373xC)
1926 /** @defgroup RCCEx_USB_Clock_Source RCC Extended USB Clock Source
1927 * @{
1928 */
1929 #define RCC_USBPLLCLK_DIV1 RCC_CFGR_USBPRE_DIV1
1930 #define RCC_USBPLLCLK_DIV1_5 RCC_CFGR_USBPRE_DIV1_5
1931
1932 #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBPLLCLK_DIV1) || \
1933 ((SOURCE) == RCC_USBPLLCLK_DIV1_5))
1934 /**
1935 * @}
1936 */
1937
1938 #endif /* STM32F302xE || STM32F303xE || */
1939 /* STM32F302xC || STM32F303xC || */
1940 /* STM32F302x8 || */
1941 /* STM32F373xC */
1942
1943 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
1944 defined(STM32F373xC) || defined(STM32F378xx)
1945 /** @defgroup RCCEx_MCOx_Clock_Prescaler RCC Extended MCOx Clock Prescaler
1946 * @{
1947 */
1948 #define RCC_MCO_NODIV ((uint32_t)0x00000000)
1949
1950 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_NODIV))
1951 /**
1952 * @}
1953 */
1954 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
1955 /* STM32F373xC || STM32F378xx */
1956
1957 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
1958 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
1959 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
1960
1961 /** @defgroup RCCEx_MCOx_Clock_Prescaler RCC Extended MCOx Clock Prescaler
1962 * @{
1963 */
1964 #define RCC_MCO_DIV1 ((uint32_t)0x00000000)
1965 #define RCC_MCO_DIV2 ((uint32_t)0x10000000)
1966 #define RCC_MCO_DIV4 ((uint32_t)0x20000000)
1967 #define RCC_MCO_DIV8 ((uint32_t)0x30000000)
1968 #define RCC_MCO_DIV16 ((uint32_t)0x40000000)
1969 #define RCC_MCO_DIV32 ((uint32_t)0x50000000)
1970 #define RCC_MCO_DIV64 ((uint32_t)0x60000000)
1971 #define RCC_MCO_DIV128 ((uint32_t)0x70000000)
1972
1973 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) || ((DIV) == RCC_MCO_DIV2) || \
1974 ((DIV) == RCC_MCO_DIV4) || ((DIV) == RCC_MCO_DIV8) || \
1975 ((DIV) == RCC_MCO_DIV16) || ((DIV) == RCC_MCO_DIV32) || \
1976 ((DIV) == RCC_MCO_DIV64) || ((DIV) == RCC_MCO_DIV128))
1977 /**
1978 * @}
1979 */
1980
1981 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
1982 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
1983 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
1984
1985 /**
1986 * @}
1987 */
1988
1989 /* Exported macro ------------------------------------------------------------*/
1990 /** @defgroup RCCEx_Exported_Macros RCC Extended Exported Macros
1991 * @{
1992 */
1993
1994 /** @defgroup RCCEx_PLL_Configuration RCC Extended PLL Configuration
1995 * @{
1996 */
1997 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
1998 /** @brief Macro to configure the PLL clock source, multiplication and division factors.
1999 * @note This macro must be used only when the PLL is disabled.
2000 *
2001 * @param __RCC_PLLSource__: specifies the PLL entry clock source.
2002 * This parameter can be one of the following values:
2003 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
2004 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
2005 * @param __PREDIV__: specifies the predivider factor for PLL VCO input clock
2006 * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
2007 * @param __PLLMUL__: specifies the multiplication factor for PLL VCO input clock
2008 * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
2009 *
2010 */
2011 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \
2012 do { \
2013 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
2014 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__))); \
2015 } while(0)
2016 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
2017
2018 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
2019 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
2020 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
2021 defined(STM32F373xC) || defined(STM32F378xx)
2022 /** @brief Macro to configure the PLL clock source and multiplication factor.
2023 * @note This macro must be used only when the PLL is disabled.
2024 *
2025 * @param __RCC_PLLSource__: specifies the PLL entry clock source.
2026 * This parameter can be one of the following values:
2027 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
2028 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
2029 * @param __PLLMUL__: specifies the multiplication factor for PLL VCO input clock
2030 * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
2031 *
2032 */
2033 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PLLMUL__) \
2034 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__)))
2035 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
2036 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2037 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2038 /* STM32F373xC || STM32F378xx */
2039 /**
2040 * @}
2041 */
2042
2043 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
2044 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
2045 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
2046 defined(STM32F373xC) || defined(STM32F378xx)
2047 /** @defgroup RCCEx_HSE_Configuration RCC Extended HSE Configuration
2048 * @{
2049 */
2050
2051 /**
2052 * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
2053 * @note Predivision factor can not be changed if PLL is used as system clock
2054 * In this case, you have to select another source of the system clock, disable the PLL and
2055 * then change the HSE predivision factor.
2056 * @param __HSEPredivValue__: specifies the division value applied to HSE.
2057 * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
2058 */
2059 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSEPredivValue__) \
2060 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSEPredivValue__))
2061 /**
2062 * @}
2063 */
2064 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
2065 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2066 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2067 /* STM32F373xC || STM32F378xx */
2068
2069 /** @defgroup RCCEx_AHB_Clock_Enable_Disable RCC Extended AHB Clock Enable Disable
2070 * @brief Enable or disable the AHB peripheral clock.
2071 * @note After reset, the peripheral clock (used for registers read/write access)
2072 * is disabled and the application software has to enable this clock before
2073 * using it.
2074 * @{
2075 */
2076 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2077 #define __ADC1_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_ADC1EN))
2078
2079 #define __ADC1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC1EN))
2080 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2081
2082 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
2083 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
2084 #define __DMA2_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA2EN))
2085 #define __GPIOE_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOEEN))
2086 #define __ADC12_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_ADC12EN))
2087 /* Aliases for STM32 F3 compatibility */
2088 #define __ADC1_CLK_ENABLE() __ADC12_CLK_ENABLE()
2089 #define __ADC2_CLK_ENABLE() __ADC12_CLK_ENABLE()
2090
2091 #define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
2092 #define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
2093 #define __ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN))
2094 /* Aliases for STM32 F3 compatibility */
2095 #define __ADC1_CLK_DISABLE() __ADC12_CLK_DISABLE()
2096 #define __ADC2_CLK_DISABLE() __ADC12_CLK_DISABLE()
2097 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2098 /* STM32F302xC || STM32F303xC || STM32F358xx */
2099
2100 #if defined(STM32F303xE) || defined(STM32F398xx) || \
2101 defined(STM32F303xC) || defined(STM32F358xx)
2102 #define __ADC34_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_ADC34EN))
2103
2104 #define __ADC34_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC34EN))
2105 #endif /* STM32F303xE || STM32F398xx || */
2106 /* STM32F303xC || STM32F358xx */
2107
2108 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
2109 #define __ADC12_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_ADC12EN))
2110 /* Aliases for STM32 F3 compatibility */
2111 #define __ADC1_CLK_ENABLE() __ADC12_CLK_ENABLE()
2112 #define __ADC2_CLK_ENABLE() __ADC12_CLK_ENABLE()
2113
2114 #define __ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN))
2115 /* Aliases for STM32 F3 compatibility */
2116 #define __ADC1_CLK_DISABLE() __ADC12_CLK_DISABLE()
2117 #define __ADC2_CLK_DISABLE() __ADC12_CLK_DISABLE()
2118 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
2119
2120 #if defined(STM32F373xC) || defined(STM32F378xx)
2121 #define __DMA2_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA2EN))
2122 #define __GPIOE_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOEEN))
2123
2124 #define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
2125 #define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
2126 #endif /* STM32F373xC || STM32F378xx */
2127
2128 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
2129 #define __FMC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_FMCEN))
2130 #define __GPIOG_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOGEN))
2131 #define __GPIOH_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOHEN))
2132
2133 #define __FMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FMCEN))
2134 #define __GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN))
2135 #define __GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN))
2136 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
2137 /**
2138 * @}
2139 */
2140
2141 /** @defgroup RCCEx_APB1_Clock_Enable_Disable RCC Extended APB1 Clock Enable Disable
2142 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
2143 * @note After reset, the peripheral clock (used for registers read/write access)
2144 * is disabled and the application software has to enable this clock before
2145 * using it.
2146 * @{
2147 */
2148 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2149 #define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
2150 #define __SPI3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI3EN))
2151 #define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
2152 #define __I2C3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C3EN))
2153
2154 #define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
2155 #define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
2156 #define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
2157 #define __I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
2158 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2159
2160 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
2161 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
2162 #define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
2163 #define __TIM4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN))
2164 #define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
2165 #define __SPI3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI3EN))
2166 #define __UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN))
2167 #define __UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN))
2168 #define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
2169
2170 #define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
2171 #define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
2172 #define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
2173 #define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
2174 #define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
2175 #define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
2176 #define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
2177 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2178 /* STM32F302xC || STM32F303xC || STM32F358xx */
2179
2180 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
2181 #define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
2182 #define __DAC2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DAC2EN))
2183
2184 #define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
2185 #define __DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
2186 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
2187
2188 #if defined(STM32F373xC) || defined(STM32F378xx)
2189 #define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
2190 #define __TIM4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN))
2191 #define __TIM5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM5EN))
2192 #define __TIM12_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM12EN))
2193 #define __TIM13_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM13EN))
2194 #define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
2195 #define __TIM18_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM18EN))
2196 #define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
2197 #define __SPI3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI3EN))
2198 #define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
2199 #define __DAC2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DAC2EN))
2200 #define __CEC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CECEN))
2201
2202 #define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
2203 #define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
2204 #define __TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
2205 #define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
2206 #define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
2207 #define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
2208 #define __TIM18_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM18EN))
2209 #define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
2210 #define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
2211 #define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
2212 #define __DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
2213 #define __CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
2214 #endif /* STM32F373xC || STM32F378xx */
2215
2216 #if defined(STM32F303xE) || defined(STM32F398xx) || \
2217 defined(STM32F303xC) || defined(STM32F358xx) || \
2218 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
2219 defined(STM32F373xC) || defined(STM32F378xx)
2220 #define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
2221
2222 #define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
2223 #endif /* STM32F303xE || STM32F398xx || */
2224 /* STM32F303xC || STM32F358xx || */
2225 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2226 /* STM32F373xC || STM32F378xx */
2227
2228 #if defined(STM32F302xE) || defined(STM32F303xE) || \
2229 defined(STM32F302xC) || defined(STM32F303xC) || \
2230 defined(STM32F302x8) || \
2231 defined(STM32F373xC)
2232 #define __USB_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USBEN))
2233
2234 #define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
2235 #endif /* STM32F302xE || STM32F303xE || */
2236 /* STM32F302xC || STM32F303xC || */
2237 /* STM32F302x8 || */
2238 /* STM32F373xC */
2239
2240 #if !defined(STM32F301x8)
2241 #define __CAN_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CANEN))
2242
2243 #define __CAN_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
2244 #endif /* STM32F301x8*/
2245
2246 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
2247 #define __I2C3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C3EN))
2248
2249 #define __I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
2250 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
2251 /**
2252 * @}
2253 */
2254
2255 /** @defgroup RCCEx_APB2_Clock_Enable_Disable RCC Extended APB2 Clock Enable Disable
2256 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
2257 * @note After reset, the peripheral clock (used for registers read/write access)
2258 * is disabled and the application software has to enable this clock before
2259 * using it.
2260 * @{
2261 */
2262 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
2263 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
2264 #define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
2265
2266 #define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
2267 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2268 /* STM32F302xC || STM32F303xC || STM32F358xx */
2269
2270 #if defined(STM32F303xE) || defined(STM32F398xx) || \
2271 defined(STM32F303xC) || defined(STM32F358xx)
2272 #define __TIM8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN))
2273
2274 #define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
2275 #endif /* STM32F303xE || STM32F398xx || */
2276 /* STM32F303xC || STM32F358xx */
2277
2278 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
2279 #define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
2280
2281 #define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
2282 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
2283
2284 #if defined(STM32F334x8)
2285 #define __HRTIM1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_HRTIM1EN))
2286
2287 #define __HRTIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_HRTIM1EN))
2288 #endif /* STM32F334x8 */
2289
2290 #if defined(STM32F373xC) || defined(STM32F378xx)
2291 #define __ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN))
2292 #define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
2293 #define __TIM19_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM19EN))
2294 #define __SDADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SDADC1EN))
2295 #define __SDADC2_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SDADC2EN))
2296 #define __SDADC3_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SDADC3EN))
2297
2298 #define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
2299 #define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
2300 #define __TIM19_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM19EN))
2301 #define __SDADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC1EN))
2302 #define __SDADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC2EN))
2303 #define __SDADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC3EN))
2304 #endif /* STM32F373xC || STM32F378xx */
2305
2306 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
2307 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
2308 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
2309 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2310 #define __TIM1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM1EN))
2311
2312 #define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
2313 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2314 /* STM32F302xC || STM32F303xC || STM32F358xx || */
2315 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2316 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2317
2318 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
2319 #define __SPI4_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI4EN))
2320
2321 #define __SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
2322 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
2323
2324 #if defined(STM32F303xE) || defined(STM32F398xx)
2325 #define __TIM20_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM20EN))
2326
2327 #define __TIM20_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM20EN))
2328 #endif /* STM32F303xE || STM32F398xx */
2329
2330 /**
2331 * @}
2332 */
2333
2334 /** @defgroup RCCEx_AHB_Force_Release_Reset RCC Extended AHB Force Release Reset
2335 * @brief Force or release AHB peripheral reset.
2336 * @{
2337 */
2338 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2339 #define __ADC1_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC1RST))
2340
2341 #define __ADC1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC1RST))
2342 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2343
2344 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
2345 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
2346 #define __GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
2347 #define __ADC12_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC12RST))
2348 /* Aliases for STM32 F3 compatibility */
2349 #define __ADC1_FORCE_RESET() __ADC12_FORCE_RESET()
2350 #define __ADC2_FORCE_RESET() __ADC12_FORCE_RESET()
2351
2352 #define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
2353 #define __ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST))
2354 /* Aliases for STM32 F3 compatibility */
2355 #define __ADC1_RELEASE_RESET() __ADC12_RELEASE_RESET()
2356 #define __ADC2_RELEASE_RESET() __ADC12_RELEASE_RESET()
2357 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2358 /* STM32F302xC || STM32F303xC || STM32F358xx */
2359
2360 #if defined(STM32F303xE) || defined(STM32F398xx) || \
2361 defined(STM32F303xC) || defined(STM32F358xx)
2362 #define __ADC34_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC34RST))
2363
2364 #define __ADC34_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC34RST))
2365 #endif /* STM32F303xE || STM32F398xx || */
2366 /* STM32F303xC || STM32F358xx */
2367
2368 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
2369 #define __ADC12_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC12RST))
2370 /* Aliases for STM32 F3 compatibility */
2371 #define __ADC1_FORCE_RESET() __ADC12_FORCE_RESET()
2372 #define __ADC2_FORCE_RESET() __ADC12_FORCE_RESET()
2373
2374 #define __ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST))
2375 /* Aliases for STM32 F3 compatibility */
2376 #define __ADC1_RELEASE_RESET() __ADC12_RELEASE_RESET()
2377 #define __ADC2_RELEASE_RESET() __ADC12_RELEASE_RESET()
2378 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
2379
2380 #if defined(STM32F373xC) || defined(STM32F378xx)
2381 #define __GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
2382
2383 #define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
2384 #endif /* STM32F373xC || STM32F378xx */
2385
2386 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
2387 #define __FMC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FMCRST))
2388 #define __GPIOG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST))
2389 #define __GPIOH_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOHRST))
2390
2391 #define __FMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FMCRST))
2392 #define __GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST))
2393 #define __GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST))
2394 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
2395 /**
2396 * @}
2397 */
2398
2399 /** @defgroup RCCEx_APB1_Force_Release_Reset RCC Extended APB1 Force Release Reset
2400 * @brief Force or release APB1 peripheral reset.
2401 * @{
2402 */
2403 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2404 #define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
2405 #define __SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
2406 #define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
2407 #define __I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
2408
2409 #define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
2410 #define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
2411 #define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
2412 #define __I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
2413 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2414
2415 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
2416 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
2417 #define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
2418 #define __TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
2419 #define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
2420 #define __SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
2421 #define __UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
2422 #define __UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
2423 #define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
2424
2425 #define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
2426 #define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
2427 #define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
2428 #define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
2429 #define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
2430 #define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
2431 #define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
2432 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2433 /* STM32F302xC || STM32F303xC || STM32F358xx */
2434
2435 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
2436 #define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
2437 #define __DAC2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC2RST))
2438
2439 #define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
2440 #define __DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
2441 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
2442
2443 #if defined(STM32F373xC) || defined(STM32F378xx)
2444 #define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
2445 #define __TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
2446 #define __TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
2447 #define __TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
2448 #define __TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
2449 #define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
2450 #define __TIM18_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM18RST))
2451 #define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
2452 #define __SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
2453 #define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
2454 #define __DAC2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC2RST))
2455 #define __CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
2456
2457 #define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
2458 #define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
2459 #define __TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
2460 #define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
2461 #define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
2462 #define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
2463 #define __TIM18_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM18RST))
2464 #define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
2465 #define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
2466 #define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
2467 #define __DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
2468 #define __CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
2469 #endif /* STM32F373xC || STM32F378xx */
2470
2471 #if defined(STM32F303xE) || defined(STM32F398xx) || \
2472 defined(STM32F303xC) || defined(STM32F358xx) || \
2473 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
2474 defined(STM32F373xC) || defined(STM32F378xx)
2475 #define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
2476
2477 #define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
2478 #endif /* STM32F303xE || STM32F398xx || */
2479 /* STM32F303xC || STM32F358xx || */
2480 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2481 /* STM32F373xC || STM32F378xx */
2482
2483 #if defined(STM32F302xE) || defined(STM32F303xE) || \
2484 defined(STM32F302xC) || defined(STM32F303xC) || \
2485 defined(STM32F302x8) || \
2486 defined(STM32F373xC)
2487 #define __USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
2488
2489 #define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
2490 #endif /* STM32F302xE || STM32F303xE || */
2491 /* STM32F302xC || STM32F303xC || */
2492 /* STM32F302x8 || */
2493 /* STM32F373xC */
2494
2495 #if !defined(STM32F301x8)
2496 #define __CAN_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST))
2497
2498 #define __CAN_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
2499 #endif /* STM32F301x8*/
2500
2501 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
2502 #define __I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
2503
2504 #define __I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
2505 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
2506 /**
2507 * @}
2508 */
2509
2510 /** @defgroup RCCEx_APB2_Force_Release_Reset RCC Extended APB2 Force Release Reset
2511 * @brief Force or release APB2 peripheral reset.
2512 * @{
2513 */
2514 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
2515 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
2516 #define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
2517
2518 #define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
2519 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2520 /* STM32F302xC || STM32F303xC || STM32F358xx */
2521
2522 #if defined(STM32F303xE) || defined(STM32F398xx) || \
2523 defined(STM32F303xC) || defined(STM32F358xx)
2524 #define __TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
2525
2526 #define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
2527 #endif /* STM32F303xE || STM32F398xx || */
2528 /* STM32F303xC || STM32F358xx */
2529
2530 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
2531 #define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
2532
2533 #define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
2534 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
2535
2536 #if defined(STM32F334x8)
2537 #define __HRTIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_HRTIM1RST))
2538
2539 #define __HRTIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_HRTIM1RST))
2540 #endif /* STM32F334x8 */
2541
2542 #if defined(STM32F373xC) || defined(STM32F378xx)
2543 #define __ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
2544 #define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
2545 #define __TIM19_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM19RST))
2546 #define __SDADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC1RST))
2547 #define __SDADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC2RST))
2548 #define __SDADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC3RST))
2549
2550 #define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
2551 #define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
2552 #define __TIM19_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM19RST))
2553 #define __SDADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC1RST))
2554 #define __SDADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC2RST))
2555 #define __SDADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC3RST))
2556 #endif /* STM32F373xC || STM32F378xx */
2557
2558 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
2559 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
2560 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
2561 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2562 #define __TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
2563
2564 #define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
2565 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2566 /* STM32F302xC || STM32F303xC || STM32F358xx || */
2567 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
2568 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2569
2570 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
2571 #define __SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
2572
2573 #define __SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
2574 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
2575
2576 #if defined(STM32F303xE) || defined(STM32F398xx)
2577 #define __TIM20_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM20RST))
2578
2579 #define __TIM20_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM20RST))
2580 #endif /* STM32F303xE || STM32F398xx */
2581
2582 /**
2583 * @}
2584 */
2585
2586 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
2587 /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
2588 * @{
2589 */
2590
2591 /** @brief Macro to configure the I2C2 clock (I2C2CLK).
2592 * @param __I2C2CLKSource__: specifies the I2C2 clock source.
2593 * This parameter can be one of the following values:
2594 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
2595 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
2596 */
2597 #define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
2598 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
2599
2600 /** @brief Macro to get the I2C2 clock source.
2601 * @retval The clock source can be one of the following values:
2602 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
2603 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
2604 */
2605 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
2606
2607 /** @brief Macro to configure the I2C3 clock (I2C3CLK).
2608 * @param __I2C3CLKSource__: specifies the I2C3 clock source.
2609 * This parameter can be one of the following values:
2610 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
2611 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
2612 */
2613 #define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
2614 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__))
2615
2616 /** @brief Macro to get the I2C3 clock source.
2617 * @retval The clock source can be one of the following values:
2618 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
2619 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
2620 */
2621 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW)))
2622
2623 /**
2624 * @}
2625 */
2626
2627 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
2628 * @{
2629 */
2630 /** @brief Macro to configure the TIM1 clock (TIM1CLK).
2631 * @param __TIM1CLKSource__: specifies the TIM1 clock source.
2632 * This parameter can be one of the following values:
2633 * @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
2634 * @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
2635 */
2636 #define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
2637 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
2638
2639 /** @brief Macro to get the TIM1 clock (TIM1CLK).
2640 * @retval The clock source can be one of the following values:
2641 * This parameter can be one of the following values:
2642 * @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
2643 * @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
2644 */
2645 #define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
2646
2647 /** @brief Macro to configure the TIM15 clock (TIM15CLK).
2648 * @param __TIM15CLKSource__: specifies the TIM15 clock source.
2649 * This parameter can be one of the following values:
2650 * @arg RCC_TIM15CLKSOURCE_HCLK: HCLK selected as TIM15 clock
2651 * @arg RCC_TIM15CLKSOURCE_PLL: PLL Clock selected as TIM15 clock
2652 */
2653 #define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \
2654 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__))
2655
2656 /** @brief Macro to get the TIM15 clock (TIM15CLK).
2657 * @retval The clock source can be one of the following values:
2658 * This parameter can be one of the following values:
2659 * @arg RCC_TIM15CLKSOURCE_HCLK: HCLK selected as TIM15 clock
2660 * @arg RCC_TIM15CLKSOURCE_PLL: PLL Clock selected as TIM15 clock
2661 */
2662 #define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW)))
2663
2664 /** @brief Macro to configure the TIM16 clock (TIM16CLK).
2665 * @param __TIM16CLKSource__: specifies the TIM16 clock source.
2666 * This parameter can be one of the following values:
2667 * @arg RCC_TIM16CLKSOURCE_HCLK: HCLK selected as TIM16 clock
2668 * @arg RCC_TIM16CLKSOURCE_PLL: PLL Clock selected as TIM16 clock
2669 */
2670 #define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \
2671 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__))
2672
2673 /** @brief Macro to get the TIM16 clock (TIM16CLK).
2674 * @retval The clock source can be one of the following values:
2675 * This parameter can be one of the following values:
2676 * @arg RCC_TIM16CLKSOURCE_HCLK: HCLK selected as TIM16 clock
2677 * @arg RCC_TIM16CLKSOURCE_PLL: PLL Clock selected as TIM16 clock
2678 */
2679 #define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW)))
2680
2681 /** @brief Macro to configure the TIM17 clock (TIM17CLK).
2682 * @param __TIM17CLKSource__: specifies the TIM17 clock source.
2683 * This parameter can be one of the following values:
2684 * @arg RCC_TIM17CLKSOURCE_HCLK: HCLK selected as TIM17 clock
2685 * @arg RCC_TIM17CLKSOURCE_PLL: PLL Clock selected as TIM17 clock
2686 */
2687 #define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \
2688 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__))
2689
2690 /** @brief Macro to get the TIM17 clock (TIM17CLK).
2691 * @retval The clock source can be one of the following values:
2692 * This parameter can be one of the following values:
2693 * @arg RCC_TIM17CLKSOURCE_HCLK: HCLK selected as TIM17 clock
2694 * @arg RCC_TIM17CLKSOURCE_PLL: PLL Clock selected as TIM17 clock
2695 */
2696 #define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
2697
2698 /**
2699 * @}
2700 */
2701
2702 /** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config
2703 * @{
2704 */
2705 /** @brief Macro to configure the I2S clock source (I2SCLK).
2706 * @note This function must be called before enabling the I2S APB clock.
2707 * @param __I2SCLKSource__: specifies the I2S clock source.
2708 * This parameter can be one of the following values:
2709 * @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source
2710 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
2711 * used as I2S clock source
2712 */
2713 #define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \
2714 MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__))
2715
2716 /** @brief Macro to get the I2S clock source (I2SCLK).
2717 * @retval The clock source can be one of the following values:
2718 * @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source
2719 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
2720 * used as I2S clock source
2721 */
2722 #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
2723 /**
2724 * @}
2725 */
2726
2727 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
2728 * @{
2729 */
2730
2731 /** @brief Macro to configure the ADC1 clock (ADC1CLK).
2732 * @param __ADC1CLKSource__: specifies the ADC1 clock source.
2733 * This parameter can be one of the following values:
2734 * @arg RCC_ADC1PLLCLK_OFF: ADC1 PLL clock disabled, ADC1 can use AHB clock
2735 * @arg RCC_ADC1PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 clock
2736 * @arg RCC_ADC1PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 clock
2737 * @arg RCC_ADC1PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 clock
2738 * @arg RCC_ADC1PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 clock
2739 * @arg RCC_ADC1PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 clock
2740 * @arg RCC_ADC1PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 clock
2741 * @arg RCC_ADC1PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 clock
2742 * @arg RCC_ADC1PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 clock
2743 * @arg RCC_ADC1PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 clock
2744 * @arg RCC_ADC1PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 clock
2745 * @arg RCC_ADC1PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 clock
2746 * @arg RCC_ADC1PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 clock
2747 */
2748 #define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \
2749 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, (uint32_t)(__ADC1CLKSource__))
2750
2751 /** @brief Macro to get the ADC1 clock
2752 * @retval The clock source can be one of the following values:
2753 * @arg RCC_ADC1PLLCLK_OFF: ADC1 PLL clock disabled, ADC1 can use AHB clock
2754 * @arg RCC_ADC1PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 clock
2755 * @arg RCC_ADC1PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 clock
2756 * @arg RCC_ADC1PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 clock
2757 * @arg RCC_ADC1PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 clock
2758 * @arg RCC_ADC1PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 clock
2759 * @arg RCC_ADC1PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 clock
2760 * @arg RCC_ADC1PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 clock
2761 * @arg RCC_ADC1PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 clock
2762 * @arg RCC_ADC1PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 clock
2763 * @arg RCC_ADC1PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 clock
2764 * @arg RCC_ADC1PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 clock
2765 * @arg RCC_ADC1PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 clock
2766 */
2767 #define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADC1PRES)))
2768 /**
2769 * @}
2770 */
2771
2772 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
2773
2774 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
2775 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
2776 /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
2777 * @{
2778 */
2779
2780 /** @brief Macro to configure the I2C2 clock (I2C2CLK).
2781 * @param __I2C2CLKSource__: specifies the I2C2 clock source.
2782 * This parameter can be one of the following values:
2783 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
2784 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
2785 */
2786 #define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
2787 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
2788
2789 /** @brief Macro to get the I2C2 clock source.
2790 * @retval The clock source can be one of the following values:
2791 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
2792 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
2793 */
2794 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
2795 /**
2796 * @}
2797 */
2798
2799 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
2800 * @{
2801 */
2802
2803 /** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
2804 * @param __ADC12CLKSource__: specifies the ADC1 & ADC2 clock source.
2805 * This parameter can be one of the following values:
2806 * @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
2807 * @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock
2808 * @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock
2809 * @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock
2810 * @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock
2811 * @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock
2812 * @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock
2813 * @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock
2814 * @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock
2815 * @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock
2816 * @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock
2817 * @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock
2818 * @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
2819 */
2820 #define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \
2821 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__))
2822
2823 /** @brief Macro to get the ADC1 & ADC2 clock
2824 * @retval The clock source can be one of the following values:
2825 * @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
2826 * @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock
2827 * @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock
2828 * @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock
2829 * @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock
2830 * @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock
2831 * @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock
2832 * @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock
2833 * @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock
2834 * @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock
2835 * @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock
2836 * @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock
2837 * @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
2838 */
2839 #define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
2840 /**
2841 * @}
2842 */
2843
2844 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
2845 * @{
2846 */
2847
2848 /** @brief Macro to configure the TIM1 clock (TIM1CLK).
2849 * @param __TIM1CLKSource__: specifies the TIM1 clock source.
2850 * This parameter can be one of the following values:
2851 * @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
2852 * @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
2853 */
2854 #define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
2855 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
2856
2857 /** @brief Macro to get the TIM1 clock (TIM1CLK).
2858 * @retval The clock source can be one of the following values:
2859 * This parameter can be one of the following values:
2860 * @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
2861 * @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
2862 */
2863 #define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
2864 /**
2865 * @}
2866 */
2867
2868 /** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config
2869 * @{
2870 */
2871
2872 /** @brief Macro to configure the I2S clock source (I2SCLK).
2873 * @note This function must be called before enabling the I2S APB clock.
2874 * @param __I2SCLKSource__: specifies the I2S clock source.
2875 * This parameter can be one of the following values:
2876 * @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source
2877 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
2878 * used as I2S clock source
2879 */
2880 #define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \
2881 MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__))
2882
2883 /** @brief Macro to get the I2S clock source (I2SCLK).
2884 * @retval The clock source can be one of the following values:
2885 * @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source
2886 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
2887 * used as I2S clock source
2888 */
2889 #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
2890 /**
2891 * @}
2892 */
2893
2894 /** @defgroup RCCEx_UARTx_Clock_Config RCC Extended UARTx Clock Config
2895 * @{
2896 */
2897
2898 /** @brief Macro to configure the UART4 clock (UART4CLK).
2899 * @param __UART4CLKSource__: specifies the UART4 clock source.
2900 * This parameter can be one of the following values:
2901 * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
2902 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
2903 * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
2904 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
2905 */
2906 #define __HAL_RCC_UART4_CONFIG(__UART4CLKSource__) \
2907 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART4SW, (uint32_t)(__UART4CLKSource__))
2908
2909 /** @brief Macro to get the UART4 clock source.
2910 * @retval The clock source can be one of the following values:
2911 * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
2912 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
2913 * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
2914 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
2915 */
2916 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART4SW)))
2917
2918 /** @brief Macro to configure the UART5 clock (UART5CLK).
2919 * @param __UART5CLKSource__: specifies the UART5 clock source.
2920 * This parameter can be one of the following values:
2921 * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
2922 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
2923 * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
2924 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
2925 */
2926 #define __HAL_RCC_UART5_CONFIG(__UART5CLKSource__) \
2927 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART5SW, (uint32_t)(__UART5CLKSource__))
2928
2929 /** @brief Macro to get the UART5 clock source.
2930 * @retval The clock source can be one of the following values:
2931 * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
2932 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
2933 * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
2934 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
2935 */
2936 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART5SW)))
2937 /**
2938 * @}
2939 */
2940 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
2941 /* STM32F302xC || STM32F303xC || STM32F358xx */
2942
2943 #if defined(STM32F303xE) || defined(STM32F398xx) || \
2944 defined(STM32F303xC) || defined(STM32F358xx)
2945 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
2946 * @{
2947 */
2948
2949 /** @brief Macro to configure the ADC3 & ADC4 clock (ADC34CLK).
2950 * @param __ADC34CLKSource__: specifies the ADC3 & ADC4 clock source.
2951 * This parameter can be one of the following values:
2952 * @arg RCC_ADC34PLLCLK_OFF: ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock
2953 * @arg RCC_ADC34PLLCLK_DIV1: PLL clock divided by 1 selected as ADC3 & ADC4 clock
2954 * @arg RCC_ADC34PLLCLK_DIV2: PLL clock divided by 2 selected as ADC3 & ADC4 clock
2955 * @arg RCC_ADC34PLLCLK_DIV4: PLL clock divided by 4 selected as ADC3 & ADC4 clock
2956 * @arg RCC_ADC34PLLCLK_DIV6: PLL clock divided by 6 selected as ADC3 & ADC4 clock
2957 * @arg RCC_ADC34PLLCLK_DIV8: PLL clock divided by 8 selected as ADC3 & ADC4 clock
2958 * @arg RCC_ADC34PLLCLK_DIV10: PLL clock divided by 10 selected as ADC3 & ADC4 clock
2959 * @arg RCC_ADC34PLLCLK_DIV12: PLL clock divided by 12 selected as ADC3 & ADC4 clock
2960 * @arg RCC_ADC34PLLCLK_DIV16: PLL clock divided by 16 selected as ADC3 & ADC4 clock
2961 * @arg RCC_ADC34PLLCLK_DIV32: PLL clock divided by 32 selected as ADC3 & ADC4 clock
2962 * @arg RCC_ADC34PLLCLK_DIV64: PLL clock divided by 64 selected as ADC3 & ADC4 clock
2963 * @arg RCC_ADC34PLLCLK_DIV128: PLL clock divided by 128 selected as ADC3 & ADC4 clock
2964 * @arg RCC_ADC34PLLCLK_DIV256: PLL clock divided by 256 selected as ADC3 & ADC4 clock
2965 */
2966 #define __HAL_RCC_ADC34_CONFIG(__ADC34CLKSource__) \
2967 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE34, (uint32_t)(__ADC34CLKSource__))
2968
2969 /** @brief Macro to get the ADC3 & ADC4 clock
2970 * @retval The clock source can be one of the following values:
2971 * @arg RCC_ADC34PLLCLK_OFF: ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock
2972 * @arg RCC_ADC34PLLCLK_DIV1: PLL clock divided by 1 selected as ADC3 & ADC4 clock
2973 * @arg RCC_ADC34PLLCLK_DIV2: PLL clock divided by 2 selected as ADC3 & ADC4 clock
2974 * @arg RCC_ADC34PLLCLK_DIV4: PLL clock divided by 4 selected as ADC3 & ADC4 clock
2975 * @arg RCC_ADC34PLLCLK_DIV6: PLL clock divided by 6 selected as ADC3 & ADC4 clock
2976 * @arg RCC_ADC34PLLCLK_DIV8: PLL clock divided by 8 selected as ADC3 & ADC4 clock
2977 * @arg RCC_ADC34PLLCLK_DIV10: PLL clock divided by 10 selected as ADC3 & ADC4 clock
2978 * @arg RCC_ADC34PLLCLK_DIV12: PLL clock divided by 12 selected as ADC3 & ADC4 clock
2979 * @arg RCC_ADC34PLLCLK_DIV16: PLL clock divided by 16 selected as ADC3 & ADC4 clock
2980 * @arg RCC_ADC34PLLCLK_DIV32: PLL clock divided by 32 selected as ADC3 & ADC4 clock
2981 * @arg RCC_ADC34PLLCLK_DIV64: PLL clock divided by 64 selected as ADC3 & ADC4 clock
2982 * @arg RCC_ADC34PLLCLK_DIV128: PLL clock divided by 128 selected as ADC3 & ADC4 clock
2983 * @arg RCC_ADC34PLLCLK_DIV256: PLL clock divided by 256 selected as ADC3 & ADC4 clock
2984 */
2985 #define __HAL_RCC_GET_ADC34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE34)))
2986 /**
2987 * @}
2988 */
2989
2990 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
2991 * @{
2992 */
2993
2994 /** @brief Macro to configure the TIM8 clock (TIM8CLK).
2995 * @param __TIM8CLKSource__: specifies the TIM8 clock source.
2996 * This parameter can be one of the following values:
2997 * @arg RCC_TIM8CLKSOURCE_HCLK: HCLK selected as TIM8 clock
2998 * @arg RCC_TIM8CLKSOURCE_PLL: PLL Clock selected as TIM8 clock
2999 */
3000 #define __HAL_RCC_TIM8_CONFIG(__TIM8CLKSource__) \
3001 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM8SW, (uint32_t)(__TIM8CLKSource__))
3002
3003 /** @brief Macro to get the TIM8 clock (TIM8CLK).
3004 * @retval The clock source can be one of the following values:
3005 * This parameter can be one of the following values:
3006 * @arg RCC_TIM8CLKSOURCE_HCLK: HCLK selected as TIM8 clock
3007 * @arg RCC_TIM8CLKSOURCE_PLL: PLL Clock selected as TIM8 clock
3008 */
3009 #define __HAL_RCC_GET_TIM8_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM8SW)))
3010
3011 /**
3012 * @}
3013 */
3014 #endif /* STM32F303xE || STM32F398xx || */
3015 /* STM32F303xC || STM32F358xx */
3016
3017 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
3018 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
3019 * @{
3020 */
3021
3022 /** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
3023 * @param __ADC12CLKSource__: specifies the ADC1 & ADC2 clock source.
3024 * This parameter can be one of the following values:
3025 * @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
3026 * @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock
3027 * @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock
3028 * @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock
3029 * @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock
3030 * @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock
3031 * @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock
3032 * @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock
3033 * @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock
3034 * @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock
3035 * @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock
3036 * @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock
3037 * @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
3038 */
3039 #define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \
3040 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__))
3041
3042 /** @brief Macro to get the ADC1 & ADC2 clock
3043 * @retval The clock source can be one of the following values:
3044 * @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
3045 * @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock
3046 * @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock
3047 * @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock
3048 * @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock
3049 * @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock
3050 * @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock
3051 * @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock
3052 * @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock
3053 * @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock
3054 * @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock
3055 * @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock
3056 * @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
3057 */
3058 #define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
3059 /**
3060 * @}
3061 */
3062
3063 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
3064 * @{
3065 */
3066 /** @brief Macro to configure the TIM1 clock (TIM1CLK).
3067 * @param __TIM1CLKSource__: specifies the TIM1 clock source.
3068 * This parameter can be one of the following values:
3069 * @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
3070 * @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
3071 */
3072 #define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
3073 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
3074
3075 /** @brief Macro to get the TIM1 clock (TIM1CLK).
3076 * @retval The clock source can be one of the following values:
3077 * This parameter can be one of the following values:
3078 * @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
3079 * @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
3080 */
3081 #define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
3082 /**
3083 * @}
3084 */
3085 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
3086
3087 #if defined(STM32F334x8)
3088 /** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config
3089 * @{
3090 */
3091 /** @brief Macro to configure the HRTIM1 clock.
3092 * @param __HRTIM1CLKSource__: specifies the HRTIM1 clock source.
3093 * This parameter can be one of the following values:
3094 * @arg RCC_HRTIM1CLKSOURCE_HCLK: HCLK selected as HRTIM1 clock
3095 * @arg RCC_HRTIM1CLKSOURCE_PLL: PLL Clock selected as HRTIM1 clock
3096 */
3097 #define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \
3098 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_HRTIM1SW, (uint32_t)(__HRTIM1CLKSource__))
3099
3100 /** @brief Macro to get the HRTIM1 clock source.
3101 * @retval The clock source can be one of the following values:
3102 * @arg RCC_HRTIM1CLKSOURCE_HCLK: HCLK selected as HRTIM1 clock
3103 * @arg RCC_HRTIM1CLKSOURCE_PLL: PLL Clock selected as HRTIM1 clock
3104 */
3105 #define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_HRTIM1SW)))
3106 /**
3107 * @}
3108 */
3109 #endif /* STM32F334x8 */
3110
3111 #if defined(STM32F373xC) || defined(STM32F378xx)
3112 /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
3113 * @{
3114 */
3115 /** @brief Macro to configure the I2C2 clock (I2C2CLK).
3116 * @param __I2C2CLKSource__: specifies the I2C2 clock source.
3117 * This parameter can be one of the following values:
3118 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
3119 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
3120 */
3121 #define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
3122 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
3123
3124 /** @brief Macro to get the I2C2 clock source.
3125 * @retval The clock source can be one of the following values:
3126 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
3127 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
3128 */
3129 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
3130 /**
3131 * @}
3132 */
3133
3134 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
3135 * @{
3136 */
3137 /** @brief Macro to configure the ADC1 clock (ADC1CLK).
3138 * @param __ADC1CLKSource__: specifies the ADC1 clock source.
3139 * This parameter can be one of the following values:
3140 * @arg RCC_ADC1PCLK2_DIV2: PCLK2 clock divided by 2 selected as ADC1 clock
3141 * @arg RCC_ADC1PCLK2_DIV4: PCLK2 clock divided by 4 selected as ADC1 clock
3142 * @arg RCC_ADC1PCLK2_DIV6: PCLK2 clock divided by 6 selected as ADC1 clock
3143 * @arg RCC_ADC1PCLK2_DIV8: PCLK2 clock divided by 8 selected as ADC1 clock
3144 */
3145 #define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \
3146 MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADC1CLKSource__))
3147
3148 /** @brief Macro to get the ADC1 clock (ADC1CLK).
3149 * @retval The clock source can be one of the following values:
3150 * @arg RCC_ADC1PCLK2_DIV2: PCLK2 clock divided by 2 selected as ADC1 clock
3151 * @arg RCC_ADC1PCLK2_DIV4: PCLK2 clock divided by 4 selected as ADC1 clock
3152 * @arg RCC_ADC1PCLK2_DIV6: PCLK2 clock divided by 6 selected as ADC1 clock
3153 * @arg RCC_ADC1PCLK2_DIV8: PCLK2 clock divided by 8 selected as ADC1 clock
3154 */
3155 #define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
3156 /**
3157 * @}
3158 */
3159
3160 /** @defgroup RCCEx_SDADCx_Clock_Config RCC Extended SDADCx Clock Config
3161 * @{
3162 */
3163 /** @brief Macro to configure the SDADCx clock (SDADCxCLK).
3164 * @param __SDADCPrescaler__: specifies the SDADCx system clock prescaler.
3165 * This parameter can be one of the following values:
3166 * @arg RCC_SDADCSYSCLK_DIV1: SYSCLK clock selected as SDADCx clock
3167 * @arg RCC_SDADCSYSCLK_DIV2: SYSCLK clock divided by 2 selected as SDADCx clock
3168 * @arg RCC_SDADCSYSCLK_DIV4: SYSCLK clock divided by 4 selected as SDADCx clock
3169 * @arg RCC_SDADCSYSCLK_DIV6: SYSCLK clock divided by 6 selected as SDADCx clock
3170 * @arg RCC_SDADCSYSCLK_DIV8: SYSCLK clock divided by 8 selected as SDADCx clock
3171 * @arg RCC_SDADCSYSCLK_DIV10: SYSCLK clock divided by 10 selected as SDADCx clock
3172 * @arg RCC_SDADCSYSCLK_DIV12: SYSCLK clock divided by 12 selected as SDADCx clock
3173 * @arg RCC_SDADCSYSCLK_DIV14: SYSCLK clock divided by 14 selected as SDADCx clock
3174 * @arg RCC_SDADCSYSCLK_DIV16: SYSCLK clock divided by 16 selected as SDADCx clock
3175 * @arg RCC_SDADCSYSCLK_DIV20: SYSCLK clock divided by 20 selected as SDADCx clock
3176 * @arg RCC_SDADCSYSCLK_DIV24: SYSCLK clock divided by 24 selected as SDADCx clock
3177 * @arg RCC_SDADCSYSCLK_DIV28: SYSCLK clock divided by 28 selected as SDADCx clock
3178 * @arg RCC_SDADCSYSCLK_DIV32: SYSCLK clock divided by 32 selected as SDADCx clock
3179 * @arg RCC_SDADCSYSCLK_DIV36: SYSCLK clock divided by 36 selected as SDADCx clock
3180 * @arg RCC_SDADCSYSCLK_DIV40: SYSCLK clock divided by 40 selected as SDADCx clock
3181 * @arg RCC_SDADCSYSCLK_DIV44: SYSCLK clock divided by 44 selected as SDADCx clock
3182 * @arg RCC_SDADCSYSCLK_DIV48: SYSCLK clock divided by 48 selected as SDADCx clock
3183 */
3184 #define __HAL_RCC_SDADC_CONFIG(__SDADCPrescaler__) \
3185 MODIFY_REG(RCC->CFGR, RCC_CFGR_SDADCPRE, (uint32_t)(__SDADCPrescaler__))
3186
3187 /** @brief Macro to get the SDADCx clock prescaler.
3188 * @retval The clock source can be one of the following values:
3189 * @arg RCC_SDADCSYSCLK_DIV1: SYSCLK clock selected as SDADCx clock
3190 * @arg RCC_SDADCSYSCLK_DIV2: SYSCLK clock divided by 2 selected as SDADCx clock
3191 * @arg RCC_SDADCSYSCLK_DIV4: SYSCLK clock divided by 4 selected as SDADCx clock
3192 * @arg RCC_SDADCSYSCLK_DIV6: SYSCLK clock divided by 6 selected as SDADCx clock
3193 * @arg RCC_SDADCSYSCLK_DIV8: SYSCLK clock divided by 8 selected as SDADCx clock
3194 * @arg RCC_SDADCSYSCLK_DIV10: SYSCLK clock divided by 10 selected as SDADCx clock
3195 * @arg RCC_SDADCSYSCLK_DIV12: SYSCLK clock divided by 12 selected as SDADCx clock
3196 * @arg RCC_SDADCSYSCLK_DIV14: SYSCLK clock divided by 14 selected as SDADCx clock
3197 * @arg RCC_SDADCSYSCLK_DIV16: SYSCLK clock divided by 16 selected as SDADCx clock
3198 * @arg RCC_SDADCSYSCLK_DIV20: SYSCLK clock divided by 20 selected as SDADCx clock
3199 * @arg RCC_SDADCSYSCLK_DIV24: SYSCLK clock divided by 24 selected as SDADCx clock
3200 * @arg RCC_SDADCSYSCLK_DIV28: SYSCLK clock divided by 28 selected as SDADCx clock
3201 * @arg RCC_SDADCSYSCLK_DIV32: SYSCLK clock divided by 32 selected as SDADCx clock
3202 * @arg RCC_SDADCSYSCLK_DIV36: SYSCLK clock divided by 36 selected as SDADCx clock
3203 * @arg RCC_SDADCSYSCLK_DIV40: SYSCLK clock divided by 40 selected as SDADCx clock
3204 * @arg RCC_SDADCSYSCLK_DIV44: SYSCLK clock divided by 44 selected as SDADCx clock
3205 * @arg RCC_SDADCSYSCLK_DIV48: SYSCLK clock divided by 48 selected as SDADCx clock
3206 */
3207 #define __HAL_RCC_GET_SDADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SDADCPRE)))
3208 /**
3209 * @}
3210 */
3211
3212 /** @defgroup RCCEx_CECx_Clock_Config RCC Extended CECx Clock Config
3213 * @{
3214 */
3215 /** @brief Macro to configure the CEC clock.
3216 * @param __CECCLKSource__: specifies the CEC clock source.
3217 * This parameter can be one of the following values:
3218 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
3219 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
3220 */
3221 #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
3222 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
3223
3224 /** @brief Macro to get the HDMI CEC clock source.
3225 * @retval The clock source can be one of the following values:
3226 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
3227 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
3228 */
3229 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
3230 /**
3231 * @}
3232 */
3233
3234 #endif /* STM32F373xC || STM32F378xx */
3235
3236 #if defined(STM32F302xE) || defined(STM32F303xE) || \
3237 defined(STM32F302xC) || defined(STM32F303xC) || \
3238 defined(STM32F302x8) || \
3239 defined(STM32F373xC)
3240
3241 /** @defgroup RCCEx_USBx_Clock_Config RCC Extended USBx Clock Config
3242 * @{
3243 */
3244 /** @brief Macro to configure the USB clock (USBCLK).
3245 * @param __USBCLKSource__: specifies the USB clock source.
3246 * This parameter can be one of the following values:
3247 * @arg RCC_USBPLLCLK_DIV1: PLL Clock divided by 1 selected as USB clock
3248 * @arg RCC_USBPLLCLK_DIV1_5: PLL Clock divided by 1.5 selected as USB clock
3249 */
3250 #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
3251 MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSource__))
3252
3253 /** @brief Macro to get the USB clock source.
3254 * @retval The clock source can be one of the following values:
3255 * @arg RCC_USBPLLCLK_DIV1: PLL Clock divided by 1 selected as USB clock
3256 * @arg RCC_USBPLLCLK_DIV1_5: PLL Clock divided by 1.5 selected as USB clock
3257 */
3258 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
3259 /**
3260 * @}
3261 */
3262
3263 #endif /* STM32F302xE || STM32F303xE || */
3264 /* STM32F302xC || STM32F303xC || */
3265 /* STM32F302x8 || */
3266 /* STM32F373xC */
3267
3268 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
3269 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
3270 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
3271
3272 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
3273 * @{
3274 */
3275 /** @brief macro to configure the MCO clock.
3276 * @param __MCOCLKSource__: specifies the MCO clock source.
3277 * This parameter can be one of the following values:
3278 * @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
3279 * @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
3280 * @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
3281 * @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
3282 * @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
3283 * @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
3284 * @param __MCODiv__: specifies the MCO clock prescaler.
3285 * This parameter can be one of the following values:
3286 * @arg RCC_MCO_NODIV: No division applied on MCO clock source
3287 */
3288 #define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
3289 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSource__) | (__MCODiv__)))
3290 /**
3291 * @}
3292 */
3293 #else
3294 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
3295 * @{
3296 */
3297
3298 #define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
3299 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSource__))
3300 /**
3301 * @}
3302 */
3303
3304 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
3305 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
3306 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
3307
3308 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
3309
3310 /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
3311 * @{
3312 */
3313 /** @brief Macro to configure the I2C3 clock (I2C3CLK).
3314 * @param __I2C3CLKSource__: specifies the I2C3 clock source.
3315 * This parameter can be one of the following values:
3316 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
3317 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
3318 */
3319 #define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
3320 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__))
3321
3322 /** @brief Macro to get the I2C3 clock source.
3323 * @retval The clock source can be one of the following values:
3324 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
3325 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
3326 */
3327 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW)))
3328 /**
3329 * @}
3330 */
3331
3332 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
3333 * @{
3334 */
3335 /** @brief Macro to configure the TIM2 clock (TIM2CLK).
3336 * @param __TIM2CLKSource__: specifies the TIM2 clock source.
3337 * This parameter can be one of the following values:
3338 * @arg RCC_TIM2CLK_HCLK: HCLK selected as TIM2 clock
3339 * @arg RCC_TIM2CLK_PLL: PLL Clock selected as TIM2 clock
3340 */
3341 #define __HAL_RCC_TIM2_CONFIG(__TIM2CLKSource__) \
3342 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM2SW, (uint32_t)(__TIM2CLKSource__))
3343
3344 /** @brief Macro to get the TIM2 clock (TIM2CLK).
3345 * @retval The clock source can be one of the following values:
3346 * This parameter can be one of the following values:
3347 * @arg RCC_TIM2CLK_HCLK: HCLK selected as TIM2 clock
3348 * @arg RCC_TIM2CLK_PLL: PLL Clock selected as TIM2 clock
3349 */
3350 #define __HAL_RCC_GET_TIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM2SW)))
3351
3352 /** @brief Macro to configure the TIM3 & TIM4 clock (TIM34CLK).
3353 * @param __TIM3CLKSource__: specifies the TIM3 & TIM4 clock source.
3354 * This parameter can be one of the following values:
3355 * @arg RCC_TIM34CLK_HCLK: HCLK selected as TIM3 & TIM4 clock
3356 * @arg RCC_TIM34CLK_PLL: PLL Clock selected as TIM3 & TIM4 clock
3357 */
3358 #define __HAL_RCC_TIM34_CONFIG(__TIM34CLKSource__) \
3359 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM34SW, (uint32_t)(__TIM34CLKSource__))
3360
3361 /** @brief Macro to get the TIM3 & TIM4 clock (TIM34CLK).
3362 * @retval The clock source can be one of the following values:
3363 * This parameter can be one of the following values:
3364 * @arg RCC_TIM34CLK_HCLK: HCLK selected as TIM3 & TIM4 clock
3365 * @arg RCC_TIM34CLK_PLL: PLL Clock selected as TIM3 & TIM4 clock
3366 */
3367 #define __HAL_RCC_GET_TIM34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM34SW)))
3368
3369 /** @brief Macro to configure the TIM15 clock (TIM15CLK).
3370 * @param __TIM15CLKSource__: specifies the TIM15 clock source.
3371 * This parameter can be one of the following values:
3372 * @arg RCC_TIM15CLK_HCLK: HCLK selected as TIM15 clock
3373 * @arg RCC_TIM15CLK_PLL: PLL Clock selected as TIM15 clock
3374 */
3375 #define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \
3376 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__))
3377
3378 /** @brief Macro to get the TIM15 clock (TIM15CLK).
3379 * @retval The clock source can be one of the following values:
3380 * This parameter can be one of the following values:
3381 * @arg RCC_TIM15CLK_HCLK: HCLK selected as TIM15 clock
3382 * @arg RCC_TIM15CLK_PLL: PLL Clock selected as TIM15 clock
3383 */
3384 #define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW)))
3385
3386 /** @brief Macro to configure the TIM16 clock (TIM16CLK).
3387 * @param __TIM16CLKSource__: specifies the TIM16 clock source.
3388 * This parameter can be one of the following values:
3389 * @arg RCC_TIM16CLK_HCLK: HCLK selected as TIM16 clock
3390 * @arg RCC_TIM16CLK_PLL: PLL Clock selected as TIM16 clock
3391 */
3392 #define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \
3393 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__))
3394
3395 /** @brief Macro to get the TIM16 clock (TIM16CLK).
3396 * @retval The clock source can be one of the following values:
3397 * This parameter can be one of the following values:
3398 * @arg RCC_TIM16CLK_HCLK: HCLK selected as TIM16 clock
3399 * @arg RCC_TIM16CLK_PLL: PLL Clock selected as TIM16 clock
3400 */
3401 #define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW)))
3402
3403 /** @brief Macro to configure the TIM17 clock (TIM17CLK).
3404 * @param __TIM17CLKSource__: specifies the TIM17 clock source.
3405 * This parameter can be one of the following values:
3406 * @arg RCC_TIM17CLK_HCLK: HCLK selected as TIM17 clock
3407 * @arg RCC_TIM17CLK_PLL: PLL Clock selected as TIM17 clock
3408 */
3409 #define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \
3410 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__))
3411
3412 /** @brief Macro to get the TIM17 clock (TIM17CLK).
3413 * @retval The clock source can be one of the following values:
3414 * This parameter can be one of the following values:
3415 * @arg RCC_TIM17CLK_HCLK: HCLK selected as TIM17 clock
3416 * @arg RCC_TIM17CLK_PLL: PLL Clock selected as TIM17 clock
3417 */
3418 #define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
3419
3420 /**
3421 * @}
3422 */
3423
3424 #endif /* STM32f302xE || STM32f303xE || STM32F398xx */
3425
3426 #if defined(STM32F303xE) || defined(STM32F398xx)
3427 /** @addtogroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
3428 * @{
3429 */
3430 /** @brief Macro to configure the TIM20 clock (TIM20CLK).
3431 * @param __TIM20CLKSource__: specifies the TIM20 clock source.
3432 * This parameter can be one of the following values:
3433 * @arg RCC_TIM20CLK_HCLK: HCLK selected as TIM20 clock
3434 * @arg RCC_TIM20CLK_PLL: PLL Clock selected as TIM20 clock
3435 */
3436 #define __HAL_RCC_TIM20_CONFIG(__TIM20CLKSource__) \
3437 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM20SW, (uint32_t)(__TIM20CLKSource__))
3438
3439 /** @brief Macro to get the TIM20 clock (TIM20CLK).
3440 * @retval The clock source can be one of the following values:
3441 * This parameter can be one of the following values:
3442 * @arg RCC_TIM20CLK_HCLK: HCLK selected as TIM20 clock
3443 * @arg RCC_TIM20CLK_PLL: PLL Clock selected as TIM20 clock
3444 */
3445 #define __HAL_RCC_GET_TIM20_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM20SW)))
3446
3447 /**
3448 * @}
3449 */
3450 #endif /* STM32f303xE || STM32F398xx */
3451
3452
3453 /**
3454 * @}
3455 */
3456
3457 /* Exported functions --------------------------------------------------------*/
3458 /** @addtogroup RCCEx_Exported_Functions RCC Extended Exported Functions
3459 * @{
3460 */
3461
3462 /** @addtogroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
3463 * @{
3464 */
3465 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
3466 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
3467 /**
3468 * @}
3469 */
3470
3471 /**
3472 * @}
3473 */
3474
3475 /**
3476 * @}
3477 */
3478
3479 /**
3480 * @}
3481 */
3482 #ifdef __cplusplus
3483 }
3484 #endif
3485
3486 #endif /* __STM32F3xx_HAL_RCC_EX_H */
3487
3488 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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