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1 /**
2 ******************************************************************************
3 * @file stm32f3xx_hal_tim.c
4 * @author MCD Application Team
5 * @version V1.1.0
6 * @date 12-Sept-2014
7 * @brief TIM HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the Timer (TIM) peripheral:
10 * + Time Base Initialization
11 * + Time Base Start
12 * + Time Base Start Interruption
13 * + Time Base Start DMA
14 * + Time Output Compare/PWM Initialization
15 * + Time Output Compare/PWM Channel Configuration
16 * + Time Output Compare/PWM Start
17 * + Time Output Compare/PWM Start Interruption
18 * + Time Output Compare/PWM Start DMA
19 * + Time Input Capture Initialization
20 * + Time Input Capture Channel Configuration
21 * + Time Input Capture Start
22 * + Time Input Capture Start Interruption
23 * + Time Input Capture Start DMA
24 * + Time One Pulse Initialization
25 * + Time One Pulse Channel Configuration
26 * + Time One Pulse Start
27 * + Time Encoder Interface Initialization
28 * + Time Encoder Interface Start
29 * + Time Encoder Interface Start Interruption
30 * + Time Encoder Interface Start DMA
31 * + Commutation Event configuration with Interruption and DMA
32 * + Time OCRef clear configuration
33 * + Time External Clock configuration
34 @verbatim
35 ==============================================================================
36 ##### TIMER Generic features #####
37 ==============================================================================
38 [..] The Timer features include:
39 (#) 16-bit up, down, up/down auto-reload counter.
40 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
41 counter clock frequency either by any factor between 1 and 65536.
42 (#) Up to 4 independent channels for:
43 (++) Input Capture
44 (++) Output Compare
45 (++) PWM generation (Edge and Center-aligned Mode)
46 (++) One-pulse mode output
47
48 ##### How to use this driver #####
49 ==============================================================================
50 [..]
51 (#) Initialize the TIM low level resources by implementing the following functions
52 depending from feature used :
53 (++) Time Base : HAL_TIM_Base_MspInit()
54 (++) Input Capture : HAL_TIM_IC_MspInit()
55 (++) Output Compare : HAL_TIM_OC_MspInit()
56 (++) PWM generation : HAL_TIM_PWM_MspInit()
57 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
58 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
59
60 (#) Initialize the TIM low level resources :
61 (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
62 (##) TIM pins configuration
63 (+++) Enable the clock for the TIM GPIOs using the following function:
64 __GPIOx_CLK_ENABLE();
65 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
66
67 (#) The external Clock can be configured, if needed (the default clock is the
68 internal clock from the APBx), using the following function:
69 HAL_TIM_ConfigClockSource, the clock configuration should be done before
70 any start function.
71
72 (#) Configure the TIM in the desired functioning mode using one of the
73 Initialization function of this driver:
74 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
75 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
76 Output Compare signal.
77 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
78 PWM signal.
79 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
80 external signal.
81 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
82 in One Pulse Mode.
83 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
84
85 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
86 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
87 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
88 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
89 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
90 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
91 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
92
93 (#) The DMA Burst is managed with the two following functions:
94 HAL_TIM_DMABurst_WriteStart()
95 HAL_TIM_DMABurst_ReadStart()
96
97 @endverbatim
98 ******************************************************************************
99 * @attention
100 *
101 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
102 *
103 * Redistribution and use in source and binary forms, with or without modification,
104 * are permitted provided that the following conditions are met:
105 * 1. Redistributions of source code must retain the above copyright notice,
106 * this list of conditions and the following disclaimer.
107 * 2. Redistributions in binary form must reproduce the above copyright notice,
108 * this list of conditions and the following disclaimer in the documentation
109 * and/or other materials provided with the distribution.
110 * 3. Neither the name of STMicroelectronics nor the names of its contributors
111 * may be used to endorse or promote products derived from this software
112 * without specific prior written permission.
113 *
114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
124 *
125 ******************************************************************************
126 */
127
128 /* Includes ------------------------------------------------------------------*/
129 #include "stm32f3xx_hal.h"
130
131 /** @addtogroup STM32F3xx_HAL_Driver
132 * @{
133 */
134
135 /** @defgroup TIM TIM HAL module driver
136 * @brief TIM HAL module driver
137 * @{
138 */
139
140 #ifdef HAL_TIM_MODULE_ENABLED
141
142 /* Private typedef -----------------------------------------------------------*/
143 /* Private define ------------------------------------------------------------*/
144 /* Private macro -------------------------------------------------------------*/
145 /* Private variables ---------------------------------------------------------*/
146 /* Private function prototypes -----------------------------------------------*/
147 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
148 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
149 uint32_t TIM_ICFilter);
150 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
151 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
152 uint32_t TIM_ICFilter);
153 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
154 uint32_t TIM_ICFilter);
155 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
156 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
157 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
158 /* Private functions ---------------------------------------------------------*/
159
160 /** @defgroup TIM_Exported_Functions TIM Exported Functions
161 * @{
162 */
163
164 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions
165 * @brief Time Base functions
166 *
167 @verbatim
168 ==============================================================================
169 ##### Time Base functions #####
170 ==============================================================================
171 [..]
172 This section provides functions allowing to:
173 (+) Initialize and configure the TIM base.
174 (+) De-initialize the TIM base.
175 (+) Start the Time Base.
176 (+) Stop the Time Base.
177 (+) Start the Time Base and enable interrupt.
178 (+) Stop the Time Base and disable interrupt.
179 (+) Start the Time Base and enable DMA transfer.
180 (+) Stop the Time Base and disable DMA transfer.
181
182 @endverbatim
183 * @{
184 */
185 /**
186 * @brief Initializes the TIM Time base Unit according to the specified
187 * parameters in the TIM_HandleTypeDef and create the associated handle.
188 * @param htim: TIM Base handle
189 * @retval HAL status
190 */
191 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
192 {
193 /* Check the TIM handle allocation */
194 if(htim == HAL_NULL)
195 {
196 return HAL_ERROR;
197 }
198
199 /* Check the parameters */
200 assert_param(IS_TIM_INSTANCE(htim->Instance));
201 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
202 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
203
204 if(htim->State == HAL_TIM_STATE_RESET)
205 {
206 /* Init the low level hardware : GPIO, CLOCK, NVIC */
207 HAL_TIM_Base_MspInit(htim);
208 }
209
210 /* Set the TIM state */
211 htim->State= HAL_TIM_STATE_BUSY;
212
213 /* Set the Time Base configuration */
214 TIM_Base_SetConfig(htim->Instance, &htim->Init);
215
216 /* Initialize the TIM state*/
217 htim->State= HAL_TIM_STATE_READY;
218
219 return HAL_OK;
220 }
221
222 /**
223 * @brief DeInitializes the TIM Base peripheral
224 * @param htim: TIM Base handle
225 * @retval HAL status
226 */
227 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
228 {
229 /* Check the parameters */
230 assert_param(IS_TIM_INSTANCE(htim->Instance));
231
232 htim->State = HAL_TIM_STATE_BUSY;
233
234 /* Disable the TIM Peripheral Clock */
235 __HAL_TIM_DISABLE(htim);
236
237 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
238 HAL_TIM_Base_MspDeInit(htim);
239
240 /* Change TIM state */
241 htim->State = HAL_TIM_STATE_RESET;
242
243 /* Release Lock */
244 __HAL_UNLOCK(htim);
245
246 return HAL_OK;
247 }
248
249 /**
250 * @brief Initializes the TIM Base MSP.
251 * @param htim: TIM handle
252 * @retval None
253 */
254 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
255 {
256 /* NOTE : This function Should not be modified, when the callback is needed,
257 the HAL_TIM_Base_MspInit could be implemented in the user file
258 */
259 }
260
261 /**
262 * @brief DeInitializes TIM Base MSP.
263 * @param htim: TIM handle
264 * @retval None
265 */
266 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
267 {
268 /* NOTE : This function Should not be modified, when the callback is needed,
269 the HAL_TIM_Base_MspDeInit could be implemented in the user file
270 */
271 }
272
273
274 /**
275 * @brief Starts the TIM Base generation.
276 * @param htim : TIM handle
277 * @retval HAL status
278 */
279 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
280 {
281 /* Check the parameters */
282 assert_param(IS_TIM_INSTANCE(htim->Instance));
283
284 /* Set the TIM state */
285 htim->State= HAL_TIM_STATE_BUSY;
286
287 /* Enable the Peripheral */
288 __HAL_TIM_ENABLE(htim);
289
290 /* Change the TIM state*/
291 htim->State= HAL_TIM_STATE_READY;
292
293 /* Return function status */
294 return HAL_OK;
295 }
296
297 /**
298 * @brief Stops the TIM Base generation.
299 * @param htim : TIM handle
300 * @retval HAL status
301 */
302 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
303 {
304 /* Check the parameters */
305 assert_param(IS_TIM_INSTANCE(htim->Instance));
306
307 /* Set the TIM state */
308 htim->State= HAL_TIM_STATE_BUSY;
309
310 /* Disable the Peripheral */
311 __HAL_TIM_DISABLE(htim);
312
313 /* Change the TIM state*/
314 htim->State= HAL_TIM_STATE_READY;
315
316 /* Return function status */
317 return HAL_OK;
318 }
319
320 /**
321 * @brief Starts the TIM Base generation in interrupt mode.
322 * @param htim : TIM handle
323 * @retval HAL status
324 */
325 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
326 {
327 /* Check the parameters */
328 assert_param(IS_TIM_INSTANCE(htim->Instance));
329
330 /* Enable the TIM Update interrupt */
331 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
332
333 /* Enable the Peripheral */
334 __HAL_TIM_ENABLE(htim);
335
336 /* Return function status */
337 return HAL_OK;
338 }
339
340 /**
341 * @brief Stops the TIM Base generation in interrupt mode.
342 * @param htim : TIM handle
343 * @retval HAL status
344 */
345 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
346 {
347 /* Check the parameters */
348 assert_param(IS_TIM_INSTANCE(htim->Instance));
349 /* Disable the TIM Update interrupt */
350 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
351
352 /* Disable the Peripheral */
353 __HAL_TIM_DISABLE(htim);
354
355 /* Return function status */
356 return HAL_OK;
357 }
358
359 /**
360 * @brief Starts the TIM Base generation in DMA mode.
361 * @param htim : TIM handle
362 * @param pData: The source Buffer address.
363 * @param Length: The length of data to be transferred from memory to peripheral.
364 * @retval HAL status
365 */
366 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
367 {
368 /* Check the parameters */
369 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
370
371 if((htim->State == HAL_TIM_STATE_BUSY))
372 {
373 return HAL_BUSY;
374 }
375 else if((htim->State == HAL_TIM_STATE_READY))
376 {
377 if((pData == 0 ) && (Length > 0))
378 {
379 return HAL_ERROR;
380 }
381 else
382 {
383 htim->State = HAL_TIM_STATE_BUSY;
384 }
385 }
386 /* Set the DMA Period elapsed callback */
387 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
388
389 /* Set the DMA error callback */
390 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
391
392 /* Enable the DMA channel */
393 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
394
395 /* Enable the TIM Update DMA request */
396 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
397
398 /* Enable the Peripheral */
399 __HAL_TIM_ENABLE(htim);
400
401 /* Return function status */
402 return HAL_OK;
403 }
404
405 /**
406 * @brief Stops the TIM Base generation in DMA mode.
407 * @param htim : TIM handle
408 * @retval HAL status
409 */
410 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
411 {
412 /* Check the parameters */
413 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
414
415 /* Disable the TIM Update DMA request */
416 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
417
418 /* Disable the Peripheral */
419 __HAL_TIM_DISABLE(htim);
420
421 /* Change the htim state */
422 htim->State = HAL_TIM_STATE_READY;
423
424 /* Return function status */
425 return HAL_OK;
426 }
427
428 /**
429 * @}
430 */
431
432 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
433 * @brief Time Output Compare functions
434 *
435 @verbatim
436 ==============================================================================
437 ##### Time Output Compare functions #####
438 ==============================================================================
439 [..]
440 This section provides functions allowing to:
441 (+) Initialize and configure the TIM Output Compare.
442 (+) De-initialize the TIM Output Compare.
443 (+) Start the Time Output Compare.
444 (+) Stop the Time Output Compare.
445 (+) Start the Time Output Compare and enable interrupt.
446 (+) Stop the Time Output Compare and disable interrupt.
447 (+) Start the Time Output Compare and enable DMA transfer.
448 (+) Stop the Time Output Compare and disable DMA transfer.
449
450 @endverbatim
451 * @{
452 */
453 /**
454 * @brief Initializes the TIM Output Compare according to the specified
455 * parameters in the TIM_HandleTypeDef and create the associated handle.
456 * @param htim: TIM Output Compare handle
457 * @retval HAL status
458 */
459 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
460 {
461 /* Check the TIM handle allocation */
462 if(htim == HAL_NULL)
463 {
464 return HAL_ERROR;
465 }
466
467 /* Check the parameters */
468 assert_param(IS_TIM_INSTANCE(htim->Instance));
469 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
470 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
471
472 if(htim->State == HAL_TIM_STATE_RESET)
473 {
474 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
475 HAL_TIM_OC_MspInit(htim);
476 }
477
478 /* Set the TIM state */
479 htim->State= HAL_TIM_STATE_BUSY;
480
481 /* Init the base time for the Output Compare */
482 TIM_Base_SetConfig(htim->Instance, &htim->Init);
483
484 /* Initialize the TIM state*/
485 htim->State= HAL_TIM_STATE_READY;
486
487 return HAL_OK;
488 }
489
490 /**
491 * @brief DeInitializes the TIM peripheral
492 * @param htim: TIM Output Compare handle
493 * @retval HAL status
494 */
495 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
496 {
497 /* Check the parameters */
498 assert_param(IS_TIM_INSTANCE(htim->Instance));
499
500 htim->State = HAL_TIM_STATE_BUSY;
501
502 /* Disable the TIM Peripheral Clock */
503 __HAL_TIM_DISABLE(htim);
504
505 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
506 HAL_TIM_OC_MspDeInit(htim);
507
508 /* Change TIM state */
509 htim->State = HAL_TIM_STATE_RESET;
510
511 /* Release Lock */
512 __HAL_UNLOCK(htim);
513
514 return HAL_OK;
515 }
516
517 /**
518 * @brief Initializes the TIM Output Compare MSP.
519 * @param htim: TIM handle
520 * @retval None
521 */
522 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
523 {
524 /* NOTE : This function Should not be modified, when the callback is needed,
525 the HAL_TIM_OC_MspInit could be implemented in the user file
526 */
527 }
528
529 /**
530 * @brief DeInitializes TIM Output Compare MSP.
531 * @param htim: TIM handle
532 * @retval None
533 */
534 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
535 {
536 /* NOTE : This function Should not be modified, when the callback is needed,
537 the HAL_TIM_OC_MspDeInit could be implemented in the user file
538 */
539 }
540
541 /**
542 * @brief Starts the TIM Output Compare signal generation.
543 * @param htim : TIM Output Compare handle
544 * @param Channel : TIM Channel to be enabled
545 * This parameter can be one of the following values:
546 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
547 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
548 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
549 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
550 * @retval HAL status
551 */
552 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
553 {
554 /* Check the parameters */
555 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
556
557 /* Enable the Output compare channel */
558 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
559
560 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
561 {
562 /* Enable the main output */
563 __HAL_TIM_MOE_ENABLE(htim);
564 }
565
566 /* Enable the Peripheral */
567 __HAL_TIM_ENABLE(htim);
568
569 /* Return function status */
570 return HAL_OK;
571 }
572
573 /**
574 * @brief Stops the TIM Output Compare signal generation.
575 * @param htim : TIM handle
576 * @param Channel : TIM Channel to be disabled
577 * This parameter can be one of the following values:
578 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
579 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
580 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
581 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
582 * @retval HAL status
583 */
584 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
585 {
586 /* Check the parameters */
587 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
588
589 /* Disable the Output compare channel */
590 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
591
592 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
593 {
594 /* Disable the Main Ouput */
595 __HAL_TIM_MOE_DISABLE(htim);
596 }
597
598 /* Disable the Peripheral */
599 __HAL_TIM_DISABLE(htim);
600
601 /* Return function status */
602 return HAL_OK;
603 }
604
605 /**
606 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
607 * @param htim : TIM OC handle
608 * @param Channel : TIM Channel to be enabled
609 * This parameter can be one of the following values:
610 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
611 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
612 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
613 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
614 * @retval HAL status
615 */
616 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
617 {
618 /* Check the parameters */
619 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
620
621 switch (Channel)
622 {
623 case TIM_CHANNEL_1:
624 {
625 /* Enable the TIM Capture/Compare 1 interrupt */
626 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
627 }
628 break;
629
630 case TIM_CHANNEL_2:
631 {
632 /* Enable the TIM Capture/Compare 2 interrupt */
633 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
634 }
635 break;
636
637 case TIM_CHANNEL_3:
638 {
639 /* Enable the TIM Capture/Compare 3 interrupt */
640 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
641 }
642 break;
643
644 case TIM_CHANNEL_4:
645 {
646 /* Enable the TIM Capture/Compare 4 interrupt */
647 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
648 }
649 break;
650
651 default:
652 break;
653 }
654
655 /* Enable the Output compare channel */
656 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
657
658 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
659 {
660 /* Enable the main output */
661 __HAL_TIM_MOE_ENABLE(htim);
662 }
663
664 /* Enable the Peripheral */
665 __HAL_TIM_ENABLE(htim);
666
667 /* Return function status */
668 return HAL_OK;
669 }
670
671 /**
672 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
673 * @param htim : TIM Output Compare handle
674 * @param Channel : TIM Channel to be disabled
675 * This parameter can be one of the following values:
676 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
677 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
678 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
679 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
680 * @retval HAL status
681 */
682 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
683 {
684 /* Check the parameters */
685 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
686
687 switch (Channel)
688 {
689 case TIM_CHANNEL_1:
690 {
691 /* Disable the TIM Capture/Compare 1 interrupt */
692 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
693 }
694 break;
695
696 case TIM_CHANNEL_2:
697 {
698 /* Disable the TIM Capture/Compare 2 interrupt */
699 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
700 }
701 break;
702
703 case TIM_CHANNEL_3:
704 {
705 /* Disable the TIM Capture/Compare 3 interrupt */
706 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
707 }
708 break;
709
710 case TIM_CHANNEL_4:
711 {
712 /* Disable the TIM Capture/Compare 4 interrupt */
713 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
714 }
715 break;
716
717 default:
718 break;
719 }
720
721 /* Disable the Output compare channel */
722 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
723
724 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
725 {
726 /* Disable the Main Ouput */
727 __HAL_TIM_MOE_DISABLE(htim);
728 }
729
730 /* Disable the Peripheral */
731 __HAL_TIM_DISABLE(htim);
732
733 /* Return function status */
734 return HAL_OK;
735 }
736
737 /**
738 * @brief Starts the TIM Output Compare signal generation in DMA mode.
739 * @param htim : TIM Output Compare handle
740 * @param Channel : TIM Channel to be enabled
741 * This parameter can be one of the following values:
742 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
743 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
744 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
745 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
746 * @param pData: The source Buffer address.
747 * @param Length: The length of data to be transferred from memory to TIM peripheral
748 * @retval HAL status
749 */
750 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
751 {
752 /* Check the parameters */
753 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
754
755 if((htim->State == HAL_TIM_STATE_BUSY))
756 {
757 return HAL_BUSY;
758 }
759 else if((htim->State == HAL_TIM_STATE_READY))
760 {
761 if(((uint32_t)pData == 0 ) && (Length > 0))
762 {
763 return HAL_ERROR;
764 }
765 else
766 {
767 htim->State = HAL_TIM_STATE_BUSY;
768 }
769 }
770 switch (Channel)
771 {
772 case TIM_CHANNEL_1:
773 {
774 /* Set the DMA Period elapsed callback */
775 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
776
777 /* Set the DMA error callback */
778 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
779
780 /* Enable the DMA channel */
781 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
782
783 /* Enable the TIM Capture/Compare 1 DMA request */
784 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
785 }
786 break;
787
788 case TIM_CHANNEL_2:
789 {
790 /* Set the DMA Period elapsed callback */
791 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
792
793 /* Set the DMA error callback */
794 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
795
796 /* Enable the DMA channel */
797 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
798
799 /* Enable the TIM Capture/Compare 2 DMA request */
800 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
801 }
802 break;
803
804 case TIM_CHANNEL_3:
805 {
806 /* Set the DMA Period elapsed callback */
807 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
808
809 /* Set the DMA error callback */
810 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
811
812 /* Enable the DMA channel */
813 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
814
815 /* Enable the TIM Capture/Compare 3 DMA request */
816 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
817 }
818 break;
819
820 case TIM_CHANNEL_4:
821 {
822 /* Set the DMA Period elapsed callback */
823 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
824
825 /* Set the DMA error callback */
826 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
827
828 /* Enable the DMA channel */
829 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
830
831 /* Enable the TIM Capture/Compare 4 DMA request */
832 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
833 }
834 break;
835
836 default:
837 break;
838 }
839
840 /* Enable the Output compare channel */
841 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
842
843 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
844 {
845 /* Enable the main output */
846 __HAL_TIM_MOE_ENABLE(htim);
847 }
848
849 /* Enable the Peripheral */
850 __HAL_TIM_ENABLE(htim);
851
852 /* Return function status */
853 return HAL_OK;
854 }
855
856 /**
857 * @brief Stops the TIM Output Compare signal generation in DMA mode.
858 * @param htim : TIM Output Compare handle
859 * @param Channel : TIM Channel to be disabled
860 * This parameter can be one of the following values:
861 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
862 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
863 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
864 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
865 * @retval HAL status
866 */
867 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
868 {
869 /* Check the parameters */
870 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
871
872 switch (Channel)
873 {
874 case TIM_CHANNEL_1:
875 {
876 /* Disable the TIM Capture/Compare 1 DMA request */
877 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
878 }
879 break;
880
881 case TIM_CHANNEL_2:
882 {
883 /* Disable the TIM Capture/Compare 2 DMA request */
884 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
885 }
886 break;
887
888 case TIM_CHANNEL_3:
889 {
890 /* Disable the TIM Capture/Compare 3 DMA request */
891 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
892 }
893 break;
894
895 case TIM_CHANNEL_4:
896 {
897 /* Disable the TIM Capture/Compare 4 interrupt */
898 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
899 }
900 break;
901
902 default:
903 break;
904 }
905
906 /* Disable the Output compare channel */
907 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
908
909 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
910 {
911 /* Disable the Main Ouput */
912 __HAL_TIM_MOE_DISABLE(htim);
913 }
914
915 /* Disable the Peripheral */
916 __HAL_TIM_DISABLE(htim);
917
918 /* Change the htim state */
919 htim->State = HAL_TIM_STATE_READY;
920
921 /* Return function status */
922 return HAL_OK;
923 }
924
925 /**
926 * @}
927 */
928
929 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
930 * @brief Time PWM functions
931 *
932 @verbatim
933 ==============================================================================
934 ##### Time PWM functions #####
935 ==============================================================================
936 [..]
937 This section provides functions allowing to:
938 (+) Initialize and configure the TIM OPWM.
939 (+) De-initialize the TIM PWM.
940 (+) Start the Time PWM.
941 (+) Stop the Time PWM.
942 (+) Start the Time PWM and enable interrupt.
943 (+) Stop the Time PWM and disable interrupt.
944 (+) Start the Time PWM and enable DMA transfer.
945 (+) Stop the Time PWM and disable DMA transfer.
946
947 @endverbatim
948 * @{
949 */
950 /**
951 * @brief Initializes the TIM PWM Time Base according to the specified
952 * parameters in the TIM_HandleTypeDef and create the associated handle.
953 * @param htim: TIM handle
954 * @retval HAL status
955 */
956 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
957 {
958 /* Check the TIM handle allocation */
959 if(htim == HAL_NULL)
960 {
961 return HAL_ERROR;
962 }
963
964 /* Check the parameters */
965 assert_param(IS_TIM_INSTANCE(htim->Instance));
966 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
967 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
968
969 if(htim->State == HAL_TIM_STATE_RESET)
970 {
971 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
972 HAL_TIM_PWM_MspInit(htim);
973 }
974
975 /* Set the TIM state */
976 htim->State= HAL_TIM_STATE_BUSY;
977
978 /* Init the base time for the PWM */
979 TIM_Base_SetConfig(htim->Instance, &htim->Init);
980
981 /* Initialize the TIM state*/
982 htim->State= HAL_TIM_STATE_READY;
983
984 return HAL_OK;
985 }
986
987 /**
988 * @brief DeInitializes the TIM peripheral
989 * @param htim: TIM handle
990 * @retval HAL status
991 */
992 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
993 {
994 /* Check the parameters */
995 assert_param(IS_TIM_INSTANCE(htim->Instance));
996
997 htim->State = HAL_TIM_STATE_BUSY;
998
999 /* Disable the TIM Peripheral Clock */
1000 __HAL_TIM_DISABLE(htim);
1001
1002 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1003 HAL_TIM_PWM_MspDeInit(htim);
1004
1005 /* Change TIM state */
1006 htim->State = HAL_TIM_STATE_RESET;
1007
1008 /* Release Lock */
1009 __HAL_UNLOCK(htim);
1010
1011 return HAL_OK;
1012 }
1013
1014 /**
1015 * @brief Initializes the TIM PWM MSP.
1016 * @param htim: TIM handle
1017 * @retval None
1018 */
1019 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1020 {
1021 /* NOTE : This function Should not be modified, when the callback is needed,
1022 the HAL_TIM_PWM_MspInit could be implemented in the user file
1023 */
1024 }
1025
1026 /**
1027 * @brief DeInitializes TIM PWM MSP.
1028 * @param htim: TIM handle
1029 * @retval None
1030 */
1031 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1032 {
1033 /* NOTE : This function Should not be modified, when the callback is needed,
1034 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1035 */
1036 }
1037
1038 /**
1039 * @brief Starts the PWM signal generation.
1040 * @param htim : TIM handle
1041 * @param Channel : TIM Channels to be enabled
1042 * This parameter can be one of the following values:
1043 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1044 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1045 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1046 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1047 * @retval HAL status
1048 */
1049 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1050 {
1051 /* Check the parameters */
1052 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1053
1054 /* Enable the Capture compare channel */
1055 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1056
1057 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1058 {
1059 /* Enable the main output */
1060 __HAL_TIM_MOE_ENABLE(htim);
1061 }
1062
1063 /* Enable the Peripheral */
1064 __HAL_TIM_ENABLE(htim);
1065
1066 /* Return function status */
1067 return HAL_OK;
1068 }
1069
1070 /**
1071 * @brief Stops the PWM signal generation.
1072 * @param htim : TIM handle
1073 * @param Channel : TIM Channels to be disabled
1074 * This parameter can be one of the following values:
1075 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1076 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1077 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1078 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1079 * @retval HAL status
1080 */
1081 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1082 {
1083 /* Check the parameters */
1084 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1085
1086 /* Disable the Capture compare channel */
1087 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1088
1089 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1090 {
1091 /* Disable the Main Ouput */
1092 __HAL_TIM_MOE_DISABLE(htim);
1093 }
1094
1095 /* Disable the Peripheral */
1096 __HAL_TIM_DISABLE(htim);
1097
1098 /* Change the htim state */
1099 htim->State = HAL_TIM_STATE_READY;
1100
1101 /* Return function status */
1102 return HAL_OK;
1103 }
1104
1105 /**
1106 * @brief Starts the PWM signal generation in interrupt mode.
1107 * @param htim : TIM handle
1108 * @param Channel : TIM Channel to be disabled
1109 * This parameter can be one of the following values:
1110 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1111 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1112 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1113 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1114 * @retval HAL status
1115 */
1116 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1117 {
1118 /* Check the parameters */
1119 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1120
1121 switch (Channel)
1122 {
1123 case TIM_CHANNEL_1:
1124 {
1125 /* Enable the TIM Capture/Compare 1 interrupt */
1126 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1127 }
1128 break;
1129
1130 case TIM_CHANNEL_2:
1131 {
1132 /* Enable the TIM Capture/Compare 2 interrupt */
1133 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1134 }
1135 break;
1136
1137 case TIM_CHANNEL_3:
1138 {
1139 /* Enable the TIM Capture/Compare 3 interrupt */
1140 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1141 }
1142 break;
1143
1144 case TIM_CHANNEL_4:
1145 {
1146 /* Enable the TIM Capture/Compare 4 interrupt */
1147 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1148 }
1149 break;
1150
1151 default:
1152 break;
1153 }
1154
1155 /* Enable the Capture compare channel */
1156 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1157
1158 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1159 {
1160 /* Enable the main output */
1161 __HAL_TIM_MOE_ENABLE(htim);
1162 }
1163
1164 /* Enable the Peripheral */
1165 __HAL_TIM_ENABLE(htim);
1166
1167 /* Return function status */
1168 return HAL_OK;
1169 }
1170
1171 /**
1172 * @brief Stops the PWM signal generation in interrupt mode.
1173 * @param htim : TIM handle
1174 * @param Channel : TIM Channels to be disabled
1175 * This parameter can be one of the following values:
1176 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1177 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1178 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1179 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1180 * @retval HAL status
1181 */
1182 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
1183 {
1184 /* Check the parameters */
1185 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1186
1187 switch (Channel)
1188 {
1189 case TIM_CHANNEL_1:
1190 {
1191 /* Disable the TIM Capture/Compare 1 interrupt */
1192 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1193 }
1194 break;
1195
1196 case TIM_CHANNEL_2:
1197 {
1198 /* Disable the TIM Capture/Compare 2 interrupt */
1199 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1200 }
1201 break;
1202
1203 case TIM_CHANNEL_3:
1204 {
1205 /* Disable the TIM Capture/Compare 3 interrupt */
1206 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1207 }
1208 break;
1209
1210 case TIM_CHANNEL_4:
1211 {
1212 /* Disable the TIM Capture/Compare 4 interrupt */
1213 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1214 }
1215 break;
1216
1217 default:
1218 break;
1219 }
1220
1221 /* Disable the Capture compare channel */
1222 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1223
1224 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1225 {
1226 /* Disable the Main Ouput */
1227 __HAL_TIM_MOE_DISABLE(htim);
1228 }
1229
1230 /* Disable the Peripheral */
1231 __HAL_TIM_DISABLE(htim);
1232
1233 /* Return function status */
1234 return HAL_OK;
1235 }
1236
1237 /**
1238 * @brief Starts the TIM PWM signal generation in DMA mode.
1239 * @param htim : TIM handle
1240 * @param Channel : TIM Channels to be enabled
1241 * This parameter can be one of the following values:
1242 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1243 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1244 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1245 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1246 * @param pData: The source Buffer address.
1247 * @param Length: The length of data to be transferred from memory to TIM peripheral
1248 * @retval HAL status
1249 */
1250 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1251 {
1252 /* Check the parameters */
1253 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1254
1255 if((htim->State == HAL_TIM_STATE_BUSY))
1256 {
1257 return HAL_BUSY;
1258 }
1259 else if((htim->State == HAL_TIM_STATE_READY))
1260 {
1261 if(((uint32_t)pData == 0 ) && (Length > 0))
1262 {
1263 return HAL_ERROR;
1264 }
1265 else
1266 {
1267 htim->State = HAL_TIM_STATE_BUSY;
1268 }
1269 }
1270 switch (Channel)
1271 {
1272 case TIM_CHANNEL_1:
1273 {
1274 /* Set the DMA Period elapsed callback */
1275 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
1276
1277 /* Set the DMA error callback */
1278 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
1279
1280 /* Enable the DMA channel */
1281 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
1282
1283 /* Enable the TIM Capture/Compare 1 DMA request */
1284 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1285 }
1286 break;
1287
1288 case TIM_CHANNEL_2:
1289 {
1290 /* Set the DMA Period elapsed callback */
1291 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
1292
1293 /* Set the DMA error callback */
1294 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
1295
1296 /* Enable the DMA channel */
1297 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
1298
1299 /* Enable the TIM Capture/Compare 2 DMA request */
1300 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1301 }
1302 break;
1303
1304 case TIM_CHANNEL_3:
1305 {
1306 /* Set the DMA Period elapsed callback */
1307 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
1308
1309 /* Set the DMA error callback */
1310 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
1311
1312 /* Enable the DMA channel */
1313 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
1314
1315 /* Enable the TIM Output Capture/Compare 3 request */
1316 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1317 }
1318 break;
1319
1320 case TIM_CHANNEL_4:
1321 {
1322 /* Set the DMA Period elapsed callback */
1323 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
1324
1325 /* Set the DMA error callback */
1326 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
1327
1328 /* Enable the DMA channel */
1329 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
1330
1331 /* Enable the TIM Capture/Compare 4 DMA request */
1332 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1333 }
1334 break;
1335
1336 default:
1337 break;
1338 }
1339
1340 /* Enable the Capture compare channel */
1341 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1342
1343 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1344 {
1345 /* Enable the main output */
1346 __HAL_TIM_MOE_ENABLE(htim);
1347 }
1348
1349 /* Enable the Peripheral */
1350 __HAL_TIM_ENABLE(htim);
1351
1352 /* Return function status */
1353 return HAL_OK;
1354 }
1355
1356 /**
1357 * @brief Stops the TIM PWM signal generation in DMA mode.
1358 * @param htim : TIM handle
1359 * @param Channel : TIM Channels to be disabled
1360 * This parameter can be one of the following values:
1361 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1362 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1363 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1364 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1365 * @retval HAL status
1366 */
1367 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1368 {
1369 /* Check the parameters */
1370 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1371
1372 switch (Channel)
1373 {
1374 case TIM_CHANNEL_1:
1375 {
1376 /* Disable the TIM Capture/Compare 1 DMA request */
1377 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1378 }
1379 break;
1380
1381 case TIM_CHANNEL_2:
1382 {
1383 /* Disable the TIM Capture/Compare 2 DMA request */
1384 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1385 }
1386 break;
1387
1388 case TIM_CHANNEL_3:
1389 {
1390 /* Disable the TIM Capture/Compare 3 DMA request */
1391 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1392 }
1393 break;
1394
1395 case TIM_CHANNEL_4:
1396 {
1397 /* Disable the TIM Capture/Compare 4 interrupt */
1398 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1399 }
1400 break;
1401
1402 default:
1403 break;
1404 }
1405
1406 /* Disable the Capture compare channel */
1407 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1408
1409 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1410 {
1411 /* Disable the Main Ouput */
1412 __HAL_TIM_MOE_DISABLE(htim);
1413 }
1414
1415 /* Disable the Peripheral */
1416 __HAL_TIM_DISABLE(htim);
1417
1418 /* Change the htim state */
1419 htim->State = HAL_TIM_STATE_READY;
1420
1421 /* Return function status */
1422 return HAL_OK;
1423 }
1424
1425 /**
1426 * @}
1427 */
1428
1429 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
1430 * @brief Time Input Capture functions
1431 *
1432 @verbatim
1433 ==============================================================================
1434 ##### Time Input Capture functions #####
1435 ==============================================================================
1436 [..]
1437 This section provides functions allowing to:
1438 (+) Initialize and configure the TIM Input Capture.
1439 (+) De-initialize the TIM Input Capture.
1440 (+) Start the Time Input Capture.
1441 (+) Stop the Time Input Capture.
1442 (+) Start the Time Input Capture and enable interrupt.
1443 (+) Stop the Time Input Capture and disable interrupt.
1444 (+) Start the Time Input Capture and enable DMA transfer.
1445 (+) Stop the Time Input Capture and disable DMA transfer.
1446
1447 @endverbatim
1448 * @{
1449 */
1450 /**
1451 * @brief Initializes the TIM Input Capture Time base according to the specified
1452 * parameters in the TIM_HandleTypeDef and create the associated handle.
1453 * @param htim: TIM Input Capture handle
1454 * @retval HAL status
1455 */
1456 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
1457 {
1458 /* Check the TIM handle allocation */
1459 if(htim == HAL_NULL)
1460 {
1461 return HAL_ERROR;
1462 }
1463
1464 /* Check the parameters */
1465 assert_param(IS_TIM_INSTANCE(htim->Instance));
1466 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1467 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1468
1469 if(htim->State == HAL_TIM_STATE_RESET)
1470 {
1471 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1472 HAL_TIM_IC_MspInit(htim);
1473 }
1474
1475 /* Set the TIM state */
1476 htim->State= HAL_TIM_STATE_BUSY;
1477
1478 /* Init the base time for the input capture */
1479 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1480
1481 /* Initialize the TIM state*/
1482 htim->State= HAL_TIM_STATE_READY;
1483
1484 return HAL_OK;
1485 }
1486
1487 /**
1488 * @brief DeInitializes the TIM peripheral
1489 * @param htim: TIM Input Capture handle
1490 * @retval HAL status
1491 */
1492 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
1493 {
1494 /* Check the parameters */
1495 assert_param(IS_TIM_INSTANCE(htim->Instance));
1496
1497 htim->State = HAL_TIM_STATE_BUSY;
1498
1499 /* Disable the TIM Peripheral Clock */
1500 __HAL_TIM_DISABLE(htim);
1501
1502 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1503 HAL_TIM_IC_MspDeInit(htim);
1504
1505 /* Change TIM state */
1506 htim->State = HAL_TIM_STATE_RESET;
1507
1508 /* Release Lock */
1509 __HAL_UNLOCK(htim);
1510
1511 return HAL_OK;
1512 }
1513
1514 /**
1515 * @brief Initializes the TIM INput Capture MSP.
1516 * @param htim: TIM handle
1517 * @retval None
1518 */
1519 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
1520 {
1521 /* NOTE : This function Should not be modified, when the callback is needed,
1522 the HAL_TIM_IC_MspInit could be implemented in the user file
1523 */
1524 }
1525
1526 /**
1527 * @brief DeInitializes TIM Input Capture MSP.
1528 * @param htim: TIM handle
1529 * @retval None
1530 */
1531 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
1532 {
1533 /* NOTE : This function Should not be modified, when the callback is needed,
1534 the HAL_TIM_IC_MspDeInit could be implemented in the user file
1535 */
1536 }
1537
1538 /**
1539 * @brief Starts the TIM Input Capture measurement.
1540 * @param htim : TIM Input Capture handle
1541 * @param Channel : TIM Channels to be enabled
1542 * This parameter can be one of the following values:
1543 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1544 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1545 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1546 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1547 * @retval HAL status
1548 */
1549 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
1550 {
1551 /* Check the parameters */
1552 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1553
1554 /* Enable the Input Capture channel */
1555 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1556
1557 /* Enable the Peripheral */
1558 __HAL_TIM_ENABLE(htim);
1559
1560 /* Return function status */
1561 return HAL_OK;
1562 }
1563
1564 /**
1565 * @brief Stops the TIM Input Capture measurement.
1566 * @param htim : TIM handle
1567 * @param Channel : TIM Channels to be disabled
1568 * This parameter can be one of the following values:
1569 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1570 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1571 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1572 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1573 * @retval HAL status
1574 */
1575 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1576 {
1577 /* Check the parameters */
1578 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1579
1580 /* Disable the Input Capture channel */
1581 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1582
1583 /* Disable the Peripheral */
1584 __HAL_TIM_DISABLE(htim);
1585
1586 /* Return function status */
1587 return HAL_OK;
1588 }
1589
1590 /**
1591 * @brief Starts the TIM Input Capture measurement in interrupt mode.
1592 * @param htim : TIM Input Capture handle
1593 * @param Channel : TIM Channels to be enabled
1594 * This parameter can be one of the following values:
1595 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1596 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1597 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1598 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1599 * @retval HAL status
1600 */
1601 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
1602 {
1603 /* Check the parameters */
1604 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1605
1606 switch (Channel)
1607 {
1608 case TIM_CHANNEL_1:
1609 {
1610 /* Enable the TIM Capture/Compare 1 interrupt */
1611 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1612 }
1613 break;
1614
1615 case TIM_CHANNEL_2:
1616 {
1617 /* Enable the TIM Capture/Compare 2 interrupt */
1618 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1619 }
1620 break;
1621
1622 case TIM_CHANNEL_3:
1623 {
1624 /* Enable the TIM Capture/Compare 3 interrupt */
1625 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1626 }
1627 break;
1628
1629 case TIM_CHANNEL_4:
1630 {
1631 /* Enable the TIM Capture/Compare 4 interrupt */
1632 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1633 }
1634 break;
1635
1636 default:
1637 break;
1638 }
1639 /* Enable the Input Capture channel */
1640 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1641
1642 /* Enable the Peripheral */
1643 __HAL_TIM_ENABLE(htim);
1644
1645 /* Return function status */
1646 return HAL_OK;
1647 }
1648
1649 /**
1650 * @brief Stops the TIM Input Capture measurement in interrupt mode.
1651 * @param htim : TIM handle
1652 * @param Channel : TIM Channels to be disabled
1653 * This parameter can be one of the following values:
1654 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1655 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1656 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1657 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1658 * @retval HAL status
1659 */
1660 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1661 {
1662 /* Check the parameters */
1663 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1664
1665 switch (Channel)
1666 {
1667 case TIM_CHANNEL_1:
1668 {
1669 /* Disable the TIM Capture/Compare 1 interrupt */
1670 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1671 }
1672 break;
1673
1674 case TIM_CHANNEL_2:
1675 {
1676 /* Disable the TIM Capture/Compare 2 interrupt */
1677 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1678 }
1679 break;
1680
1681 case TIM_CHANNEL_3:
1682 {
1683 /* Disable the TIM Capture/Compare 3 interrupt */
1684 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1685 }
1686 break;
1687
1688 case TIM_CHANNEL_4:
1689 {
1690 /* Disable the TIM Capture/Compare 4 interrupt */
1691 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1692 }
1693 break;
1694
1695 default:
1696 break;
1697 }
1698
1699 /* Disable the Input Capture channel */
1700 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1701
1702 /* Disable the Peripheral */
1703 __HAL_TIM_DISABLE(htim);
1704
1705 /* Return function status */
1706 return HAL_OK;
1707 }
1708
1709 /**
1710 * @brief Starts the TIM Input Capture measurement on in DMA mode.
1711 * @param htim : TIM Input Capture handle
1712 * @param Channel : TIM Channels to be enabled
1713 * This parameter can be one of the following values:
1714 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1715 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1716 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1717 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1718 * @param pData: The destination Buffer address.
1719 * @param Length: The length of data to be transferred from TIM peripheral to memory.
1720 * @retval HAL status
1721 */
1722 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1723 {
1724 /* Check the parameters */
1725 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1726 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
1727
1728 if((htim->State == HAL_TIM_STATE_BUSY))
1729 {
1730 return HAL_BUSY;
1731 }
1732 else if((htim->State == HAL_TIM_STATE_READY))
1733 {
1734 if((pData == 0 ) && (Length > 0))
1735 {
1736 return HAL_ERROR;
1737 }
1738 else
1739 {
1740 htim->State = HAL_TIM_STATE_BUSY;
1741 }
1742 }
1743
1744 switch (Channel)
1745 {
1746 case TIM_CHANNEL_1:
1747 {
1748 /* Set the DMA Period elapsed callback */
1749 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
1750
1751 /* Set the DMA error callback */
1752 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
1753
1754 /* Enable the DMA channel */
1755 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
1756
1757 /* Enable the TIM Capture/Compare 1 DMA request */
1758 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1759 }
1760 break;
1761
1762 case TIM_CHANNEL_2:
1763 {
1764 /* Set the DMA Period elapsed callback */
1765 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
1766
1767 /* Set the DMA error callback */
1768 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
1769
1770 /* Enable the DMA channel */
1771 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
1772
1773 /* Enable the TIM Capture/Compare 2 DMA request */
1774 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1775 }
1776 break;
1777
1778 case TIM_CHANNEL_3:
1779 {
1780 /* Set the DMA Period elapsed callback */
1781 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
1782
1783 /* Set the DMA error callback */
1784 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
1785
1786 /* Enable the DMA channel */
1787 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
1788
1789 /* Enable the TIM Capture/Compare 3 DMA request */
1790 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1791 }
1792 break;
1793
1794 case TIM_CHANNEL_4:
1795 {
1796 /* Set the DMA Period elapsed callback */
1797 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
1798
1799 /* Set the DMA error callback */
1800 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
1801
1802 /* Enable the DMA channel */
1803 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
1804
1805 /* Enable the TIM Capture/Compare 4 DMA request */
1806 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1807 }
1808 break;
1809
1810 default:
1811 break;
1812 }
1813
1814 /* Enable the Input Capture channel */
1815 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1816
1817 /* Enable the Peripheral */
1818 __HAL_TIM_ENABLE(htim);
1819
1820 /* Return function status */
1821 return HAL_OK;
1822 }
1823
1824 /**
1825 * @brief Stops the TIM Input Capture measurement on in DMA mode.
1826 * @param htim : TIM Input Capture handle
1827 * @param Channel : TIM Channels to be disabled
1828 * This parameter can be one of the following values:
1829 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1830 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1831 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1832 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1833 * @retval HAL status
1834 */
1835 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1836 {
1837 /* Check the parameters */
1838 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1839 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
1840
1841 switch (Channel)
1842 {
1843 case TIM_CHANNEL_1:
1844 {
1845 /* Disable the TIM Capture/Compare 1 DMA request */
1846 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1847 }
1848 break;
1849
1850 case TIM_CHANNEL_2:
1851 {
1852 /* Disable the TIM Capture/Compare 2 DMA request */
1853 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1854 }
1855 break;
1856
1857 case TIM_CHANNEL_3:
1858 {
1859 /* Disable the TIM Capture/Compare 3 DMA request */
1860 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1861 }
1862 break;
1863
1864 case TIM_CHANNEL_4:
1865 {
1866 /* Disable the TIM Capture/Compare 4 DMA request */
1867 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1868 }
1869 break;
1870
1871 default:
1872 break;
1873 }
1874
1875 /* Disable the Input Capture channel */
1876 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1877
1878 /* Disable the Peripheral */
1879 __HAL_TIM_DISABLE(htim);
1880
1881 /* Change the htim state */
1882 htim->State = HAL_TIM_STATE_READY;
1883
1884 /* Return function status */
1885 return HAL_OK;
1886 }
1887 /**
1888 * @}
1889 */
1890
1891 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
1892 * @brief Time One Pulse functions
1893 *
1894 @verbatim
1895 ==============================================================================
1896 ##### Time One Pulse functions #####
1897 ==============================================================================
1898 [..]
1899 This section provides functions allowing to:
1900 (+) Initialize and configure the TIM One Pulse.
1901 (+) De-initialize the TIM One Pulse.
1902 (+) Start the Time One Pulse.
1903 (+) Stop the Time One Pulse.
1904 (+) Start the Time One Pulse and enable interrupt.
1905 (+) Stop the Time One Pulse and disable interrupt.
1906 (+) Start the Time One Pulse and enable DMA transfer.
1907 (+) Stop the Time One Pulse and disable DMA transfer.
1908
1909 @endverbatim
1910 * @{
1911 */
1912 /**
1913 * @brief Initializes the TIM One Pulse Time Base according to the specified
1914 * parameters in the TIM_HandleTypeDef and create the associated handle.
1915 * @param htim: TIM OnePulse handle
1916 * @param OnePulseMode: Select the One pulse mode.
1917 * This parameter can be one of the following values:
1918 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
1919 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
1920 * @retval HAL status
1921 */
1922 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
1923 {
1924 /* Check the TIM handle allocation */
1925 if(htim == HAL_NULL)
1926 {
1927 return HAL_ERROR;
1928 }
1929
1930 /* Check the parameters */
1931 assert_param(IS_TIM_INSTANCE(htim->Instance));
1932 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1933 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1934 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
1935
1936 if(htim->State == HAL_TIM_STATE_RESET)
1937 {
1938 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1939 HAL_TIM_OnePulse_MspInit(htim);
1940 }
1941
1942 /* Set the TIM state */
1943 htim->State= HAL_TIM_STATE_BUSY;
1944
1945 /* Configure the Time base in the One Pulse Mode */
1946 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1947
1948 /* Reset the OPM Bit */
1949 htim->Instance->CR1 &= ~TIM_CR1_OPM;
1950
1951 /* Configure the OPM Mode */
1952 htim->Instance->CR1 |= OnePulseMode;
1953
1954 /* Initialize the TIM state*/
1955 htim->State= HAL_TIM_STATE_READY;
1956
1957 return HAL_OK;
1958 }
1959
1960 /**
1961 * @brief DeInitializes the TIM One Pulse
1962 * @param htim: TIM One Pulse handle
1963 * @retval HAL status
1964 */
1965 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
1966 {
1967 /* Check the parameters */
1968 assert_param(IS_TIM_INSTANCE(htim->Instance));
1969
1970 htim->State = HAL_TIM_STATE_BUSY;
1971
1972 /* Disable the TIM Peripheral Clock */
1973 __HAL_TIM_DISABLE(htim);
1974
1975 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
1976 HAL_TIM_OnePulse_MspDeInit(htim);
1977
1978 /* Change TIM state */
1979 htim->State = HAL_TIM_STATE_RESET;
1980
1981 /* Release Lock */
1982 __HAL_UNLOCK(htim);
1983
1984 return HAL_OK;
1985 }
1986
1987 /**
1988 * @brief Initializes the TIM One Pulse MSP.
1989 * @param htim: TIM handle
1990 * @retval None
1991 */
1992 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
1993 {
1994 /* NOTE : This function Should not be modified, when the callback is needed,
1995 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
1996 */
1997 }
1998
1999 /**
2000 * @brief DeInitializes TIM One Pulse MSP.
2001 * @param htim: TIM handle
2002 * @retval None
2003 */
2004 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
2005 {
2006 /* NOTE : This function Should not be modified, when the callback is needed,
2007 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2008 */
2009 }
2010
2011 /**
2012 * @brief Starts the TIM One Pulse signal generation.
2013 * @param htim : TIM One Pulse handle
2014 * @param OutputChannel : TIM Channels to be enabled
2015 * This parameter can be one of the following values:
2016 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2017 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2018 * @retval HAL status
2019 */
2020 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2021 {
2022 /* Enable the Capture compare and the Input Capture channels
2023 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2024 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2025 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2026 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2027
2028 No need to enable the counter, it's enabled automatically by hardware
2029 (the counter starts in response to a stimulus and generate a pulse */
2030
2031 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2032 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2033
2034 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2035 {
2036 /* Enable the main output */
2037 __HAL_TIM_MOE_ENABLE(htim);
2038 }
2039
2040 /* Return function status */
2041 return HAL_OK;
2042 }
2043
2044 /**
2045 * @brief Stops the TIM One Pulse signal generation.
2046 * @param htim : TIM One Pulse handle
2047 * @param OutputChannel : TIM Channels to be disable
2048 * This parameter can be one of the following values:
2049 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2050 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2051 * @retval HAL status
2052 */
2053 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2054 {
2055 /* Disable the Capture compare and the Input Capture channels
2056 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2057 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2058 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2059 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2060
2061 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2062 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2063
2064 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2065 {
2066 /* Disable the Main Ouput */
2067 __HAL_TIM_MOE_DISABLE(htim);
2068 }
2069
2070 /* Disable the Peripheral */
2071 __HAL_TIM_DISABLE(htim);
2072
2073 /* Return function status */
2074 return HAL_OK;
2075 }
2076
2077 /**
2078 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2079 * @param htim : TIM One Pulse handle
2080 * @param OutputChannel : TIM Channels to be enabled
2081 * This parameter can be one of the following values:
2082 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2083 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2084 * @retval HAL status
2085 */
2086 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2087 {
2088 /* Enable the Capture compare and the Input Capture channels
2089 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2090 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2091 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2092 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2093
2094 No need to enable the counter, it's enabled automatically by hardware
2095 (the counter starts in response to a stimulus and generate a pulse */
2096
2097 /* Enable the TIM Capture/Compare 1 interrupt */
2098 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2099
2100 /* Enable the TIM Capture/Compare 2 interrupt */
2101 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2102
2103 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2104 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2105
2106 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2107 {
2108 /* Enable the main output */
2109 __HAL_TIM_MOE_ENABLE(htim);
2110 }
2111
2112 /* Return function status */
2113 return HAL_OK;
2114 }
2115
2116 /**
2117 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2118 * @param htim : TIM One Pulse handle
2119 * @param OutputChannel : TIM Channels to be enabled
2120 * This parameter can be one of the following values:
2121 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2122 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2123 * @retval HAL status
2124 */
2125 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2126 {
2127 /* Disable the TIM Capture/Compare 1 interrupt */
2128 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2129
2130 /* Disable the TIM Capture/Compare 2 interrupt */
2131 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2132
2133 /* Disable the Capture compare and the Input Capture channels
2134 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2135 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2136 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2137 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2138 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2139 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2140
2141 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2142 {
2143 /* Disable the Main Ouput */
2144 __HAL_TIM_MOE_DISABLE(htim);
2145 }
2146
2147 /* Disable the Peripheral */
2148 __HAL_TIM_DISABLE(htim);
2149
2150 /* Return function status */
2151 return HAL_OK;
2152 }
2153
2154 /**
2155 * @}
2156 */
2157
2158 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
2159 * @brief Time Encoder functions
2160 *
2161 @verbatim
2162 ==============================================================================
2163 ##### Time Encoder functions #####
2164 ==============================================================================
2165 [..]
2166 This section provides functions allowing to:
2167 (+) Initialize and configure the TIM Encoder.
2168 (+) De-initialize the TIM Encoder.
2169 (+) Start the Time Encoder.
2170 (+) Stop the Time Encoder.
2171 (+) Start the Time Encoder and enable interrupt.
2172 (+) Stop the Time Encoder and disable interrupt.
2173 (+) Start the Time Encoder and enable DMA transfer.
2174 (+) Stop the Time Encoder and disable DMA transfer.
2175
2176 @endverbatim
2177 * @{
2178 */
2179 /**
2180 * @brief Initializes the TIM Encoder Interface and create the associated handle.
2181 * @param htim: TIM Encoder Interface handle
2182 * @param sConfig: TIM Encoder Interface configuration structure
2183 * @retval HAL status
2184 */
2185 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
2186 {
2187 uint32_t tmpsmcr = 0;
2188 uint32_t tmpccmr1 = 0;
2189 uint32_t tmpccer = 0;
2190
2191 /* Check the TIM handle allocation */
2192 if(htim == HAL_NULL)
2193 {
2194 return HAL_ERROR;
2195 }
2196
2197 /* Check the parameters */
2198 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2199 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
2200 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
2201 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
2202 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
2203 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
2204 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
2205 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
2206 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
2207 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
2208
2209 if(htim->State == HAL_TIM_STATE_RESET)
2210 {
2211 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2212 HAL_TIM_Encoder_MspInit(htim);
2213 }
2214
2215 /* Set the TIM state */
2216 htim->State= HAL_TIM_STATE_BUSY;
2217
2218 /* Reset the SMS bits */
2219 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
2220
2221 /* Configure the Time base in the Encoder Mode */
2222 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2223
2224 /* Get the TIMx SMCR register value */
2225 tmpsmcr = htim->Instance->SMCR;
2226
2227 /* Get the TIMx CCMR1 register value */
2228 tmpccmr1 = htim->Instance->CCMR1;
2229
2230 /* Get the TIMx CCER register value */
2231 tmpccer = htim->Instance->CCER;
2232
2233 /* Set the encoder Mode */
2234 tmpsmcr |= sConfig->EncoderMode;
2235
2236 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
2237 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
2238 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
2239
2240 /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
2241 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
2242 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
2243 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
2244 tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
2245
2246 /* Set the TI1 and the TI2 Polarities */
2247 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
2248 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
2249 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
2250
2251 /* Write to TIMx SMCR */
2252 htim->Instance->SMCR = tmpsmcr;
2253
2254 /* Write to TIMx CCMR1 */
2255 htim->Instance->CCMR1 = tmpccmr1;
2256
2257 /* Write to TIMx CCER */
2258 htim->Instance->CCER = tmpccer;
2259
2260 /* Initialize the TIM state*/
2261 htim->State= HAL_TIM_STATE_READY;
2262
2263 return HAL_OK;
2264 }
2265
2266
2267 /**
2268 * @brief DeInitializes the TIM Encoder interface
2269 * @param htim: TIM Encoder handle
2270 * @retval HAL status
2271 */
2272 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
2273 {
2274 /* Check the parameters */
2275 assert_param(IS_TIM_INSTANCE(htim->Instance));
2276
2277 htim->State = HAL_TIM_STATE_BUSY;
2278
2279 /* Disable the TIM Peripheral Clock */
2280 __HAL_TIM_DISABLE(htim);
2281
2282 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2283 HAL_TIM_Encoder_MspDeInit(htim);
2284
2285 /* Change TIM state */
2286 htim->State = HAL_TIM_STATE_RESET;
2287
2288 /* Release Lock */
2289 __HAL_UNLOCK(htim);
2290
2291 return HAL_OK;
2292 }
2293
2294 /**
2295 * @brief Initializes the TIM Encoder Interface MSP.
2296 * @param htim: TIM handle
2297 * @retval None
2298 */
2299 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
2300 {
2301 /* NOTE : This function Should not be modified, when the callback is needed,
2302 the HAL_TIM_Encoder_MspInit could be implemented in the user file
2303 */
2304 }
2305
2306 /**
2307 * @brief DeInitializes TIM Encoder Interface MSP.
2308 * @param htim: TIM handle
2309 * @retval None
2310 */
2311 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
2312 {
2313 /* NOTE : This function Should not be modified, when the callback is needed,
2314 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
2315 */
2316 }
2317
2318 /**
2319 * @brief Starts the TIM Encoder Interface.
2320 * @param htim : TIM Encoder Interface handle
2321 * @param Channel : TIM Channels to be enabled
2322 * This parameter can be one of the following values:
2323 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2324 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2325 * @retval HAL status
2326 */
2327 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2328 {
2329 /* Check the parameters */
2330 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2331
2332 /* Enable the encoder interface channels */
2333 switch (Channel)
2334 {
2335 case TIM_CHANNEL_1:
2336 {
2337 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2338 break;
2339 }
2340 case TIM_CHANNEL_2:
2341 {
2342 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2343 break;
2344 }
2345 default :
2346 {
2347 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2348 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2349 break;
2350 }
2351 }
2352 /* Enable the Peripheral */
2353 __HAL_TIM_ENABLE(htim);
2354
2355 /* Return function status */
2356 return HAL_OK;
2357 }
2358
2359 /**
2360 * @brief Stops the TIM Encoder Interface.
2361 * @param htim : TIM Encoder Interface handle
2362 * @param Channel : TIM Channels to be disabled
2363 * This parameter can be one of the following values:
2364 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2365 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2366 * @retval HAL status
2367 */
2368 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2369 {
2370 /* Check the parameters */
2371 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2372
2373 /* Disable the Input Capture channels 1 and 2
2374 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2375 switch (Channel)
2376 {
2377 case TIM_CHANNEL_1:
2378 {
2379 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2380 break;
2381 }
2382 case TIM_CHANNEL_2:
2383 {
2384 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2385 break;
2386 }
2387 default :
2388 {
2389 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2390 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2391 break;
2392 }
2393 }
2394
2395 /* Disable the Peripheral */
2396 __HAL_TIM_DISABLE(htim);
2397
2398 /* Return function status */
2399 return HAL_OK;
2400 }
2401
2402 /**
2403 * @brief Starts the TIM Encoder Interface in interrupt mode.
2404 * @param htim : TIM Encoder Interface handle
2405 * @param Channel : TIM Channels to be enabled
2406 * This parameter can be one of the following values:
2407 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2408 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2409 * @retval HAL status
2410 */
2411 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2412 {
2413 /* Check the parameters */
2414 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2415
2416 /* Enable the encoder interface channels */
2417 /* Enable the capture compare Interrupts 1 and/or 2 */
2418 switch (Channel)
2419 {
2420 case TIM_CHANNEL_1:
2421 {
2422 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2423 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2424 break;
2425 }
2426 case TIM_CHANNEL_2:
2427 {
2428 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2429 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2430 break;
2431 }
2432 default :
2433 {
2434 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2435 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2436 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2437 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2438 break;
2439 }
2440 }
2441
2442 /* Enable the Peripheral */
2443 __HAL_TIM_ENABLE(htim);
2444
2445 /* Return function status */
2446 return HAL_OK;
2447 }
2448
2449 /**
2450 * @brief Stops the TIM Encoder Interface in interrupt mode.
2451 * @param htim : TIM Encoder Interface handle
2452 * @param Channel : TIM Channels to be disabled
2453 * This parameter can be one of the following values:
2454 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2455 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2456 * @retval HAL status
2457 */
2458 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2459 {
2460 /* Check the parameters */
2461 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2462
2463 /* Disable the Input Capture channels 1 and 2
2464 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2465 if(Channel == TIM_CHANNEL_1)
2466 {
2467 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2468
2469 /* Disable the capture compare Interrupts 1 */
2470 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2471 }
2472 else if(Channel == TIM_CHANNEL_2)
2473 {
2474 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2475
2476 /* Disable the capture compare Interrupts 2 */
2477 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2478 }
2479 else
2480 {
2481 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2482 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2483
2484 /* Disable the capture compare Interrupts 1 and 2 */
2485 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2486 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2487 }
2488
2489 /* Disable the Peripheral */
2490 __HAL_TIM_DISABLE(htim);
2491
2492 /* Change the htim state */
2493 htim->State = HAL_TIM_STATE_READY;
2494
2495 /* Return function status */
2496 return HAL_OK;
2497 }
2498
2499 /**
2500 * @brief Starts the TIM Encoder Interface in DMA mode.
2501 * @param htim : TIM Encoder Interface handle
2502 * @param Channel : TIM Channels to be enabled
2503 * This parameter can be one of the following values:
2504 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2505 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2506 * @param pData1: The destination Buffer address for IC1.
2507 * @param pData2: The destination Buffer address for IC2.
2508 * @param Length: The length of data to be transferred from TIM peripheral to memory.
2509 * @retval HAL status
2510 */
2511 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
2512 {
2513 /* Check the parameters */
2514 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2515
2516 if((htim->State == HAL_TIM_STATE_BUSY))
2517 {
2518 return HAL_BUSY;
2519 }
2520 else if((htim->State == HAL_TIM_STATE_READY))
2521 {
2522 if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
2523 {
2524 return HAL_ERROR;
2525 }
2526 else
2527 {
2528 htim->State = HAL_TIM_STATE_BUSY;
2529 }
2530 }
2531
2532 switch (Channel)
2533 {
2534 case TIM_CHANNEL_1:
2535 {
2536 /* Set the DMA Period elapsed callback */
2537 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
2538
2539 /* Set the DMA error callback */
2540 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
2541
2542 /* Enable the DMA channel */
2543 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
2544
2545 /* Enable the TIM Input Capture DMA request */
2546 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2547
2548 /* Enable the Peripheral */
2549 __HAL_TIM_ENABLE(htim);
2550
2551 /* Enable the Capture compare channel */
2552 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2553 }
2554 break;
2555
2556 case TIM_CHANNEL_2:
2557 {
2558 /* Set the DMA Period elapsed callback */
2559 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
2560
2561 /* Set the DMA error callback */
2562 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError;
2563 /* Enable the DMA channel */
2564 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
2565
2566 /* Enable the TIM Input Capture DMA request */
2567 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2568
2569 /* Enable the Peripheral */
2570 __HAL_TIM_ENABLE(htim);
2571
2572 /* Enable the Capture compare channel */
2573 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2574 }
2575 break;
2576
2577 case TIM_CHANNEL_ALL:
2578 {
2579 /* Set the DMA Period elapsed callback */
2580 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
2581
2582 /* Set the DMA error callback */
2583 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
2584
2585 /* Enable the DMA channel */
2586 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
2587
2588 /* Set the DMA Period elapsed callback */
2589 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
2590
2591 /* Set the DMA error callback */
2592 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
2593
2594 /* Enable the DMA channel */
2595 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
2596
2597 /* Enable the Peripheral */
2598 __HAL_TIM_ENABLE(htim);
2599
2600 /* Enable the Capture compare channel */
2601 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2602 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2603
2604 /* Enable the TIM Input Capture DMA request */
2605 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2606 /* Enable the TIM Input Capture DMA request */
2607 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2608 }
2609 break;
2610
2611 default:
2612 break;
2613 }
2614 /* Return function status */
2615 return HAL_OK;
2616 }
2617
2618 /**
2619 * @brief Stops the TIM Encoder Interface in DMA mode.
2620 * @param htim : TIM Encoder Interface handle
2621 * @param Channel : TIM Channels to be enabled
2622 * This parameter can be one of the following values:
2623 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2624 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2625 * @retval HAL status
2626 */
2627 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2628 {
2629 /* Check the parameters */
2630 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2631
2632 /* Disable the Input Capture channels 1 and 2
2633 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2634 if(Channel == TIM_CHANNEL_1)
2635 {
2636 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2637
2638 /* Disable the capture compare DMA Request 1 */
2639 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2640 }
2641 else if(Channel == TIM_CHANNEL_2)
2642 {
2643 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2644
2645 /* Disable the capture compare DMA Request 2 */
2646 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2647 }
2648 else
2649 {
2650 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2651 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2652
2653 /* Disable the capture compare DMA Request 1 and 2 */
2654 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2655 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2656 }
2657
2658 /* Disable the Peripheral */
2659 __HAL_TIM_DISABLE(htim);
2660
2661 /* Change the htim state */
2662 htim->State = HAL_TIM_STATE_READY;
2663
2664 /* Return function status */
2665 return HAL_OK;
2666 }
2667
2668 /**
2669 * @}
2670 */
2671 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
2672 * @brief IRQ handler management
2673 *
2674 @verbatim
2675 ==============================================================================
2676 ##### IRQ handler management #####
2677 ==============================================================================
2678 [..]
2679 This section provides Timer IRQ handler function.
2680
2681 @endverbatim
2682 * @{
2683 */
2684 /**
2685 * @brief This function handles TIM interrupts requests.
2686 * @param htim: TIM handle
2687 * @retval None
2688 */
2689 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
2690 {
2691 /* Capture compare 1 event */
2692 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
2693 {
2694 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC1) !=RESET)
2695 {
2696 {
2697 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
2698 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
2699
2700 /* Input capture event */
2701 if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
2702 {
2703 HAL_TIM_IC_CaptureCallback(htim);
2704 }
2705 /* Output compare event */
2706 else
2707 {
2708 HAL_TIM_OC_DelayElapsedCallback(htim);
2709 HAL_TIM_PWM_PulseFinishedCallback(htim);
2710 }
2711 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2712 }
2713 }
2714 }
2715 /* Capture compare 2 event */
2716 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
2717 {
2718 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC2) !=RESET)
2719 {
2720 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
2721 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
2722 /* Input capture event */
2723 if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
2724 {
2725 HAL_TIM_IC_CaptureCallback(htim);
2726 }
2727 /* Output compare event */
2728 else
2729 {
2730 HAL_TIM_OC_DelayElapsedCallback(htim);
2731 HAL_TIM_PWM_PulseFinishedCallback(htim);
2732 }
2733 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2734 }
2735 }
2736 /* Capture compare 3 event */
2737 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
2738 {
2739 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC3) !=RESET)
2740 {
2741 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
2742 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
2743 /* Input capture event */
2744 if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
2745 {
2746 HAL_TIM_IC_CaptureCallback(htim);
2747 }
2748 /* Output compare event */
2749 else
2750 {
2751 HAL_TIM_OC_DelayElapsedCallback(htim);
2752 HAL_TIM_PWM_PulseFinishedCallback(htim);
2753 }
2754 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2755 }
2756 }
2757 /* Capture compare 4 event */
2758 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
2759 {
2760 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC4) !=RESET)
2761 {
2762 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
2763 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
2764 /* Input capture event */
2765 if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
2766 {
2767 HAL_TIM_IC_CaptureCallback(htim);
2768 }
2769 /* Output compare event */
2770 else
2771 {
2772 HAL_TIM_OC_DelayElapsedCallback(htim);
2773 HAL_TIM_PWM_PulseFinishedCallback(htim);
2774 }
2775 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2776 }
2777 }
2778 /* TIM Update event */
2779 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
2780 {
2781 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_UPDATE) !=RESET)
2782 {
2783 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
2784 HAL_TIM_PeriodElapsedCallback(htim);
2785 }
2786 }
2787 /* TIM Break input event */
2788 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
2789 {
2790 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_BREAK) !=RESET)
2791 {
2792 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
2793 HAL_TIMEx_BreakCallback(htim);
2794 }
2795 }
2796 /* TIM Trigger detection event */
2797 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
2798 {
2799 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_TRIGGER) !=RESET)
2800 {
2801 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
2802 HAL_TIM_TriggerCallback(htim);
2803 }
2804 }
2805 /* TIM commutation event */
2806 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
2807 {
2808 if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_COM) !=RESET)
2809 {
2810 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
2811 HAL_TIMEx_CommutationCallback(htim);
2812 }
2813 }
2814 }
2815
2816 /**
2817 * @}
2818 */
2819
2820 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
2821 * @brief Peripheral Control functions
2822 *
2823 @verbatim
2824 ==============================================================================
2825 ##### Peripheral Control functions #####
2826 ==============================================================================
2827 [..]
2828 This section provides functions allowing to:
2829 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
2830 (+) Configure External Clock source.
2831 (+) Configure Complementary channels, break features and dead time.
2832 (+) Configure Master and the Slave synchronization.
2833 (+) Configure the DMA Burst Mode.
2834
2835 @endverbatim
2836 * @{
2837 */
2838
2839 /**
2840 * @brief Initializes the TIM Output Compare Channels according to the specified
2841 * parameters in the TIM_OC_InitTypeDef.
2842 * @param htim: TIM Output Compare handle
2843 * @param sConfig: TIM Output Compare configuration structure
2844 * @param Channel : TIM Channels to be enabled
2845 * This parameter can be one of the following values:
2846 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2847 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2848 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2849 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2850 * @retval HAL status
2851 */
2852 __weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
2853 {
2854 /* Check the parameters */
2855 assert_param(IS_TIM_CHANNELS(Channel));
2856 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
2857 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
2858 assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
2859 assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
2860 assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
2861
2862 /* Check input state */
2863 __HAL_LOCK(htim);
2864
2865 htim->State = HAL_TIM_STATE_BUSY;
2866
2867 switch (Channel)
2868 {
2869 case TIM_CHANNEL_1:
2870 {
2871 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
2872 /* Configure the TIM Channel 1 in Output Compare */
2873 TIM_OC1_SetConfig(htim->Instance, sConfig);
2874 }
2875 break;
2876
2877 case TIM_CHANNEL_2:
2878 {
2879 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2880 /* Configure the TIM Channel 2 in Output Compare */
2881 TIM_OC2_SetConfig(htim->Instance, sConfig);
2882 }
2883 break;
2884
2885 case TIM_CHANNEL_3:
2886 {
2887 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
2888 /* Configure the TIM Channel 3 in Output Compare */
2889 TIM_OC3_SetConfig(htim->Instance, sConfig);
2890 }
2891 break;
2892
2893 case TIM_CHANNEL_4:
2894 {
2895 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
2896 /* Configure the TIM Channel 4 in Output Compare */
2897 TIM_OC4_SetConfig(htim->Instance, sConfig);
2898 }
2899 break;
2900
2901 default:
2902 break;
2903 }
2904 htim->State = HAL_TIM_STATE_READY;
2905
2906 __HAL_UNLOCK(htim);
2907
2908 return HAL_OK;
2909 }
2910
2911 /**
2912 * @brief Initializes the TIM Input Capture Channels according to the specified
2913 * parameters in the TIM_IC_InitTypeDef.
2914 * @param htim: TIM IC handle
2915 * @param sConfig: TIM Input Capture configuration structure
2916 * @param Channel : TIM Channels to be enabled
2917 * This parameter can be one of the following values:
2918 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2919 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2920 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2921 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2922 * @retval HAL status
2923 */
2924 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
2925 {
2926 /* Check the parameters */
2927 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
2928 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
2929 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
2930 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
2931 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
2932
2933 __HAL_LOCK(htim);
2934
2935 htim->State = HAL_TIM_STATE_BUSY;
2936
2937 if (Channel == TIM_CHANNEL_1)
2938 {
2939 /* TI1 Configuration */
2940 TIM_TI1_SetConfig(htim->Instance,
2941 sConfig->ICPolarity,
2942 sConfig->ICSelection,
2943 sConfig->ICFilter);
2944
2945 /* Reset the IC1PSC Bits */
2946 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
2947
2948 /* Set the IC1PSC value */
2949 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
2950 }
2951 else if (Channel == TIM_CHANNEL_2)
2952 {
2953 /* TI2 Configuration */
2954 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2955
2956 TIM_TI2_SetConfig(htim->Instance,
2957 sConfig->ICPolarity,
2958 sConfig->ICSelection,
2959 sConfig->ICFilter);
2960
2961 /* Reset the IC2PSC Bits */
2962 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
2963
2964 /* Set the IC2PSC value */
2965 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
2966 }
2967 else if (Channel == TIM_CHANNEL_3)
2968 {
2969 /* TI3 Configuration */
2970 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
2971
2972 TIM_TI3_SetConfig(htim->Instance,
2973 sConfig->ICPolarity,
2974 sConfig->ICSelection,
2975 sConfig->ICFilter);
2976
2977 /* Reset the IC3PSC Bits */
2978 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
2979
2980 /* Set the IC3PSC value */
2981 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
2982 }
2983 else
2984 {
2985 /* TI4 Configuration */
2986 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
2987
2988 TIM_TI4_SetConfig(htim->Instance,
2989 sConfig->ICPolarity,
2990 sConfig->ICSelection,
2991 sConfig->ICFilter);
2992
2993 /* Reset the IC4PSC Bits */
2994 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
2995
2996 /* Set the IC4PSC value */
2997 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
2998 }
2999
3000 htim->State = HAL_TIM_STATE_READY;
3001
3002 __HAL_UNLOCK(htim);
3003
3004 return HAL_OK;
3005 }
3006
3007 /**
3008 * @brief Initializes the TIM PWM channels according to the specified
3009 * parameters in the TIM_OC_InitTypeDef.
3010 * @param htim: TIM handle
3011 * @param sConfig: TIM PWM configuration structure
3012 * @param Channel : TIM Channels to be enabled
3013 * This parameter can be one of the following values:
3014 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3015 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3016 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3017 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3018 * @retval HAL status
3019 */
3020 __weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
3021 {
3022 __HAL_LOCK(htim);
3023
3024 /* Check the parameters */
3025 assert_param(IS_TIM_CHANNELS(Channel));
3026 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
3027 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
3028 assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
3029 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
3030 assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
3031 assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
3032
3033 htim->State = HAL_TIM_STATE_BUSY;
3034
3035 switch (Channel)
3036 {
3037 case TIM_CHANNEL_1:
3038 {
3039 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3040 /* Configure the Channel 1 in PWM mode */
3041 TIM_OC1_SetConfig(htim->Instance, sConfig);
3042
3043 /* Set the Preload enable bit for channel1 */
3044 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
3045
3046 /* Configure the Output Fast mode */
3047 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
3048 htim->Instance->CCMR1 |= sConfig->OCFastMode;
3049 }
3050 break;
3051
3052 case TIM_CHANNEL_2:
3053 {
3054 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3055 /* Configure the Channel 2 in PWM mode */
3056 TIM_OC2_SetConfig(htim->Instance, sConfig);
3057
3058 /* Set the Preload enable bit for channel2 */
3059 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
3060
3061 /* Configure the Output Fast mode */
3062 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
3063 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
3064 }
3065 break;
3066
3067 case TIM_CHANNEL_3:
3068 {
3069 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3070 /* Configure the Channel 3 in PWM mode */
3071 TIM_OC3_SetConfig(htim->Instance, sConfig);
3072
3073 /* Set the Preload enable bit for channel3 */
3074 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
3075
3076 /* Configure the Output Fast mode */
3077 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
3078 htim->Instance->CCMR2 |= sConfig->OCFastMode;
3079 }
3080 break;
3081
3082 case TIM_CHANNEL_4:
3083 {
3084 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3085 /* Configure the Channel 4 in PWM mode */
3086 TIM_OC4_SetConfig(htim->Instance, sConfig);
3087
3088 /* Set the Preload enable bit for channel4 */
3089 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
3090
3091 /* Configure the Output Fast mode */
3092 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
3093 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
3094 }
3095 break;
3096
3097 default:
3098 break;
3099 }
3100
3101 htim->State = HAL_TIM_STATE_READY;
3102
3103 __HAL_UNLOCK(htim);
3104
3105 return HAL_OK;
3106 }
3107
3108 /**
3109 * @brief Initializes the TIM One Pulse Channels according to the specified
3110 * parameters in the TIM_OnePulse_InitTypeDef.
3111 * @param htim: TIM One Pulse handle
3112 * @param sConfig: TIM One Pulse configuration structure
3113 * @param OutputChannel : TIM Channels to be enabled
3114 * This parameter can be one of the following values:
3115 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3116 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3117 * @param InputChannel : TIM Channels to be enabled
3118 * This parameter can be one of the following values:
3119 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3120 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3121 * @retval HAL status
3122 */
3123 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
3124 {
3125 TIM_OC_InitTypeDef temp1;
3126
3127 /* Check the parameters */
3128 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
3129 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
3130
3131 if(OutputChannel != InputChannel)
3132 {
3133 __HAL_LOCK(htim);
3134
3135 htim->State = HAL_TIM_STATE_BUSY;
3136
3137 /* Extract the Ouput compare configuration from sConfig structure */
3138 temp1.OCMode = sConfig->OCMode;
3139 temp1.Pulse = sConfig->Pulse;
3140 temp1.OCPolarity = sConfig->OCPolarity;
3141 temp1.OCNPolarity = sConfig->OCNPolarity;
3142 temp1.OCIdleState = sConfig->OCIdleState;
3143 temp1.OCNIdleState = sConfig->OCNIdleState;
3144
3145 switch (OutputChannel)
3146 {
3147 case TIM_CHANNEL_1:
3148 {
3149 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3150
3151 TIM_OC1_SetConfig(htim->Instance, &temp1);
3152 }
3153 break;
3154 case TIM_CHANNEL_2:
3155 {
3156 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3157
3158 TIM_OC2_SetConfig(htim->Instance, &temp1);
3159 }
3160 break;
3161 default:
3162 break;
3163 }
3164 switch (InputChannel)
3165 {
3166 case TIM_CHANNEL_1:
3167 {
3168 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3169
3170 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
3171 sConfig->ICSelection, sConfig->ICFilter);
3172
3173 /* Reset the IC1PSC Bits */
3174 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
3175
3176 /* Select the Trigger source */
3177 htim->Instance->SMCR &= ~TIM_SMCR_TS;
3178 htim->Instance->SMCR |= TIM_TS_TI1FP1;
3179
3180 /* Select the Slave Mode */
3181 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3182 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
3183 }
3184 break;
3185 case TIM_CHANNEL_2:
3186 {
3187 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3188
3189 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
3190 sConfig->ICSelection, sConfig->ICFilter);
3191
3192 /* Reset the IC2PSC Bits */
3193 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
3194
3195 /* Select the Trigger source */
3196 htim->Instance->SMCR &= ~TIM_SMCR_TS;
3197 htim->Instance->SMCR |= TIM_TS_TI2FP2;
3198
3199 /* Select the Slave Mode */
3200 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3201 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
3202 }
3203 break;
3204
3205 default:
3206 break;
3207 }
3208
3209 htim->State = HAL_TIM_STATE_READY;
3210
3211 __HAL_UNLOCK(htim);
3212
3213 return HAL_OK;
3214 }
3215 else
3216 {
3217 return HAL_ERROR;
3218 }
3219 }
3220
3221 /**
3222 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
3223 * @param htim: TIM handle
3224 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write
3225 * This parameters can be on of the following values:
3226 * @arg TIM_DMABase_CR1
3227 * @arg TIM_DMABase_CR2
3228 * @arg TIM_DMABase_SMCR
3229 * @arg TIM_DMABase_DIER
3230 * @arg TIM_DMABase_SR
3231 * @arg TIM_DMABase_EGR
3232 * @arg TIM_DMABase_CCMR1
3233 * @arg TIM_DMABase_CCMR2
3234 * @arg TIM_DMABase_CCER
3235 * @arg TIM_DMABase_CNT
3236 * @arg TIM_DMABase_PSC
3237 * @arg TIM_DMABase_ARR
3238 * @arg TIM_DMABase_RCR
3239 * @arg TIM_DMABase_CCR1
3240 * @arg TIM_DMABase_CCR2
3241 * @arg TIM_DMABase_CCR3
3242 * @arg TIM_DMABase_CCR4
3243 * @arg TIM_DMABase_BDTR
3244 * @arg TIM_DMABase_DCR
3245 * @param BurstRequestSrc: TIM DMA Request sources
3246 * This parameters can be on of the following values:
3247 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
3248 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
3249 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
3250 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
3251 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
3252 * @arg TIM_DMA_COM: TIM Commutation DMA source
3253 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
3254 * @param BurstBuffer: The Buffer address.
3255 * @param BurstLength: DMA Burst length. This parameter can be one value
3256 * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
3257 * @retval HAL status
3258 */
3259 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
3260 uint32_t* BurstBuffer, uint32_t BurstLength)
3261 {
3262 /* Check the parameters */
3263 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
3264 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
3265 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3266 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
3267
3268 if((htim->State == HAL_TIM_STATE_BUSY))
3269 {
3270 return HAL_BUSY;
3271 }
3272 else if((htim->State == HAL_TIM_STATE_READY))
3273 {
3274 if((BurstBuffer == 0 ) && (BurstLength > 0))
3275 {
3276 return HAL_ERROR;
3277 }
3278 else
3279 {
3280 htim->State = HAL_TIM_STATE_BUSY;
3281 }
3282 }
3283 switch(BurstRequestSrc)
3284 {
3285 case TIM_DMA_UPDATE:
3286 {
3287 /* Set the DMA Period elapsed callback */
3288 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
3289
3290 /* Set the DMA error callback */
3291 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
3292
3293 /* Enable the DMA channel */
3294 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3295 }
3296 break;
3297 case TIM_DMA_CC1:
3298 {
3299 /* Set the DMA Period elapsed callback */
3300 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
3301
3302 /* Set the DMA error callback */
3303 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
3304
3305 /* Enable the DMA channel */
3306 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3307 }
3308 break;
3309 case TIM_DMA_CC2:
3310 {
3311 /* Set the DMA Period elapsed callback */
3312 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
3313
3314 /* Set the DMA error callback */
3315 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
3316
3317 /* Enable the DMA channel */
3318 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3319 }
3320 break;
3321 case TIM_DMA_CC3:
3322 {
3323 /* Set the DMA Period elapsed callback */
3324 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
3325
3326 /* Set the DMA error callback */
3327 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
3328
3329 /* Enable the DMA channel */
3330 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3331 }
3332 break;
3333 case TIM_DMA_CC4:
3334 {
3335 /* Set the DMA Period elapsed callback */
3336 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt;
3337
3338 /* Set the DMA error callback */
3339 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
3340
3341 /* Enable the DMA channel */
3342 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3343 }
3344 break;
3345 case TIM_DMA_COM:
3346 {
3347 /* Set the DMA Period elapsed callback */
3348 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
3349
3350 /* Set the DMA error callback */
3351 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
3352
3353 /* Enable the DMA channel */
3354 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3355 }
3356 break;
3357 case TIM_DMA_TRIGGER:
3358 {
3359 /* Set the DMA Period elapsed callback */
3360 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
3361
3362 /* Set the DMA error callback */
3363 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
3364
3365 /* Enable the DMA channel */
3366 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
3367 }
3368 break;
3369 default:
3370 break;
3371 }
3372 /* configure the DMA Burst Mode */
3373 htim->Instance->DCR = BurstBaseAddress | BurstLength;
3374
3375 /* Enable the TIM DMA Request */
3376 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
3377
3378 htim->State = HAL_TIM_STATE_READY;
3379
3380 /* Return function status */
3381 return HAL_OK;
3382 }
3383
3384 /**
3385 * @brief Stops the TIM DMA Burst mode
3386 * @param htim: TIM handle
3387 * @param BurstRequestSrc: TIM DMA Request sources to disable
3388 * @retval HAL status
3389 */
3390 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
3391 {
3392 /* Check the parameters */
3393 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3394
3395 /* Abort the DMA transfer (at least disable the DMA channel) */
3396 switch(BurstRequestSrc)
3397 {
3398 case TIM_DMA_UPDATE:
3399 {
3400 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
3401 }
3402 break;
3403 case TIM_DMA_CC1:
3404 {
3405 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
3406 }
3407 break;
3408 case TIM_DMA_CC2:
3409 {
3410 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
3411 }
3412 break;
3413 case TIM_DMA_CC3:
3414 {
3415 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
3416 }
3417 break;
3418 case TIM_DMA_CC4:
3419 {
3420 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
3421 }
3422 break;
3423 case TIM_DMA_COM:
3424 {
3425 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
3426 }
3427 break;
3428 case TIM_DMA_TRIGGER:
3429 {
3430 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
3431 }
3432 break;
3433 default:
3434 break;
3435 }
3436
3437 /* Disable the TIM Update DMA request */
3438 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
3439
3440 /* Return function status */
3441 return HAL_OK;
3442 }
3443
3444 /**
3445 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
3446 * @param htim: TIM handle
3447 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read
3448 * This parameters can be on of the following values:
3449 * @arg TIM_DMABase_CR1
3450 * @arg TIM_DMABase_CR2
3451 * @arg TIM_DMABase_SMCR
3452 * @arg TIM_DMABase_DIER
3453 * @arg TIM_DMABase_SR
3454 * @arg TIM_DMABase_EGR
3455 * @arg TIM_DMABase_CCMR1
3456 * @arg TIM_DMABase_CCMR2
3457 * @arg TIM_DMABase_CCER
3458 * @arg TIM_DMABase_CNT
3459 * @arg TIM_DMABase_PSC
3460 * @arg TIM_DMABase_ARR
3461 * @arg TIM_DMABase_RCR
3462 * @arg TIM_DMABase_CCR1
3463 * @arg TIM_DMABase_CCR2
3464 * @arg TIM_DMABase_CCR3
3465 * @arg TIM_DMABase_CCR4
3466 * @arg TIM_DMABase_BDTR
3467 * @arg TIM_DMABase_DCR
3468 * @param BurstRequestSrc: TIM DMA Request sources
3469 * This parameters can be on of the following values:
3470 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
3471 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
3472 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
3473 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
3474 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
3475 * @arg TIM_DMA_COM: TIM Commutation DMA source
3476 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
3477 * @param BurstBuffer: The Buffer address.
3478 * @param BurstLength: DMA Burst length. This parameter can be one value
3479 * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
3480 * @retval HAL status
3481 */
3482 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
3483 uint32_t *BurstBuffer, uint32_t BurstLength)
3484 {
3485 /* Check the parameters */
3486 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
3487 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
3488 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3489 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
3490
3491 if((htim->State == HAL_TIM_STATE_BUSY))
3492 {
3493 return HAL_BUSY;
3494 }
3495 else if((htim->State == HAL_TIM_STATE_READY))
3496 {
3497 if((BurstBuffer == 0 ) && (BurstLength > 0))
3498 {
3499 return HAL_ERROR;
3500 }
3501 else
3502 {
3503 htim->State = HAL_TIM_STATE_BUSY;
3504 }
3505 }
3506 switch(BurstRequestSrc)
3507 {
3508 case TIM_DMA_UPDATE:
3509 {
3510 /* Set the DMA Period elapsed callback */
3511 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
3512
3513 /* Set the DMA error callback */
3514 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ;
3515
3516 /* Enable the DMA channel */
3517 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3518 }
3519 break;
3520 case TIM_DMA_CC1:
3521 {
3522 /* Set the DMA Period elapsed callback */
3523 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
3524
3525 /* Set the DMA error callback */
3526 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ;
3527
3528 /* Enable the DMA channel */
3529 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3530 }
3531 break;
3532 case TIM_DMA_CC2:
3533 {
3534 /* Set the DMA Period elapsed callback */
3535 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
3536
3537 /* Set the DMA error callback */
3538 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ;
3539
3540 /* Enable the DMA channel */
3541 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3542 }
3543 break;
3544 case TIM_DMA_CC3:
3545 {
3546 /* Set the DMA Period elapsed callback */
3547 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
3548
3549 /* Set the DMA error callback */
3550 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ;
3551
3552 /* Enable the DMA channel */
3553 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3554 }
3555 break;
3556 case TIM_DMA_CC4:
3557 {
3558 /* Set the DMA Period elapsed callback */
3559 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt;
3560
3561 /* Set the DMA error callback */
3562 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ;
3563
3564 /* Enable the DMA channel */
3565 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3566 }
3567 break;
3568 case TIM_DMA_COM:
3569 {
3570 /* Set the DMA Period elapsed callback */
3571 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = HAL_TIMEx_DMACommutationCplt;
3572
3573 /* Set the DMA error callback */
3574 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = HAL_TIM_DMAError ;
3575
3576 /* Enable the DMA channel */
3577 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3578 }
3579 break;
3580 case TIM_DMA_TRIGGER:
3581 {
3582 /* Set the DMA Period elapsed callback */
3583 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
3584
3585 /* Set the DMA error callback */
3586 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ;
3587
3588 /* Enable the DMA channel */
3589 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
3590 }
3591 break;
3592 default:
3593 break;
3594 }
3595
3596 /* configure the DMA Burst Mode */
3597 htim->Instance->DCR = BurstBaseAddress | BurstLength;
3598
3599 /* Enable the TIM DMA Request */
3600 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
3601
3602 htim->State = HAL_TIM_STATE_READY;
3603
3604 /* Return function status */
3605 return HAL_OK;
3606 }
3607
3608 /**
3609 * @brief Stop the DMA burst reading
3610 * @param htim: TIM handle
3611 * @param BurstRequestSrc: TIM DMA Request sources to disable.
3612 * @retval HAL status
3613 */
3614 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
3615 {
3616 /* Check the parameters */
3617 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3618
3619 /* Abort the DMA transfer (at least disable the DMA channel) */
3620 switch(BurstRequestSrc)
3621 {
3622 case TIM_DMA_UPDATE:
3623 {
3624 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
3625 }
3626 break;
3627 case TIM_DMA_CC1:
3628 {
3629 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
3630 }
3631 break;
3632 case TIM_DMA_CC2:
3633 {
3634 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
3635 }
3636 break;
3637 case TIM_DMA_CC3:
3638 {
3639 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
3640 }
3641 break;
3642 case TIM_DMA_CC4:
3643 {
3644 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
3645 }
3646 break;
3647 case TIM_DMA_COM:
3648 {
3649 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
3650 }
3651 break;
3652 case TIM_DMA_TRIGGER:
3653 {
3654 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
3655 }
3656 break;
3657 default:
3658 break;
3659 }
3660
3661 /* Disable the TIM Update DMA request */
3662 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
3663
3664 /* Return function status */
3665 return HAL_OK;
3666 }
3667
3668 /**
3669 * @brief Generate a software event
3670 * @param htim: TIM handle
3671 * @param EventSource: specifies the event source.
3672 * This parameter can be one of the following values:
3673 * @arg TIM_EventSource_Update: Timer update Event source
3674 * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
3675 * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
3676 * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
3677 * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
3678 * @arg TIM_EventSource_COM: Timer COM event source
3679 * @arg TIM_EventSource_Trigger: Timer Trigger Event source
3680 * @arg TIM_EventSource_Break: Timer Break event source
3681 * @arg TIM_EventSource_Break2: Timer Break2 event source
3682 * @retval None
3683 * @note TIM_EventSource_Break2 isn't relevant for STM32F37xx and STM32F38xx
3684 * devices
3685 */
3686
3687 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
3688 {
3689 /* Check the parameters */
3690 assert_param(IS_TIM_INSTANCE(htim->Instance));
3691 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
3692
3693 /* Process Locked */
3694 __HAL_LOCK(htim);
3695
3696 /* Change the TIM state */
3697 htim->State = HAL_TIM_STATE_BUSY;
3698
3699 /* Set the event sources */
3700 htim->Instance->EGR = EventSource;
3701
3702 /* Change the TIM state */
3703 htim->State = HAL_TIM_STATE_READY;
3704
3705 __HAL_UNLOCK(htim);
3706
3707 /* Return function status */
3708 return HAL_OK;
3709 }
3710
3711 /**
3712 * @brief Configures the OCRef clear feature
3713 * @param htim: TIM handle
3714 * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
3715 * contains the OCREF clear feature and parameters for the TIM peripheral.
3716 * @param Channel: specifies the TIM Channel
3717 * This parameter can be one of the following values:
3718 * @arg TIM_Channel_1: TIM Channel 1
3719 * @arg TIM_Channel_2: TIM Channel 2
3720 * @arg TIM_Channel_3: TIM Channel 3
3721 * @arg TIM_Channel_4: TIM Channel 4
3722 * @retval HAL status
3723 */
3724 __weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
3725 {
3726 /* Check the parameters */
3727 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3728 assert_param(IS_TIM_CHANNELS(Channel));
3729 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
3730
3731 /* Process Locked */
3732 __HAL_LOCK(htim);
3733
3734 htim->State = HAL_TIM_STATE_BUSY;
3735
3736 if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
3737 {
3738 /* Check the parameters */
3739 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
3740 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
3741 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
3742
3743 TIM_ETR_SetConfig(htim->Instance,
3744 sClearInputConfig->ClearInputPrescaler,
3745 sClearInputConfig->ClearInputPolarity,
3746 sClearInputConfig->ClearInputFilter);
3747 }
3748
3749 switch (Channel)
3750 {
3751 case TIM_CHANNEL_1:
3752 {
3753 if(sClearInputConfig->ClearInputState != RESET)
3754 {
3755 /* Enable the Ocref clear feature for Channel 1 */
3756 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
3757 }
3758 else
3759 {
3760 /* Disable the Ocref clear feature for Channel 1 */
3761 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
3762 }
3763 }
3764 break;
3765 case TIM_CHANNEL_2:
3766 {
3767 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3768 if(sClearInputConfig->ClearInputState != RESET)
3769 {
3770 /* Enable the Ocref clear feature for Channel 2 */
3771 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
3772 }
3773 else
3774 {
3775 /* Disable the Ocref clear feature for Channel 2 */
3776 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
3777 }
3778 }
3779 break;
3780 case TIM_CHANNEL_3:
3781 {
3782 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3783 if(sClearInputConfig->ClearInputState != RESET)
3784 {
3785 /* Enable the Ocref clear feature for Channel 3 */
3786 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
3787 }
3788 else
3789 {
3790 /* Disable the Ocref clear feature for Channel 3 */
3791 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
3792 }
3793 }
3794 break;
3795 case TIM_CHANNEL_4:
3796 {
3797 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3798 if(sClearInputConfig->ClearInputState != RESET)
3799 {
3800 /* Enable the Ocref clear feature for Channel 4 */
3801 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
3802 }
3803 else
3804 {
3805 /* Disable the Ocref clear feature for Channel 4 */
3806 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
3807 }
3808 }
3809 break;
3810 default:
3811 break;
3812 }
3813
3814 htim->State = HAL_TIM_STATE_READY;
3815
3816 __HAL_UNLOCK(htim);
3817
3818 return HAL_OK;
3819 }
3820
3821 /**
3822 * @brief Configures the clock source to be used
3823 * @param htim: TIM handle
3824 * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
3825 * contains the clock source information for the TIM peripheral.
3826 * @retval HAL status
3827 */
3828 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
3829 {
3830 uint32_t tmpsmcr = 0;
3831
3832 /* Process Locked */
3833 __HAL_LOCK(htim);
3834
3835 htim->State = HAL_TIM_STATE_BUSY;
3836
3837 /* Check the parameters */
3838 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
3839 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
3840 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
3841 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
3842
3843 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
3844 tmpsmcr = htim->Instance->SMCR;
3845 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
3846 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
3847 htim->Instance->SMCR = tmpsmcr;
3848
3849 switch (sClockSourceConfig->ClockSource)
3850 {
3851 case TIM_CLOCKSOURCE_INTERNAL:
3852 {
3853 assert_param(IS_TIM_INSTANCE(htim->Instance));
3854 /* Disable slave mode to clock the prescaler directly with the internal clock */
3855 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3856 }
3857 break;
3858
3859 case TIM_CLOCKSOURCE_ETRMODE1:
3860 {
3861 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
3862 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
3863
3864 /* Configure the ETR Clock source */
3865 TIM_ETR_SetConfig(htim->Instance,
3866 sClockSourceConfig->ClockPrescaler,
3867 sClockSourceConfig->ClockPolarity,
3868 sClockSourceConfig->ClockFilter);
3869 /* Get the TIMx SMCR register value */
3870 tmpsmcr = htim->Instance->SMCR;
3871 /* Reset the SMS and TS Bits */
3872 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
3873 /* Select the External clock mode1 and the ETRF trigger */
3874 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
3875 /* Write to TIMx SMCR */
3876 htim->Instance->SMCR = tmpsmcr;
3877 }
3878 break;
3879
3880 case TIM_CLOCKSOURCE_ETRMODE2:
3881 {
3882 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
3883 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
3884
3885 /* Configure the ETR Clock source */
3886 TIM_ETR_SetConfig(htim->Instance,
3887 sClockSourceConfig->ClockPrescaler,
3888 sClockSourceConfig->ClockPolarity,
3889 sClockSourceConfig->ClockFilter);
3890 /* Enable the External clock mode2 */
3891 htim->Instance->SMCR |= TIM_SMCR_ECE;
3892 }
3893 break;
3894
3895 case TIM_CLOCKSOURCE_TI1:
3896 {
3897 /* Check whether or not the timer instance supports external clock mode 1 */
3898 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
3899
3900 TIM_TI1_ConfigInputStage(htim->Instance,
3901 sClockSourceConfig->ClockPolarity,
3902 sClockSourceConfig->ClockFilter);
3903 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
3904 }
3905 break;
3906 case TIM_CLOCKSOURCE_TI2:
3907 {
3908 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
3909 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
3910
3911 TIM_TI2_ConfigInputStage(htim->Instance,
3912 sClockSourceConfig->ClockPolarity,
3913 sClockSourceConfig->ClockFilter);
3914 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
3915 }
3916 break;
3917 case TIM_CLOCKSOURCE_TI1ED:
3918 {
3919 /* Check whether or not the timer instance supports external clock mode 1 */
3920 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
3921
3922 TIM_TI1_ConfigInputStage(htim->Instance,
3923 sClockSourceConfig->ClockPolarity,
3924 sClockSourceConfig->ClockFilter);
3925 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
3926 }
3927 break;
3928 case TIM_CLOCKSOURCE_ITR0:
3929 {
3930 /* Check whether or not the timer instance supports external clock mode 1 */
3931 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
3932
3933 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
3934 }
3935 break;
3936 case TIM_CLOCKSOURCE_ITR1:
3937 {
3938 /* Check whether or not the timer instance supports external clock mode 1 */
3939 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
3940
3941 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
3942 }
3943 break;
3944 case TIM_CLOCKSOURCE_ITR2:
3945 {
3946 /* Check whether or not the timer instance supports external clock mode 1 */
3947 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
3948
3949 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
3950 }
3951 break;
3952 case TIM_CLOCKSOURCE_ITR3:
3953 {
3954 /* Check whether or not the timer instance supports external clock mode 1 */
3955 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
3956
3957 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
3958 }
3959 break;
3960
3961 default:
3962 break;
3963 }
3964 htim->State = HAL_TIM_STATE_READY;
3965
3966 __HAL_UNLOCK(htim);
3967
3968 return HAL_OK;
3969 }
3970
3971 /**
3972 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
3973 * or a XOR combination between CH1_input, CH2_input & CH3_input
3974 * @param htim: TIM handle.
3975 * @param TI1_Selection: Indicate whether or not channel 1 is connected to the
3976 * output of a XOR gate.
3977 * This parameter can be one of the following values:
3978 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
3979 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
3980 * pins are connected to the TI1 input (XOR combination)
3981 * @retval HAL status
3982 */
3983 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
3984 {
3985 uint32_t tmpcr2 = 0;
3986
3987 /* Check the parameters */
3988 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
3989 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
3990
3991 /* Get the TIMx CR2 register value */
3992 tmpcr2 = htim->Instance->CR2;
3993
3994 /* Reset the TI1 selection */
3995 tmpcr2 &= ~TIM_CR2_TI1S;
3996
3997 /* Set the the TI1 selection */
3998 tmpcr2 |= TI1_Selection;
3999
4000 /* Write to TIMxCR2 */
4001 htim->Instance->CR2 = tmpcr2;
4002
4003 return HAL_OK;
4004 }
4005
4006 /**
4007 * @brief Configures the TIM in Slave mode
4008 * @param htim: TIM handle.
4009 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
4010 * contains the selected trigger (internal trigger input, filtered
4011 * timer input or external trigger input) and the ) and the Slave
4012 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
4013 * @retval HAL status
4014 */
4015 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
4016 {
4017 uint32_t tmpsmcr = 0;
4018 uint32_t tmpccmr1 = 0;
4019 uint32_t tmpccer = 0;
4020
4021 /* Check the parameters */
4022 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
4023 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
4024 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
4025
4026 __HAL_LOCK(htim);
4027
4028 htim->State = HAL_TIM_STATE_BUSY;
4029
4030 /* Get the TIMx SMCR register value */
4031 tmpsmcr = htim->Instance->SMCR;
4032
4033 /* Reset the Trigger Selection Bits */
4034 tmpsmcr &= ~TIM_SMCR_TS;
4035 /* Set the Input Trigger source */
4036 tmpsmcr |= sSlaveConfig->InputTrigger;
4037
4038 /* Reset the slave mode Bits */
4039 tmpsmcr &= ~TIM_SMCR_SMS;
4040 /* Set the slave mode */
4041 tmpsmcr |= sSlaveConfig->SlaveMode;
4042
4043 /* Write to TIMx SMCR */
4044 htim->Instance->SMCR = tmpsmcr;
4045
4046 /* Configure the trigger prescaler, filter, and polarity */
4047 switch (sSlaveConfig->InputTrigger)
4048 {
4049 case TIM_TS_ETRF:
4050 {
4051 /* Check the parameters */
4052 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
4053 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
4054 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
4055 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
4056 /* Configure the ETR Trigger source */
4057 TIM_ETR_SetConfig(htim->Instance,
4058 sSlaveConfig->TriggerPrescaler,
4059 sSlaveConfig->TriggerPolarity,
4060 sSlaveConfig->TriggerFilter);
4061 }
4062 break;
4063
4064 case TIM_TS_TI1F_ED:
4065 {
4066 /* Check the parameters */
4067 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4068 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
4069 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
4070
4071 /* Disable the Channel 1: Reset the CC1E Bit */
4072 tmpccer = htim->Instance->CCER;
4073 htim->Instance->CCER &= ~TIM_CCER_CC1E;
4074 tmpccmr1 = htim->Instance->CCMR1;
4075
4076 /* Set the filter */
4077 tmpccmr1 &= ~TIM_CCMR1_IC1F;
4078 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
4079
4080 /* Write to TIMx CCMR1 and CCER registers */
4081 htim->Instance->CCMR1 = tmpccmr1;
4082 htim->Instance->CCER = tmpccer;
4083
4084 }
4085 break;
4086
4087 case TIM_TS_TI1FP1:
4088 {
4089 /* Check the parameters */
4090 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4091 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
4092 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
4093
4094 /* Configure TI1 Filter and Polarity */
4095 TIM_TI1_ConfigInputStage(htim->Instance,
4096 sSlaveConfig->TriggerPolarity,
4097 sSlaveConfig->TriggerFilter);
4098 }
4099 break;
4100
4101 case TIM_TS_TI2FP2:
4102 {
4103 /* Check the parameters */
4104 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4105 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
4106 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
4107
4108 /* Configure TI2 Filter and Polarity */
4109 TIM_TI2_ConfigInputStage(htim->Instance,
4110 sSlaveConfig->TriggerPolarity,
4111 sSlaveConfig->TriggerFilter);
4112 }
4113 break;
4114
4115 case TIM_TS_ITR0:
4116 {
4117 /* Check the parameter */
4118 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4119 }
4120 break;
4121
4122 case TIM_TS_ITR1:
4123 {
4124 /* Check the parameter */
4125 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4126 }
4127 break;
4128
4129 case TIM_TS_ITR2:
4130 {
4131 /* Check the parameter */
4132 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4133 }
4134 break;
4135
4136 case TIM_TS_ITR3:
4137 {
4138 /* Check the parameter */
4139 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4140 }
4141 break;
4142
4143 default:
4144 break;
4145 }
4146
4147 htim->State = HAL_TIM_STATE_READY;
4148
4149 __HAL_UNLOCK(htim);
4150
4151 return HAL_OK;
4152 }
4153
4154 /**
4155 * @brief Read the captured value from Capture Compare unit
4156 * @param htim: TIM handle.
4157 * @param Channel : TIM Channels to be enabled
4158 * This parameter can be one of the following values:
4159 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4160 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4161 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4162 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4163 * @retval Captured value
4164 */
4165 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
4166 {
4167 uint32_t tmpreg = 0;
4168
4169 __HAL_LOCK(htim);
4170
4171 switch (Channel)
4172 {
4173 case TIM_CHANNEL_1:
4174 {
4175 /* Check the parameters */
4176 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4177
4178 /* Return the capture 1 value */
4179 tmpreg = htim->Instance->CCR1;
4180
4181 break;
4182 }
4183 case TIM_CHANNEL_2:
4184 {
4185 /* Check the parameters */
4186 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4187
4188 /* Return the capture 2 value */
4189 tmpreg = htim->Instance->CCR2;
4190
4191 break;
4192 }
4193
4194 case TIM_CHANNEL_3:
4195 {
4196 /* Check the parameters */
4197 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4198
4199 /* Return the capture 3 value */
4200 tmpreg = htim->Instance->CCR3;
4201
4202 break;
4203 }
4204
4205 case TIM_CHANNEL_4:
4206 {
4207 /* Check the parameters */
4208 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4209
4210 /* Return the capture 4 value */
4211 tmpreg = htim->Instance->CCR4;
4212
4213 break;
4214 }
4215
4216 default:
4217 break;
4218 }
4219
4220 __HAL_UNLOCK(htim);
4221 return tmpreg;
4222 }
4223
4224 /**
4225 * @}
4226 */
4227
4228 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
4229 * @brief TIM Callbacks functions
4230 *
4231 @verbatim
4232 ==============================================================================
4233 ##### TIM Callbacks functions #####
4234 ==============================================================================
4235 [..]
4236 This section provides TIM callback functions:
4237 (+) Timer Period elapsed callback
4238 (+) Timer Output Compare callback
4239 (+) Timer Input capture callback
4240 (+) Timer Trigger callback
4241 (+) Timer Error callback
4242
4243 @endverbatim
4244 * @{
4245 */
4246
4247 /**
4248 * @brief Period elapsed callback in non blocking mode
4249 * @param htim : TIM handle
4250 * @retval None
4251 */
4252 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
4253 {
4254 /* NOTE : This function Should not be modified, when the callback is needed,
4255 the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
4256 */
4257
4258 }
4259 /**
4260 * @brief Output Compare callback in non blocking mode
4261 * @param htim : TIM OC handle
4262 * @retval None
4263 */
4264 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
4265 {
4266 /* NOTE : This function Should not be modified, when the callback is needed,
4267 the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
4268 */
4269 }
4270 /**
4271 * @brief Input Capture callback in non blocking mode
4272 * @param htim : TIM IC handle
4273 * @retval None
4274 */
4275 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
4276 {
4277 /* NOTE : This function Should not be modified, when the callback is needed,
4278 the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
4279 */
4280 }
4281
4282 /**
4283 * @brief PWM Pulse finished callback in non blocking mode
4284 * @param htim : TIM handle
4285 * @retval None
4286 */
4287 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
4288 {
4289 /* NOTE : This function Should not be modified, when the callback is needed,
4290 the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
4291 */
4292 }
4293
4294 /**
4295 * @brief Hall Trigger detection callback in non blocking mode
4296 * @param htim : TIM handle
4297 * @retval None
4298 */
4299 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
4300 {
4301 /* NOTE : This function Should not be modified, when the callback is needed,
4302 the HAL_TIM_TriggerCallback could be implemented in the user file
4303 */
4304 }
4305
4306 /**
4307 * @brief Timer error callback in non blocking mode
4308 * @param htim : TIM handle
4309 * @retval None
4310 */
4311 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
4312 {
4313 /* NOTE : This function Should not be modified, when the callback is needed,
4314 the HAL_TIM_ErrorCallback could be implemented in the user file
4315 */
4316 }
4317
4318 /**
4319 * @}
4320 */
4321
4322 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
4323 * @brief Peripheral State functions
4324 *
4325 @verbatim
4326 ==============================================================================
4327 ##### Peripheral State functions #####
4328 ==============================================================================
4329 [..]
4330 This subsection permit to get in run-time the status of the peripheral
4331 and the data flow.
4332
4333 @endverbatim
4334 * @{
4335 */
4336
4337 /**
4338 * @brief Return the TIM Base state
4339 * @param htim: TIM Base handle
4340 * @retval HAL state
4341 */
4342 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
4343 {
4344 return htim->State;
4345 }
4346
4347 /**
4348 * @brief Return the TIM OC state
4349 * @param htim: TIM Ouput Compare handle
4350 * @retval HAL state
4351 */
4352 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
4353 {
4354 return htim->State;
4355 }
4356
4357 /**
4358 * @brief Return the TIM PWM state
4359 * @param htim: TIM handle
4360 * @retval HAL state
4361 */
4362 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
4363 {
4364 return htim->State;
4365 }
4366
4367 /**
4368 * @brief Return the TIM Input Capture state
4369 * @param htim: TIM IC handle
4370 * @retval HAL state
4371 */
4372 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
4373 {
4374 return htim->State;
4375 }
4376
4377 /**
4378 * @brief Return the TIM One Pulse Mode state
4379 * @param htim: TIM OPM handle
4380 * @retval HAL state
4381 */
4382 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
4383 {
4384 return htim->State;
4385 }
4386
4387 /**
4388 * @brief Return the TIM Encoder Mode state
4389 * @param htim: TIM Encoder handle
4390 * @retval HAL state
4391 */
4392 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
4393 {
4394 return htim->State;
4395 }
4396
4397 /**
4398 * @}
4399 */
4400
4401 /**
4402 * @brief TIM DMA error callback
4403 * @param hdma : pointer to DMA handle.
4404 * @retval None
4405 */
4406 void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma)
4407 {
4408 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4409
4410 htim->State= HAL_TIM_STATE_READY;
4411
4412 HAL_TIM_ErrorCallback(htim);
4413 }
4414
4415 /**
4416 * @brief TIM DMA Delay Pulse complete callback.
4417 * @param hdma : pointer to DMA handle.
4418 * @retval None
4419 */
4420 void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
4421 {
4422 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4423
4424 htim->State= HAL_TIM_STATE_READY;
4425
4426 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
4427 {
4428 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
4429 }
4430 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
4431 {
4432 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
4433 }
4434 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
4435 {
4436 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
4437 }
4438 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
4439 {
4440 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
4441 }
4442
4443 HAL_TIM_PWM_PulseFinishedCallback(htim);
4444
4445 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
4446 }
4447 /**
4448 * @brief TIM DMA Capture complete callback.
4449 * @param hdma : pointer to DMA handle.
4450 * @retval None
4451 */
4452 void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
4453 {
4454 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4455
4456 htim->State= HAL_TIM_STATE_READY;
4457
4458 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
4459 {
4460 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
4461 }
4462 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
4463 {
4464 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
4465 }
4466 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
4467 {
4468 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
4469 }
4470 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
4471 {
4472 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
4473 }
4474
4475 HAL_TIM_IC_CaptureCallback(htim);
4476
4477 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
4478 }
4479
4480 /**
4481 * @brief TIM DMA Period Elapse complete callback.
4482 * @param hdma : pointer to DMA handle.
4483 * @retval None
4484 */
4485 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
4486 {
4487 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4488
4489 htim->State= HAL_TIM_STATE_READY;
4490
4491 HAL_TIM_PeriodElapsedCallback(htim);
4492 }
4493
4494 /**
4495 * @brief TIM DMA Trigger callback.
4496 * @param hdma : pointer to DMA handle.
4497 * @retval None
4498 */
4499 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
4500 {
4501 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4502
4503 htim->State= HAL_TIM_STATE_READY;
4504
4505 HAL_TIM_TriggerCallback(htim);
4506 }
4507
4508 /**
4509 * @brief Time Base configuration
4510 * @param TIMx: TIM periheral
4511 * @param Structure: TIM Base configuration structure
4512 * @retval None
4513 */
4514 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
4515 {
4516 uint32_t tmpcr1 = 0;
4517 tmpcr1 = TIMx->CR1;
4518
4519 /* Set TIM Time Base Unit parameters ---------------------------------------*/
4520 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
4521 {
4522 /* Select the Counter Mode */
4523 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
4524 tmpcr1 |= Structure->CounterMode;
4525 }
4526
4527 if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
4528 {
4529 /* Set the clock division */
4530 tmpcr1 &= ~TIM_CR1_CKD;
4531 tmpcr1 |= (uint32_t)Structure->ClockDivision;
4532 }
4533
4534 TIMx->CR1 = tmpcr1;
4535
4536 /* Set the Autoreload value */
4537 TIMx->ARR = (uint32_t)Structure->Period ;
4538
4539 /* Set the Prescaler value */
4540 TIMx->PSC = (uint32_t)Structure->Prescaler;
4541
4542 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
4543 {
4544 /* Set the Repetition Counter value */
4545 TIMx->RCR = Structure->RepetitionCounter;
4546 }
4547
4548 /* Generate an update event to reload the Prescaler
4549 and the repetition counter(only for TIM1 and TIM8) value immediatly */
4550 TIMx->EGR = TIM_EGR_UG;
4551 }
4552
4553 /**
4554 * @brief Time Ouput Compare 1 configuration
4555 * @param TIMx to select the TIM peripheral
4556 * @param OC_Config: The ouput configuration structure
4557 * @retval None
4558 */
4559 void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4560 {
4561 uint32_t tmpccmrx = 0;
4562 uint32_t tmpccer = 0;
4563 uint32_t tmpcr2 = 0;
4564
4565 /* Disable the Channel 1: Reset the CC1E Bit */
4566 TIMx->CCER &= ~TIM_CCER_CC1E;
4567
4568 /* Get the TIMx CCER register value */
4569 tmpccer = TIMx->CCER;
4570 /* Get the TIMx CR2 register value */
4571 tmpcr2 = TIMx->CR2;
4572
4573 /* Get the TIMx CCMR1 register value */
4574 tmpccmrx = TIMx->CCMR1;
4575
4576 /* Reset the Output Compare Mode Bits */
4577 tmpccmrx &= ~TIM_CCMR1_OC1M;
4578 tmpccmrx &= ~TIM_CCMR1_CC1S;
4579 /* Select the Output Compare Mode */
4580 tmpccmrx |= OC_Config->OCMode;
4581
4582 /* Reset the Output Polarity level */
4583 tmpccer &= ~TIM_CCER_CC1P;
4584 /* Set the Output Compare Polarity */
4585 tmpccer |= OC_Config->OCPolarity;
4586
4587 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
4588 {
4589 /* Check parameters */
4590 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
4591
4592 /* Reset the Output N Polarity level */
4593 tmpccer &= ~TIM_CCER_CC1NP;
4594 /* Set the Output N Polarity */
4595 tmpccer |= OC_Config->OCNPolarity;
4596 /* Reset the Output N State */
4597 tmpccer &= ~TIM_CCER_CC1NE;
4598 }
4599
4600 if(IS_TIM_BREAK_INSTANCE(TIMx))
4601 {
4602 /* Check parameters */
4603 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
4604 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
4605
4606 /* Reset the Output Compare and Output Compare N IDLE State */
4607 tmpcr2 &= ~TIM_CR2_OIS1;
4608 tmpcr2 &= ~TIM_CR2_OIS1N;
4609 /* Set the Output Idle state */
4610 tmpcr2 |= OC_Config->OCIdleState;
4611 /* Set the Output N Idle state */
4612 tmpcr2 |= OC_Config->OCNIdleState;
4613 }
4614 /* Write to TIMx CR2 */
4615 TIMx->CR2 = tmpcr2;
4616
4617 /* Write to TIMx CCMR1 */
4618 TIMx->CCMR1 = tmpccmrx;
4619
4620 /* Set the Capture Compare Register value */
4621 TIMx->CCR1 = OC_Config->Pulse;
4622
4623 /* Write to TIMx CCER */
4624 TIMx->CCER = tmpccer;
4625 }
4626
4627 /**
4628 * @brief Time Ouput Compare 2 configuration
4629 * @param TIMx to select the TIM peripheral
4630 * @param OC_Config: The ouput configuration structure
4631 * @retval None
4632 */
4633 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4634 {
4635 uint32_t tmpccmrx = 0;
4636 uint32_t tmpccer = 0;
4637 uint32_t tmpcr2 = 0;
4638
4639 /* Disable the Channel 2: Reset the CC2E Bit */
4640 TIMx->CCER &= ~TIM_CCER_CC2E;
4641
4642 /* Get the TIMx CCER register value */
4643 tmpccer = TIMx->CCER;
4644 /* Get the TIMx CR2 register value */
4645 tmpcr2 = TIMx->CR2;
4646
4647 /* Get the TIMx CCMR1 register value */
4648 tmpccmrx = TIMx->CCMR1;
4649
4650 /* Reset the Output Compare mode and Capture/Compare selection Bits */
4651 tmpccmrx &= ~TIM_CCMR1_OC2M;
4652 tmpccmrx &= ~TIM_CCMR1_CC2S;
4653
4654 /* Select the Output Compare Mode */
4655 tmpccmrx |= (OC_Config->OCMode << 8);
4656
4657 /* Reset the Output Polarity level */
4658 tmpccer &= ~TIM_CCER_CC2P;
4659 /* Set the Output Compare Polarity */
4660 tmpccer |= (OC_Config->OCPolarity << 4);
4661
4662 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
4663 {
4664 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
4665 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
4666 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
4667
4668 /* Reset the Output N Polarity level */
4669 tmpccer &= ~TIM_CCER_CC2NP;
4670 /* Set the Output N Polarity */
4671 tmpccer |= (OC_Config->OCNPolarity << 4);
4672 /* Reset the Output N State */
4673 tmpccer &= ~TIM_CCER_CC2NE;
4674
4675 }
4676
4677 if(IS_TIM_BREAK_INSTANCE(TIMx))
4678 {
4679 /* Check parameters */
4680 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
4681 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
4682
4683 /* Reset the Output Compare and Output Compare N IDLE State */
4684 tmpcr2 &= ~TIM_CR2_OIS2;
4685 tmpcr2 &= ~TIM_CR2_OIS2N;
4686 /* Set the Output Idle state */
4687 tmpcr2 |= (OC_Config->OCIdleState << 2);
4688 /* Set the Output N Idle state */
4689 tmpcr2 |= (OC_Config->OCNIdleState << 2);
4690 }
4691
4692 /* Write to TIMx CR2 */
4693 TIMx->CR2 = tmpcr2;
4694
4695 /* Write to TIMx CCMR1 */
4696 TIMx->CCMR1 = tmpccmrx;
4697
4698 /* Set the Capture Compare Register value */
4699 TIMx->CCR2 = OC_Config->Pulse;
4700
4701 /* Write to TIMx CCER */
4702 TIMx->CCER = tmpccer;
4703 }
4704
4705 /**
4706 * @brief Time Ouput Compare 3 configuration
4707 * @param TIMx to select the TIM peripheral
4708 * @param OC_Config: The ouput configuration structure
4709 * @retval None
4710 */
4711 void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4712 {
4713 uint32_t tmpccmrx = 0;
4714 uint32_t tmpccer = 0;
4715 uint32_t tmpcr2 = 0;
4716
4717 /* Disable the Channel 3: Reset the CC2E Bit */
4718 TIMx->CCER &= ~TIM_CCER_CC3E;
4719
4720 /* Get the TIMx CCER register value */
4721 tmpccer = TIMx->CCER;
4722 /* Get the TIMx CR2 register value */
4723 tmpcr2 = TIMx->CR2;
4724
4725 /* Get the TIMx CCMR2 register value */
4726 tmpccmrx = TIMx->CCMR2;
4727
4728 /* Reset the Output Compare mode and Capture/Compare selection Bits */
4729 tmpccmrx &= ~TIM_CCMR2_OC3M;
4730 tmpccmrx &= ~TIM_CCMR2_CC3S;
4731 /* Select the Output Compare Mode */
4732 tmpccmrx |= OC_Config->OCMode;
4733
4734 /* Reset the Output Polarity level */
4735 tmpccer &= ~TIM_CCER_CC3P;
4736 /* Set the Output Compare Polarity */
4737 tmpccer |= (OC_Config->OCPolarity << 8);
4738
4739 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
4740 {
4741 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
4742 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
4743 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
4744
4745 /* Reset the Output N Polarity level */
4746 tmpccer &= ~TIM_CCER_CC3NP;
4747 /* Set the Output N Polarity */
4748 tmpccer |= (OC_Config->OCNPolarity << 8);
4749 /* Reset the Output N State */
4750 tmpccer &= ~TIM_CCER_CC3NE;
4751 }
4752
4753 if(IS_TIM_BREAK_INSTANCE(TIMx))
4754 {
4755 /* Check parameters */
4756 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
4757 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
4758
4759 /* Reset the Output Compare and Output Compare N IDLE State */
4760 tmpcr2 &= ~TIM_CR2_OIS3;
4761 tmpcr2 &= ~TIM_CR2_OIS3N;
4762 /* Set the Output Idle state */
4763 tmpcr2 |= (OC_Config->OCIdleState << 4);
4764 /* Set the Output N Idle state */
4765 tmpcr2 |= (OC_Config->OCNIdleState << 4);
4766 }
4767
4768 /* Write to TIMx CR2 */
4769 TIMx->CR2 = tmpcr2;
4770
4771 /* Write to TIMx CCMR2 */
4772 TIMx->CCMR2 = tmpccmrx;
4773
4774 /* Set the Capture Compare Register value */
4775 TIMx->CCR3 = OC_Config->Pulse;
4776
4777 /* Write to TIMx CCER */
4778 TIMx->CCER = tmpccer;
4779 }
4780
4781 /**
4782 * @brief Time Ouput Compare 4 configuration
4783 * @param TIMx to select the TIM peripheral
4784 * @param OC_Config: The ouput configuration structure
4785 * @retval None
4786 */
4787 void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4788 {
4789 uint32_t tmpccmrx = 0;
4790 uint32_t tmpccer = 0;
4791 uint32_t tmpcr2 = 0;
4792
4793 /* Disable the Channel 4: Reset the CC4E Bit */
4794 TIMx->CCER &= ~TIM_CCER_CC4E;
4795
4796 /* Get the TIMx CCER register value */
4797 tmpccer = TIMx->CCER;
4798 /* Get the TIMx CR2 register value */
4799 tmpcr2 = TIMx->CR2;
4800
4801 /* Get the TIMx CCMR2 register value */
4802 tmpccmrx = TIMx->CCMR2;
4803
4804 /* Reset the Output Compare mode and Capture/Compare selection Bits */
4805 tmpccmrx &= ~TIM_CCMR2_OC4M;
4806 tmpccmrx &= ~TIM_CCMR2_CC4S;
4807
4808 /* Select the Output Compare Mode */
4809 tmpccmrx |= (OC_Config->OCMode << 8);
4810
4811 /* Reset the Output Polarity level */
4812 tmpccer &= ~TIM_CCER_CC4P;
4813 /* Set the Output Compare Polarity */
4814 tmpccer |= (OC_Config->OCPolarity << 12);
4815
4816 if(IS_TIM_BREAK_INSTANCE(TIMx))
4817 {
4818 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
4819
4820 /* Reset the Output Compare IDLE State */
4821 tmpcr2 &= ~TIM_CR2_OIS4;
4822 /* Set the Output Idle state */
4823 tmpcr2 |= (OC_Config->OCIdleState << 6);
4824 }
4825
4826 /* Write to TIMx CR2 */
4827 TIMx->CR2 = tmpcr2;
4828
4829 /* Write to TIMx CCMR2 */
4830 TIMx->CCMR2 = tmpccmrx;
4831
4832 /* Set the Capture Compare Register value */
4833 TIMx->CCR4 = OC_Config->Pulse;
4834
4835 /* Write to TIMx CCER */
4836 TIMx->CCER = tmpccer;
4837 }
4838
4839 /**
4840 * @brief Configure the TI1 as Input.
4841 * @param TIMx to select the TIM peripheral.
4842 * @param TIM_ICPolarity : The Input Polarity.
4843 * This parameter can be one of the following values:
4844 * @arg TIM_ICPolarity_Rising
4845 * @arg TIM_ICPolarity_Falling
4846 * @arg TIM_ICPolarity_BothEdge
4847 * @param TIM_ICSelection: specifies the input to be used.
4848 * This parameter can be one of the following values:
4849 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
4850 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
4851 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
4852 * @param TIM_ICFilter: Specifies the Input Capture Filter.
4853 * This parameter must be a value between 0x00 and 0x0F.
4854 * @retval None
4855 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
4856 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
4857 * protected against un-initialized filter and polarity values.
4858 */
4859 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
4860 uint32_t TIM_ICFilter)
4861 {
4862 uint32_t tmpccmr1 = 0;
4863 uint32_t tmpccer = 0;
4864
4865 /* Disable the Channel 1: Reset the CC1E Bit */
4866 TIMx->CCER &= ~TIM_CCER_CC1E;
4867 tmpccmr1 = TIMx->CCMR1;
4868 tmpccer = TIMx->CCER;
4869
4870 /* Select the Input */
4871 if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
4872 {
4873 tmpccmr1 &= ~TIM_CCMR1_CC1S;
4874 tmpccmr1 |= TIM_ICSelection;
4875 }
4876 else
4877 {
4878 tmpccmr1 |= TIM_CCMR1_CC1S_0;
4879 }
4880
4881 /* Set the filter */
4882 tmpccmr1 &= ~TIM_CCMR1_IC1F;
4883 tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
4884
4885 /* Select the Polarity and set the CC1E Bit */
4886 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
4887 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
4888
4889 /* Write to TIMx CCMR1 and CCER registers */
4890 TIMx->CCMR1 = tmpccmr1;
4891 TIMx->CCER = tmpccer;
4892 }
4893
4894 /**
4895 * @brief Configure the Polarity and Filter for TI1.
4896 * @param TIMx to select the TIM peripheral.
4897 * @param TIM_ICPolarity : The Input Polarity.
4898 * This parameter can be one of the following values:
4899 * @arg TIM_ICPolarity_Rising
4900 * @arg TIM_ICPolarity_Falling
4901 * @arg TIM_ICPolarity_BothEdge
4902 * @param TIM_ICFilter: Specifies the Input Capture Filter.
4903 * This parameter must be a value between 0x00 and 0x0F.
4904 * @retval None
4905 */
4906 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
4907 {
4908 uint32_t tmpccmr1 = 0;
4909 uint32_t tmpccer = 0;
4910
4911 /* Disable the Channel 1: Reset the CC1E Bit */
4912 tmpccer = TIMx->CCER;
4913 TIMx->CCER &= ~TIM_CCER_CC1E;
4914 tmpccmr1 = TIMx->CCMR1;
4915
4916 /* Set the filter */
4917 tmpccmr1 &= ~TIM_CCMR1_IC1F;
4918 tmpccmr1 |= (TIM_ICFilter << 4);
4919
4920 /* Select the Polarity and set the CC1E Bit */
4921 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
4922 tmpccer |= TIM_ICPolarity;
4923
4924 /* Write to TIMx CCMR1 and CCER registers */
4925 TIMx->CCMR1 = tmpccmr1;
4926 TIMx->CCER = tmpccer;
4927 }
4928
4929 /**
4930 * @brief Configure the TI2 as Input.
4931 * @param TIMx to select the TIM peripheral
4932 * @param TIM_ICPolarity : The Input Polarity.
4933 * This parameter can be one of the following values:
4934 * @arg TIM_ICPolarity_Rising
4935 * @arg TIM_ICPolarity_Falling
4936 * @arg TIM_ICPolarity_BothEdge
4937 * @param TIM_ICSelection: specifies the input to be used.
4938 * This parameter can be one of the following values:
4939 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
4940 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
4941 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
4942 * @param TIM_ICFilter: Specifies the Input Capture Filter.
4943 * This parameter must be a value between 0x00 and 0x0F.
4944 * @retval None
4945 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
4946 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
4947 * protected against un-initialized filter and polarity values.
4948 */
4949 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
4950 uint32_t TIM_ICFilter)
4951 {
4952 uint32_t tmpccmr1 = 0;
4953 uint32_t tmpccer = 0;
4954
4955 /* Disable the Channel 2: Reset the CC2E Bit */
4956 TIMx->CCER &= ~TIM_CCER_CC2E;
4957 tmpccmr1 = TIMx->CCMR1;
4958 tmpccer = TIMx->CCER;
4959
4960 /* Select the Input */
4961 tmpccmr1 &= ~TIM_CCMR1_CC2S;
4962 tmpccmr1 |= (TIM_ICSelection << 8);
4963
4964 /* Set the filter */
4965 tmpccmr1 &= ~TIM_CCMR1_IC2F;
4966 tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
4967
4968 /* Select the Polarity and set the CC2E Bit */
4969 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
4970 tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
4971
4972 /* Write to TIMx CCMR1 and CCER registers */
4973 TIMx->CCMR1 = tmpccmr1 ;
4974 TIMx->CCER = tmpccer;
4975 }
4976
4977 /**
4978 * @brief Configure the Polarity and Filter for TI2.
4979 * @param TIMx to select the TIM peripheral.
4980 * @param TIM_ICPolarity : The Input Polarity.
4981 * This parameter can be one of the following values:
4982 * @arg TIM_ICPolarity_Rising
4983 * @arg TIM_ICPolarity_Falling
4984 * @arg TIM_ICPolarity_BothEdge
4985 * @param TIM_ICFilter: Specifies the Input Capture Filter.
4986 * This parameter must be a value between 0x00 and 0x0F.
4987 * @retval None
4988 */
4989 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
4990 {
4991 uint32_t tmpccmr1 = 0;
4992 uint32_t tmpccer = 0;
4993
4994 /* Disable the Channel 2: Reset the CC2E Bit */
4995 TIMx->CCER &= ~TIM_CCER_CC2E;
4996 tmpccmr1 = TIMx->CCMR1;
4997 tmpccer = TIMx->CCER;
4998
4999 /* Set the filter */
5000 tmpccmr1 &= ~TIM_CCMR1_IC2F;
5001 tmpccmr1 |= (TIM_ICFilter << 12);
5002
5003 /* Select the Polarity and set the CC2E Bit */
5004 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
5005 tmpccer |= (TIM_ICPolarity << 4);
5006
5007 /* Write to TIMx CCMR1 and CCER registers */
5008 TIMx->CCMR1 = tmpccmr1 ;
5009 TIMx->CCER = tmpccer;
5010 }
5011
5012 /**
5013 * @brief Configure the TI3 as Input.
5014 * @param TIMx to select the TIM peripheral
5015 * @param TIM_ICPolarity : The Input Polarity.
5016 * This parameter can be one of the following values:
5017 * @arg TIM_ICPolarity_Rising
5018 * @arg TIM_ICPolarity_Falling
5019 * @arg TIM_ICPolarity_BothEdge
5020 * @param TIM_ICSelection: specifies the input to be used.
5021 * This parameter can be one of the following values:
5022 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
5023 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
5024 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
5025 * @param TIM_ICFilter: Specifies the Input Capture Filter.
5026 * This parameter must be a value between 0x00 and 0x0F.
5027 * @retval None
5028 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
5029 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
5030 * protected against un-initialized filter and polarity values.
5031 */
5032 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
5033 uint32_t TIM_ICFilter)
5034 {
5035 uint32_t tmpccmr2 = 0;
5036 uint32_t tmpccer = 0;
5037
5038 /* Disable the Channel 3: Reset the CC3E Bit */
5039 TIMx->CCER &= ~TIM_CCER_CC3E;
5040 tmpccmr2 = TIMx->CCMR2;
5041 tmpccer = TIMx->CCER;
5042
5043 /* Select the Input */
5044 tmpccmr2 &= ~TIM_CCMR2_CC3S;
5045 tmpccmr2 |= TIM_ICSelection;
5046
5047 /* Set the filter */
5048 tmpccmr2 &= ~TIM_CCMR2_IC3F;
5049 tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
5050
5051 /* Select the Polarity and set the CC3E Bit */
5052 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
5053 tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
5054
5055 /* Write to TIMx CCMR2 and CCER registers */
5056 TIMx->CCMR2 = tmpccmr2;
5057 TIMx->CCER = tmpccer;
5058 }
5059
5060 /**
5061 * @brief Configure the TI4 as Input.
5062 * @param TIMx to select the TIM peripheral
5063 * @param TIM_ICPolarity : The Input Polarity.
5064 * This parameter can be one of the following values:
5065 * @arg TIM_ICPolarity_Rising
5066 * @arg TIM_ICPolarity_Falling
5067 * @arg TIM_ICPolarity_BothEdge
5068 * @param TIM_ICSelection: specifies the input to be used.
5069 * This parameter can be one of the following values:
5070 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
5071 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
5072 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
5073 * @param TIM_ICFilter: Specifies the Input Capture Filter.
5074 * This parameter must be a value between 0x00 and 0x0F.
5075 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
5076 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
5077 * protected against un-initialized filter and polarity values.
5078 * @retval None
5079 */
5080 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
5081 uint32_t TIM_ICFilter)
5082 {
5083 uint32_t tmpccmr2 = 0;
5084 uint32_t tmpccer = 0;
5085
5086 /* Disable the Channel 4: Reset the CC4E Bit */
5087 TIMx->CCER &= ~TIM_CCER_CC4E;
5088 tmpccmr2 = TIMx->CCMR2;
5089 tmpccer = TIMx->CCER;
5090
5091 /* Select the Input */
5092 tmpccmr2 &= ~TIM_CCMR2_CC4S;
5093 tmpccmr2 |= (TIM_ICSelection << 8);
5094
5095 /* Set the filter */
5096 tmpccmr2 &= ~TIM_CCMR2_IC4F;
5097 tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
5098
5099 /* Select the Polarity and set the CC4E Bit */
5100 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
5101 tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
5102
5103 /* Write to TIMx CCMR2 and CCER registers */
5104 TIMx->CCMR2 = tmpccmr2;
5105 TIMx->CCER = tmpccer ;
5106 }
5107
5108 /**
5109 * @brief Selects the Input Trigger source
5110 * @param TIMx to select the TIM peripheral
5111 * @param InputTriggerSource: The Input Trigger source.
5112 * This parameter can be one of the following values:
5113 * @arg TIM_TS_ITR0: Internal Trigger 0
5114 * @arg TIM_TS_ITR1: Internal Trigger 1
5115 * @arg TIM_TS_ITR2: Internal Trigger 2
5116 * @arg TIM_TS_ITR3: Internal Trigger 3
5117 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
5118 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
5119 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
5120 * @arg TIM_TS_ETRF: External Trigger input
5121 * @retval None
5122 */
5123 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
5124 {
5125 uint32_t tmpsmcr = 0;
5126
5127 /* Get the TIMx SMCR register value */
5128 tmpsmcr = TIMx->SMCR;
5129 /* Reset the TS Bits */
5130 tmpsmcr &= ~TIM_SMCR_TS;
5131 /* Set the Input Trigger source and the slave mode*/
5132 tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
5133 /* Write to TIMx SMCR */
5134 TIMx->SMCR = tmpsmcr;
5135 }
5136 /**
5137 * @brief Configures the TIMx External Trigger (ETR).
5138 * @param TIMx to select the TIM peripheral
5139 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
5140 * This parameter can be one of the following values:
5141 * @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
5142 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
5143 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
5144 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
5145 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
5146 * This parameter can be one of the following values:
5147 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
5148 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
5149 * @param ExtTRGFilter: External Trigger Filter.
5150 * This parameter must be a value between 0x00 and 0x0F
5151 * @retval None
5152 */
5153 void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
5154 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
5155 {
5156 uint32_t tmpsmcr = 0;
5157
5158 tmpsmcr = TIMx->SMCR;
5159
5160 /* Reset the ETR Bits */
5161 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
5162
5163 /* Set the Prescaler, the Filter value and the Polarity */
5164 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
5165
5166 /* Write to TIMx SMCR */
5167 TIMx->SMCR = tmpsmcr;
5168 }
5169
5170 /**
5171 * @brief Enables or disables the TIM Capture Compare Channel x.
5172 * @param TIMx to select the TIM peripheral
5173 * @param Channel: specifies the TIM Channel
5174 * This parameter can be one of the following values:
5175 * @arg TIM_Channel_1: TIM Channel 1
5176 * @arg TIM_Channel_2: TIM Channel 2
5177 * @arg TIM_Channel_3: TIM Channel 3
5178 * @arg TIM_Channel_4: TIM Channel 4
5179 * @param ChannelState: specifies the TIM Channel CCxE bit new state.
5180 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
5181 * @retval None
5182 */
5183 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
5184 {
5185 uint32_t tmp = 0;
5186
5187 /* Check the parameters */
5188 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
5189 assert_param(IS_TIM_CHANNELS(Channel));
5190
5191 tmp = TIM_CCER_CC1E << Channel;
5192
5193 /* Reset the CCxE Bit */
5194 TIMx->CCER &= ~tmp;
5195
5196 /* Set or reset the CCxE Bit */
5197 TIMx->CCER |= (uint32_t)(ChannelState << Channel);
5198 }
5199
5200
5201 /**
5202 * @}
5203 */
5204
5205 #endif /* HAL_TIM_MODULE_ENABLED */
5206 /**
5207 * @}
5208 */
5209
5210 /**
5211 * @}
5212 */
5213 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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