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[tmk_keyboard.git] / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_STM / TARGET_STM32F3 / stm32f3xx_hal_tim.h
1 /**
2 ******************************************************************************
3 * @file stm32f3xx_hal_tim.h
4 * @author MCD Application Team
5 * @version V1.1.0
6 * @date 12-Sept-2014
7 * @brief Header file of TIM HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F3xx_HAL_TIM_H
40 #define __STM32F3xx_HAL_TIM_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f3xx_hal_def.h"
48
49 /** @addtogroup STM32F3xx_HAL_Driver
50 * @{
51 */
52
53 /** @addtogroup TIM
54 * @{
55 */
56
57 /* Exported types ------------------------------------------------------------*/
58 /** @defgroup TIM_Exported_Types TIM Exported Types
59 * @{
60 */
61
62 /**
63 * @brief TIM Time base Configuration Structure definition
64 */
65 typedef struct
66 {
67 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
68 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
69
70 uint32_t CounterMode; /*!< Specifies the counter mode.
71 This parameter can be a value of @ref TIM_Counter_Mode */
72
73 uint32_t Period; /*!< Specifies the period value to be loaded into the active
74 Auto-Reload Register at the next update event.
75 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
76
77 uint32_t ClockDivision; /*!< Specifies the clock division.
78 This parameter can be a value of @ref TIM_ClockDivision */
79
80 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
81 reaches zero, an update event is generated and counting restarts
82 from the RCR value (N).
83 This means in PWM mode that (N+1) corresponds to:
84 - the number of PWM periods in edge-aligned mode
85 - the number of half PWM period in center-aligned mode
86 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
87 @note This parameter is valid only for TIM1 and TIM8. */
88 } TIM_Base_InitTypeDef;
89
90 /**
91 * @brief TIM Output Compare Configuration Structure definition
92 */
93 typedef struct
94 {
95 uint32_t OCMode; /*!< Specifies the TIM mode.
96 This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
97
98 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
99 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
100
101 uint32_t OCPolarity; /*!< Specifies the output polarity.
102 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
103
104 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
105 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
106 @note This parameter is valid only for TIM1 and TIM8. */
107
108 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
109 This parameter can be a value of @ref TIM_Output_Fast_State
110 @note This parameter is valid only in PWM1 and PWM2 mode. */
111
112
113 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
114 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
115 @note This parameter is valid only for TIM1 and TIM8. */
116
117 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
118 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
119 @note This parameter is valid only for TIM1 and TIM8. */
120 } TIM_OC_InitTypeDef;
121
122 /**
123 * @brief TIM One Pulse Mode Configuration Structure definition
124 */
125 typedef struct
126 {
127 uint32_t OCMode; /*!< Specifies the TIM mode.
128 This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
129
130 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
131 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
132
133 uint32_t OCPolarity; /*!< Specifies the output polarity.
134 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
135
136 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
137 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
138 @note This parameter is valid only for TIM1 and TIM8. */
139
140 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
141 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
142 @note This parameter is valid only for TIM1 and TIM8. */
143
144 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
145 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
146 @note This parameter is valid only for TIM1 and TIM8. */
147
148 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
149 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
150
151 uint32_t ICSelection; /*!< Specifies the input.
152 This parameter can be a value of @ref TIM_Input_Capture_Selection */
153
154 uint32_t ICFilter; /*!< Specifies the input capture filter.
155 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
156 } TIM_OnePulse_InitTypeDef;
157
158
159 /**
160 * @brief TIM Input Capture Configuration Structure definition
161 */
162 typedef struct
163 {
164 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
165 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
166
167 uint32_t ICSelection; /*!< Specifies the input.
168 This parameter can be a value of @ref TIM_Input_Capture_Selection */
169
170 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
171 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
172
173 uint32_t ICFilter; /*!< Specifies the input capture filter.
174 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
175 } TIM_IC_InitTypeDef;
176
177 /**
178 * @brief TIM Encoder Configuration Structure definition
179 */
180 typedef struct
181 {
182 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
183 This parameter can be a value of @ref TIM_Encoder_Mode */
184
185 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
186 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
187
188 uint32_t IC1Selection; /*!< Specifies the input.
189 This parameter can be a value of @ref TIM_Input_Capture_Selection */
190
191 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
192 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
193
194 uint32_t IC1Filter; /*!< Specifies the input capture filter.
195 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
196
197 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
198 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
199
200 uint32_t IC2Selection; /*!< Specifies the input.
201 This parameter can be a value of @ref TIM_Input_Capture_Selection */
202
203 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
204 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
205
206 uint32_t IC2Filter; /*!< Specifies the input capture filter.
207 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
208 } TIM_Encoder_InitTypeDef;
209
210
211 /**
212 * @brief Clock Configuration Handle Structure definition
213 */
214 typedef struct
215 {
216 uint32_t ClockSource; /*!< TIM clock sources
217 This parameter can be a value of @ref TIM_Clock_Source */
218 uint32_t ClockPolarity; /*!< TIM clock polarity
219 This parameter can be a value of @ref TIM_Clock_Polarity */
220 uint32_t ClockPrescaler; /*!< TIM clock prescaler
221 This parameter can be a value of @ref TIM_Clock_Prescaler */
222 uint32_t ClockFilter; /*!< TIM clock filter
223 This parameter can be a value of @ref TIM_Clock_Filter */
224 }TIM_ClockConfigTypeDef;
225
226 /**
227 * @brief Clear Input Configuration Handle Structure definition
228 */
229 typedef struct
230 {
231 uint32_t ClearInputState; /*!< TIM clear Input state
232 This parameter can be ENABLE or DISABLE */
233 uint32_t ClearInputSource; /*!< TIM clear Input sources
234 This parameter can be a value of @ref TIMEx_ClearInput_Source */
235 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
236 This parameter can be a value of @ref TIM_ClearInput_Polarity */
237 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
238 This parameter can be a value of @ref TIM_ClearInput_Prescaler */
239 uint32_t ClearInputFilter; /*!< TIM Clear Input filter
240 This parameter can be a value of @ref TIM_ClearInput_Filter */
241 }TIM_ClearInputConfigTypeDef;
242
243 /**
244 * @brief TIM Slave configuration Structure definition
245 */
246 typedef struct {
247 uint32_t SlaveMode; /*!< Slave mode selection
248 This parameter can be a value of @ref TIMEx_Slave_Mode */
249 uint32_t InputTrigger; /*!< Input Trigger source
250 This parameter can be a value of @ref TIM_Trigger_Selection */
251 uint32_t TriggerPolarity; /*!< Input Trigger polarity
252 This parameter can be a value of @ref TIM_Trigger_Polarity */
253 uint32_t TriggerPrescaler; /*!< Input trigger prescaler
254 This parameter can be a value of @ref TIM_Trigger_Prescaler */
255 uint32_t TriggerFilter; /*!< Input trigger filter
256 This parameter can be a value of @ref TIM_Trigger_Filter */
257
258 }TIM_SlaveConfigTypeDef;
259
260 /**
261 * @brief HAL State structures definition
262 */
263 typedef enum
264 {
265 HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */
266 HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
267 HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
268 HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
269 HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
270 }HAL_TIM_StateTypeDef;
271
272 /**
273 * @brief HAL Active channel structures definition
274 */
275 typedef enum
276 {
277 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */
278 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */
279 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */
280 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */
281 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
282 }HAL_TIM_ActiveChannel;
283
284 /**
285 * @brief TIM Time Base Handle Structure definition
286 */
287 typedef struct
288 {
289 TIM_TypeDef *Instance; /*!< Register base address */
290 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
291 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
292 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
293 This array is accessed by a @ref DMA_Handle_index */
294 HAL_LockTypeDef Lock; /*!< Locking object */
295 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
296 }TIM_HandleTypeDef;
297
298 /**
299 * @}
300 */
301
302 /* Exported constants --------------------------------------------------------*/
303 /** @defgroup TIM_Exported_Constants TIM Exported Constants
304 * @{
305 */
306
307 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
308 * @{
309 */
310 #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */
311 #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
312 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
313 /**
314 * @}
315 */
316
317 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
318 * @{
319 */
320 #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
321 #define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */
322 /**
323 * @}
324 */
325
326 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
327 * @{
328 */
329 #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */
330 #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
331 #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
332 #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
333 /**
334 * @}
335 */
336
337 /** @defgroup TIM_Counter_Mode TIM Counter Mode
338 * @{
339 */
340
341 #define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
342 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
343 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
344 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
345 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
346
347 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
348 ((MODE) == TIM_COUNTERMODE_DOWN) || \
349 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
350 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
351 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
352 /**
353 * @}
354 */
355
356 /** @defgroup TIM_ClockDivision TIM Clock Division
357 * @{
358 */
359
360 #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
361 #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
362 #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
363
364 #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
365 ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
366 ((DIV) == TIM_CLOCKDIVISION_DIV4))
367 /**
368 * @}
369 */
370
371 /** @defgroup TIM_Output_Compare_State TIM Output Compare State
372 * @{
373 */
374
375 #define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
376 #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
377
378 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
379 ((STATE) == TIM_OUTPUTSTATE_ENABLE))
380 /**
381 * @}
382 */
383 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
384 * @{
385 */
386 #define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
387 #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
388
389 #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
390 ((STATE) == TIM_OCFAST_ENABLE))
391 /**
392 * @}
393 */
394 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
395 * @{
396 */
397
398 #define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
399 #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
400
401 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
402 ((STATE) == TIM_OUTPUTNSTATE_ENABLE))
403 /**
404 * @}
405 */
406
407 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
408 * @{
409 */
410
411 #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
412 #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
413
414 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
415 ((POLARITY) == TIM_OCPOLARITY_LOW))
416 /**
417 * @}
418 */
419
420 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
421 * @{
422 */
423
424 #define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
425 #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
426
427 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
428 ((POLARITY) == TIM_OCNPOLARITY_LOW))
429 /**
430 * @}
431 */
432
433 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
434 * @{
435 */
436
437 #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
438 #define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
439 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
440 ((STATE) == TIM_OCIDLESTATE_RESET))
441 /**
442 * @}
443 */
444
445 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
446 * @{
447 */
448
449 #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
450 #define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
451 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
452 ((STATE) == TIM_OCNIDLESTATE_RESET))
453 /**
454 * @}
455 */
456
457
458
459 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
460 * @{
461 */
462
463 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
464 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
465 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
466
467 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
468 ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
469 ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
470 /**
471 * @}
472 */
473
474 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
475 * @{
476 */
477
478 #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
479 connected to IC1, IC2, IC3 or IC4, respectively */
480 #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
481 connected to IC2, IC1, IC4 or IC3, respectively */
482 #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
483
484 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
485 ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
486 ((SELECTION) == TIM_ICSELECTION_TRC))
487 /**
488 * @}
489 */
490
491 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
492 * @{
493 */
494
495 #define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */
496 #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
497 #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
498 #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
499
500 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
501 ((PRESCALER) == TIM_ICPSC_DIV2) || \
502 ((PRESCALER) == TIM_ICPSC_DIV4) || \
503 ((PRESCALER) == TIM_ICPSC_DIV8))
504 /**
505 * @}
506 */
507
508 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
509 * @{
510 */
511
512 #define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
513 #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
514 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
515 ((MODE) == TIM_OPMODE_REPETITIVE))
516 /**
517 * @}
518 */
519 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
520 * @{
521 */
522 #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
523 #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
524 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
525 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
526 ((MODE) == TIM_ENCODERMODE_TI2) || \
527 ((MODE) == TIM_ENCODERMODE_TI12))
528 /**
529 * @}
530 */
531 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition
532 * @{
533 */
534 #define TIM_IT_UPDATE (TIM_DIER_UIE)
535 #define TIM_IT_CC1 (TIM_DIER_CC1IE)
536 #define TIM_IT_CC2 (TIM_DIER_CC2IE)
537 #define TIM_IT_CC3 (TIM_DIER_CC3IE)
538 #define TIM_IT_CC4 (TIM_DIER_CC4IE)
539 #define TIM_IT_COM (TIM_DIER_COMIE)
540 #define TIM_IT_TRIGGER (TIM_DIER_TIE)
541 #define TIM_IT_BREAK (TIM_DIER_BIE)
542
543 #define IS_TIM_IT(IT) ((((IT) & 0xFFFFFF00) == 0x00000000) && ((IT) != 0x00000000))
544
545 #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_UPDATE) || \
546 ((IT) == TIM_IT_CC1) || \
547 ((IT) == TIM_IT_CC2) || \
548 ((IT) == TIM_IT_CC3) || \
549 ((IT) == TIM_IT_CC4) || \
550 ((IT) == TIM_IT_COM) || \
551 ((IT) == TIM_IT_TRIGGER) || \
552 ((IT) == TIM_IT_BREAK))
553 /**
554 * @}
555 */
556 #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
557 #define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
558
559 /** @defgroup TIM_DMA_sources TIM DMA Sources
560 * @{
561 */
562
563 #define TIM_DMA_UPDATE (TIM_DIER_UDE)
564 #define TIM_DMA_CC1 (TIM_DIER_CC1DE)
565 #define TIM_DMA_CC2 (TIM_DIER_CC2DE)
566 #define TIM_DMA_CC3 (TIM_DIER_CC3DE)
567 #define TIM_DMA_CC4 (TIM_DIER_CC4DE)
568 #define TIM_DMA_COM (TIM_DIER_COMDE)
569 #define TIM_DMA_TRIGGER (TIM_DIER_TDE)
570 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
571
572 /**
573 * @}
574 */
575
576 /** @defgroup TIM_Flag_definition TIM Flag Definition
577 * @{
578 */
579
580 #define TIM_FLAG_UPDATE (TIM_SR_UIF)
581 #define TIM_FLAG_CC1 (TIM_SR_CC1IF)
582 #define TIM_FLAG_CC2 (TIM_SR_CC2IF)
583 #define TIM_FLAG_CC3 (TIM_SR_CC3IF)
584 #define TIM_FLAG_CC4 (TIM_SR_CC4IF)
585 #define TIM_FLAG_COM (TIM_SR_COMIF)
586 #define TIM_FLAG_TRIGGER (TIM_SR_TIF)
587 #define TIM_FLAG_BREAK (TIM_SR_BIF)
588 #define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
589 #define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
590 #define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
591 #define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
592
593 #define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) || \
594 ((FLAG) == TIM_FLAG_CC1) || \
595 ((FLAG) == TIM_FLAG_CC2) || \
596 ((FLAG) == TIM_FLAG_CC3) || \
597 ((FLAG) == TIM_FLAG_CC4) || \
598 ((FLAG) == TIM_FLAG_COM) || \
599 ((FLAG) == TIM_FLAG_TRIGGER) || \
600 ((FLAG) == TIM_FLAG_BREAK) || \
601 ((FLAG) == TIM_FLAG_CC1OF) || \
602 ((FLAG) == TIM_FLAG_CC2OF) || \
603 ((FLAG) == TIM_FLAG_CC3OF) || \
604 ((FLAG) == TIM_FLAG_CC4OF))
605 /**
606 * @}
607 */
608
609 /** @defgroup TIM_Clock_Source TIM Clock Source
610 * @{
611 */
612 #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
613 #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
614 #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
615 #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
616 #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
617 #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
618 #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
619 #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
620 #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
621 #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
622
623 #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
624 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
625 ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
626 ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
627 ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
628 ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
629 ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
630 ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
631 ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
632 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
633 /**
634 * @}
635 */
636
637 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
638 * @{
639 */
640 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
641 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
642 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
643 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
644 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
645
646 #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
647 ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
648 ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
649 ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
650 ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
651 /**
652 * @}
653 */
654 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
655 * @{
656 */
657 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
658 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
659 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
660 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
661
662 #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
663 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
664 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
665 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
666 /**
667 * @}
668 */
669 /** @defgroup TIM_Clock_Filter TIM Clock Filter
670 * @{
671 */
672
673 #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
674 /**
675 * @}
676 */
677
678 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
679 * @{
680 */
681 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
682 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
683
684
685 #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
686 ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
687 /**
688 * @}
689 */
690
691 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
692 * @{
693 */
694 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
695 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
696 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
697 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
698 #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
699 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
700 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
701 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
702 /**
703 * @}
704 */
705
706 /** @defgroup TIM_ClearInput_Filter TIM Clear Input Filter
707 * @{
708 */
709
710 #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
711 /**
712 * @}
713 */
714
715 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM Off-state Selection for Run Mode
716 * @{
717 */
718 #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
719 #define TIM_OSSR_DISABLE ((uint32_t)0x0000)
720
721 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
722 ((STATE) == TIM_OSSR_DISABLE))
723 /**
724 * @}
725 */
726
727 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM Off-state Selection for Idle Mode
728 * @{
729 */
730 #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
731 #define TIM_OSSI_DISABLE ((uint32_t)0x0000)
732
733 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
734 ((STATE) == TIM_OSSI_DISABLE))
735 /**
736 * @}
737 */
738 /** @defgroup TIM_Lock_level TIM Lock Configuration
739 * @{
740 */
741 #define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
742 #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
743 #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
744 #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
745
746 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
747 ((LEVEL) == TIM_LOCKLEVEL_1) || \
748 ((LEVEL) == TIM_LOCKLEVEL_2) || \
749 ((LEVEL) == TIM_LOCKLEVEL_3))
750 /**
751 * @}
752 */
753 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
754 * @{
755 */
756 #define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
757 #define TIM_BREAK_DISABLE ((uint32_t)0x0000)
758
759 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
760 ((STATE) == TIM_BREAK_DISABLE))
761 /**
762 * @}
763 */
764 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity
765 * @{
766 */
767 #define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
768 #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
769
770 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
771 ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
772 /**
773 * @}
774 */
775 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
776 * @{
777 */
778 #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
779 #define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
780
781 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
782 ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
783 /**
784 * @}
785 */
786
787 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
788 * @{
789 */
790 #define TIM_TRGO_RESET ((uint32_t)0x0000)
791 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
792 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
793 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
794 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
795 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
796 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
797 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
798
799 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
800 ((SOURCE) == TIM_TRGO_ENABLE) || \
801 ((SOURCE) == TIM_TRGO_UPDATE) || \
802 ((SOURCE) == TIM_TRGO_OC1) || \
803 ((SOURCE) == TIM_TRGO_OC1REF) || \
804 ((SOURCE) == TIM_TRGO_OC2REF) || \
805 ((SOURCE) == TIM_TRGO_OC3REF) || \
806 ((SOURCE) == TIM_TRGO_OC4REF))
807
808
809 /**
810 * @}
811 */
812 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
813 * @{
814 */
815
816 #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
817 #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
818 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
819 ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
820 /**
821 * @}
822 */
823 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
824 * @{
825 */
826
827 #define TIM_TS_ITR0 ((uint32_t)0x0000)
828 #define TIM_TS_ITR1 ((uint32_t)0x0010)
829 #define TIM_TS_ITR2 ((uint32_t)0x0020)
830 #define TIM_TS_ITR3 ((uint32_t)0x0030)
831 #define TIM_TS_TI1F_ED ((uint32_t)0x0040)
832 #define TIM_TS_TI1FP1 ((uint32_t)0x0050)
833 #define TIM_TS_TI2FP2 ((uint32_t)0x0060)
834 #define TIM_TS_ETRF ((uint32_t)0x0070)
835 #define TIM_TS_NONE ((uint32_t)0xFFFF)
836 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
837 ((SELECTION) == TIM_TS_ITR1) || \
838 ((SELECTION) == TIM_TS_ITR2) || \
839 ((SELECTION) == TIM_TS_ITR3) || \
840 ((SELECTION) == TIM_TS_TI1F_ED) || \
841 ((SELECTION) == TIM_TS_TI1FP1) || \
842 ((SELECTION) == TIM_TS_TI2FP2) || \
843 ((SELECTION) == TIM_TS_ETRF))
844 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
845 ((SELECTION) == TIM_TS_ITR1) || \
846 ((SELECTION) == TIM_TS_ITR2) || \
847 ((SELECTION) == TIM_TS_ITR3))
848 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
849 ((SELECTION) == TIM_TS_ITR1) || \
850 ((SELECTION) == TIM_TS_ITR2) || \
851 ((SELECTION) == TIM_TS_ITR3) || \
852 ((SELECTION) == TIM_TS_NONE))
853 /**
854 * @}
855 */
856
857 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
858 * @{
859 */
860 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
861 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
862 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
863 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
864 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
865
866 #define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
867 ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
868 ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
869 ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
870 ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
871 /**
872 * @}
873 */
874
875 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
876 * @{
877 */
878 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
879 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
880 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
881 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
882
883 #define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
884 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
885 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
886 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
887 /**
888 * @}
889 */
890
891 /** @defgroup TIM_Trigger_Filter TIM Trigger Filter
892 * @{
893 */
894
895 #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
896 /**
897 * @}
898 */
899
900 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
901 * @{
902 */
903
904 #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
905 #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
906
907 #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
908 ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
909
910 /**
911 * @}
912 */
913
914 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
915 * @{
916 */
917
918 #define TIM_DMABurstLength_1Transfer (0x00000000)
919 #define TIM_DMABurstLength_2Transfers (0x00000100)
920 #define TIM_DMABurstLength_3Transfers (0x00000200)
921 #define TIM_DMABurstLength_4Transfers (0x00000300)
922 #define TIM_DMABurstLength_5Transfers (0x00000400)
923 #define TIM_DMABurstLength_6Transfers (0x00000500)
924 #define TIM_DMABurstLength_7Transfers (0x00000600)
925 #define TIM_DMABurstLength_8Transfers (0x00000700)
926 #define TIM_DMABurstLength_9Transfers (0x00000800)
927 #define TIM_DMABurstLength_10Transfers (0x00000900)
928 #define TIM_DMABurstLength_11Transfers (0x00000A00)
929 #define TIM_DMABurstLength_12Transfers (0x00000B00)
930 #define TIM_DMABurstLength_13Transfers (0x00000C00)
931 #define TIM_DMABurstLength_14Transfers (0x00000D00)
932 #define TIM_DMABurstLength_15Transfers (0x00000E00)
933 #define TIM_DMABurstLength_16Transfers (0x00000F00)
934 #define TIM_DMABurstLength_17Transfers (0x00001000)
935 #define TIM_DMABurstLength_18Transfers (0x00001100)
936 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
937 ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
938 ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
939 ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
940 ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
941 ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
942 ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
943 ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
944 ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
945 ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
946 ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
947 ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
948 ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
949 ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
950 ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
951 ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
952 ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
953 ((LENGTH) == TIM_DMABurstLength_18Transfers))
954 /**
955 * @}
956 */
957
958 /** @defgroup TIM_Input_Capture_Filer_Value TIM Input Capture Value
959 * @{
960 */
961
962 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
963 /**
964 * @}
965 */
966
967 /** @defgroup DMA_Handle_index TIM DMA Handle Index
968 * @{
969 */
970 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */
971 #define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
972 #define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
973 #define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
974 #define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
975 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */
976 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */
977 /**
978 * @}
979 */
980
981 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State
982 * @{
983 */
984 #define TIM_CCx_ENABLE ((uint32_t)0x0001)
985 #define TIM_CCx_DISABLE ((uint32_t)0x0000)
986 #define TIM_CCxN_ENABLE ((uint32_t)0x0004)
987 #define TIM_CCxN_DISABLE ((uint32_t)0x0000)
988 /**
989 * @}
990 */
991
992 /**
993 * @}
994 */
995
996 /* Exported macros -----------------------------------------------------------*/
997 /** @defgroup TIM_Exported_Macros TIM Exported Macros
998 * @{
999 */
1000
1001 /** @brief Reset TIM handle state
1002 * @param __HANDLE__: TIM handle.
1003 * @retval None
1004 */
1005 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
1006
1007 /**
1008 * @brief Enable the TIM peripheral.
1009 * @param __HANDLE__: TIM handle
1010 * @retval None
1011 */
1012 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
1013
1014 /**
1015 * @brief Enable the TIM main Output.
1016 * @param __HANDLE__: TIM handle
1017 * @retval None
1018 */
1019 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
1020
1021 /* The counter of a timer instance is disabled only if all the CCx and CCxN
1022 channels have been disabled */
1023 #define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
1024 #define CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
1025
1026 /**
1027 * @brief Disable the TIM peripheral.
1028 * @param __HANDLE__: TIM handle
1029 * @retval None
1030 */
1031 #define __HAL_TIM_DISABLE(__HANDLE__) \
1032 do { \
1033 if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
1034 { \
1035 if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
1036 { \
1037 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
1038 } \
1039 } \
1040 } while(0)
1041 /* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
1042 channels have been disabled */
1043 /**
1044 * @brief Disable the TIM main Output.
1045 * @param __HANDLE__: TIM handle
1046 * @retval None
1047 */
1048 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
1049 do { \
1050 if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
1051 { \
1052 if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
1053 { \
1054 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
1055 } \
1056 } \
1057 } while(0)
1058
1059 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
1060 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
1061 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
1062 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
1063 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
1064 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
1065
1066 #define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
1067 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
1068
1069 #define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
1070 #define __HAL_TIM_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
1071
1072 #define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \
1073 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
1074 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
1075 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
1076 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
1077
1078 #define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \
1079 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
1080 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
1081 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
1082 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
1083
1084 /**
1085 * @brief Sets the TIM Counter Register value on runtime.
1086 * @param __HANDLE__: TIM handle.
1087 * @param __COUNTER__: specifies the Counter register new value.
1088 * @retval None
1089 */
1090 #define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
1091
1092 /**
1093 * @brief Gets the TIM Counter Register value on runtime.
1094 * @param __HANDLE__: TIM handle.
1095 * @retval None
1096 */
1097 #define __HAL_TIM_GetCounter(__HANDLE__) \
1098 ((__HANDLE__)->Instance->CNT)
1099
1100 /**
1101 * @brief Sets the TIM Autoreload Register value on runtime without calling
1102 * another time any Init function.
1103 * @param __HANDLE__: TIM handle.
1104 * @param __AUTORELOAD__: specifies the Counter register new value.
1105 * @retval None
1106 */
1107 #define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \
1108 do{ \
1109 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
1110 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
1111 } while(0)
1112
1113 /**
1114 * @brief Gets the TIM Autoreload Register value on runtime
1115 * @param __HANDLE__: TIM handle.
1116 * @retval None
1117 */
1118 #define __HAL_TIM_GetAutoreload(__HANDLE__) \
1119 ((__HANDLE__)->Instance->ARR)
1120
1121 /**
1122 * @brief Sets the TIM Clock Division value on runtime without calling
1123 * another time any Init function.
1124 * @param __HANDLE__: TIM handle.
1125 * @param __CKD__: specifies the clock division value.
1126 * This parameter can be one of the following value:
1127 * @arg TIM_CLOCKDIVISION_DIV1
1128 * @arg TIM_CLOCKDIVISION_DIV2
1129 * @arg TIM_CLOCKDIVISION_DIV4
1130 * @retval None
1131 */
1132 #define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \
1133 do{ \
1134 (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
1135 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
1136 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
1137 } while(0)
1138
1139 /**
1140 * @brief Gets the TIM Clock Division value on runtime
1141 * @param __HANDLE__: TIM handle.
1142 * @retval None
1143 */
1144 #define __HAL_TIM_GetClockDivision(__HANDLE__) \
1145 ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
1146
1147 /**
1148 * @brief Sets the TIM Input Capture prescaler on runtime without calling
1149 * another time HAL_TIM_IC_ConfigChannel() function.
1150 * @param __HANDLE__: TIM handle.
1151 * @param __CHANNEL__ : TIM Channels to be configured.
1152 * This parameter can be one of the following values:
1153 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1154 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1155 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1156 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1157 * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
1158 * This parameter can be one of the following values:
1159 * @arg TIM_ICPSC_DIV1: no prescaler
1160 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1161 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1162 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1163 * @retval None
1164 */
1165 #define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \
1166 do{ \
1167 __HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \
1168 __HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
1169 } while(0)
1170
1171 /**
1172 * @brief Gets the TIM Input Capture prescaler on runtime
1173 * @param __HANDLE__: TIM handle.
1174 * @param __CHANNEL__ : TIM Channels to be configured.
1175 * This parameter can be one of the following values:
1176 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
1177 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
1178 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
1179 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
1180 * @retval None
1181 */
1182 #define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \
1183 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
1184 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
1185 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
1186 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
1187
1188 /**
1189 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
1190 * @param __HANDLE__: TIM handle.
1191 * @note When the USR bit of the TIMx_CR1 register is set, only counter
1192 * overflow/underflow generates an update interrupt or DMA request (if
1193 * enabled)
1194 * @retval None
1195 */
1196 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
1197 ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
1198
1199 /**
1200 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
1201 * @param __HANDLE__: TIM handle.
1202 * @note When the USR bit of the TIMx_CR1 register is reset, any of the
1203 * following events generate an update interrupt or DMA request (if
1204 * enabled):
1205 * \96 Counter overflow/underflow
1206 * \96 Setting the UG bit
1207 * \96 Update generation through the slave mode controller
1208 * @retval None
1209 */
1210 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
1211 ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
1212
1213 /**
1214 * @}
1215 */
1216
1217 /* Include TIM HAL Extended module */
1218 #include "stm32f3xx_hal_tim_ex.h"
1219
1220 /* Exported functions --------------------------------------------------------*/
1221 /** @addtogroup TIM_Exported_Functions TIM Exported Functions
1222 * @{
1223 */
1224
1225 /** @addtogroup TIM_Exported_Functions_Group1 Time Base functions
1226 * @brief Time Base functions
1227 * @{
1228 */
1229 /* Time Base functions ********************************************************/
1230 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
1231 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
1232 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
1233 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
1234 /* Blocking mode: Polling */
1235 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
1236 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
1237 /* Non-Blocking mode: Interrupt */
1238 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
1239 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
1240 /* Non-Blocking mode: DMA */
1241 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
1242 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
1243 /**
1244 * @}
1245 */
1246
1247 /** @addtogroup TIM_Exported_Functions_Group2 Time Output Compare functions
1248 * @brief Time Output Compare functions
1249 * @{
1250 */
1251 /* Timer Output Compare functions **********************************************/
1252 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
1253 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
1254 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
1255 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
1256 /* Blocking mode: Polling */
1257 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1258 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1259 /* Non-Blocking mode: Interrupt */
1260 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1261 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1262 /* Non-Blocking mode: DMA */
1263 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1264 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1265 /**
1266 * @}
1267 */
1268
1269 /** @addtogroup TIM_Exported_Functions_Group3 Time PWM functions
1270 * @brief Time PWM functions
1271 * @{
1272 */
1273 /* Timer PWM functions *********************************************************/
1274 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
1275 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
1276 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
1277 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
1278 /* Blocking mode: Polling */
1279 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1280 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1281 /* Non-Blocking mode: Interrupt */
1282 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1283 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1284 /* Non-Blocking mode: DMA */
1285 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1286 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1287 /**
1288 * @}
1289 */
1290
1291 /** @addtogroup TIM_Exported_Functions_Group4 Time Input Capture functions
1292 * @brief Time Input Capture functions
1293 * @{
1294 */
1295 /* Timer Input Capture functions ***********************************************/
1296 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
1297 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
1298 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
1299 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
1300 /* Blocking mode: Polling */
1301 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1302 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1303 /* Non-Blocking mode: Interrupt */
1304 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1305 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1306 /* Non-Blocking mode: DMA */
1307 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1308 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1309 /**
1310 * @}
1311 */
1312
1313 /** @addtogroup TIM_Exported_Functions_Group5 Time One Pulse functions
1314 * @brief Time One Pulse functions
1315 * @{
1316 */
1317 /* Timer One Pulse functions ***************************************************/
1318 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
1319 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
1320 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
1321 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
1322 /* Blocking mode: Polling */
1323 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1324 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1325 /* Non-Blocking mode: Interrupt */
1326 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1327 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1328 /**
1329 * @}
1330 */
1331
1332 /** @addtogroup TIM_Exported_Functions_Group6 Time Encoder functions
1333 * @brief Time Encoder functions
1334 * @{
1335 */
1336 /* Timer Encoder functions *****************************************************/
1337 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
1338 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
1339 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
1340 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
1341 /* Blocking mode: Polling */
1342 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1343 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1344 /* Non-Blocking mode: Interrupt */
1345 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1346 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1347 /* Non-Blocking mode: DMA */
1348 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
1349 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1350 /**
1351 * @}
1352 */
1353
1354 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
1355 * @brief IRQ handler management
1356 * @{
1357 */
1358 /* Interrupt Handler functions **********************************************/
1359 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
1360 /**
1361 * @}
1362 */
1363
1364 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
1365 * @brief Peripheral Control functions
1366 * @{
1367 */
1368 /* Control functions *********************************************************/
1369 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
1370 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
1371 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
1372 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
1373 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
1374 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
1375 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
1376 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
1377 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
1378 uint32_t *BurstBuffer, uint32_t BurstLength);
1379 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
1380 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
1381 uint32_t *BurstBuffer, uint32_t BurstLength);
1382 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
1383 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
1384 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
1385 /**
1386 * @}
1387 */
1388
1389 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
1390 * @brief TIM Callbacks functions
1391 * @{
1392 */
1393 /* Callback in non blocking modes (Interrupt and DMA) *************************/
1394 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
1395 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
1396 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
1397 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
1398 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
1399 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
1400 /**
1401 * @}
1402 */
1403
1404 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
1405 * @brief Peripheral State functions
1406 * @{
1407 */
1408 /* Peripheral State functions **************************************************/
1409 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
1410 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
1411 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
1412 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
1413 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
1414 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
1415 /**
1416 * @}
1417 */
1418
1419 /**
1420 * @}
1421 */
1422
1423 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
1424 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
1425 void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
1426 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
1427 void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
1428 void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
1429 void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
1430 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
1431
1432 void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
1433 void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
1434 void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
1435 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
1436
1437 /**
1438 * @}
1439 */
1440
1441 /**
1442 * @}
1443 */
1444
1445 #ifdef __cplusplus
1446 }
1447 #endif
1448
1449 #endif /* __STM32F3xx_HAL_TIM_H */
1450
1451 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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