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[tmk_keyboard.git] / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_STM / TARGET_STM32F3 / stm32f3xx_hal_tim_ex.h
1 /**
2 ******************************************************************************
3 * @file stm32f3xx_hal_tim_ex.h
4 * @author MCD Application Team
5 * @version V1.1.0
6 * @date 12-Sept-2014
7 * @brief Header file of TIM HAL Extended module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F3xx_HAL_TIM_EX_H
40 #define __STM32F3xx_HAL_TIM_EX_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f3xx_hal_def.h"
48
49 /** @addtogroup STM32F3xx_HAL_Driver
50 * @{
51 */
52
53 /** @addtogroup TIMEx
54 * @{
55 */
56
57 /* Exported types ------------------------------------------------------------*/
58 /** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
59 * @{
60 */
61
62 /**
63 * @brief TIM Hall sensor Configuration Structure definition
64 */
65
66 typedef struct
67 {
68
69 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
70 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
71
72 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
73 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
74
75 uint32_t IC1Filter; /*!< Specifies the input capture filter.
76 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
77 uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
78 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
79 } TIM_HallSensor_InitTypeDef;
80
81 #if defined(STM32F373xC) || defined(STM32F378xx)
82 /**
83 * @brief TIM Master configuration Structure definition
84 * @note STM32F373xC and STM32F378xx: timer instances provide a single TRGO
85 * output
86 */
87 typedef struct {
88 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
89 This parameter can be a value of @ref TIM_Master_Mode_Selection */
90 uint32_t MasterSlaveMode; /*!< Master/slave mode selection
91 This parameter can be a value of @ref TIM_Master_Slave_Mode */
92 }TIM_MasterConfigTypeDef;
93
94 /**
95 * @brief TIM Break and Dead time configuration Structure definition
96 * @note STM32F373xC and STM32F378xx: single break input with configurable polarity.
97 */
98 typedef struct
99 {
100 uint32_t OffStateRunMode; /*!< TIM off state in run mode
101 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
102 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
103 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
104 uint32_t LockLevel; /*!< TIM Lock level
105 This parameter can be a value of @ref TIM_Lock_level */
106 uint32_t DeadTime; /*!< TIM dead Time
107 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
108 uint32_t BreakState; /*!< TIM Break State
109 This parameter can be a value of @ref TIM_Break_Input_enable_disable */
110 uint32_t BreakPolarity; /*!< TIM Break input polarity
111 This parameter can be a value of @ref TIM_Break_Polarity */
112 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
113 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
114 } TIM_BreakDeadTimeConfigTypeDef;
115
116 #endif /* STM32F373xC || STM32F378xx */
117
118 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
119 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
120 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
121 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
122 /**
123 * @brief TIM Break input(s) and Dead time configuration Structure definition
124 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
125 * filter and polarity.
126 */
127 typedef struct
128 {
129 uint32_t OffStateRunMode; /*!< TIM off state in run mode
130 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
131 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
132 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
133 uint32_t LockLevel; /*!< TIM Lock level
134 This parameter can be a value of @ref TIM_Lock_level */
135 uint32_t DeadTime; /*!< TIM dead Time
136 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
137 uint32_t BreakState; /*!< TIM Break State
138 This parameter can be a value of @ref TIM_Break_Input_enable_disable */
139 uint32_t BreakPolarity; /*!< TIM Break input polarity
140 This parameter can be a value of @ref TIM_Break_Polarity */
141 uint32_t BreakFilter; /*!< Specifies the brek input filter.
142 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
143 uint32_t Break2State; /*!< TIM Break2 State
144 This parameter can be a value of @ref TIMEx_Break2_Input_enable_disable */
145 uint32_t Break2Polarity; /*!< TIM Break2 input polarity
146 This parameter can be a value of @ref TIMEx_Break2_Polarity */
147 uint32_t Break2Filter; /*!< TIM break2 input filter.
148 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
149 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
150 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
151 } TIM_BreakDeadTimeConfigTypeDef;
152
153 /**
154 * @brief TIM Master configuration Structure definition
155 * @note Advanced timers provide TRGO2 internal line which is redirected
156 * to the ADC
157 */
158 typedef struct {
159 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
160 This parameter can be a value of @ref TIM_Master_Mode_Selection */
161 uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
162 This parameter can be a value of @ref TIMEx_Master_Mode_Selection_2 */
163 uint32_t MasterSlaveMode; /*!< Master/slave mode selection
164 This parameter can be a value of @ref TIM_Master_Slave_Mode */
165 }TIM_MasterConfigTypeDef;
166 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
167 /* STM32F302xC || STM32F303xC || STM32F358xx || */
168 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
169 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
170 /**
171 * @}
172 */
173
174 /* Exported constants --------------------------------------------------------*/
175 /** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
176 * @{
177 */
178
179 #if defined(STM32F373xC) || defined(STM32F378xx)
180 /** @defgroup TIMEx_Channel TIM Extended Channel
181 * @{
182 */
183 #define TIM_CHANNEL_1 ((uint32_t)0x0000)
184 #define TIM_CHANNEL_2 ((uint32_t)0x0004)
185 #define TIM_CHANNEL_3 ((uint32_t)0x0008)
186 #define TIM_CHANNEL_4 ((uint32_t)0x000C)
187 #define TIM_CHANNEL_ALL ((uint32_t)0x0018)
188
189 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
190 ((CHANNEL) == TIM_CHANNEL_2) || \
191 ((CHANNEL) == TIM_CHANNEL_3) || \
192 ((CHANNEL) == TIM_CHANNEL_4) || \
193 ((CHANNEL) == TIM_CHANNEL_ALL))
194
195 #define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
196 ((CHANNEL) == TIM_CHANNEL_2))
197
198 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
199 ((CHANNEL) == TIM_CHANNEL_2))
200
201 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
202 ((CHANNEL) == TIM_CHANNEL_2) || \
203 ((CHANNEL) == TIM_CHANNEL_3))
204 /**
205 * @}
206 */
207
208 /** @defgroup TIMEx_Output_Compare_and_PWM_modes TIM Extended Output Compare and PWM Modes
209 * @{
210 */
211
212 #define TIM_OCMODE_TIMING ((uint32_t)0x0000)
213 #define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
214 #define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
215 #define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
216 #define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
217 #define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M)
218 #define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
219 #define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
220
221 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
222 ((MODE) == TIM_OCMODE_PWM2))
223
224 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
225 ((MODE) == TIM_OCMODE_ACTIVE) || \
226 ((MODE) == TIM_OCMODE_INACTIVE) || \
227 ((MODE) == TIM_OCMODE_TOGGLE) || \
228 ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
229 ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
230 /**
231 * @}
232 */
233
234 /** @defgroup TIMEx_ClearInput_Source TIM Extended Clear Input Source
235 * @{
236 */
237 #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
238 #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
239
240 #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
241 ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
242 /**
243 * @}
244 */
245
246 /** @defgroup TIMEx_Slave_Mode TIM Extended Slave Mode
247 * @{
248 */
249
250 #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
251 #define TIM_SLAVEMODE_RESET ((uint16_t)0x0004)
252 #define TIM_SLAVEMODE_GATED ((uint16_t)0x0005)
253 #define TIM_SLAVEMODE_TRIGGER ((uint16_t)0x0006)
254 #define TIM_SLAVEMODE_EXTERNAL1 ((uint16_t)0x0007)
255
256 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
257 ((MODE) == TIM_SLAVEMODE_RESET) || \
258 ((MODE) == TIM_SLAVEMODE_GATED) || \
259 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
260 ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
261 /**
262 * @}
263 */
264
265 /** @defgroup TIMEx_Event_Source TIM Extended Event Source
266 * @{
267 */
268
269 #define TIM_EventSource_Update TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
270 #define TIM_EventSource_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
271 #define TIM_EventSource_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
272 #define TIM_EventSource_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
273 #define TIM_EventSource_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
274 #define TIM_EventSource_COM TIM_EGR_COMG /*!< A commutation event is generated */
275 #define TIM_EventSource_Trigger TIM_EGR_TG /*!< A trigger event is generated */
276 #define TIM_EventSource_Break TIM_EGR_BG /*!< A break event is generated */
277 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
278
279 /**
280 * @}
281 */
282
283 /** @defgroup TIMEx_DMA_Base_address TIM Extended DMA BAse Address
284 * @{
285 */
286
287 #define TIM_DMABase_CR1 (0x00000000)
288 #define TIM_DMABase_CR2 (0x00000001)
289 #define TIM_DMABase_SMCR (0x00000002)
290 #define TIM_DMABase_DIER (0x00000003)
291 #define TIM_DMABase_SR (0x00000004)
292 #define TIM_DMABase_EGR (0x00000005)
293 #define TIM_DMABase_CCMR1 (0x00000006)
294 #define TIM_DMABase_CCMR2 (0x00000007)
295 #define TIM_DMABase_CCER (0x00000008)
296 #define TIM_DMABase_CNT (0x00000009)
297 #define TIM_DMABase_PSC (0x0000000A)
298 #define TIM_DMABase_ARR (0x0000000B)
299 #define TIM_DMABase_RCR (0x0000000C)
300 #define TIM_DMABase_CCR1 (0x0000000D)
301 #define TIM_DMABase_CCR2 (0x0000000E)
302 #define TIM_DMABase_CCR3 (0x0000000F)
303 #define TIM_DMABase_CCR4 (0x00000010)
304 #define TIM_DMABase_BDTR (0x00000011)
305 #define TIM_DMABase_DCR (0x00000012)
306 #define TIM_DMABase_OR (0x00000013)
307 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
308 ((BASE) == TIM_DMABase_CR2) || \
309 ((BASE) == TIM_DMABase_SMCR) || \
310 ((BASE) == TIM_DMABase_DIER) || \
311 ((BASE) == TIM_DMABase_SR) || \
312 ((BASE) == TIM_DMABase_EGR) || \
313 ((BASE) == TIM_DMABase_CCMR1) || \
314 ((BASE) == TIM_DMABase_CCMR2) || \
315 ((BASE) == TIM_DMABase_CCER) || \
316 ((BASE) == TIM_DMABase_CNT) || \
317 ((BASE) == TIM_DMABase_PSC) || \
318 ((BASE) == TIM_DMABase_ARR) || \
319 ((BASE) == TIM_DMABase_RCR) || \
320 ((BASE) == TIM_DMABase_CCR1) || \
321 ((BASE) == TIM_DMABase_CCR2) || \
322 ((BASE) == TIM_DMABase_CCR3) || \
323 ((BASE) == TIM_DMABase_CCR4) || \
324 ((BASE) == TIM_DMABase_BDTR) || \
325 ((BASE) == TIM_DMABase_DCR) || \
326 ((BASE) == TIM_DMABase_OR))
327 /**
328 * @}
329 */
330 #endif /* STM32F373xC || STM32F378xx */
331
332 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
333 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
334 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
335 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
336 /** @defgroup TIMEx_Channel TIM Extended Channel
337 * @{
338 */
339
340 #define TIM_CHANNEL_1 ((uint32_t)0x0000)
341 #define TIM_CHANNEL_2 ((uint32_t)0x0004)
342 #define TIM_CHANNEL_3 ((uint32_t)0x0008)
343 #define TIM_CHANNEL_4 ((uint32_t)0x000C)
344 #define TIM_CHANNEL_5 ((uint32_t)0x0010)
345 #define TIM_CHANNEL_6 ((uint32_t)0x0014)
346 #define TIM_CHANNEL_ALL ((uint32_t)0x003C)
347
348 #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
349 ((CHANNEL) == TIM_CHANNEL_2) || \
350 ((CHANNEL) == TIM_CHANNEL_3) || \
351 ((CHANNEL) == TIM_CHANNEL_4) || \
352 ((CHANNEL) == TIM_CHANNEL_5) || \
353 ((CHANNEL) == TIM_CHANNEL_6) || \
354 ((CHANNEL) == TIM_CHANNEL_ALL))
355
356 #define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
357 ((CHANNEL) == TIM_CHANNEL_2))
358
359 #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
360 ((CHANNEL) == TIM_CHANNEL_2))
361
362 #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
363 ((CHANNEL) == TIM_CHANNEL_2) || \
364 ((CHANNEL) == TIM_CHANNEL_3))
365 /**
366 * @}
367 */
368
369 /** @defgroup TIMEx_Output_Compare_and_PWM_modes TIM Extended Output Compare and PWM Modes
370 * @{
371 */
372 #define TIM_OCMODE_TIMING ((uint32_t)0x0000)
373 #define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0)
374 #define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1)
375 #define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
376 #define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
377 #define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
378 #define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
379 #define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2)
380
381 #define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3)
382 #define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)
383 #define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)
384 #define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
385 #define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
386 #define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)
387
388 #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
389 ((MODE) == TIM_OCMODE_PWM2) || \
390 ((MODE) == TIM_OCMODE_COMBINED_PWM1) || \
391 ((MODE) == TIM_OCMODE_COMBINED_PWM2) || \
392 ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
393 ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM2))
394
395 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
396 ((MODE) == TIM_OCMODE_ACTIVE) || \
397 ((MODE) == TIM_OCMODE_INACTIVE) || \
398 ((MODE) == TIM_OCMODE_TOGGLE) || \
399 ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
400 ((MODE) == TIM_OCMODE_FORCED_INACTIVE) || \
401 ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
402 ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM2))
403 /**
404 * @}
405 */
406
407 /** @defgroup TIMEx_ClearInput_Source TIM Extended Clear Input Source
408 * @{
409 */
410 #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
411 #define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002)
412 #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
413
414 #define IS_TIM_CLEARINPUT_SOURCE(MODE) (((MODE) == TIM_CLEARINPUTSOURCE_ETR) || \
415 ((MODE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
416 ((MODE) == TIM_CLEARINPUTSOURCE_NONE))
417 /**
418 * @}
419 */
420
421 /** @defgroup TIMEx_BreakInput_Filter TIM Extended Break Input Filter
422 * @{
423 */
424
425 #define IS_TIM_BREAK_FILTER(BRKFILTER) ((BRKFILTER) <= 0xF)
426 /**
427 * @}
428 */
429
430 /** @defgroup TIMEx_Break2_Input_enable_disable TIMEX Break input 2 Enable
431 * @{
432 */
433 #define TIM_BREAK2_DISABLE ((uint32_t)0x00000000)
434 #define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E)
435
436 #define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_BREAK2_ENABLE) || \
437 ((STATE) == TIM_BREAK2_DISABLE))
438 /**
439 * @}
440 */
441 /** @defgroup TIMEx_Break2_Polarity TIM Extended Break Input 2 Polarity
442 * @{
443 */
444 #define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000)
445 #define TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P)
446
447 #define IS_TIM_BREAK2_POLARITY(POLARITY) (((POLARITY) == TIM_BREAK2POLARITY_LOW) || \
448 ((POLARITY) == TIM_BREAK2POLARITY_HIGH))
449 /**
450 * @}
451 */
452
453 /** @defgroup TIMEx_Master_Mode_Selection_2 TIM Extended Master Mode Selection 2 (TRGO2)
454 * @{
455 */
456 #define TIM_TRGO2_RESET ((uint32_t)0x00000000)
457 #define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0))
458 #define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1))
459 #define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
460 #define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2))
461 #define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
462 #define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1))
463 #define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
464 #define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3))
465 #define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0))
466 #define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1))
467 #define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
468 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2))
469 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0))
470 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1))
471 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0))
472
473 #define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2_RESET) || \
474 ((SOURCE) == TIM_TRGO2_ENABLE) || \
475 ((SOURCE) == TIM_TRGO2_UPDATE) || \
476 ((SOURCE) == TIM_TRGO2_OC1) || \
477 ((SOURCE) == TIM_TRGO2_OC1REF) || \
478 ((SOURCE) == TIM_TRGO2_OC2REF) || \
479 ((SOURCE) == TIM_TRGO2_OC3REF) || \
480 ((SOURCE) == TIM_TRGO2_OC3REF) || \
481 ((SOURCE) == TIM_TRGO2_OC4REF) || \
482 ((SOURCE) == TIM_TRGO2_OC5REF) || \
483 ((SOURCE) == TIM_TRGO2_OC6REF) || \
484 ((SOURCE) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
485 ((SOURCE) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
486 ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \
487 ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
488 ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \
489 ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
490 /**
491 * @}
492 */
493
494 /** @defgroup TIMEx_Slave_Mode TIM Extended Slave mode
495 * @{
496 */
497 #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
498 #define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2))
499 #define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0))
500 #define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1))
501 #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0))
502 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3))
503
504 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
505 ((MODE) == TIM_SLAVEMODE_RESET) || \
506 ((MODE) == TIM_SLAVEMODE_GATED) || \
507 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
508 ((MODE) == TIM_SLAVEMODE_EXTERNAL1) || \
509 ((MODE) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
510 /**
511 * @}
512 */
513
514 /** @defgroup TIM_Event_Source TIM Extended Event Source
515 * @{
516 */
517
518 #define TIM_EventSource_Update TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
519 #define TIM_EventSource_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
520 #define TIM_EventSource_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
521 #define TIM_EventSource_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
522 #define TIM_EventSource_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
523 #define TIM_EventSource_COM TIM_EGR_COMG /*!< A commutation event is generated */
524 #define TIM_EventSource_Trigger TIM_EGR_TG /*!< A trigger event is generated */
525 #define TIM_EventSource_Break TIM_EGR_BG /*!< A break event is generated */
526 #define TIM_EventSource_Break2 TIM_EGR_B2G /*!< A break 2 event is generated */
527 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFE00) == 0x00000000) && ((SOURCE) != 0x00000000))
528
529 /**
530 * @}
531 */
532
533 /** @defgroup TIM_DMA_Base_address TIM Extended DMA Base Address
534 * @{
535 */
536
537 #define TIM_DMABase_CR1 (0x00000000)
538 #define TIM_DMABase_CR2 (0x00000001)
539 #define TIM_DMABase_SMCR (0x00000002)
540 #define TIM_DMABase_DIER (0x00000003)
541 #define TIM_DMABase_SR (0x00000004)
542 #define TIM_DMABase_EGR (0x00000005)
543 #define TIM_DMABase_CCMR1 (0x00000006)
544 #define TIM_DMABase_CCMR2 (0x00000007)
545 #define TIM_DMABase_CCER (0x00000008)
546 #define TIM_DMABase_CNT (0x00000009)
547 #define TIM_DMABase_PSC (0x0000000A)
548 #define TIM_DMABase_ARR (0x0000000B)
549 #define TIM_DMABase_RCR (0x0000000C)
550 #define TIM_DMABase_CCR1 (0x0000000D)
551 #define TIM_DMABase_CCR2 (0x0000000E)
552 #define TIM_DMABase_CCR3 (0x0000000F)
553 #define TIM_DMABase_CCR4 (0x00000010)
554 #define TIM_DMABase_BDTR (0x00000011)
555 #define TIM_DMABase_DCR (0x00000012)
556 #define TIM_DMABase_CCMR3 (0x00000015)
557 #define TIM_DMABase_CCR5 (0x00000016)
558 #define TIM_DMABase_CCR6 (0x00000017)
559 #define TIM_DMABase_OR (0x00000018)
560 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
561 ((BASE) == TIM_DMABase_CR2) || \
562 ((BASE) == TIM_DMABase_SMCR) || \
563 ((BASE) == TIM_DMABase_DIER) || \
564 ((BASE) == TIM_DMABase_SR) || \
565 ((BASE) == TIM_DMABase_EGR) || \
566 ((BASE) == TIM_DMABase_CCMR1) || \
567 ((BASE) == TIM_DMABase_CCMR2) || \
568 ((BASE) == TIM_DMABase_CCER) || \
569 ((BASE) == TIM_DMABase_CNT) || \
570 ((BASE) == TIM_DMABase_PSC) || \
571 ((BASE) == TIM_DMABase_ARR) || \
572 ((BASE) == TIM_DMABase_RCR) || \
573 ((BASE) == TIM_DMABase_CCR1) || \
574 ((BASE) == TIM_DMABase_CCR2) || \
575 ((BASE) == TIM_DMABase_CCR3) || \
576 ((BASE) == TIM_DMABase_CCR4) || \
577 ((BASE) == TIM_DMABase_BDTR) || \
578 ((BASE) == TIM_DMABase_CCMR3) || \
579 ((BASE) == TIM_DMABase_CCR5) || \
580 ((BASE) == TIM_DMABase_CCR6) || \
581 ((BASE) == TIM_DMABase_OR))
582 /**
583 * @}
584 */
585 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
586 /* STM32F302xC || STM32F303xC || STM32F358xx || */
587 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
588 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
589
590 #if defined(STM32F302xE) || \
591 defined(STM32F302xC) || \
592 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
593 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
594 /** @defgroup TIMEx_Remap TIM Extended Remapping
595 * @{
596 */
597 #define TIM_TIM1_ADC1_NONE (0x00000000) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
598 #define TIM_TIM1_ADC1_AWD1 (0x00000001) /* !< TIM1_ETR is connected to ADC1 AWD1 */
599 #define TIM_TIM1_ADC1_AWD2 (0x00000002) /* !< TIM1_ETR is connected to ADC1 AWD2 */
600 #define TIM_TIM1_ADC1_AWD3 (0x00000003) /* !< TIM1_ETR is connected to ADC1 AWD3 */
601 #define TIM_TIM16_GPIO (0x00000000) /* !< TIM16 TI1 is connected to GPIO */
602 #define TIM_TIM16_RTC (0x00000001) /* !< TIM16 TI1 is connected to RTC_clock */
603 #define TIM_TIM16_HSE (0x00000002) /* !< TIM16 TI1 is connected to HSE/32 */
604 #define TIM_TIM16_MCO (0x00000003) /* !< TIM16 TI1 is connected to MCO */
605
606 #define IS_TIM_REMAP(REMAP) (((REMAP) == TIM_TIM1_ADC1_NONE) ||\
607 ((REMAP) == TIM_TIM1_ADC1_AWD1) ||\
608 ((REMAP) == TIM_TIM1_ADC1_AWD2) ||\
609 ((REMAP) == TIM_TIM1_ADC1_AWD3) ||\
610 ((REMAP) == TIM_TIM16_GPIO) ||\
611 ((REMAP) == TIM_TIM16_RTC) ||\
612 ((REMAP) == TIM_TIM16_HSE) ||\
613 ((REMAP) == TIM_TIM16_MCO))
614 /**
615 * @}
616 */
617 #endif /* STM32F302xE || */
618 /* STM32F302xC || */
619 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
620 /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
621
622 #if defined(STM32F303xC) || defined(STM32F358xx)
623 /** @defgroup TIMEx_Remap TIM Extended Remapping 1
624 * @{
625 */
626 #define TIM_TIM1_ADC1_NONE (0x00000000) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
627 #define TIM_TIM1_ADC1_AWD1 (0x00000001) /* !< TIM1_ETR is connected to ADC1 AWD1 */
628 #define TIM_TIM1_ADC1_AWD2 (0x00000002) /* !< TIM1_ETR is connected to ADC1 AWD2 */
629 #define TIM_TIM1_ADC1_AWD3 (0x00000003) /* !< TIM1_ETR is connected to ADC1 AWD3 */
630 #define TIM_TIM8_ADC2_NONE (0x00000000) /* !< TIM8_ETR is not connected to any AWD (analog watchdog) */
631 #define TIM_TIM8_ADC2_AWD1 (0x00000001) /* !< TIM8_ETR is connected to ADC2 AWD1 */
632 #define TIM_TIM8_ADC2_AWD2 (0x00000002) /* !< TIM8_ETR is connected to ADC2 AWD2 */
633 #define TIM_TIM8_ADC2_AWD3 (0x00000003) /* !< TIM8_ETR is connected to ADC2 AWD3 */
634 #define TIM_TIM16_GPIO (0x00000000) /* !< TIM16 TI1 is connected to GPIO */
635 #define TIM_TIM16_RTC (0x00000001) /* !< TIM16 TI1 is connected to RTC_clock */
636 #define TIM_TIM16_HSE (0x00000002) /* !< TIM16 TI1 is connected to HSE/32 */
637 #define TIM_TIM16_MCO (0x00000003) /* !< TIM16 TI1 is connected to MCO */
638
639 #define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) ||\
640 ((REMAP1) == TIM_TIM1_ADC1_AWD1) ||\
641 ((REMAP1) == TIM_TIM1_ADC1_AWD2) ||\
642 ((REMAP1) == TIM_TIM1_ADC1_AWD3) ||\
643 ((REMAP1) == TIM_TIM8_ADC2_NONE) ||\
644 ((REMAP1) == TIM_TIM8_ADC2_AWD1) ||\
645 ((REMAP1) == TIM_TIM8_ADC2_AWD2) ||\
646 ((REMAP1) == TIM_TIM8_ADC2_AWD3) ||\
647 ((REMAP1) == TIM_TIM16_GPIO) ||\
648 ((REMAP1) == TIM_TIM16_RTC) ||\
649 ((REMAP1) == TIM_TIM16_HSE) ||\
650 ((REMAP1) == TIM_TIM16_MCO))
651 /**
652 * @}
653 */
654
655 /** @defgroup TIMEx_Remap2 TIM Extended Remapping 2
656 * @{
657 */
658 #define TIM_TIM1_ADC4_NONE (0x00000000) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
659 #define TIM_TIM1_ADC4_AWD1 (0x00000004) /* !< TIM1_ETR is connected to ADC4 AWD1 */
660 #define TIM_TIM1_ADC4_AWD2 (0x00000008) /* !< TIM1_ETR is connected to ADC4 AWD2 */
661 #define TIM_TIM1_ADC4_AWD3 (0x0000000C) /* !< TIM1_ETR is connected to ADC4 AWD3 */
662 #define TIM_TIM8_ADC3_NONE (0x00000000) /* !< TIM8_ETR is not connected to any AWD (analog watchdog) */
663 #define TIM_TIM8_ADC3_AWD1 (0x00000004) /* !< TIM8_ETR is connected to ADC3 AWD1 */
664 #define TIM_TIM8_ADC3_AWD2 (0x00000008) /* !< TIM8_ETR is connected to ADC3 AWD2 */
665 #define TIM_TIM8_ADC3_AWD3 (0x0000000C) /* !< TIM8_ETR is connected to ADC3 AWD3 */
666 #define TIM_TIM16_NONE (0x00000000) /* !< Non significant value for TIM16 */
667
668 #define IS_TIM_REMAP2(REMAP2) (((REMAP2) == TIM_TIM1_ADC4_NONE) ||\
669 ((REMAP2) == TIM_TIM1_ADC4_AWD1) ||\
670 ((REMAP2) == TIM_TIM1_ADC4_AWD2) ||\
671 ((REMAP2) == TIM_TIM1_ADC4_AWD3) ||\
672 ((REMAP2) == TIM_TIM8_ADC3_NONE) ||\
673 ((REMAP2) == TIM_TIM8_ADC3_AWD1) ||\
674 ((REMAP2) == TIM_TIM8_ADC3_AWD2) ||\
675 ((REMAP2) == TIM_TIM8_ADC3_AWD3) ||\
676 ((REMAP2) == TIM_TIM16_NONE))
677 /**
678 * @}
679 */
680 #endif /* STM32F303xC || STM32F358xx */
681
682 #if defined(STM32F303xE) || defined(STM32F398xx)
683 /** @defgroup TIMEx_Remap TIM Extended Remapping 1
684 * @{
685 */
686 #define TIM_TIM1_ADC1_NONE (0x00000000) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
687 #define TIM_TIM1_ADC1_AWD1 (0x00000001) /* !< TIM1_ETR is connected to ADC1 AWD1 */
688 #define TIM_TIM1_ADC1_AWD2 (0x00000002) /* !< TIM1_ETR is connected to ADC1 AWD2 */
689 #define TIM_TIM1_ADC1_AWD3 (0x00000003) /* !< TIM1_ETR is connected to ADC1 AWD3 */
690 #define TIM_TIM8_ADC2_NONE (0x00000000) /* !< TIM8_ETR is not connected to any AWD (analog watchdog) */
691 #define TIM_TIM8_ADC2_AWD1 (0x00000001) /* !< TIM8_ETR is connected to ADC2 AWD1 */
692 #define TIM_TIM8_ADC2_AWD2 (0x00000002) /* !< TIM8_ETR is connected to ADC2 AWD2 */
693 #define TIM_TIM8_ADC2_AWD3 (0x00000003) /* !< TIM8_ETR is connected to ADC2 AWD3 */
694 #define TIM_TIM16_GPIO (0x00000000) /* !< TIM16 TI1 is connected to GPIO */
695 #define TIM_TIM16_RTC (0x00000001) /* !< TIM16 TI1 is connected to RTC_clock */
696 #define TIM_TIM16_HSE (0x00000002) /* !< TIM16 TI1 is connected to HSE/32 */
697 #define TIM_TIM16_MCO (0x00000003) /* !< TIM16 TI1 is connected to MCO */
698 #define TIM_TIM20_ADC3_NONE (0x00000000) /* !< TIM20_ETR is not connected to any AWD (analog watchdog) */
699 #define TIM_TIM20_ADC3_AWD1 (0x00000001) /* !< TIM20_ETR is connected to ADC3 AWD1 */
700 #define TIM_TIM20_ADC3_AWD2 (0x00000002) /* !< TIM20_ETR is connected to ADC3 AWD2 */
701 #define TIM_TIM20_ADC3_AWD3 (0x00000003) /* !< TIM20_ETR is connected to ADC3 AWD3 */
702
703 #define IS_TIM_REMAP(REMAP1) (((REMAP1) == TIM_TIM1_ADC1_NONE) ||\
704 ((REMAP1) == TIM_TIM1_ADC1_AWD1) ||\
705 ((REMAP1) == TIM_TIM1_ADC1_AWD2) ||\
706 ((REMAP1) == TIM_TIM1_ADC1_AWD3) ||\
707 ((REMAP1) == TIM_TIM8_ADC2_NONE) ||\
708 ((REMAP1) == TIM_TIM8_ADC2_AWD1) ||\
709 ((REMAP1) == TIM_TIM8_ADC2_AWD2) ||\
710 ((REMAP1) == TIM_TIM8_ADC2_AWD3) ||\
711 ((REMAP1) == TIM_TIM16_GPIO) ||\
712 ((REMAP1) == TIM_TIM16_RTC) ||\
713 ((REMAP1) == TIM_TIM16_HSE) ||\
714 ((REMAP1) == TIM_TIM16_MCO) ||\
715 ((REMAP1) == TIM_TIM20_ADC3_NONE) ||\
716 ((REMAP1) == TIM_TIM20_ADC3_AWD1) ||\
717 ((REMAP1) == TIM_TIM20_ADC3_AWD2) ||\
718 ((REMAP1) == TIM_TIM20_ADC3_AWD3))
719 /**
720 * @}
721 */
722
723 /** @defgroup TIMEx_Remap2 TIM Extended Remapping 2
724 * @{
725 */
726 #define TIM_TIM1_ADC4_NONE (0x00000000) /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
727 #define TIM_TIM1_ADC4_AWD1 (0x00000004) /* !< TIM1_ETR is connected to ADC4 AWD1 */
728 #define TIM_TIM1_ADC4_AWD2 (0x00000008) /* !< TIM1_ETR is connected to ADC4 AWD2 */
729 #define TIM_TIM1_ADC4_AWD3 (0x0000000C) /* !< TIM1_ETR is connected to ADC4 AWD3 */
730 #define TIM_TIM8_ADC3_NONE (0x00000000) /* !< TIM8_ETR is not connected to any AWD (analog watchdog) */
731 #define TIM_TIM8_ADC3_AWD1 (0x00000004) /* !< TIM8_ETR is connected to ADC3 AWD1 */
732 #define TIM_TIM8_ADC3_AWD2 (0x00000008) /* !< TIM8_ETR is connected to ADC3 AWD2 */
733 #define TIM_TIM8_ADC3_AWD3 (0x0000000C) /* !< TIM8_ETR is connected to ADC3 AWD3 */
734 #define TIM_TIM16_NONE (0x00000000) /* !< Non significant value for TIM16 */
735 #define TIM_TIM20_ADC4_NONE (0x00000000) /* !< TIM20_ETR is not connected to any AWD (analog watchdog) */
736 #define TIM_TIM20_ADC4_AWD1 (0x00000004) /* !< TIM20_ETR is connected to ADC4 AWD1 */
737 #define TIM_TIM20_ADC4_AWD2 (0x00000008) /* !< TIM20_ETR is connected to ADC4 AWD2 */
738 #define TIM_TIM20_ADC4_AWD3 (0x0000000C) /* !< TIM20_ETR is connected to ADC4 AWD3 */
739
740 #define IS_TIM_REMAP2(REMAP2) (((REMAP2) == TIM_TIM1_ADC4_NONE) ||\
741 ((REMAP2) == TIM_TIM1_ADC4_AWD1) ||\
742 ((REMAP2) == TIM_TIM1_ADC4_AWD2) ||\
743 ((REMAP2) == TIM_TIM1_ADC4_AWD3) ||\
744 ((REMAP2) == TIM_TIM8_ADC3_NONE) ||\
745 ((REMAP2) == TIM_TIM8_ADC3_AWD1) ||\
746 ((REMAP2) == TIM_TIM8_ADC3_AWD2) ||\
747 ((REMAP2) == TIM_TIM8_ADC3_AWD3) ||\
748 ((REMAP2) == TIM_TIM16_NONE) ||\
749 ((REMAP2) == TIM_TIM20_ADC4_NONE) ||\
750 ((REMAP2) == TIM_TIM20_ADC4_AWD1) ||\
751 ((REMAP2) == TIM_TIM20_ADC4_AWD2) ||\
752 ((REMAP2) == TIM_TIM20_ADC4_AWD3))
753 /**
754 * @}
755 */
756 #endif /* STM32F303xE || STM32F398xx */
757
758
759 #if defined(STM32F373xC) || defined(STM32F378xx)
760 /** @defgroup TIMEx_Remap TIM Extended remapping
761 * @{
762 */
763
764 #define TIM_TIM2_TIM8_TRGO (0x00000000) /*!< TIM8 TRGOUT is connected to TIM2_ITR1 */
765 #define TIM_TIM2_ETH_PTP (0x00000400) /*!< PTP trigger output is connected to TIM2_ITR1 */
766 #define TIM_TIM2_USBFS_SOF (0x00000800) /*!< OTG FS SOF is connected to the TIM2_ITR1 input */
767 #define TIM_TIM2_USBHS_SOF (0x00000C00) /*!< OTG HS SOF is connected to the TIM2_ITR1 input */
768 #define TIM_TIM14_GPIO (0x00000000) /* !< TIM14 TI1 is connected to GPIO */
769 #define TIM_TIM14_RTC (0x00000001) /* !< TIM14 TI1 is connected to RTC_clock */
770 #define TIM_TIM14_HSE (0x00000002) /* !< TIM14 TI1 is connected to HSE/32 */
771 #define TIM_TIM14_MCO (0x00000003) /* !< TIM14 TI1 is connected to MCO */
772
773 #define IS_TIM_REMAP(REMAP) (((REMAP) == TIM_TIM2_TIM8_TRGO) ||\
774 ((REMAP) == TIM_TIM2_ETH_PTP) ||\
775 ((REMAP) == TIM_TIM2_USBFS_SOF) ||\
776 ((REMAP) == TIM_TIM2_USBHS_SOF) ||\
777 ((REMAP) == TIM_TIM14_GPIO) ||\
778 ((REMAP) == TIM_TIM14_RTC) ||\
779 ((REMAP) == TIM_TIM14_HSE) ||\
780 ((REMAP) == TIM_TIM14_MCO))
781
782 /**
783 * @}
784 */
785 #endif /* STM32F373xC || STM32F378xx */
786
787 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
788 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
789 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
790 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
791 /** @defgroup TIMEx_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
792 * @{
793 */
794 #define TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
795 #define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
796 #define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
797 #define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
798
799 #define IS_TIM_GROUPCH5(OCREF) ((((OCREF) & 0x1FFFFFFF) == 0x00000000))
800 /**
801 * @}
802 */
803 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
804 /* STM32F302xC || STM32F303xC || STM32F358xx || */
805 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
806 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
807
808 /** @defgroup TIM_Clock_Filter TIM Clock Filter
809 * @{
810 */
811 #define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFF)
812 /**
813 * @}
814 */
815
816 /**
817 * @}
818 */
819
820 /* Exported macro ------------------------------------------------------------*/
821 /** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
822 * @{
823 */
824
825 #if defined(STM32F373xC) || defined(STM32F378xx)
826 /**
827 * @brief Sets the TIM Capture Compare Register value on runtime without
828 * calling another time ConfigChannel function.
829 * @param __HANDLE__: TIM handle.
830 * @param __CHANNEL__ : TIM Channels to be configured.
831 * This parameter can be one of the following values:
832 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
833 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
834 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
835 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
836 * @param __COMPARE__: specifies the Capture Compare register new value.
837 * @retval None
838 */
839 #define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
840 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
841
842 /**
843 * @brief Gets the TIM Capture Compare Register value on runtime
844 * @param __HANDLE__: TIM handle.
845 * @param __CHANNEL__ : TIM Channel associated with the capture compare register
846 * This parameter can be one of the following values:
847 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
848 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
849 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
850 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
851 * @retval None
852 */
853 #define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \
854 (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
855 #endif /* STM32F373xC || STM32F378xx */
856
857 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
858 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
859 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
860 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
861 /**
862 * @brief Sets the TIM Capture Compare Register value on runtime without
863 * calling another time ConfigChannel function.
864 * @param __HANDLE__: TIM handle.
865 * @param __CHANNEL__ : TIM Channels to be configured.
866 * This parameter can be one of the following values:
867 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
868 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
869 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
870 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
871 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
872 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
873 * @param __COMPARE__: specifies the Capture Compare register new value.
874 * @retval None
875 */
876 #define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
877 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
878 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
879 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
880 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
881 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
882 ((__HANDLE__)->Instance->CCR6 |= (__COMPARE__)))
883
884 /**
885 * @brief Gets the TIM Capture Compare Register value on runtime
886 * @param __HANDLE__: TIM handle.
887 * @param __CHANNEL__ : TIM Channel associated with the capture compare register
888 * This parameter can be one of the following values:
889 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
890 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
891 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
892 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
893 * @arg TIM_CHANNEL_5: get capture/compare 5 register value
894 * @arg TIM_CHANNEL_6: get capture/compare 6 register value
895 * @retval None
896 */
897 #define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \
898 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
899 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
900 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
901 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
902 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
903 ((__HANDLE__)->Instance->CCR6))
904 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
905 /* STM32F302xC || STM32F303xC || STM32F358xx || */
906 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
907 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
908 /**
909 * @}
910 */
911
912 /* Exported functions --------------------------------------------------------*/
913 /** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
914 * @{
915 */
916
917 /** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
918 * @brief Timer Hall Sensor functions
919 * @{
920 */
921 /* Timer Hall Sensor functions **********************************************/
922 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig);
923 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
924
925 void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
926 void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
927
928 /* Blocking mode: Polling */
929 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
930 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
931 /* Non-Blocking mode: Interrupt */
932 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
933 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
934 /* Non-Blocking mode: DMA */
935 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
936 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
937 /**
938 * @}
939 */
940
941 /** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
942 * @brief Timer Complementary Output Compare functions
943 * @{
944 */
945 /* Timer Complementary Output Compare functions *****************************/
946 /* Blocking mode: Polling */
947 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
948 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
949
950 /* Non-Blocking mode: Interrupt */
951 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
952 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
953
954 /* Non-Blocking mode: DMA */
955 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
956 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
957 /**
958 * @}
959 */
960
961 /** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
962 * @brief Timer Complementary PWM functions
963 * @{
964 */
965 /* Timer Complementary PWM functions ****************************************/
966 /* Blocking mode: Polling */
967 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
968 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
969
970 /* Non-Blocking mode: Interrupt */
971 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
972 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
973 /* Non-Blocking mode: DMA */
974 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
975 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
976 /**
977 * @}
978 */
979
980 /** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
981 * @brief Timer Complementary One Pulse functions
982 * @{
983 */
984 /* Timer Complementary One Pulse functions **********************************/
985 /* Blocking mode: Polling */
986 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
987 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
988
989 /* Non-Blocking mode: Interrupt */
990 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
991 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
992 /**
993 * @}
994 */
995
996 /** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
997 * @brief Peripheral Control functions
998 * @{
999 */
1000 /* Extended Control functions ************************************************/
1001 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
1002 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
1003 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
1004 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig);
1005 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
1006
1007 #if defined(STM32F303xE) || defined(STM32F398xx) || \
1008 defined(STM32F303xC) || defined(STM32F358xx)
1009 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap1, uint32_t Remap2);
1010 #endif /* STM32F303xE || STM32F398xx || */
1011 /* STM32F303xC || STM32F358xx */
1012
1013 #if defined(STM32F302xE) || \
1014 defined(STM32F302xC) || \
1015 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
1016 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
1017 defined(STM32F373xC) || defined(STM32F378xx)
1018 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
1019 #endif /* STM32F302xE || */
1020 /* STM32F302xC || */
1021 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
1022 /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
1023 /* STM32F373xC || STM32F378xx */
1024
1025 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
1026 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
1027 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
1028 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
1029 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
1030 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
1031 /* STM32F302xC || STM32F303xC || STM32F358xx || */
1032 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
1033 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
1034 /**
1035 * @}
1036 */
1037
1038 /** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
1039 * @brief Extended Callbacks functions
1040 * @{
1041 */
1042 /* Extended Callback *********************************************************/
1043 void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim);
1044 void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
1045 void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
1046 /**
1047 * @}
1048 */
1049
1050 /** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
1051 * @brief Extended Peripheral State functions
1052 * @{
1053 */
1054 /* Extended Peripheral State functions **************************************/
1055 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
1056 /**
1057 * @}
1058 */
1059
1060 /**
1061 * @}
1062 */
1063
1064 /**
1065 * @}
1066 */
1067
1068 /**
1069 * @}
1070 */
1071
1072 #ifdef __cplusplus
1073 }
1074 #endif
1075
1076
1077 #endif /* __STM32F3xx_HAL_TIM_EX_H */
1078
1079 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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