tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_dma.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f30x_dma.h
   4   * @author  MCD Application Team
   5   * @version V1.1.0
   6   * @date    27-February-2014
   7   * @brief   This file contains all the functions prototypes for the DMA firmware
   8   *          library.
   9   ******************************************************************************
  10   * @attention
  11   *
  12   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  13   *
  14   * Redistribution and use in source and binary forms, with or without modification,
  15   * are permitted provided that the following conditions are met:
  16   *   1. Redistributions of source code must retain the above copyright notice,
  17   *      this list of conditions and the following disclaimer.
  18   *   2. Redistributions in binary form must reproduce the above copyright notice,
  19   *      this list of conditions and the following disclaimer in the documentation
  20   *      and/or other materials provided with the distribution.
  21   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  22   *      may be used to endorse or promote products derived from this software
  23   *      without specific prior written permission.
  24   *
  25   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  26   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  27   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  28   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  29   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  30   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  31   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  32   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  33   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  34   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35   *
  36   ******************************************************************************
  37   */
  38
  39 /* Define to prevent recursive inclusion -------------------------------------*/
  40 #ifndef __STM32F30x_DMA_H
  41 #define __STM32F30x_DMA_H
  42
  43 #ifdef __cplusplus
  44  extern "C" {
  45 #endif
  46
  47 /* Includes ------------------------------------------------------------------*/
  48 #include "stm32f30x.h"
  49
  50 /** @addtogroup STM32F30x_StdPeriph_Driver
  51   * @{
  52   */
  53
  54 /** @addtogroup DMA
  55   * @{
  56   */
  57
  58 /* Exported types ------------------------------------------------------------*/
  59
  60 /**
  61   * @brief  DMA Init structures definition
  62   */
  63 typedef struct
  64 {
  65   uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx.              */
  66
  67   uint32_t DMA_MemoryBaseAddr;     /*!< Specifies the memory base address for DMAy Channelx.                  */
  68
  69   uint32_t DMA_DIR;                /*!< Specifies if the peripheral is the source or destination.
  70                                         This parameter can be a value of @ref DMA_data_transfer_direction     */
  71
  72   uint16_t DMA_BufferSize;         /*!< Specifies the buffer size, in data unit, of the specified Channel.
  73                                         The data unit is equal to the configuration set in DMA_PeripheralDataSize
  74                                         or DMA_MemoryDataSize members depending in the transfer direction.    */
  75
  76   uint32_t DMA_PeripheralInc;      /*!< Specifies whether the Peripheral address register is incremented or not.
  77                                         This parameter can be a value of @ref DMA_peripheral_incremented_mode */
  78
  79   uint32_t DMA_MemoryInc;          /*!< Specifies whether the memory address register is incremented or not.
  80                                         This parameter can be a value of @ref DMA_memory_incremented_mode     */
  81
  82   uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
  83                                         This parameter can be a value of @ref DMA_peripheral_data_size        */
  84
  85   uint32_t DMA_MemoryDataSize;     /*!< Specifies the Memory data width.
  86                                         This parameter can be a value of @ref DMA_memory_data_size            */
  87
  88   uint32_t DMA_Mode;               /*!< Specifies the operation mode of the DMAy Channelx.
  89                                         This parameter can be a value of @ref DMA_circular_normal_mode
  90                                         @note: The circular buffer mode cannot be used if the memory-to-memory
  91                                               data transfer is configured on the selected Channel */
  92
  93   uint32_t DMA_Priority;           /*!< Specifies the software priority for the DMAy Channelx.
  94                                         This parameter can be a value of @ref DMA_priority_level              */
  95
  96   uint32_t DMA_M2M;                /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
  97                                         This parameter can be a value of @ref DMA_memory_to_memory            */
  98 }DMA_InitTypeDef;
  99
 100 /* Exported constants --------------------------------------------------------*/
 101
 102 /** @defgroup DMA_Exported_Constants
 103   * @{
 104   */
 105
 106 #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
 107                                    ((PERIPH) == DMA1_Channel2) || \
 108                                    ((PERIPH) == DMA1_Channel3) || \
 109                                    ((PERIPH) == DMA1_Channel4) || \
 110                                    ((PERIPH) == DMA1_Channel5) || \
 111                                    ((PERIPH) == DMA1_Channel6) || \
 112                                    ((PERIPH) == DMA1_Channel7) || \
 113                                    ((PERIPH) == DMA2_Channel1) || \
 114                                    ((PERIPH) == DMA2_Channel2) || \
 115                                    ((PERIPH) == DMA2_Channel3) || \
 116                                    ((PERIPH) == DMA2_Channel4) || \
 117                                    ((PERIPH) == DMA2_Channel5))
 118
 119 /** @defgroup DMA_data_transfer_direction
 120   * @{
 121   */
 122
 123 #define DMA_DIR_PeripheralSRC              ((uint32_t)0x00000000)
 124 #define DMA_DIR_PeripheralDST              DMA_CCR_DIR
 125
 126 #define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \
 127                          ((DIR) == DMA_DIR_PeripheralDST))
 128 /**
 129   * @}
 130   */
 131
 132
 133 /** @defgroup DMA_peripheral_incremented_mode
 134   * @{
 135   */
 136
 137 #define DMA_PeripheralInc_Disable          ((uint32_t)0x00000000)
 138 #define DMA_PeripheralInc_Enable           DMA_CCR_PINC
 139
 140 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \
 141                                             ((STATE) == DMA_PeripheralInc_Enable))
 142 /**
 143   * @}
 144   */
 145
 146 /** @defgroup DMA_memory_incremented_mode
 147   * @{
 148   */
 149
 150 #define DMA_MemoryInc_Disable              ((uint32_t)0x00000000)
 151 #define DMA_MemoryInc_Enable               DMA_CCR_MINC
 152
 153 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \
 154                                         ((STATE) == DMA_MemoryInc_Enable))
 155 /**
 156   * @}
 157   */
 158
 159 /** @defgroup DMA_peripheral_data_size
 160   * @{
 161   */
 162
 163 #define DMA_PeripheralDataSize_Byte        ((uint32_t)0x00000000)
 164 #define DMA_PeripheralDataSize_HalfWord    DMA_CCR_PSIZE_0
 165 #define DMA_PeripheralDataSize_Word        DMA_CCR_PSIZE_1
 166
 167 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
 168                                            ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
 169                                            ((SIZE) == DMA_PeripheralDataSize_Word))
 170 /**
 171   * @}
 172   */
 173
 174 /** @defgroup DMA_memory_data_size
 175   * @{
 176   */
 177
 178 #define DMA_MemoryDataSize_Byte            ((uint32_t)0x00000000)
 179 #define DMA_MemoryDataSize_HalfWord        DMA_CCR_MSIZE_0
 180 #define DMA_MemoryDataSize_Word            DMA_CCR_MSIZE_1
 181
 182 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
 183                                        ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
 184                                        ((SIZE) == DMA_MemoryDataSize_Word))
 185 /**
 186   * @}
 187   */
 188
 189 /** @defgroup DMA_circular_normal_mode
 190   * @{
 191   */
 192
 193 #define DMA_Mode_Normal                    ((uint32_t)0x00000000)
 194 #define DMA_Mode_Circular                  DMA_CCR_CIRC
 195
 196 #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular))
 197 /**
 198   * @}
 199   */
 200
 201 /** @defgroup DMA_priority_level
 202   * @{
 203   */
 204
 205 #define DMA_Priority_VeryHigh              DMA_CCR_PL
 206 #define DMA_Priority_High                  DMA_CCR_PL_1
 207 #define DMA_Priority_Medium                DMA_CCR_PL_0
 208 #define DMA_Priority_Low                   ((uint32_t)0x00000000)
 209
 210 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
 211                                    ((PRIORITY) == DMA_Priority_High) || \
 212                                    ((PRIORITY) == DMA_Priority_Medium) || \
 213                                    ((PRIORITY) == DMA_Priority_Low))
 214 /**
 215   * @}
 216   */
 217
 218 /** @defgroup DMA_memory_to_memory
 219   * @{
 220   */
 221
 222 #define DMA_M2M_Disable                    ((uint32_t)0x00000000)
 223 #define DMA_M2M_Enable                     DMA_CCR_MEM2MEM
 224
 225 #define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable))
 226
 227 /**
 228   * @}
 229   */
 230
 231 /** @defgroup DMA_interrupts_definition
 232   * @{
 233   */
 234
 235 #define DMA_IT_TC                          ((uint32_t)0x00000002)
 236 #define DMA_IT_HT                          ((uint32_t)0x00000004)
 237 #define DMA_IT_TE                          ((uint32_t)0x00000008)
 238 #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
 239
 240 #define DMA1_IT_GL1                        ((uint32_t)0x00000001)
 241 #define DMA1_IT_TC1                        ((uint32_t)0x00000002)
 242 #define DMA1_IT_HT1                        ((uint32_t)0x00000004)
 243 #define DMA1_IT_TE1                        ((uint32_t)0x00000008)
 244 #define DMA1_IT_GL2                        ((uint32_t)0x00000010)
 245 #define DMA1_IT_TC2                        ((uint32_t)0x00000020)
 246 #define DMA1_IT_HT2                        ((uint32_t)0x00000040)
 247 #define DMA1_IT_TE2                        ((uint32_t)0x00000080)
 248 #define DMA1_IT_GL3                        ((uint32_t)0x00000100)
 249 #define DMA1_IT_TC3                        ((uint32_t)0x00000200)
 250 #define DMA1_IT_HT3                        ((uint32_t)0x00000400)
 251 #define DMA1_IT_TE3                        ((uint32_t)0x00000800)
 252 #define DMA1_IT_GL4                        ((uint32_t)0x00001000)
 253 #define DMA1_IT_TC4                        ((uint32_t)0x00002000)
 254 #define DMA1_IT_HT4                        ((uint32_t)0x00004000)
 255 #define DMA1_IT_TE4                        ((uint32_t)0x00008000)
 256 #define DMA1_IT_GL5                        ((uint32_t)0x00010000)
 257 #define DMA1_IT_TC5                        ((uint32_t)0x00020000)
 258 #define DMA1_IT_HT5                        ((uint32_t)0x00040000)
 259 #define DMA1_IT_TE5                        ((uint32_t)0x00080000)
 260 #define DMA1_IT_GL6                        ((uint32_t)0x00100000)
 261 #define DMA1_IT_TC6                        ((uint32_t)0x00200000)
 262 #define DMA1_IT_HT6                        ((uint32_t)0x00400000)
 263 #define DMA1_IT_TE6                        ((uint32_t)0x00800000)
 264 #define DMA1_IT_GL7                        ((uint32_t)0x01000000)
 265 #define DMA1_IT_TC7                        ((uint32_t)0x02000000)
 266 #define DMA1_IT_HT7                        ((uint32_t)0x04000000)
 267 #define DMA1_IT_TE7                        ((uint32_t)0x08000000)
 268
 269 #define DMA2_IT_GL1                        ((uint32_t)0x10000001)
 270 #define DMA2_IT_TC1                        ((uint32_t)0x10000002)
 271 #define DMA2_IT_HT1                        ((uint32_t)0x10000004)
 272 #define DMA2_IT_TE1                        ((uint32_t)0x10000008)
 273 #define DMA2_IT_GL2                        ((uint32_t)0x10000010)
 274 #define DMA2_IT_TC2                        ((uint32_t)0x10000020)
 275 #define DMA2_IT_HT2                        ((uint32_t)0x10000040)
 276 #define DMA2_IT_TE2                        ((uint32_t)0x10000080)
 277 #define DMA2_IT_GL3                        ((uint32_t)0x10000100)
 278 #define DMA2_IT_TC3                        ((uint32_t)0x10000200)
 279 #define DMA2_IT_HT3                        ((uint32_t)0x10000400)
 280 #define DMA2_IT_TE3                        ((uint32_t)0x10000800)
 281 #define DMA2_IT_GL4                        ((uint32_t)0x10001000)
 282 #define DMA2_IT_TC4                        ((uint32_t)0x10002000)
 283 #define DMA2_IT_HT4                        ((uint32_t)0x10004000)
 284 #define DMA2_IT_TE4                        ((uint32_t)0x10008000)
 285 #define DMA2_IT_GL5                        ((uint32_t)0x10010000)
 286 #define DMA2_IT_TC5                        ((uint32_t)0x10020000)
 287 #define DMA2_IT_HT5                        ((uint32_t)0x10040000)
 288 #define DMA2_IT_TE5                        ((uint32_t)0x10080000)
 289
 290 #define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
 291
 292 #define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
 293                            ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
 294                            ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
 295                            ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
 296                            ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
 297                            ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
 298                            ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
 299                            ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
 300                            ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
 301                            ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
 302                            ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
 303                            ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
 304                            ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
 305                            ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
 306                            ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
 307                            ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
 308                            ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
 309                            ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
 310                            ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
 311                            ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
 312                            ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
 313                            ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
 314                            ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
 315                            ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
 316
 317 /**
 318   * @}
 319   */
 320
 321 /** @defgroup DMA_flags_definition
 322   * @{
 323   */
 324
 325 #define DMA1_FLAG_GL1                      ((uint32_t)0x00000001)
 326 #define DMA1_FLAG_TC1                      ((uint32_t)0x00000002)
 327 #define DMA1_FLAG_HT1                      ((uint32_t)0x00000004)
 328 #define DMA1_FLAG_TE1                      ((uint32_t)0x00000008)
 329 #define DMA1_FLAG_GL2                      ((uint32_t)0x00000010)
 330 #define DMA1_FLAG_TC2                      ((uint32_t)0x00000020)
 331 #define DMA1_FLAG_HT2                      ((uint32_t)0x00000040)
 332 #define DMA1_FLAG_TE2                      ((uint32_t)0x00000080)
 333 #define DMA1_FLAG_GL3                      ((uint32_t)0x00000100)
 334 #define DMA1_FLAG_TC3                      ((uint32_t)0x00000200)
 335 #define DMA1_FLAG_HT3                      ((uint32_t)0x00000400)
 336 #define DMA1_FLAG_TE3                      ((uint32_t)0x00000800)
 337 #define DMA1_FLAG_GL4                      ((uint32_t)0x00001000)
 338 #define DMA1_FLAG_TC4                      ((uint32_t)0x00002000)
 339 #define DMA1_FLAG_HT4                      ((uint32_t)0x00004000)
 340 #define DMA1_FLAG_TE4                      ((uint32_t)0x00008000)
 341 #define DMA1_FLAG_GL5                      ((uint32_t)0x00010000)
 342 #define DMA1_FLAG_TC5                      ((uint32_t)0x00020000)
 343 #define DMA1_FLAG_HT5                      ((uint32_t)0x00040000)
 344 #define DMA1_FLAG_TE5                      ((uint32_t)0x00080000)
 345 #define DMA1_FLAG_GL6                      ((uint32_t)0x00100000)
 346 #define DMA1_FLAG_TC6                      ((uint32_t)0x00200000)
 347 #define DMA1_FLAG_HT6                      ((uint32_t)0x00400000)
 348 #define DMA1_FLAG_TE6                      ((uint32_t)0x00800000)
 349 #define DMA1_FLAG_GL7                      ((uint32_t)0x01000000)
 350 #define DMA1_FLAG_TC7                      ((uint32_t)0x02000000)
 351 #define DMA1_FLAG_HT7                      ((uint32_t)0x04000000)
 352 #define DMA1_FLAG_TE7                      ((uint32_t)0x08000000)
 353
 354 #define DMA2_FLAG_GL1                      ((uint32_t)0x10000001)
 355 #define DMA2_FLAG_TC1                      ((uint32_t)0x10000002)
 356 #define DMA2_FLAG_HT1                      ((uint32_t)0x10000004)
 357 #define DMA2_FLAG_TE1                      ((uint32_t)0x10000008)
 358 #define DMA2_FLAG_GL2                      ((uint32_t)0x10000010)
 359 #define DMA2_FLAG_TC2                      ((uint32_t)0x10000020)
 360 #define DMA2_FLAG_HT2                      ((uint32_t)0x10000040)
 361 #define DMA2_FLAG_TE2                      ((uint32_t)0x10000080)
 362 #define DMA2_FLAG_GL3                      ((uint32_t)0x10000100)
 363 #define DMA2_FLAG_TC3                      ((uint32_t)0x10000200)
 364 #define DMA2_FLAG_HT3                      ((uint32_t)0x10000400)
 365 #define DMA2_FLAG_TE3                      ((uint32_t)0x10000800)
 366 #define DMA2_FLAG_GL4                      ((uint32_t)0x10001000)
 367 #define DMA2_FLAG_TC4                      ((uint32_t)0x10002000)
 368 #define DMA2_FLAG_HT4                      ((uint32_t)0x10004000)
 369 #define DMA2_FLAG_TE4                      ((uint32_t)0x10008000)
 370 #define DMA2_FLAG_GL5                      ((uint32_t)0x10010000)
 371 #define DMA2_FLAG_TC5                      ((uint32_t)0x10020000)
 372 #define DMA2_FLAG_HT5                      ((uint32_t)0x10040000)
 373 #define DMA2_FLAG_TE5                      ((uint32_t)0x10080000)
 374
 375 #define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
 376
 377 #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
 378                                ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
 379                                ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
 380                                ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
 381                                ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
 382                                ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
 383                                ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
 384                                ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
 385                                ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
 386                                ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
 387                                ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
 388                                ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
 389                                ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
 390                                ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
 391                                ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
 392                                ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
 393                                ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
 394                                ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
 395                                ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
 396                                ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
 397                                ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
 398                                ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
 399                                ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
 400                                ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
 401
 402 /**
 403   * @}
 404   */
 405
 406 /**
 407   * @}
 408   */
 409
 410 /* Exported macro ------------------------------------------------------------*/
 411 /* Exported functions ------------------------------------------------------- */
 412
 413 /* Function used to set the DMA configuration to the default reset state ******/
 414 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
 415
 416 /* Initialization and Configuration functions *********************************/
 417 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
 418 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
 419 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
 420
 421 /* Data Counter functions******************************************************/
 422 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
 423 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
 424
 425 /* Interrupts and flags management functions **********************************/
 426 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
 427 FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
 428 void DMA_ClearFlag(uint32_t DMAy_FLAG);
 429 ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
 430 void DMA_ClearITPendingBit(uint32_t DMAy_IT);
 431
 432 #ifdef __cplusplus
 433 }
 434 #endif
 435
 436 #endif /*__STM32F30x_DMA_H */
 437
 438 /**
 439   * @}
 440   */
 441
 442 /**
 443   * @}
 444   */
 445
 446 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/