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[tmk_keyboard.git] / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_STM / TARGET_STM32F3XX / stm32f30x_rcc.c
1 /**
2 ******************************************************************************
3 * @file stm32f30x_rcc.c
4 * @author MCD Application Team
5 * @version V1.1.0
6 * @date 27-February-2014
7 * @brief This file provides firmware functions to manage the following
8 * functionalities of the Reset and clock control (RCC) peripheral:
9 * + Internal/external clocks, PLL, CSS and MCO configuration
10 * + System, AHB and APB busses clocks configuration
11 * + Peripheral clocks configuration
12 * + Interrupts and flags management
13 *
14 @verbatim
15
16 ===============================================================================
17 ##### RCC specific features #####
18 ===============================================================================
19 [..] After reset the device is running from HSI (8 MHz) with Flash 0 WS,
20 all peripherals are off except internal SRAM, Flash and SWD.
21 (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
22 all peripherals mapped on these busses are running at HSI speed.
23 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
24 (+) All GPIOs are in input floating state, except the SWD pins which
25 are assigned to be used for debug purpose.
26 [..] Once the device starts from reset, the user application has to:
27 (+) Configure the clock source to be used to drive the System clock
28 (if the application needs higher frequency/performance).
29 (+) Configure the System clock frequency and Flash settings.
30 (+) Configure the AHB and APB busses prescalers.
31 (+) Enable the clock for the peripheral(s) to be used.
32 (+) Configure the clock source(s) for peripherals which clocks are not
33 derived from the System clock (ADC, TIM, I2C, USART, RTC and IWDG).
34
35 @endverbatim
36
37 ******************************************************************************
38 * @attention
39 *
40 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
41 *
42 * Redistribution and use in source and binary forms, with or without modification,
43 * are permitted provided that the following conditions are met:
44 * 1. Redistributions of source code must retain the above copyright notice,
45 * this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright notice,
47 * this list of conditions and the following disclaimer in the documentation
48 * and/or other materials provided with the distribution.
49 * 3. Neither the name of STMicroelectronics nor the names of its contributors
50 * may be used to endorse or promote products derived from this software
51 * without specific prior written permission.
52 *
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
54 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
56 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
60 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
61 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 *
64 ******************************************************************************
65 */
66
67 /* Includes ------------------------------------------------------------------*/
68 #include "stm32f30x_rcc.h"
69
70 /** @addtogroup STM32F30x_StdPeriph_Driver
71 * @{
72 */
73
74 /** @defgroup RCC
75 * @brief RCC driver modules
76 * @{
77 */
78
79 /* Private typedef -----------------------------------------------------------*/
80 /* Private define ------------------------------------------------------------*/
81 /* ------------ RCC registers bit address in the alias region ----------- */
82 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
83
84 /* --- CR Register ---*/
85
86 /* Alias word address of HSION bit */
87 #define CR_OFFSET (RCC_OFFSET + 0x00)
88 #define HSION_BitNumber 0x00
89 #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
90
91 /* Alias word address of PLLON bit */
92 #define PLLON_BitNumber 0x18
93 #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
94
95 /* Alias word address of CSSON bit */
96 #define CSSON_BitNumber 0x13
97 #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
98
99 /* --- CFGR Register ---*/
100 /* Alias word address of USBPRE bit */
101 #define CFGR_OFFSET (RCC_OFFSET + 0x04)
102 #define USBPRE_BitNumber 0x16
103 #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
104 /* Alias word address of I2SSRC bit */
105 #define I2SSRC_BitNumber 0x17
106 #define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
107
108 /* --- BDCR Register ---*/
109
110 /* Alias word address of RTCEN bit */
111 #define BDCR_OFFSET (RCC_OFFSET + 0x20)
112 #define RTCEN_BitNumber 0x0F
113 #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
114
115 /* Alias word address of BDRST bit */
116 #define BDRST_BitNumber 0x10
117 #define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
118
119 /* --- CSR Register ---*/
120
121 /* Alias word address of LSION bit */
122 #define CSR_OFFSET (RCC_OFFSET + 0x24)
123 #define LSION_BitNumber 0x00
124 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
125
126 /* ---------------------- RCC registers bit mask ------------------------ */
127 /* RCC Flag Mask */
128 #define FLAG_MASK ((uint8_t)0x1F)
129
130 /* CFGR register byte 3 (Bits[31:23]) base address */
131 #define CFGR_BYTE3_ADDRESS ((uint32_t)0x40021007)
132
133 /* CIR register byte 2 (Bits[15:8]) base address */
134 #define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009)
135
136 /* CIR register byte 3 (Bits[23:16]) base address */
137 #define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A)
138
139 /* CR register byte 2 (Bits[23:16]) base address */
140 #define CR_BYTE2_ADDRESS ((uint32_t)0x40021002)
141
142 /* Private macro -------------------------------------------------------------*/
143 /* Private variables ---------------------------------------------------------*/
144 const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
145 const uint16_t ADCPrescTable[16] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256, 0, 0, 0, 0 };
146
147 /* Private function prototypes -----------------------------------------------*/
148 /* Private functions ---------------------------------------------------------*/
149
150 /** @defgroup RCC_Private_Functions
151 * @{
152 */
153
154 /** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
155 * @brief Internal and external clocks, PLL, CSS and MCO configuration functions
156 *
157 @verbatim
158 ===============================================================================
159 ##### Internal-external clocks, PLL, CSS and MCO configuration functions #####
160 ===============================================================================
161 [..] This section provides functions allowing to configure the internal/external
162 clocks, PLL, CSS and MCO.
163 (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly
164 or through the PLL as System clock source.
165 The HSI clock can be used also to clock the USART and I2C peripherals.
166 (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC
167 clock source.
168 (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or
169 through the PLL as System clock source. Can be used also as RTC clock source.
170 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
171 LSE can be used also to clock the USART peripherals.
172 (#) PLL (clocked by HSI or HSE), for System clock.
173 (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs
174 (HSE used directly or through PLL as System clock source), the System clock
175 is automatically switched to HSI and an interrupt is generated if enabled.
176 The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt)
177 exception vector.
178 (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE,
179 PLL clock on PA8 pin.
180
181 @endverbatim
182 * @{
183 */
184
185 /**
186 * @brief Resets the RCC clock configuration to the default reset state.
187 * @note The default reset state of the clock configuration is given below:
188 * @note HSI ON and used as system clock source
189 * @note HSE and PLL OFF
190 * @note AHB, APB1 and APB2 prescalers set to 1.
191 * @note CSS and MCO OFF
192 * @note All interrupts disabled
193 * @note However, this function doesn't modify the configuration of the
194 * @note Peripheral clocks
195 * @note LSI, LSE and RTC clocks
196 * @param None
197 * @retval None
198 */
199 void RCC_DeInit(void)
200 {
201 /* Set HSION bit */
202 RCC->CR |= (uint32_t)0x00000001;
203
204 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */
205 RCC->CFGR &= (uint32_t)0xF8FFC000;
206
207 /* Reset HSEON, CSSON and PLLON bits */
208 RCC->CR &= (uint32_t)0xFEF6FFFF;
209
210 /* Reset HSEBYP bit */
211 RCC->CR &= (uint32_t)0xFFFBFFFF;
212
213 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
214 RCC->CFGR &= (uint32_t)0xFF80FFFF;
215
216 /* Reset PREDIV1[3:0] and ADCPRE[13:4] bits */
217 RCC->CFGR2 &= (uint32_t)0xFFFFC000;
218
219 /* Reset USARTSW[1:0], I2CSW and TIMSW bits */
220 RCC->CFGR3 &= (uint32_t)0xF00ECCC;
221
222 /* Disable all interrupts */
223 RCC->CIR = 0x00000000;
224 }
225
226 /**
227 * @brief Configures the External High Speed oscillator (HSE).
228 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
229 * software should wait on HSERDY flag to be set indicating that HSE clock
230 * is stable and can be used to clock the PLL and/or system clock.
231 * @note HSE state can not be changed if it is used directly or through the
232 * PLL as system clock. In this case, you have to select another source
233 * of the system clock then change the HSE state (ex. disable it).
234 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
235 * @note This function resets the CSSON bit, so if the Clock security system(CSS)
236 * was previously enabled you have to enable it again after calling this
237 * function.
238 * @param RCC_HSE: specifies the new state of the HSE.
239 * This parameter can be one of the following values:
240 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
241 * 6 HSE oscillator clock cycles.
242 * @arg RCC_HSE_ON: turn ON the HSE oscillator
243 * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
244 * @retval None
245 */
246 void RCC_HSEConfig(uint8_t RCC_HSE)
247 {
248 /* Check the parameters */
249 assert_param(IS_RCC_HSE(RCC_HSE));
250
251 /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
252 *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE_OFF;
253
254 /* Set the new HSE configuration -------------------------------------------*/
255 *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE;
256
257 }
258
259 /**
260 * @brief Waits for HSE start-up.
261 * @note This function waits on HSERDY flag to be set and return SUCCESS if
262 * this flag is set, otherwise returns ERROR if the timeout is reached
263 * and this flag is not set. The timeout value is defined by the constant
264 * HSE_STARTUP_TIMEOUT in stm32f30x.h file. You can tailor it depending
265 * on the HSE crystal used in your application.
266 * @param None
267 * @retval An ErrorStatus enumeration value:
268 * - SUCCESS: HSE oscillator is stable and ready to use
269 * - ERROR: HSE oscillator not yet ready
270 */
271 ErrorStatus RCC_WaitForHSEStartUp(void)
272 {
273 __IO uint32_t StartUpCounter = 0;
274 ErrorStatus status = ERROR;
275 FlagStatus HSEStatus = RESET;
276
277 /* Wait till HSE is ready and if timeout is reached exit */
278 do
279 {
280 HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
281 StartUpCounter++;
282 } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
283
284 if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
285 {
286 status = SUCCESS;
287 }
288 else
289 {
290 status = ERROR;
291 }
292 return (status);
293 }
294
295 /**
296 * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
297 * @note The calibration is used to compensate for the variations in voltage
298 * and temperature that influence the frequency of the internal HSI RC.
299 * Refer to the Application Note AN3300 for more details on how to
300 * calibrate the HSI.
301 * @param HSICalibrationValue: specifies the HSI calibration trimming value.
302 * This parameter must be a number between 0 and 0x1F.
303 * @retval None
304 */
305 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
306 {
307 uint32_t tmpreg = 0;
308
309 /* Check the parameters */
310 assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue));
311
312 tmpreg = RCC->CR;
313
314 /* Clear HSITRIM[4:0] bits */
315 tmpreg &= ~RCC_CR_HSITRIM;
316
317 /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
318 tmpreg |= (uint32_t)HSICalibrationValue << 3;
319
320 /* Store the new value */
321 RCC->CR = tmpreg;
322 }
323
324 /**
325 * @brief Enables or disables the Internal High Speed oscillator (HSI).
326 * @note After enabling the HSI, the application software should wait on
327 * HSIRDY flag to be set indicating that HSI clock is stable and can
328 * be used to clock the PLL and/or system clock.
329 * @note HSI can not be stopped if it is used directly or through the PLL
330 * as system clock. In this case, you have to select another source
331 * of the system clock then stop the HSI.
332 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
333 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
334 * clock cycles.
335 * @param NewState: new state of the HSI.
336 * This parameter can be: ENABLE or DISABLE.
337 * @retval None
338 */
339 void RCC_HSICmd(FunctionalState NewState)
340 {
341 /* Check the parameters */
342 assert_param(IS_FUNCTIONAL_STATE(NewState));
343
344 *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
345 }
346
347 /**
348 * @brief Configures the External Low Speed oscillator (LSE).
349 * @note As the LSE is in the Backup domain and write access is denied to this
350 * domain after reset, you have to enable write access using
351 * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE
352 * (to be done once after reset).
353 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application
354 * software should wait on LSERDY flag to be set indicating that LSE clock
355 * is stable and can be used to clock the RTC.
356 * @param RCC_LSE: specifies the new state of the LSE.
357 * This parameter can be one of the following values:
358 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
359 * 6 LSE oscillator clock cycles.
360 * @arg RCC_LSE_ON: turn ON the LSE oscillator
361 * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
362 * @retval None
363 */
364 void RCC_LSEConfig(uint32_t RCC_LSE)
365 {
366 /* Check the parameters */
367 assert_param(IS_RCC_LSE(RCC_LSE));
368
369 /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
370 /* Reset LSEON bit */
371 RCC->BDCR &= ~(RCC_BDCR_LSEON);
372
373 /* Reset LSEBYP bit */
374 RCC->BDCR &= ~(RCC_BDCR_LSEBYP);
375
376 /* Configure LSE */
377 RCC->BDCR |= RCC_LSE;
378 }
379
380 /**
381 * @brief Configures the External Low Speed oscillator (LSE) drive capability.
382 * @param RCC_LSEDrive: specifies the new state of the LSE drive capability.
383 * This parameter can be one of the following values:
384 * @arg RCC_LSEDrive_Low: LSE oscillator low drive capability.
385 * @arg RCC_LSEDrive_MediumLow: LSE oscillator medium low drive capability.
386 * @arg RCC_LSEDrive_MediumHigh: LSE oscillator medium high drive capability.
387 * @arg RCC_LSEDrive_High: LSE oscillator high drive capability.
388 * @retval None
389 */
390 void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive)
391 {
392 /* Check the parameters */
393 assert_param(IS_RCC_LSE_DRIVE(RCC_LSEDrive));
394
395 /* Clear LSEDRV[1:0] bits */
396 RCC->BDCR &= ~(RCC_BDCR_LSEDRV);
397
398 /* Set the LSE Drive */
399 RCC->BDCR |= RCC_LSEDrive;
400 }
401
402 /**
403 * @brief Enables or disables the Internal Low Speed oscillator (LSI).
404 * @note After enabling the LSI, the application software should wait on
405 * LSIRDY flag to be set indicating that LSI clock is stable and can
406 * be used to clock the IWDG and/or the RTC.
407 * @note LSI can not be disabled if the IWDG is running.
408 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
409 * clock cycles.
410 * @param NewState: new state of the LSI.
411 * This parameter can be: ENABLE or DISABLE.
412 * @retval None
413 */
414 void RCC_LSICmd(FunctionalState NewState)
415 {
416 /* Check the parameters */
417 assert_param(IS_FUNCTIONAL_STATE(NewState));
418
419 *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
420 }
421
422 /**
423 * @brief Configures the PLL clock source and multiplication factor.
424 * @note This function must be used only when the PLL is disabled.
425 * @note The minimum input clock frequency for PLL is 2 MHz (when using HSE as
426 * PLL source).
427 * @param RCC_PLLSource: specifies the PLL entry clock source.
428 * This parameter can be one of the following values:
429 * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as
430 * PLL clock entry
431 * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock source
432 * @param RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock
433 * This parameter can be RCC_PLLMul_x where x:[2,16]
434 *
435 * @retval None
436 */
437 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
438 {
439 /* Check the parameters */
440 assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
441 assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
442
443 /* Clear PLL Source [16] and Multiplier [21:18] bits */
444 RCC->CFGR &= ~(RCC_CFGR_PLLMULL | RCC_CFGR_PLLSRC);
445
446 /* Set the PLL Source and Multiplier */
447 RCC->CFGR |= (uint32_t)(RCC_PLLSource | RCC_PLLMul);
448 }
449
450 /**
451 * @brief Enables or disables the PLL.
452 * @note After enabling the PLL, the application software should wait on
453 * PLLRDY flag to be set indicating that PLL clock is stable and can
454 * be used as system clock source.
455 * @note The PLL can not be disabled if it is used as system clock source
456 * @note The PLL is disabled by hardware when entering STOP and STANDBY modes.
457 * @param NewState: new state of the PLL.
458 * This parameter can be: ENABLE or DISABLE.
459 * @retval None
460 */
461 void RCC_PLLCmd(FunctionalState NewState)
462 {
463 /* Check the parameters */
464 assert_param(IS_FUNCTIONAL_STATE(NewState));
465
466 *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
467 }
468
469 /**
470 * @brief Configures the PREDIV1 division factor.
471 * @note This function must be used only when the PLL is disabled.
472 * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
473 * This parameter can be RCC_PREDIV1_Divx where x:[1,16]
474 * @retval None
475 */
476 void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div)
477 {
478 uint32_t tmpreg = 0;
479
480 /* Check the parameters */
481 assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));
482
483 tmpreg = RCC->CFGR2;
484 /* Clear PREDIV1[3:0] bits */
485 tmpreg &= ~(RCC_CFGR2_PREDIV1);
486
487 /* Set the PREDIV1 division factor */
488 tmpreg |= RCC_PREDIV1_Div;
489
490 /* Store the new value */
491 RCC->CFGR2 = tmpreg;
492 }
493
494 /**
495 * @brief Enables or disables the Clock Security System.
496 * @note If a failure is detected on the HSE oscillator clock, this oscillator
497 * is automatically disabled and an interrupt is generated to inform the
498 * software about the failure (Clock Security System Interrupt, CSSI),
499 * allowing the MCU to perform rescue operations. The CSSI is linked to
500 * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
501 * @param NewState: new state of the Clock Security System.
502 * This parameter can be: ENABLE or DISABLE.
503 * @retval None
504 */
505 void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
506 {
507 /* Check the parameters */
508 assert_param(IS_FUNCTIONAL_STATE(NewState));
509
510 *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
511 }
512
513 #ifdef STM32F303xC
514 /**
515 * @brief Selects the clock source to output on MCO pin (PA8).
516 * @note PA8 should be configured in alternate function mode.
517 * @param RCC_MCOSource: specifies the clock source to output.
518 * This parameter can be one of the following values:
519 * @arg RCC_MCOSource_NoClock: No clock selected.
520 * @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected.
521 * @arg RCC_MCOSource_LSI: LSI oscillator clock selected.
522 * @arg RCC_MCOSource_LSE: LSE oscillator clock selected.
523 * @arg RCC_MCOSource_SYSCLK: System clock selected.
524 * @arg RCC_MCOSource_HSI: HSI oscillator clock selected.
525 * @arg RCC_MCOSource_HSE: HSE oscillator clock selected.
526 * @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected.
527 * @arg RCC_MCOSource_PLLCLK: PLL clock selected.
528 * @arg RCC_MCOSource_HSI48: HSI48 clock selected.
529 * @retval None
530 */
531 void RCC_MCOConfig(uint8_t RCC_MCOSource)
532 {
533 uint32_t tmpreg = 0;
534
535 /* Check the parameters */
536 assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
537
538 /* Get CFGR value */
539 tmpreg = RCC->CFGR;
540 /* Clear MCO[3:0] bits */
541 tmpreg &= ~(RCC_CFGR_MCO | RCC_CFGR_PLLNODIV);
542 /* Set the RCC_MCOSource */
543 tmpreg |= RCC_MCOSource<<24;
544 /* Store the new value */
545 RCC->CFGR = tmpreg;
546 }
547 #else
548
549 /**
550 * @brief Selects the clock source to output on MCO pin (PA8) and the corresponding
551 * prescsaler.
552 * @note PA8 should be configured in alternate function mode.
553 * @param RCC_MCOSource: specifies the clock source to output.
554 * This parameter can be one of the following values:
555 * @arg RCC_MCOSource_NoClock: No clock selected.
556 * @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected.
557 * @arg RCC_MCOSource_LSI: LSI oscillator clock selected.
558 * @arg RCC_MCOSource_LSE: LSE oscillator clock selected.
559 * @arg RCC_MCOSource_SYSCLK: System clock selected.
560 * @arg RCC_MCOSource_HSI: HSI oscillator clock selected.
561 * @arg RCC_MCOSource_HSE: HSE oscillator clock selected.
562 * @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected.
563 * @arg RCC_MCOSource_PLLCLK: PLL clock selected.
564 * @arg RCC_MCOSource_HSI48: HSI48 clock selected.
565 * @param RCC_MCOPrescaler: specifies the prescaler on MCO pin.
566 * This parameter can be one of the following values:
567 * @arg RCC_MCOPrescaler_1: MCO clock is divided by 1.
568 * @arg RCC_MCOPrescaler_2: MCO clock is divided by 2.
569 * @arg RCC_MCOPrescaler_4: MCO clock is divided by 4.
570 * @arg RCC_MCOPrescaler_8: MCO clock is divided by 8.
571 * @arg RCC_MCOPrescaler_16: MCO clock is divided by 16.
572 * @arg RCC_MCOPrescaler_32: MCO clock is divided by 32.
573 * @arg RCC_MCOPrescaler_64: MCO clock is divided by 64.
574 * @arg RCC_MCOPrescaler_128: MCO clock is divided by 128.
575 * @retval None
576 */
577 void RCC_MCOConfig(uint8_t RCC_MCOSource, uint32_t RCC_MCOPrescaler)
578 {
579 uint32_t tmpreg = 0;
580
581 /* Check the parameters */
582 assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
583 assert_param(IS_RCC_MCO_PRESCALER(RCC_MCOPrescaler));
584
585 /* Get CFGR value */
586 tmpreg = RCC->CFGR;
587 /* Clear MCOPRE[2:0] bits */
588 tmpreg &= ~(RCC_CFGR_MCO_PRE | RCC_CFGR_MCO | RCC_CFGR_PLLNODIV);
589 /* Set the RCC_MCOSource and RCC_MCOPrescaler */
590 tmpreg |= (RCC_MCOPrescaler | RCC_MCOSource<<24);
591 /* Store the new value */
592 RCC->CFGR = tmpreg;
593 }
594 #endif /* STM32F303xC */
595
596 /**
597 * @}
598 */
599
600 /** @defgroup RCC_Group2 System AHB, APB1 and APB2 busses clocks configuration functions
601 * @brief System, AHB and APB busses clocks configuration functions
602 *
603 @verbatim
604 ===============================================================================
605 ##### System, AHB, APB1 and APB2 busses clocks configuration functions #####
606 ===============================================================================
607 [..] This section provide functions allowing to configure the System, AHB, APB1 and
608 APB2 busses clocks.
609 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
610 HSE and PLL.
611 The AHB clock (HCLK) is derived from System clock through configurable prescaler
612 and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA and GPIO).
613 APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through
614 configurable prescalers and used to clock the peripherals mapped on these busses.
615 You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.
616
617 (#) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 72 MHz.
618 Depending on the maximum frequency, the FLASH wait states (WS) should be
619 adapted accordingly:
620 +---------------------------------+
621 | Wait states | HCLK clock |
622 | (Latency) | frequency (MHz) |
623 |-------------- |-----------------|
624 |0WS(1CPU cycle)| 0 < HCLK <= 24 |
625 |---------------|-----------------|
626 |1WS(2CPU cycle)|24 < HCLK <=48 |
627 |---------------|-----------------|
628 |2WS(3CPU cycle)|48 < HCLK <= 72 |
629 +---------------------------------+
630
631 (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
632 prefetch is disabled.
633 [..]
634 (@) All the peripheral clocks are derived from the System clock (SYSCLK)
635 except:
636 (+@) The FLASH program/erase clock which is always HSI 8MHz clock.
637 (+@) The USB 48 MHz clock which is derived from the PLL VCO clock.
638 (+@) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE.
639 (+@) The I2C clock which can be derived as well from HSI 8MHz clock.
640 (+@) The ADC clock which is derived from PLL output.
641 (+@) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC
642 (HSE divided by a programmable prescaler). The System clock (SYSCLK)
643 frequency must be higher or equal to the RTC clock frequency.
644 (+@) IWDG clock which is always the LSI clock.
645 [..] It is recommended to use the following software sequences to tune the number
646 of wait states needed to access the Flash memory with the CPU frequency (HCLK).
647 (+) Increasing the CPU frequency
648 (++) Program the Flash Prefetch buffer, using "FLASH_PrefetchBufferCmd(ENABLE)"
649 function
650 (++) Check that Flash Prefetch buffer activation is taken into account by
651 reading FLASH_ACR using the FLASH_GetPrefetchBufferStatus() function
652 (++) Program Flash WS to 1 or 2, using "FLASH_SetLatency()" function
653 (++) Check that the new number of WS is taken into account by reading FLASH_ACR
654 (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
655 (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
656 (++) Check that the new CPU clock source is taken into account by reading
657 the clock source status, using "RCC_GetSYSCLKSource()" function
658 (+) Decreasing the CPU frequency
659 (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
660 (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
661 (++) Check that the new CPU clock source is taken into account by reading
662 the clock source status, using "RCC_GetSYSCLKSource()" function
663 (++) Program the new number of WS, using "FLASH_SetLatency()" function
664 (++) Check that the new number of WS is taken into account by reading FLASH_ACR
665 (++) Disable the Flash Prefetch buffer using "FLASH_PrefetchBufferCmd(DISABLE)"
666 function
667 (++) Check that Flash Prefetch buffer deactivation is taken into account by reading FLASH_ACR
668 using the FLASH_GetPrefetchBufferStatus() function.
669
670 @endverbatim
671 * @{
672 */
673
674 /**
675 * @brief Configures the system clock (SYSCLK).
676 * @note The HSI is used (enabled by hardware) as system clock source after
677 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
678 * of failure of the HSE used directly or indirectly as system clock
679 * (if the Clock Security System CSS is enabled).
680 * @note A switch from one clock source to another occurs only if the target
681 * clock source is ready (clock stable after startup delay or PLL locked).
682 * If a clock source which is not yet ready is selected, the switch will
683 * occur when the clock source will be ready.
684 * You can use RCC_GetSYSCLKSource() function to know which clock is
685 * currently used as system clock source.
686 * @param RCC_SYSCLKSource: specifies the clock source used as system clock source
687 * This parameter can be one of the following values:
688 * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source
689 * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source
690 * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
691 * @retval None
692 */
693 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
694 {
695 uint32_t tmpreg = 0;
696
697 /* Check the parameters */
698 assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
699
700 tmpreg = RCC->CFGR;
701
702 /* Clear SW[1:0] bits */
703 tmpreg &= ~RCC_CFGR_SW;
704
705 /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
706 tmpreg |= RCC_SYSCLKSource;
707
708 /* Store the new value */
709 RCC->CFGR = tmpreg;
710 }
711
712 /**
713 * @brief Returns the clock source used as system clock.
714 * @param None
715 * @retval The clock source used as system clock. The returned value can be one
716 * of the following values:
717 * - 0x00: HSI used as system clock
718 * - 0x04: HSE used as system clock
719 * - 0x08: PLL used as system clock
720 */
721 uint8_t RCC_GetSYSCLKSource(void)
722 {
723 return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
724 }
725
726 /**
727 * @brief Configures the AHB clock (HCLK).
728 * @note Depending on the device voltage range, the software has to set correctly
729 * these bits to ensure that the system frequency does not exceed the
730 * maximum allowed frequency (for more details refer to section above
731 * "CPU, AHB and APB busses clocks configuration functions").
732 * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
733 * the system clock (SYSCLK).
734 * This parameter can be one of the following values:
735 * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
736 * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
737 * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
738 * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
739 * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
740 * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
741 * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
742 * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
743 * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
744 * @retval None
745 */
746 void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
747 {
748 uint32_t tmpreg = 0;
749
750 /* Check the parameters */
751 assert_param(IS_RCC_HCLK(RCC_SYSCLK));
752
753 tmpreg = RCC->CFGR;
754
755 /* Clear HPRE[3:0] bits */
756 tmpreg &= ~RCC_CFGR_HPRE;
757
758 /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
759 tmpreg |= RCC_SYSCLK;
760
761 /* Store the new value */
762 RCC->CFGR = tmpreg;
763 }
764
765 /**
766 * @brief Configures the Low Speed APB clock (PCLK1).
767 * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
768 * the AHB clock (HCLK).
769 * This parameter can be one of the following values:
770 * @arg RCC_HCLK_Div1: APB1 clock = HCLK
771 * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
772 * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
773 * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
774 * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
775 * @retval None
776 */
777 void RCC_PCLK1Config(uint32_t RCC_HCLK)
778 {
779 uint32_t tmpreg = 0;
780
781 /* Check the parameters */
782 assert_param(IS_RCC_PCLK(RCC_HCLK));
783
784 tmpreg = RCC->CFGR;
785 /* Clear PPRE1[2:0] bits */
786 tmpreg &= ~RCC_CFGR_PPRE1;
787
788 /* Set PPRE1[2:0] bits according to RCC_HCLK value */
789 tmpreg |= RCC_HCLK;
790
791 /* Store the new value */
792 RCC->CFGR = tmpreg;
793 }
794
795 /**
796 * @brief Configures the High Speed APB clock (PCLK2).
797 * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
798 * the AHB clock (HCLK).
799 * This parameter can be one of the following values:
800 * @arg RCC_HCLK_Div1: APB2 clock = HCLK
801 * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
802 * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
803 * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
804 * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
805 * @retval None
806 */
807 void RCC_PCLK2Config(uint32_t RCC_HCLK)
808 {
809 uint32_t tmpreg = 0;
810
811 /* Check the parameters */
812 assert_param(IS_RCC_PCLK(RCC_HCLK));
813
814 tmpreg = RCC->CFGR;
815 /* Clear PPRE2[2:0] bits */
816 tmpreg &= ~RCC_CFGR_PPRE2;
817 /* Set PPRE2[2:0] bits according to RCC_HCLK value */
818 tmpreg |= RCC_HCLK << 3;
819 /* Store the new value */
820 RCC->CFGR = tmpreg;
821 }
822
823 /**
824 * @brief Returns the frequencies of the System, AHB, APB2 and APB1 busses clocks.
825 *
826 * @note This function returns the frequencies of :
827 * System, AHB, APB2 and APB1 busses clocks, ADC1/2/3/4 clocks,
828 * USART1/2/3/4/5 clocks, I2C1/2 clocks and TIM1/8 Clocks.
829 *
830 * @note The frequency returned by this function is not the real frequency
831 * in the chip. It is calculated based on the predefined constant and
832 * the source selected by RCC_SYSCLKConfig().
833 *
834 * @note If SYSCLK source is HSI, function returns constant HSI_VALUE(*)
835 *
836 * @note If SYSCLK source is HSE, function returns constant HSE_VALUE(**)
837 *
838 * @note If SYSCLK source is PLL, function returns constant HSE_VALUE(**)
839 * or HSI_VALUE(*) multiplied by the PLL factors.
840 *
841 * @note (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
842 * 8 MHz) but the real value may vary depending on the variations
843 * in voltage and temperature, refer to RCC_AdjustHSICalibrationValue().
844 *
845 * @note (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
846 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
847 * frequency of the crystal used. Otherwise, this function may
848 * return wrong result.
849 *
850 * @note The result of this function could be not correct when using fractional
851 * value for HSE crystal.
852 *
853 * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
854 * the clocks frequencies.
855 *
856 * @note This function can be used by the user application to compute the
857 * baudrate for the communication peripherals or configure other parameters.
858 * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
859 * must be called to update the structure's field. Otherwise, any
860 * configuration based on this function will be incorrect.
861 *
862 * @retval None
863 */
864 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
865 {
866 uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0, presc = 0, pllclk = 0;
867 uint32_t apb2presc = 0, ahbpresc = 0;
868
869 /* Get SYSCLK source -------------------------------------------------------*/
870 tmp = RCC->CFGR & RCC_CFGR_SWS;
871
872 switch (tmp)
873 {
874 case 0x00: /* HSI used as system clock */
875 RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
876 break;
877 case 0x04: /* HSE used as system clock */
878 RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
879 break;
880 case 0x08: /* PLL used as system clock */
881 /* Get PLL clock source and multiplication factor ----------------------*/
882 pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
883 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
884 pllmull = ( pllmull >> 18) + 2;
885
886 if (pllsource == 0x00)
887 {
888 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
889 pllclk = (HSI_VALUE >> 1) * pllmull;
890 }
891 else
892 {
893 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
894 /* HSE oscillator clock selected as PREDIV1 clock entry */
895 pllclk = (HSE_VALUE / prediv1factor) * pllmull;
896 }
897 RCC_Clocks->SYSCLK_Frequency = pllclk;
898 break;
899 default: /* HSI used as system clock */
900 RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
901 break;
902 }
903 /* Compute HCLK, PCLK clocks frequencies -----------------------------------*/
904 /* Get HCLK prescaler */
905 tmp = RCC->CFGR & RCC_CFGR_HPRE;
906 tmp = tmp >> 4;
907 ahbpresc = APBAHBPrescTable[tmp];
908 /* HCLK clock frequency */
909 RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> ahbpresc;
910
911 /* Get PCLK1 prescaler */
912 tmp = RCC->CFGR & RCC_CFGR_PPRE1;
913 tmp = tmp >> 8;
914 presc = APBAHBPrescTable[tmp];
915 /* PCLK1 clock frequency */
916 RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
917
918 /* Get PCLK2 prescaler */
919 tmp = RCC->CFGR & RCC_CFGR_PPRE2;
920 tmp = tmp >> 11;
921 apb2presc = APBAHBPrescTable[tmp];
922 /* PCLK2 clock frequency */
923 RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> apb2presc;
924
925 /* Get ADC12CLK prescaler */
926 tmp = RCC->CFGR2 & RCC_CFGR2_ADCPRE12;
927 tmp = tmp >> 4;
928 presc = ADCPrescTable[tmp & 0x0F];
929 if (((tmp & 0x10) != 0) && (presc != 0))
930 {
931 /* ADC12CLK clock frequency is derived from PLL clock */
932 RCC_Clocks->ADC12CLK_Frequency = pllclk / presc;
933 }
934 else
935 {
936 /* ADC12CLK clock frequency is AHB clock */
937 RCC_Clocks->ADC12CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
938 }
939
940 /* Get ADC34CLK prescaler */
941 tmp = RCC->CFGR2 & RCC_CFGR2_ADCPRE34;
942 tmp = tmp >> 9;
943 presc = ADCPrescTable[tmp & 0x0F];
944 if (((tmp & 0x10) != 0) && (presc != 0))
945 {
946 /* ADC34CLK clock frequency is derived from PLL clock */
947 RCC_Clocks->ADC34CLK_Frequency = pllclk / presc;
948 }
949 else
950 {
951 /* ADC34CLK clock frequency is AHB clock */
952 RCC_Clocks->ADC34CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
953 }
954
955 /* I2C1CLK clock frequency */
956 if((RCC->CFGR3 & RCC_CFGR3_I2C1SW) != RCC_CFGR3_I2C1SW)
957 {
958 /* I2C1 Clock is HSI Osc. */
959 RCC_Clocks->I2C1CLK_Frequency = HSI_VALUE;
960 }
961 else
962 {
963 /* I2C1 Clock is System Clock */
964 RCC_Clocks->I2C1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
965 }
966
967 /* I2C2CLK clock frequency */
968 if((RCC->CFGR3 & RCC_CFGR3_I2C2SW) != RCC_CFGR3_I2C2SW)
969 {
970 /* I2C2 Clock is HSI Osc. */
971 RCC_Clocks->I2C2CLK_Frequency = HSI_VALUE;
972 }
973 else
974 {
975 /* I2C2 Clock is System Clock */
976 RCC_Clocks->I2C2CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
977 }
978
979 /* I2C3CLK clock frequency */
980 if((RCC->CFGR3 & RCC_CFGR3_I2C3SW) != RCC_CFGR3_I2C3SW)
981 {
982 /* I2C3 Clock is HSI Osc. */
983 RCC_Clocks->I2C3CLK_Frequency = HSI_VALUE;
984 }
985 else
986 {
987 /* I2C3 Clock is System Clock */
988 RCC_Clocks->I2C3CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
989 }
990
991 /* TIM1CLK clock frequency */
992 if(((RCC->CFGR3 & RCC_CFGR3_TIM1SW) == RCC_CFGR3_TIM1SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
993 && (apb2presc == ahbpresc))
994 {
995 /* TIM1 Clock is 2 * pllclk */
996 RCC_Clocks->TIM1CLK_Frequency = pllclk * 2;
997 }
998 else
999 {
1000 /* TIM1 Clock is APB2 clock. */
1001 RCC_Clocks->TIM1CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
1002 }
1003
1004 /* TIM1CLK clock frequency */
1005 if(((RCC->CFGR3 & RCC_CFGR3_HRTIM1SW) == RCC_CFGR3_HRTIM1SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
1006 && (apb2presc == ahbpresc))
1007 {
1008 /* HRTIM1 Clock is 2 * pllclk */
1009 RCC_Clocks->HRTIM1CLK_Frequency = pllclk * 2;
1010 }
1011 else
1012 {
1013 /* HRTIM1 Clock is APB2 clock. */
1014 RCC_Clocks->HRTIM1CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
1015 }
1016
1017 /* TIM8CLK clock frequency */
1018 if(((RCC->CFGR3 & RCC_CFGR3_TIM8SW) == RCC_CFGR3_TIM8SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
1019 && (apb2presc == ahbpresc))
1020 {
1021 /* TIM8 Clock is 2 * pllclk */
1022 RCC_Clocks->TIM8CLK_Frequency = pllclk * 2;
1023 }
1024 else
1025 {
1026 /* TIM8 Clock is APB2 clock. */
1027 RCC_Clocks->TIM8CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
1028 }
1029
1030 /* TIM15CLK clock frequency */
1031 if(((RCC->CFGR3 & RCC_CFGR3_TIM15SW) == RCC_CFGR3_TIM15SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
1032 && (apb2presc == ahbpresc))
1033 {
1034 /* TIM15 Clock is 2 * pllclk */
1035 RCC_Clocks->TIM15CLK_Frequency = pllclk * 2;
1036 }
1037 else
1038 {
1039 /* TIM15 Clock is APB2 clock. */
1040 RCC_Clocks->TIM15CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
1041 }
1042
1043 /* TIM16CLK clock frequency */
1044 if(((RCC->CFGR3 & RCC_CFGR3_TIM16SW) == RCC_CFGR3_TIM16SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
1045 && (apb2presc == ahbpresc))
1046 {
1047 /* TIM16 Clock is 2 * pllclk */
1048 RCC_Clocks->TIM16CLK_Frequency = pllclk * 2;
1049 }
1050 else
1051 {
1052 /* TIM16 Clock is APB2 clock. */
1053 RCC_Clocks->TIM16CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
1054 }
1055
1056 /* TIM17CLK clock frequency */
1057 if(((RCC->CFGR3 & RCC_CFGR3_TIM17SW) == RCC_CFGR3_TIM17SW)&& (RCC_Clocks->SYSCLK_Frequency == pllclk) \
1058 && (apb2presc == ahbpresc))
1059 {
1060 /* TIM17 Clock is 2 * pllclk */
1061 RCC_Clocks->TIM17CLK_Frequency = pllclk * 2;
1062 }
1063 else
1064 {
1065 /* TIM17 Clock is APB2 clock. */
1066 RCC_Clocks->TIM16CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
1067 }
1068
1069 /* USART1CLK clock frequency */
1070 if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == 0x0)
1071 {
1072 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F301x8) || defined(STM32F302x8)
1073 /* USART1 Clock is PCLK1 instead of PCLK2 (limitation described in the
1074 STM32F302/01/34 x4/x6/x8 respective erratasheets) */
1075 RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->PCLK1_Frequency;
1076 #else
1077 /* USART Clock is PCLK2 */
1078 RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->PCLK2_Frequency;
1079 #endif
1080 }
1081 else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_0)
1082 {
1083 /* USART Clock is System Clock */
1084 RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
1085 }
1086 else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_1)
1087 {
1088 /* USART Clock is LSE Osc. */
1089 RCC_Clocks->USART1CLK_Frequency = LSE_VALUE;
1090 }
1091 else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW)
1092 {
1093 /* USART Clock is HSI Osc. */
1094 RCC_Clocks->USART1CLK_Frequency = HSI_VALUE;
1095 }
1096
1097 /* USART2CLK clock frequency */
1098 if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == 0x0)
1099 {
1100 /* USART Clock is PCLK */
1101 RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->PCLK1_Frequency;
1102 }
1103 else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_0)
1104 {
1105 /* USART Clock is System Clock */
1106 RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
1107 }
1108 else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_1)
1109 {
1110 /* USART Clock is LSE Osc. */
1111 RCC_Clocks->USART2CLK_Frequency = LSE_VALUE;
1112 }
1113 else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW)
1114 {
1115 /* USART Clock is HSI Osc. */
1116 RCC_Clocks->USART2CLK_Frequency = HSI_VALUE;
1117 }
1118
1119 /* USART3CLK clock frequency */
1120 if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == 0x0)
1121 {
1122 /* USART Clock is PCLK */
1123 RCC_Clocks->USART3CLK_Frequency = RCC_Clocks->PCLK1_Frequency;
1124 }
1125 else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW_0)
1126 {
1127 /* USART Clock is System Clock */
1128 RCC_Clocks->USART3CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
1129 }
1130 else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW_1)
1131 {
1132 /* USART Clock is LSE Osc. */
1133 RCC_Clocks->USART3CLK_Frequency = LSE_VALUE;
1134 }
1135 else if((RCC->CFGR3 & RCC_CFGR3_USART3SW) == RCC_CFGR3_USART3SW)
1136 {
1137 /* USART Clock is HSI Osc. */
1138 RCC_Clocks->USART3CLK_Frequency = HSI_VALUE;
1139 }
1140
1141 /* UART4CLK clock frequency */
1142 if((RCC->CFGR3 & RCC_CFGR3_UART4SW) == 0x0)
1143 {
1144 /* USART Clock is PCLK */
1145 RCC_Clocks->UART4CLK_Frequency = RCC_Clocks->PCLK1_Frequency;
1146 }
1147 else if((RCC->CFGR3 & RCC_CFGR3_UART4SW) == RCC_CFGR3_UART4SW_0)
1148 {
1149 /* USART Clock is System Clock */
1150 RCC_Clocks->UART4CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
1151 }
1152 else if((RCC->CFGR3 & RCC_CFGR3_UART4SW) == RCC_CFGR3_UART4SW_1)
1153 {
1154 /* USART Clock is LSE Osc. */
1155 RCC_Clocks->UART4CLK_Frequency = LSE_VALUE;
1156 }
1157 else if((RCC->CFGR3 & RCC_CFGR3_UART4SW) == RCC_CFGR3_UART4SW)
1158 {
1159 /* USART Clock is HSI Osc. */
1160 RCC_Clocks->UART4CLK_Frequency = HSI_VALUE;
1161 }
1162
1163 /* UART5CLK clock frequency */
1164 if((RCC->CFGR3 & RCC_CFGR3_UART5SW) == 0x0)
1165 {
1166 /* USART Clock is PCLK */
1167 RCC_Clocks->UART5CLK_Frequency = RCC_Clocks->PCLK1_Frequency;
1168 }
1169 else if((RCC->CFGR3 & RCC_CFGR3_UART5SW) == RCC_CFGR3_UART5SW_0)
1170 {
1171 /* USART Clock is System Clock */
1172 RCC_Clocks->UART5CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
1173 }
1174 else if((RCC->CFGR3 & RCC_CFGR3_UART5SW) == RCC_CFGR3_UART5SW_1)
1175 {
1176 /* USART Clock is LSE Osc. */
1177 RCC_Clocks->UART5CLK_Frequency = LSE_VALUE;
1178 }
1179 else if((RCC->CFGR3 & RCC_CFGR3_UART5SW) == RCC_CFGR3_UART5SW)
1180 {
1181 /* USART Clock is HSI Osc. */
1182 RCC_Clocks->UART5CLK_Frequency = HSI_VALUE;
1183 }
1184 }
1185
1186 /**
1187 * @}
1188 */
1189
1190 /** @defgroup RCC_Group3 Peripheral clocks configuration functions
1191 * @brief Peripheral clocks configuration functions
1192 *
1193 @verbatim
1194 ===============================================================================
1195 ##### Peripheral clocks configuration functions #####
1196 ===============================================================================
1197 [..] This section provide functions allowing to configure the Peripheral clocks.
1198 (#) The RTC clock which is derived from the LSE, LSI or HSE_Div32
1199 (HSE divided by 32).
1200 (#) After restart from Reset or wakeup from STANDBY, all peripherals are
1201 off except internal SRAM, Flash and SWD. Before to start using
1202 a peripheral you have to enable its interface clock. You can do this
1203 using RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd()
1204 and RCC_APB1PeriphClockCmd() functions.
1205 (#) To reset the peripherals configuration (to the default state after
1206 device reset) you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd()
1207 and RCC_APB1PeriphResetCmd() functions.
1208 @endverbatim
1209 * @{
1210 */
1211
1212 /**
1213 * @brief Configures the ADC clock (ADCCLK).
1214 * @param RCC_PLLCLK: defines the ADC clock divider. This clock is derived from
1215 * the PLL Clock.
1216 * This parameter can be one of the following values:
1217 * @arg RCC_ADC12PLLCLK_OFF: ADC12 clock disabled
1218 * @arg RCC_ADC12PLLCLK_Div1: ADC12 clock = PLLCLK/1
1219 * @arg RCC_ADC12PLLCLK_Div2: ADC12 clock = PLLCLK/2
1220 * @arg RCC_ADC12PLLCLK_Div4: ADC12 clock = PLLCLK/4
1221 * @arg RCC_ADC12PLLCLK_Div6: ADC12 clock = PLLCLK/6
1222 * @arg RCC_ADC12PLLCLK_Div8: ADC12 clock = PLLCLK/8
1223 * @arg RCC_ADC12PLLCLK_Div10: ADC12 clock = PLLCLK/10
1224 * @arg RCC_ADC12PLLCLK_Div12: ADC12 clock = PLLCLK/12
1225 * @arg RCC_ADC12PLLCLK_Div16: ADC12 clock = PLLCLK/16
1226 * @arg RCC_ADC12PLLCLK_Div32: ADC12 clock = PLLCLK/32
1227 * @arg RCC_ADC12PLLCLK_Div64: ADC12 clock = PLLCLK/64
1228 * @arg RCC_ADC12PLLCLK_Div128: ADC12 clock = PLLCLK/128
1229 * @arg RCC_ADC12PLLCLK_Div256: ADC12 clock = PLLCLK/256
1230 * @arg RCC_ADC34PLLCLK_OFF: ADC34 clock disabled
1231 * @arg RCC_ADC34PLLCLK_Div1: ADC34 clock = PLLCLK/1
1232 * @arg RCC_ADC34PLLCLK_Div2: ADC34 clock = PLLCLK/2
1233 * @arg RCC_ADC34PLLCLK_Div4: ADC34 clock = PLLCLK/4
1234 * @arg RCC_ADC34PLLCLK_Div6: ADC34 clock = PLLCLK/6
1235 * @arg RCC_ADC34PLLCLK_Div8: ADC34 clock = PLLCLK/8
1236 * @arg RCC_ADC34PLLCLK_Div10: ADC34 clock = PLLCLK/10
1237 * @arg RCC_ADC34PLLCLK_Div12: ADC34 clock = PLLCLK/12
1238 * @arg RCC_ADC34PLLCLK_Div16: ADC34 clock = PLLCLK/16
1239 * @arg RCC_ADC34PLLCLK_Div32: ADC34 clock = PLLCLK/32
1240 * @arg RCC_ADC34PLLCLK_Div64: ADC34 clock = PLLCLK/64
1241 * @arg RCC_ADC34PLLCLK_Div128: ADC34 clock = PLLCLK/128
1242 * @arg RCC_ADC34PLLCLK_Div256: ADC34 clock = PLLCLK/256
1243 * @retval None
1244 */
1245 void RCC_ADCCLKConfig(uint32_t RCC_PLLCLK)
1246 {
1247 uint32_t tmp = 0;
1248
1249 /* Check the parameters */
1250 assert_param(IS_RCC_ADCCLK(RCC_PLLCLK));
1251
1252 tmp = (RCC_PLLCLK >> 28);
1253
1254 /* Clears ADCPRE34 bits */
1255 if (tmp != 0)
1256 {
1257 RCC->CFGR2 &= ~RCC_CFGR2_ADCPRE34;
1258 }
1259 /* Clears ADCPRE12 bits */
1260 else
1261 {
1262 RCC->CFGR2 &= ~RCC_CFGR2_ADCPRE12;
1263 }
1264 /* Set ADCPRE bits according to RCC_PLLCLK value */
1265 RCC->CFGR2 |= RCC_PLLCLK;
1266 }
1267
1268 /**
1269 * @brief Configures the I2C clock (I2CCLK).
1270 * @param RCC_I2CCLK: defines the I2C clock source. This clock is derived
1271 * from the HSI or System clock.
1272 * This parameter can be one of the following values:
1273 * @arg RCC_I2CxCLK_HSI: I2Cx clock = HSI
1274 * @arg RCC_I2CxCLK_SYSCLK: I2Cx clock = System Clock
1275 * (x can be 1 or 2 or 3).
1276 * @retval None
1277 */
1278 void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK)
1279 {
1280 uint32_t tmp = 0;
1281
1282 /* Check the parameters */
1283 assert_param(IS_RCC_I2CCLK(RCC_I2CCLK));
1284
1285 tmp = (RCC_I2CCLK >> 28);
1286
1287 /* Clear I2CSW bit */
1288 switch (tmp)
1289 {
1290 case 0x00:
1291 RCC->CFGR3 &= ~RCC_CFGR3_I2C1SW;
1292 break;
1293 case 0x01:
1294 RCC->CFGR3 &= ~RCC_CFGR3_I2C2SW;
1295 break;
1296 case 0x02:
1297 RCC->CFGR3 &= ~RCC_CFGR3_I2C3SW;
1298 break;
1299 default:
1300 break;
1301 }
1302
1303 /* Set I2CSW bits according to RCC_I2CCLK value */
1304 RCC->CFGR3 |= RCC_I2CCLK;
1305 }
1306
1307 /**
1308 * @brief Configures the TIMx clock sources(TIMCLK).
1309 * @note The configuration of the TIMx clock source is only possible when the
1310 * SYSCLK = PLL and HCLK and PCLK2 clocks are not divided in respect to SYSCLK
1311 * @note If one of the previous conditions is missed, the TIM clock source
1312 * configuration is lost and calling again this function becomes mandatory.
1313 * @param RCC_TIMCLK: defines the TIMx clock source.
1314 * This parameter can be one of the following values:
1315 * @arg RCC_TIMxCLK_HCLK: TIMx clock = APB high speed clock (doubled frequency
1316 * when prescaled)
1317 * @arg RCC_TIMxCLK_PLLCLK: TIMx clock = PLL output (running up to 144 MHz)
1318 * (x can be 1, 8, 15, 16, 17).
1319 * @retval None
1320 */
1321 void RCC_TIMCLKConfig(uint32_t RCC_TIMCLK)
1322 {
1323 uint32_t tmp = 0;
1324
1325 /* Check the parameters */
1326 assert_param(IS_RCC_TIMCLK(RCC_TIMCLK));
1327
1328 tmp = (RCC_TIMCLK >> 28);
1329
1330 /* Clear TIMSW bit */
1331
1332 switch (tmp)
1333 {
1334 case 0x00:
1335 RCC->CFGR3 &= ~RCC_CFGR3_TIM1SW;
1336 break;
1337 case 0x01:
1338 RCC->CFGR3 &= ~RCC_CFGR3_TIM8SW;
1339 break;
1340 case 0x02:
1341 RCC->CFGR3 &= ~RCC_CFGR3_TIM15SW;
1342 break;
1343 case 0x03:
1344 RCC->CFGR3 &= ~RCC_CFGR3_TIM16SW;
1345 break;
1346 case 0x04:
1347 RCC->CFGR3 &= ~RCC_CFGR3_TIM17SW;
1348 break;
1349 default:
1350 break;
1351 }
1352
1353 /* Set I2CSW bits according to RCC_TIMCLK value */
1354 RCC->CFGR3 |= RCC_TIMCLK;
1355 }
1356
1357 /**
1358 * @brief Configures the HRTIM1 clock sources(HRTIM1CLK).
1359 * @note The configuration of the HRTIM1 clock source is only possible when the
1360 * SYSCLK = PLL and HCLK and PCLK2 clocks are not divided in respect to SYSCLK
1361 * @note If one of the previous conditions is missed, the TIM clock source
1362 * configuration is lost and calling again this function becomes mandatory.
1363 * @param RCC_HRTIMCLK: defines the TIMx clock source.
1364 * This parameter can be one of the following values:
1365 * @arg RCC_HRTIM1CLK_HCLK: TIMx clock = APB high speed clock (doubled frequency
1366 * when prescaled)
1367 * @arg RCC_HRTIM1CLK_PLLCLK: TIMx clock = PLL output (running up to 144 MHz)
1368 * (x can be 1 or 8).
1369 * @retval None
1370 */
1371 void RCC_HRTIM1CLKConfig(uint32_t RCC_HRTIMCLK)
1372 {
1373 /* Check the parameters */
1374 assert_param(IS_RCC_HRTIMCLK(RCC_HRTIMCLK));
1375
1376 /* Clear HRTIMSW bit */
1377 RCC->CFGR3 &= ~RCC_CFGR3_HRTIM1SW;
1378
1379 /* Set HRTIMSW bits according to RCC_HRTIMCLK value */
1380 RCC->CFGR3 |= RCC_HRTIMCLK;
1381 }
1382
1383 /**
1384 * @brief Configures the USART clock (USARTCLK).
1385 * @param RCC_USARTCLK: defines the USART clock source. This clock is derived
1386 * from the HSI or System clock.
1387 * This parameter can be one of the following values:
1388 * @arg RCC_USARTxCLK_PCLK: USART clock = APB Clock (PCLK)
1389 * @arg RCC_USARTxCLK_SYSCLK: USART clock = System Clock
1390 * @arg RCC_USARTxCLK_LSE: USART clock = LSE Clock
1391 * @arg RCC_USARTxCLK_HSI: USART clock = HSI Clock
1392 * (x can be 1, 2, 3, 4 or 5).
1393 * @retval None
1394 */
1395 void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK)
1396 {
1397 uint32_t tmp = 0;
1398
1399 /* Check the parameters */
1400 assert_param(IS_RCC_USARTCLK(RCC_USARTCLK));
1401
1402 tmp = (RCC_USARTCLK >> 28);
1403
1404 /* Clear USARTSW[1:0] bit */
1405 switch (tmp)
1406 {
1407 case 0x01: /* clear USART1SW */
1408 RCC->CFGR3 &= ~RCC_CFGR3_USART1SW;
1409 break;
1410 case 0x02: /* clear USART2SW */
1411 RCC->CFGR3 &= ~RCC_CFGR3_USART2SW;
1412 break;
1413 case 0x03: /* clear USART3SW */
1414 RCC->CFGR3 &= ~RCC_CFGR3_USART3SW;
1415 break;
1416 case 0x04: /* clear UART4SW */
1417 RCC->CFGR3 &= ~RCC_CFGR3_UART4SW;
1418 break;
1419 case 0x05: /* clear UART5SW */
1420 RCC->CFGR3 &= ~RCC_CFGR3_UART5SW;
1421 break;
1422 default:
1423 break;
1424 }
1425
1426 /* Set USARTSW bits according to RCC_USARTCLK value */
1427 RCC->CFGR3 |= RCC_USARTCLK;
1428 }
1429
1430 /**
1431 * @brief Configures the USB clock (USBCLK).
1432 * @param RCC_USBCLKSource: specifies the USB clock source. This clock is
1433 * derived from the PLL output.
1434 * This parameter can be one of the following values:
1435 * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB
1436 * clock source
1437 * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
1438 * @retval None
1439 */
1440 void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
1441 {
1442 /* Check the parameters */
1443 assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
1444
1445 *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource;
1446 }
1447
1448 /**
1449 * @brief Configures the RTC clock (RTCCLK).
1450 * @note As the RTC clock configuration bits are in the Backup domain and write
1451 * access is denied to this domain after reset, you have to enable write
1452 * access using PWR_BackupAccessCmd(ENABLE) function before to configure
1453 * the RTC clock source (to be done once after reset).
1454 * @note Once the RTC clock is configured it can't be changed unless the RTC
1455 * is reset using RCC_BackupResetCmd function, or by a Power On Reset (POR)
1456 *
1457 * @param RCC_RTCCLKSource: specifies the RTC clock source.
1458 * This parameter can be one of the following values:
1459 * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
1460 * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
1461 * @arg RCC_RTCCLKSource_HSE_Div32: HSE divided by 32 selected as RTC clock
1462 *
1463 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
1464 * work in STOP and STANDBY modes, and can be used as wakeup source.
1465 * However, when the HSE clock is used as RTC clock source, the RTC
1466 * cannot be used in STOP and STANDBY modes.
1467 * @note The maximum input clock frequency for RTC is 2MHz (when using HSE as
1468 * RTC clock source).
1469 * @retval None
1470 */
1471 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
1472 {
1473 /* Check the parameters */
1474 assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
1475
1476 /* Select the RTC clock source */
1477 RCC->BDCR |= RCC_RTCCLKSource;
1478 }
1479
1480 /**
1481 * @brief Configures the I2S clock source (I2SCLK).
1482 * @note This function must be called before enabling the SPI2 and SPI3 clocks.
1483 * @param RCC_I2SCLKSource: specifies the I2S clock source.
1484 * This parameter can be one of the following values:
1485 * @arg RCC_I2S2CLKSource_SYSCLK: SYSCLK clock used as I2S clock source
1486 * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin
1487 * used as I2S clock source
1488 * @retval None
1489 */
1490 void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
1491 {
1492 /* Check the parameters */
1493 assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
1494
1495 *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource;
1496 }
1497
1498 /**
1499 * @brief Enables or disables the RTC clock.
1500 * @note This function must be used only after the RTC clock source was selected
1501 * using the RCC_RTCCLKConfig function.
1502 * @param NewState: new state of the RTC clock.
1503 * This parameter can be: ENABLE or DISABLE.
1504 * @retval None
1505 */
1506 void RCC_RTCCLKCmd(FunctionalState NewState)
1507 {
1508 /* Check the parameters */
1509 assert_param(IS_FUNCTIONAL_STATE(NewState));
1510
1511 *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
1512 }
1513
1514 /**
1515 * @brief Forces or releases the Backup domain reset.
1516 * @note This function resets the RTC peripheral (including the backup registers)
1517 * and the RTC clock source selection in RCC_BDCR register.
1518 * @param NewState: new state of the Backup domain reset.
1519 * This parameter can be: ENABLE or DISABLE.
1520 * @retval None
1521 */
1522 void RCC_BackupResetCmd(FunctionalState NewState)
1523 {
1524 /* Check the parameters */
1525 assert_param(IS_FUNCTIONAL_STATE(NewState));
1526
1527 *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
1528 }
1529
1530 /**
1531 * @brief Enables or disables the AHB peripheral clock.
1532 * @note After reset, the peripheral clock (used for registers read/write access)
1533 * is disabled and the application software has to enable this clock before
1534 * using it.
1535 * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
1536 * This parameter can be any combination of the following values:
1537 * @arg RCC_AHBPeriph_GPIOA
1538 * @arg RCC_AHBPeriph_GPIOB
1539 * @arg RCC_AHBPeriph_GPIOC
1540 * @arg RCC_AHBPeriph_GPIOD
1541 * @arg RCC_AHBPeriph_GPIOE
1542 * @arg RCC_AHBPeriph_GPIOF
1543 * @arg RCC_AHBPeriph_TS
1544 * @arg RCC_AHBPeriph_CRC
1545 * @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode)
1546 * @arg RCC_AHBPeriph_SRAM
1547 * @arg RCC_AHBPeriph_DMA2
1548 * @arg RCC_AHBPeriph_DMA1
1549 * @arg RCC_AHBPeriph_ADC34
1550 * @arg RCC_AHBPeriph_ADC12
1551 * @param NewState: new state of the specified peripheral clock.
1552 * This parameter can be: ENABLE or DISABLE.
1553 * @retval None
1554 */
1555 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
1556 {
1557 /* Check the parameters */
1558 assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
1559 assert_param(IS_FUNCTIONAL_STATE(NewState));
1560
1561 if (NewState != DISABLE)
1562 {
1563 RCC->AHBENR |= RCC_AHBPeriph;
1564 }
1565 else
1566 {
1567 RCC->AHBENR &= ~RCC_AHBPeriph;
1568 }
1569 }
1570
1571 /**
1572 * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
1573 * @note After reset, the peripheral clock (used for registers read/write access)
1574 * is disabled and the application software has to enable this clock before
1575 * using it.
1576 * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
1577 * This parameter can be any combination of the following values:
1578 * @arg RCC_APB2Periph_SYSCFG
1579 * @arg RCC_APB2Periph_SPI1
1580 * @arg RCC_APB2Periph_USART1
1581 * @arg RCC_APB2Periph_TIM15
1582 * @arg RCC_APB2Periph_TIM16
1583 * @arg RCC_APB2Periph_TIM17
1584 * @arg RCC_APB2Periph_TIM1
1585 * @arg RCC_APB2Periph_TIM8
1586 * @arg RCC_APB2Periph_HRTIM1
1587 * @param NewState: new state of the specified peripheral clock.
1588 * This parameter can be: ENABLE or DISABLE.
1589 * @retval None
1590 */
1591 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
1592 {
1593 /* Check the parameters */
1594 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
1595 assert_param(IS_FUNCTIONAL_STATE(NewState));
1596
1597 if (NewState != DISABLE)
1598 {
1599 RCC->APB2ENR |= RCC_APB2Periph;
1600 }
1601 else
1602 {
1603 RCC->APB2ENR &= ~RCC_APB2Periph;
1604 }
1605 }
1606
1607 /**
1608 * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
1609 * @note After reset, the peripheral clock (used for registers read/write access)
1610 * is disabled and the application software has to enable this clock before
1611 * using it.
1612 * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
1613 * This parameter can be any combination of the following values:
1614 * @arg RCC_APB1Periph_TIM2
1615 * @arg RCC_APB1Periph_TIM3
1616 * @arg RCC_APB1Periph_TIM4
1617 * @arg RCC_APB1Periph_TIM6
1618 * @arg RCC_APB1Periph_TIM7
1619 * @arg RCC_APB1Periph_WWDG
1620 * @arg RCC_APB1Periph_SPI2
1621 * @arg RCC_APB1Periph_SPI3
1622 * @arg RCC_APB1Periph_USART2
1623 * @arg RCC_APB1Periph_USART3
1624 * @arg RCC_APB1Periph_UART4
1625 * @arg RCC_APB1Periph_UART5
1626 * @arg RCC_APB1Periph_I2C1
1627 * @arg RCC_APB1Periph_I2C2
1628 * @arg RCC_APB1Periph_USB
1629 * @arg RCC_APB1Periph_CAN1
1630 * @arg RCC_APB1Periph_PWR
1631 * @arg RCC_APB1Periph_DAC1
1632 * @arg RCC_APB1Periph_DAC2
1633 * @param NewState: new state of the specified peripheral clock.
1634 * This parameter can be: ENABLE or DISABLE.
1635 * @retval None
1636 */
1637 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
1638 {
1639 /* Check the parameters */
1640 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
1641 assert_param(IS_FUNCTIONAL_STATE(NewState));
1642
1643 if (NewState != DISABLE)
1644 {
1645 RCC->APB1ENR |= RCC_APB1Periph;
1646 }
1647 else
1648 {
1649 RCC->APB1ENR &= ~RCC_APB1Periph;
1650 }
1651 }
1652
1653 /**
1654 * @brief Forces or releases AHB peripheral reset.
1655 * @param RCC_AHBPeriph: specifies the AHB peripheral to reset.
1656 * This parameter can be any combination of the following values:
1657 * @arg RCC_AHBPeriph_GPIOA
1658 * @arg RCC_AHBPeriph_GPIOB
1659 * @arg RCC_AHBPeriph_GPIOC
1660 * @arg RCC_AHBPeriph_GPIOD
1661 * @arg RCC_AHBPeriph_GPIOE
1662 * @arg RCC_AHBPeriph_GPIOF
1663 * @arg RCC_AHBPeriph_TS
1664 * @arg RCC_AHBPeriph_ADC34
1665 * @arg RCC_AHBPeriph_ADC12
1666 * @param NewState: new state of the specified peripheral reset.
1667 * This parameter can be: ENABLE or DISABLE.
1668 * @retval None
1669 */
1670 void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
1671 {
1672 /* Check the parameters */
1673 assert_param(IS_RCC_AHB_RST_PERIPH(RCC_AHBPeriph));
1674 assert_param(IS_FUNCTIONAL_STATE(NewState));
1675
1676 if (NewState != DISABLE)
1677 {
1678 RCC->AHBRSTR |= RCC_AHBPeriph;
1679 }
1680 else
1681 {
1682 RCC->AHBRSTR &= ~RCC_AHBPeriph;
1683 }
1684 }
1685
1686 /**
1687 * @brief Forces or releases High Speed APB (APB2) peripheral reset.
1688 * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
1689 * This parameter can be any combination of the following values:
1690 * @arg RCC_APB2Periph_SYSCFG
1691 * @arg RCC_APB2Periph_SPI1
1692 * @arg RCC_APB2Periph_USART1
1693 * @arg RCC_APB2Periph_TIM15
1694 * @arg RCC_APB2Periph_TIM16
1695 * @arg RCC_APB2Periph_TIM17
1696 * @arg RCC_APB2Periph_TIM1
1697 * @arg RCC_APB2Periph_TIM8
1698 * @arg RCC_APB2Periph_HRTIM1
1699 * @param NewState: new state of the specified peripheral reset.
1700 * This parameter can be: ENABLE or DISABLE.
1701 * @retval None
1702 */
1703 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
1704 {
1705 /* Check the parameters */
1706 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
1707 assert_param(IS_FUNCTIONAL_STATE(NewState));
1708
1709 if (NewState != DISABLE)
1710 {
1711 RCC->APB2RSTR |= RCC_APB2Periph;
1712 }
1713 else
1714 {
1715 RCC->APB2RSTR &= ~RCC_APB2Periph;
1716 }
1717 }
1718
1719 /**
1720 * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
1721 * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
1722 * This parameter can be any combination of the following values:
1723 * @arg RCC_APB1Periph_TIM2
1724 * @arg RCC_APB1Periph_TIM3
1725 * @arg RCC_APB1Periph_TIM4
1726 * @arg RCC_APB1Periph_TIM6
1727 * @arg RCC_APB1Periph_TIM7
1728 * @arg RCC_APB1Periph_WWDG
1729 * @arg RCC_APB1Periph_SPI2
1730 * @arg RCC_APB1Periph_SPI3
1731 * @arg RCC_APB1Periph_USART2
1732 * @arg RCC_APB1Periph_USART3
1733 * @arg RCC_APB1Periph_UART4
1734 * @arg RCC_APB1Periph_UART5
1735 * @arg RCC_APB1Periph_I2C1
1736 * @arg RCC_APB1Periph_I2C2
1737 * @arg RCC_APB1Periph_I2C3
1738 * @arg RCC_APB1Periph_USB
1739 * @arg RCC_APB1Periph_CAN1
1740 * @arg RCC_APB1Periph_PWR
1741 * @arg RCC_APB1Periph_DAC
1742 * @param NewState: new state of the specified peripheral clock.
1743 * This parameter can be: ENABLE or DISABLE.
1744 * @retval None
1745 */
1746 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
1747 {
1748 /* Check the parameters */
1749 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
1750 assert_param(IS_FUNCTIONAL_STATE(NewState));
1751
1752 if (NewState != DISABLE)
1753 {
1754 RCC->APB1RSTR |= RCC_APB1Periph;
1755 }
1756 else
1757 {
1758 RCC->APB1RSTR &= ~RCC_APB1Periph;
1759 }
1760 }
1761
1762 /**
1763 * @}
1764 */
1765
1766 /** @defgroup RCC_Group4 Interrupts and flags management functions
1767 * @brief Interrupts and flags management functions
1768 *
1769 @verbatim
1770 ===============================================================================
1771 ##### Interrupts and flags management functions #####
1772 ===============================================================================
1773
1774 @endverbatim
1775 * @{
1776 */
1777
1778 /**
1779 * @brief Enables or disables the specified RCC interrupts.
1780 * @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
1781 * and if the HSE clock fails, the CSS interrupt occurs and an NMI is
1782 * automatically generated. The NMI will be executed indefinitely, and
1783 * since NMI has higher priority than any other IRQ (and main program)
1784 * the application will be stacked in the NMI ISR unless the CSS interrupt
1785 * pending bit is cleared.
1786 * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
1787 * This parameter can be any combination of the following values:
1788 * @arg RCC_IT_LSIRDY: LSI ready interrupt
1789 * @arg RCC_IT_LSERDY: LSE ready interrupt
1790 * @arg RCC_IT_HSIRDY: HSI ready interrupt
1791 * @arg RCC_IT_HSERDY: HSE ready interrupt
1792 * @arg RCC_IT_PLLRDY: PLL ready interrupt
1793 * @param NewState: new state of the specified RCC interrupts.
1794 * This parameter can be: ENABLE or DISABLE.
1795 * @retval None
1796 */
1797 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
1798 {
1799 /* Check the parameters */
1800 assert_param(IS_RCC_IT(RCC_IT));
1801 assert_param(IS_FUNCTIONAL_STATE(NewState));
1802
1803 if (NewState != DISABLE)
1804 {
1805 /* Perform Byte access to RCC_CIR[13:8] bits to enable the selected interrupts */
1806 *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
1807 }
1808 else
1809 {
1810 /* Perform Byte access to RCC_CIR[13:8] bits to disable the selected interrupts */
1811 *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
1812 }
1813 }
1814
1815 /**
1816 * @brief Checks whether the specified RCC flag is set or not.
1817 * @param RCC_FLAG: specifies the flag to check.
1818 * This parameter can be one of the following values:
1819 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
1820 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
1821 * @arg RCC_FLAG_PLLRDY: PLL clock ready
1822 * @arg RCC_FLAG_MCOF: MCO Flag
1823 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
1824 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
1825 * @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
1826 * @arg RCC_FLAG_PINRST: Pin reset
1827 * @arg RCC_FLAG_PORRST: POR/PDR reset
1828 * @arg RCC_FLAG_SFTRST: Software reset
1829 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
1830 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
1831 * @arg RCC_FLAG_LPWRRST: Low Power reset
1832 * @retval The new state of RCC_FLAG (SET or RESET).
1833 */
1834 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
1835 {
1836 uint32_t tmp = 0;
1837 uint32_t statusreg = 0;
1838 FlagStatus bitstatus = RESET;
1839
1840 /* Check the parameters */
1841 assert_param(IS_RCC_FLAG(RCC_FLAG));
1842
1843 /* Get the RCC register index */
1844 tmp = RCC_FLAG >> 5;
1845
1846 if (tmp == 0) /* The flag to check is in CR register */
1847 {
1848 statusreg = RCC->CR;
1849 }
1850 else if (tmp == 1) /* The flag to check is in BDCR register */
1851 {
1852 statusreg = RCC->BDCR;
1853 }
1854 else if (tmp == 4) /* The flag to check is in CFGR register */
1855 {
1856 statusreg = RCC->CFGR;
1857 }
1858 else /* The flag to check is in CSR register */
1859 {
1860 statusreg = RCC->CSR;
1861 }
1862
1863 /* Get the flag position */
1864 tmp = RCC_FLAG & FLAG_MASK;
1865
1866 if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
1867 {
1868 bitstatus = SET;
1869 }
1870 else
1871 {
1872 bitstatus = RESET;
1873 }
1874 /* Return the flag status */
1875 return bitstatus;
1876 }
1877
1878 /**
1879 * @brief Clears the RCC reset flags.
1880 * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST,
1881 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
1882 * @param None
1883 * @retval None
1884 */
1885 void RCC_ClearFlag(void)
1886 {
1887 /* Set RMVF bit to clear the reset flags */
1888 RCC->CSR |= RCC_CSR_RMVF;
1889 }
1890
1891 /**
1892 * @brief Checks whether the specified RCC interrupt has occurred or not.
1893 * @param RCC_IT: specifies the RCC interrupt source to check.
1894 * This parameter can be one of the following values:
1895 * @arg RCC_IT_LSIRDY: LSI ready interrupt
1896 * @arg RCC_IT_LSERDY: LSE ready interrupt
1897 * @arg RCC_IT_HSIRDY: HSI ready interrupt
1898 * @arg RCC_IT_HSERDY: HSE ready interrupt
1899 * @arg RCC_IT_PLLRDY: PLL ready interrupt
1900 * @arg RCC_IT_CSS: Clock Security System interrupt
1901 * @retval The new state of RCC_IT (SET or RESET).
1902 */
1903 ITStatus RCC_GetITStatus(uint8_t RCC_IT)
1904 {
1905 ITStatus bitstatus = RESET;
1906
1907 /* Check the parameters */
1908 assert_param(IS_RCC_GET_IT(RCC_IT));
1909
1910 /* Check the status of the specified RCC interrupt */
1911 if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
1912 {
1913 bitstatus = SET;
1914 }
1915 else
1916 {
1917 bitstatus = RESET;
1918 }
1919 /* Return the RCC_IT status */
1920 return bitstatus;
1921 }
1922
1923 /**
1924 * @brief Clears the RCC's interrupt pending bits.
1925 * @param RCC_IT: specifies the interrupt pending bit to clear.
1926 * This parameter can be any combination of the following values:
1927 * @arg RCC_IT_LSIRDY: LSI ready interrupt
1928 * @arg RCC_IT_LSERDY: LSE ready interrupt
1929 * @arg RCC_IT_HSIRDY: HSI ready interrupt
1930 * @arg RCC_IT_HSERDY: HSE ready interrupt
1931 * @arg RCC_IT_PLLRDY: PLL ready interrupt
1932 * @arg RCC_IT_CSS: Clock Security System interrupt
1933 * @retval None
1934 */
1935 void RCC_ClearITPendingBit(uint8_t RCC_IT)
1936 {
1937 /* Check the parameters */
1938 assert_param(IS_RCC_CLEAR_IT(RCC_IT));
1939
1940 /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
1941 pending bits */
1942 *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
1943 }
1944
1945 /**
1946 * @}
1947 */
1948
1949 /**
1950 * @}
1951 */
1952
1953 /**
1954 * @}
1955 */
1956
1957 /**
1958 * @}
1959 */
1960
1961 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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