tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_rcc.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f30x_rcc.h
   4   * @author  MCD Application Team
   5   * @version V1.1.0
   6   * @date    27-February-2014
   7   * @brief   This file contains all the functions prototypes for the RCC
   8   *          firmware library.
   9   ******************************************************************************
  10   * @attention
  11   *
  12   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  13   *
  14   * Redistribution and use in source and binary forms, with or without modification,
  15   * are permitted provided that the following conditions are met:
  16   *   1. Redistributions of source code must retain the above copyright notice,
  17   *      this list of conditions and the following disclaimer.
  18   *   2. Redistributions in binary form must reproduce the above copyright notice,
  19   *      this list of conditions and the following disclaimer in the documentation
  20   *      and/or other materials provided with the distribution.
  21   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  22   *      may be used to endorse or promote products derived from this software
  23   *      without specific prior written permission.
  24   *
  25   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  26   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  27   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  28   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  29   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  30   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  31   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  32   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  33   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  34   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35   *
  36   ******************************************************************************
  37   */
  38
  39 /* Define to prevent recursive inclusion -------------------------------------*/
  40 #ifndef __STM32F30x_RCC_H
  41 #define __STM32F30x_RCC_H
  42
  43 #ifdef __cplusplus
  44  extern "C" {
  45 #endif
  46
  47 /* Includes ------------------------------------------------------------------*/
  48 #include "stm32f30x.h"
  49
  50 /** @addtogroup STM32F30x_StdPeriph_Driver
  51   * @{
  52   */
  53
  54 /** @addtogroup RCC
  55   * @{
  56   */
  57
  58 /* Exported types ------------------------------------------------------------*/
  59
  60 typedef struct
  61 {
  62   uint32_t SYSCLK_Frequency;
  63   uint32_t HCLK_Frequency;
  64   uint32_t PCLK1_Frequency;
  65   uint32_t PCLK2_Frequency;
  66   uint32_t ADC12CLK_Frequency;
  67   uint32_t ADC34CLK_Frequency;
  68   uint32_t I2C1CLK_Frequency;
  69   uint32_t I2C2CLK_Frequency;
  70   uint32_t I2C3CLK_Frequency;
  71   uint32_t TIM1CLK_Frequency;
  72   uint32_t HRTIM1CLK_Frequency;
  73   uint32_t TIM8CLK_Frequency;
  74   uint32_t USART1CLK_Frequency;
  75   uint32_t USART2CLK_Frequency;
  76   uint32_t USART3CLK_Frequency;
  77   uint32_t UART4CLK_Frequency;
  78   uint32_t UART5CLK_Frequency;
  79   uint32_t TIM15CLK_Frequency;
  80   uint32_t TIM16CLK_Frequency;
  81   uint32_t TIM17CLK_Frequency;
  82 }RCC_ClocksTypeDef;
  83
  84 /* Exported constants --------------------------------------------------------*/
  85
  86 /** @defgroup RCC_Exported_Constants
  87   * @{
  88   */
  89
  90 /** @defgroup RCC_HSE_configuration
  91   * @{
  92   */
  93
  94 #define RCC_HSE_OFF                      ((uint8_t)0x00)
  95 #define RCC_HSE_ON                       ((uint8_t)0x01)
  96 #define RCC_HSE_Bypass                   ((uint8_t)0x05)
  97 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
  98                          ((HSE) == RCC_HSE_Bypass))
  99
 100 /**
 101   * @}
 102   */
 103
 104 /** @defgroup RCC_PLL_Clock_Source
 105   * @{
 106   */
 107
 108 #define RCC_PLLSource_HSI_Div2           RCC_CFGR_PLLSRC_HSI_Div2
 109 #define RCC_PLLSource_PREDIV1            RCC_CFGR_PLLSRC_PREDIV1
 110
 111 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
 112                                    ((SOURCE) == RCC_PLLSource_PREDIV1))
 113 /**
 114   * @}
 115   */
 116
 117 /** @defgroup RCC_PLL_Multiplication_Factor
 118   * @{
 119   */
 120
 121 #define RCC_PLLMul_2                    RCC_CFGR_PLLMULL2
 122 #define RCC_PLLMul_3                    RCC_CFGR_PLLMULL3
 123 #define RCC_PLLMul_4                    RCC_CFGR_PLLMULL4
 124 #define RCC_PLLMul_5                    RCC_CFGR_PLLMULL5
 125 #define RCC_PLLMul_6                    RCC_CFGR_PLLMULL6
 126 #define RCC_PLLMul_7                    RCC_CFGR_PLLMULL7
 127 #define RCC_PLLMul_8                    RCC_CFGR_PLLMULL8
 128 #define RCC_PLLMul_9                    RCC_CFGR_PLLMULL9
 129 #define RCC_PLLMul_10                   RCC_CFGR_PLLMULL10
 130 #define RCC_PLLMul_11                   RCC_CFGR_PLLMULL11
 131 #define RCC_PLLMul_12                   RCC_CFGR_PLLMULL12
 132 #define RCC_PLLMul_13                   RCC_CFGR_PLLMULL13
 133 #define RCC_PLLMul_14                   RCC_CFGR_PLLMULL14
 134 #define RCC_PLLMul_15                   RCC_CFGR_PLLMULL15
 135 #define RCC_PLLMul_16                   RCC_CFGR_PLLMULL16
 136 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3)   || \
 137                              ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5)   || \
 138                              ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7)   || \
 139                              ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9)   || \
 140                              ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
 141                              ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
 142                              ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
 143                              ((MUL) == RCC_PLLMul_16))
 144 /**
 145   * @}
 146   */
 147
 148 /** @defgroup RCC_PREDIV1_division_factor
 149   * @{
 150   */
 151 #define  RCC_PREDIV1_Div1               RCC_CFGR2_PREDIV1_DIV1
 152 #define  RCC_PREDIV1_Div2               RCC_CFGR2_PREDIV1_DIV2
 153 #define  RCC_PREDIV1_Div3               RCC_CFGR2_PREDIV1_DIV3
 154 #define  RCC_PREDIV1_Div4               RCC_CFGR2_PREDIV1_DIV4
 155 #define  RCC_PREDIV1_Div5               RCC_CFGR2_PREDIV1_DIV5
 156 #define  RCC_PREDIV1_Div6               RCC_CFGR2_PREDIV1_DIV6
 157 #define  RCC_PREDIV1_Div7               RCC_CFGR2_PREDIV1_DIV7
 158 #define  RCC_PREDIV1_Div8               RCC_CFGR2_PREDIV1_DIV8
 159 #define  RCC_PREDIV1_Div9               RCC_CFGR2_PREDIV1_DIV9
 160 #define  RCC_PREDIV1_Div10              RCC_CFGR2_PREDIV1_DIV10
 161 #define  RCC_PREDIV1_Div11              RCC_CFGR2_PREDIV1_DIV11
 162 #define  RCC_PREDIV1_Div12              RCC_CFGR2_PREDIV1_DIV12
 163 #define  RCC_PREDIV1_Div13              RCC_CFGR2_PREDIV1_DIV13
 164 #define  RCC_PREDIV1_Div14              RCC_CFGR2_PREDIV1_DIV14
 165 #define  RCC_PREDIV1_Div15              RCC_CFGR2_PREDIV1_DIV15
 166 #define  RCC_PREDIV1_Div16              RCC_CFGR2_PREDIV1_DIV16
 167
 168 #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
 169                                  ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
 170                                  ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
 171                                  ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
 172                                  ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
 173                                  ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
 174                                  ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
 175                                  ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
 176 /**
 177   * @}
 178   */
 179
 180 /** @defgroup RCC_System_Clock_Source
 181   * @{
 182   */
 183
 184 #define RCC_SYSCLKSource_HSI             RCC_CFGR_SW_HSI
 185 #define RCC_SYSCLKSource_HSE             RCC_CFGR_SW_HSE
 186 #define RCC_SYSCLKSource_PLLCLK          RCC_CFGR_SW_PLL
 187 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
 188                                       ((SOURCE) == RCC_SYSCLKSource_HSE) || \
 189                                       ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
 190 /**
 191   * @}
 192   */
 193
 194 /** @defgroup RCC_AHB_Clock_Source
 195   * @{
 196   */
 197
 198 #define RCC_SYSCLK_Div1                  RCC_CFGR_HPRE_DIV1
 199 #define RCC_SYSCLK_Div2                  RCC_CFGR_HPRE_DIV2
 200 #define RCC_SYSCLK_Div4                  RCC_CFGR_HPRE_DIV4
 201 #define RCC_SYSCLK_Div8                  RCC_CFGR_HPRE_DIV8
 202 #define RCC_SYSCLK_Div16                 RCC_CFGR_HPRE_DIV16
 203 #define RCC_SYSCLK_Div64                 RCC_CFGR_HPRE_DIV64
 204 #define RCC_SYSCLK_Div128                RCC_CFGR_HPRE_DIV128
 205 #define RCC_SYSCLK_Div256                RCC_CFGR_HPRE_DIV256
 206 #define RCC_SYSCLK_Div512                RCC_CFGR_HPRE_DIV512
 207 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
 208                            ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
 209                            ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
 210                            ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
 211                            ((HCLK) == RCC_SYSCLK_Div512))
 212 /**
 213   * @}
 214   */
 215
 216 /** @defgroup RCC_APB1_APB2_clock_source
 217   * @{
 218   */
 219
 220 #define RCC_HCLK_Div1                    ((uint32_t)0x00000000)
 221 #define RCC_HCLK_Div2                    ((uint32_t)0x00000400)
 222 #define RCC_HCLK_Div4                    ((uint32_t)0x00000500)
 223 #define RCC_HCLK_Div8                    ((uint32_t)0x00000600)
 224 #define RCC_HCLK_Div16                   ((uint32_t)0x00000700)
 225 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
 226                            ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
 227                            ((PCLK) == RCC_HCLK_Div16))
 228 /**
 229   * @}
 230   */
 231
 232 /** @defgroup RCC_ADC_clock_source
 233   * @{
 234   */
 235
 236 /* ADC1 & ADC2 */
 237 #define RCC_ADC12PLLCLK_OFF                    ((uint32_t)0x00000000)
 238 #define RCC_ADC12PLLCLK_Div1                   ((uint32_t)0x00000100)
 239 #define RCC_ADC12PLLCLK_Div2                   ((uint32_t)0x00000110)
 240 #define RCC_ADC12PLLCLK_Div4                   ((uint32_t)0x00000120)
 241 #define RCC_ADC12PLLCLK_Div6                   ((uint32_t)0x00000130)
 242 #define RCC_ADC12PLLCLK_Div8                   ((uint32_t)0x00000140)
 243 #define RCC_ADC12PLLCLK_Div10                  ((uint32_t)0x00000150)
 244 #define RCC_ADC12PLLCLK_Div12                  ((uint32_t)0x00000160)
 245 #define RCC_ADC12PLLCLK_Div16                  ((uint32_t)0x00000170)
 246 #define RCC_ADC12PLLCLK_Div32                  ((uint32_t)0x00000180)
 247 #define RCC_ADC12PLLCLK_Div64                  ((uint32_t)0x00000190)
 248 #define RCC_ADC12PLLCLK_Div128                 ((uint32_t)0x000001A0)
 249 #define RCC_ADC12PLLCLK_Div256                 ((uint32_t)0x000001B0)
 250
 251 /* ADC3 & ADC4 */
 252 #define RCC_ADC34PLLCLK_OFF                    ((uint32_t)0x10000000)
 253 #define RCC_ADC34PLLCLK_Div1                   ((uint32_t)0x10002000)
 254 #define RCC_ADC34PLLCLK_Div2                   ((uint32_t)0x10002200)
 255 #define RCC_ADC34PLLCLK_Div4                   ((uint32_t)0x10002400)
 256 #define RCC_ADC34PLLCLK_Div6                   ((uint32_t)0x10002600)
 257 #define RCC_ADC34PLLCLK_Div8                   ((uint32_t)0x10002800)
 258 #define RCC_ADC34PLLCLK_Div10                  ((uint32_t)0x10002A00)
 259 #define RCC_ADC34PLLCLK_Div12                  ((uint32_t)0x10002C00)
 260 #define RCC_ADC34PLLCLK_Div16                  ((uint32_t)0x10002E00)
 261 #define RCC_ADC34PLLCLK_Div32                  ((uint32_t)0x10003000)
 262 #define RCC_ADC34PLLCLK_Div64                  ((uint32_t)0x10003200)
 263 #define RCC_ADC34PLLCLK_Div128                 ((uint32_t)0x10003400)
 264 #define RCC_ADC34PLLCLK_Div256                 ((uint32_t)0x10003600)
 265
 266 #define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_Div1) || \
 267                                ((ADCCLK) == RCC_ADC12PLLCLK_Div2) || ((ADCCLK) == RCC_ADC12PLLCLK_Div4) || \
 268                                ((ADCCLK) == RCC_ADC12PLLCLK_Div6) || ((ADCCLK) == RCC_ADC12PLLCLK_Div8) || \
 269                                ((ADCCLK) == RCC_ADC12PLLCLK_Div10) || ((ADCCLK) == RCC_ADC12PLLCLK_Div12) || \
 270                                ((ADCCLK) == RCC_ADC12PLLCLK_Div16) || ((ADCCLK) == RCC_ADC12PLLCLK_Div32) || \
 271                                ((ADCCLK) == RCC_ADC12PLLCLK_Div64) || ((ADCCLK) == RCC_ADC12PLLCLK_Div128) || \
 272                                ((ADCCLK) == RCC_ADC12PLLCLK_Div256) || ((ADCCLK) == RCC_ADC34PLLCLK_OFF) || \
 273                                ((ADCCLK) == RCC_ADC34PLLCLK_Div1) || ((ADCCLK) == RCC_ADC34PLLCLK_Div2) || \
 274                                ((ADCCLK) == RCC_ADC34PLLCLK_Div4) || ((ADCCLK) == RCC_ADC34PLLCLK_Div6) || \
 275                                ((ADCCLK) == RCC_ADC34PLLCLK_Div8) || ((ADCCLK) == RCC_ADC34PLLCLK_Div10) || \
 276                                ((ADCCLK) == RCC_ADC34PLLCLK_Div12) || ((ADCCLK) == RCC_ADC34PLLCLK_Div16) || \
 277                                ((ADCCLK) == RCC_ADC34PLLCLK_Div32) || ((ADCCLK) == RCC_ADC34PLLCLK_Div64) || \
 278                                ((ADCCLK) == RCC_ADC34PLLCLK_Div128) || ((ADCCLK) == RCC_ADC34PLLCLK_Div256))
 279
 280 /**
 281   * @}
 282   */
 283
 284 /** @defgroup RCC_TIM_clock_source
 285   * @{
 286   */
 287
 288 #define RCC_TIM1CLK_HCLK                  ((uint32_t)0x00000000)
 289 #define RCC_TIM1CLK_PLLCLK                RCC_CFGR3_TIM1SW
 290
 291 #define RCC_TIM8CLK_HCLK                  ((uint32_t)0x10000000)
 292 #define RCC_TIM8CLK_PLLCLK                ((uint32_t)0x10000200)
 293
 294 #define RCC_TIM15CLK_HCLK                  ((uint32_t)0x20000000)
 295 #define RCC_TIM15CLK_PLLCLK                ((uint32_t)0x20000400)
 296
 297 #define RCC_TIM16CLK_HCLK                  ((uint32_t)0x30000000)
 298 #define RCC_TIM16CLK_PLLCLK                ((uint32_t)0x30000800)
 299
 300 #define RCC_TIM17CLK_HCLK                  ((uint32_t)0x40000000)
 301 #define RCC_TIM17CLK_PLLCLK                ((uint32_t)0x40002000)
 302
 303 #define IS_RCC_TIMCLK(TIMCLK) (((TIMCLK) == RCC_TIM1CLK_HCLK) || ((TIMCLK) == RCC_TIM1CLK_PLLCLK) || \
 304                                ((TIMCLK) == RCC_TIM8CLK_HCLK) || ((TIMCLK) == RCC_TIM8CLK_PLLCLK) || \
 305                                ((TIMCLK) == RCC_TIM15CLK_HCLK) || ((TIMCLK) == RCC_TIM15CLK_PLLCLK) || \
 306                                ((TIMCLK) == RCC_TIM16CLK_HCLK) || ((TIMCLK) == RCC_TIM16CLK_PLLCLK) || \
 307                                ((TIMCLK) == RCC_TIM17CLK_HCLK) || ((TIMCLK) == RCC_TIM17CLK_PLLCLK))
 308
 309 /**
 310   * @}
 311   */
 312
 313 /** @defgroup RCC_HRTIM_clock_source
 314   * @{
 315   */
 316
 317 #define RCC_HRTIM1CLK_HCLK                  ((uint32_t)0x00000000)
 318 #define RCC_HRTIM1CLK_PLLCLK                RCC_CFGR3_HRTIM1SW
 319
 320 #define IS_RCC_HRTIMCLK(HRTIMCLK) (((HRTIMCLK) == RCC_HRTIM1CLK_HCLK) || ((HRTIMCLK) == RCC_HRTIM1CLK_PLLCLK))
 321
 322 /**
 323   * @}
 324   */
 325
 326 /** @defgroup RCC_I2C_clock_source
 327   * @{
 328   */
 329
 330 #define RCC_I2C1CLK_HSI                   ((uint32_t)0x00000000)
 331 #define RCC_I2C1CLK_SYSCLK                RCC_CFGR3_I2C1SW
 332
 333 #define RCC_I2C2CLK_HSI                   ((uint32_t)0x10000000)
 334 #define RCC_I2C2CLK_SYSCLK                ((uint32_t)0x10000020)
 335
 336 #define RCC_I2C3CLK_HSI                   ((uint32_t)0x20000000)
 337 #define RCC_I2C3CLK_SYSCLK                ((uint32_t)0x20000040)
 338
 339 #define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK) || \
 340                                ((I2CCLK) == RCC_I2C2CLK_HSI) || ((I2CCLK) == RCC_I2C2CLK_SYSCLK) || \
 341                                ((I2CCLK) == RCC_I2C3CLK_HSI) || ((I2CCLK) == RCC_I2C3CLK_SYSCLK))
 342
 343 /**
 344   * @}
 345   */
 346
 347 /** @defgroup RCC_USART_clock_source
 348   * @{
 349   */
 350
 351 #define RCC_USART1CLK_PCLK                  ((uint32_t)0x10000000)
 352 #define RCC_USART1CLK_SYSCLK                ((uint32_t)0x10000001)
 353 #define RCC_USART1CLK_LSE                   ((uint32_t)0x10000002)
 354 #define RCC_USART1CLK_HSI                   ((uint32_t)0x10000003)
 355
 356 #define RCC_USART2CLK_PCLK                  ((uint32_t)0x20000000)
 357 #define RCC_USART2CLK_SYSCLK                ((uint32_t)0x20010000)
 358 #define RCC_USART2CLK_LSE                   ((uint32_t)0x20020000)
 359 #define RCC_USART2CLK_HSI                   ((uint32_t)0x20030000)
 360
 361 #define RCC_USART3CLK_PCLK                  ((uint32_t)0x30000000)
 362 #define RCC_USART3CLK_SYSCLK                ((uint32_t)0x30040000)
 363 #define RCC_USART3CLK_LSE                   ((uint32_t)0x30080000)
 364 #define RCC_USART3CLK_HSI                   ((uint32_t)0x300C0000)
 365
 366 #define RCC_UART4CLK_PCLK                   ((uint32_t)0x40000000)
 367 #define RCC_UART4CLK_SYSCLK                 ((uint32_t)0x40100000)
 368 #define RCC_UART4CLK_LSE                    ((uint32_t)0x40200000)
 369 #define RCC_UART4CLK_HSI                    ((uint32_t)0x40300000)
 370
 371 #define RCC_UART5CLK_PCLK                   ((uint32_t)0x50000000)
 372 #define RCC_UART5CLK_SYSCLK                 ((uint32_t)0x50400000)
 373 #define RCC_UART5CLK_LSE                    ((uint32_t)0x50800000)
 374 #define RCC_UART5CLK_HSI                    ((uint32_t)0x50C00000)
 375
 376 #define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \
 377                                    ((USARTCLK) == RCC_USART1CLK_LSE) || ((USARTCLK) == RCC_USART1CLK_HSI) ||\
 378                                    ((USARTCLK) == RCC_USART2CLK_PCLK) || ((USARTCLK) == RCC_USART2CLK_SYSCLK) || \
 379                                    ((USARTCLK) == RCC_USART2CLK_LSE) || ((USARTCLK) == RCC_USART2CLK_HSI) || \
 380                                    ((USARTCLK) == RCC_USART3CLK_PCLK) || ((USARTCLK) == RCC_USART3CLK_SYSCLK) || \
 381                                    ((USARTCLK) == RCC_USART3CLK_LSE) || ((USARTCLK) == RCC_USART3CLK_HSI) || \
 382                                    ((USARTCLK) == RCC_UART4CLK_PCLK) || ((USARTCLK) == RCC_UART4CLK_SYSCLK) || \
 383                                    ((USARTCLK) == RCC_UART4CLK_LSE) || ((USARTCLK) == RCC_UART4CLK_HSI) || \
 384                                    ((USARTCLK) == RCC_UART5CLK_PCLK) || ((USARTCLK) == RCC_UART5CLK_SYSCLK) || \
 385                                    ((USARTCLK) == RCC_UART5CLK_LSE) || ((USARTCLK) == RCC_UART5CLK_HSI))
 386
 387 /**
 388   * @}
 389   */
 390
 391 /** @defgroup RCC_Interrupt_Source
 392   * @{
 393   */
 394
 395 #define RCC_IT_LSIRDY                    ((uint8_t)0x01)
 396 #define RCC_IT_LSERDY                    ((uint8_t)0x02)
 397 #define RCC_IT_HSIRDY                    ((uint8_t)0x04)
 398 #define RCC_IT_HSERDY                    ((uint8_t)0x08)
 399 #define RCC_IT_PLLRDY                    ((uint8_t)0x10)
 400 #define RCC_IT_CSS                       ((uint8_t)0x80)
 401
 402 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
 403
 404 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
 405                            ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
 406                            ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
 407
 408
 409 #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
 410
 411 /**
 412   * @}
 413   */
 414
 415 /** @defgroup RCC_LSE_configuration
 416   * @{
 417   */
 418
 419 #define RCC_LSE_OFF                      ((uint32_t)0x00000000)
 420 #define RCC_LSE_ON                       RCC_BDCR_LSEON
 421 #define RCC_LSE_Bypass                   ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP))
 422 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
 423                          ((LSE) == RCC_LSE_Bypass))
 424 /**
 425   * @}
 426   */
 427
 428 /** @defgroup RCC_RTC_Clock_Source
 429   * @{
 430   */
 431
 432 #define RCC_RTCCLKSource_LSE             RCC_BDCR_RTCSEL_LSE
 433 #define RCC_RTCCLKSource_LSI             RCC_BDCR_RTCSEL_LSI
 434 #define RCC_RTCCLKSource_HSE_Div32       RCC_BDCR_RTCSEL_HSE
 435
 436 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
 437                                       ((SOURCE) == RCC_RTCCLKSource_LSI) || \
 438                                       ((SOURCE) == RCC_RTCCLKSource_HSE_Div32))
 439 /**
 440   * @}
 441   */
 442
 443 /** @defgroup RCC_I2S_Clock_Source
 444   * @{
 445   */
 446 #define RCC_I2S2CLKSource_SYSCLK             ((uint8_t)0x00)
 447 #define RCC_I2S2CLKSource_Ext                ((uint8_t)0x01)
 448
 449 #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
 450
 451 /** @defgroup RCC_LSE_Drive_Configuration
 452   * @{
 453   */
 454
 455 #define RCC_LSEDrive_Low                 ((uint32_t)0x00000000)
 456 #define RCC_LSEDrive_MediumLow           RCC_BDCR_LSEDRV_0
 457 #define RCC_LSEDrive_MediumHigh          RCC_BDCR_LSEDRV_1
 458 #define RCC_LSEDrive_High                RCC_BDCR_LSEDRV
 459 #define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \
 460                                  ((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High))
 461 /**
 462   * @}
 463   */
 464
 465 /** @defgroup RCC_AHB_Peripherals
 466   * @{
 467   */
 468
 469 #define RCC_AHBPeriph_ADC34               RCC_AHBENR_ADC34EN
 470 #define RCC_AHBPeriph_ADC12               RCC_AHBENR_ADC12EN
 471 #define RCC_AHBPeriph_GPIOA               RCC_AHBENR_GPIOAEN
 472 #define RCC_AHBPeriph_GPIOB               RCC_AHBENR_GPIOBEN
 473 #define RCC_AHBPeriph_GPIOC               RCC_AHBENR_GPIOCEN
 474 #define RCC_AHBPeriph_GPIOD               RCC_AHBENR_GPIODEN
 475 #define RCC_AHBPeriph_GPIOE               RCC_AHBENR_GPIOEEN
 476 #define RCC_AHBPeriph_GPIOF               RCC_AHBENR_GPIOFEN
 477 #define RCC_AHBPeriph_TS                  RCC_AHBENR_TSEN
 478 #define RCC_AHBPeriph_CRC                 RCC_AHBENR_CRCEN
 479 #define RCC_AHBPeriph_FLITF               RCC_AHBENR_FLITFEN
 480 #define RCC_AHBPeriph_SRAM                RCC_AHBENR_SRAMEN
 481 #define RCC_AHBPeriph_DMA2                RCC_AHBENR_DMA2EN
 482 #define RCC_AHBPeriph_DMA1                RCC_AHBENR_DMA1EN
 483
 484 #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xCE81FFA8) == 0x00) && ((PERIPH) != 0x00))
 485 #define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xCE81FFFF) == 0x00) && ((PERIPH) != 0x00))
 486
 487 /**
 488   * @}
 489   */
 490
 491 /** @defgroup RCC_APB2_Peripherals
 492   * @{
 493   */
 494
 495 #define RCC_APB2Periph_SYSCFG            RCC_APB2ENR_SYSCFGEN
 496 #define RCC_APB2Periph_TIM1              RCC_APB2ENR_TIM1EN
 497 #define RCC_APB2Periph_SPI1              RCC_APB2ENR_SPI1EN
 498 #define RCC_APB2Periph_TIM8              RCC_APB2ENR_TIM8EN
 499 #define RCC_APB2Periph_USART1            RCC_APB2ENR_USART1EN
 500 #define RCC_APB2Periph_TIM15             RCC_APB2ENR_TIM15EN
 501 #define RCC_APB2Periph_TIM16             RCC_APB2ENR_TIM16EN
 502 #define RCC_APB2Periph_TIM17             RCC_APB2ENR_TIM17EN
 503 #define RCC_APB2Periph_HRTIM1            RCC_APB2ENR_HRTIM1
 504
 505 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xDFF887FE) == 0x00) && ((PERIPH) != 0x00))
 506
 507 /**
 508   * @}
 509   */
 510
 511 /** @defgroup RCC_APB1_Peripherals
 512   * @{
 513   */
 514 #define RCC_APB1Periph_TIM2              RCC_APB1ENR_TIM2EN
 515 #define RCC_APB1Periph_TIM3              RCC_APB1ENR_TIM3EN
 516 #define RCC_APB1Periph_TIM4              RCC_APB1ENR_TIM4EN
 517 #define RCC_APB1Periph_TIM6              RCC_APB1ENR_TIM6EN
 518 #define RCC_APB1Periph_TIM7              RCC_APB1ENR_TIM7EN
 519 #define RCC_APB1Periph_WWDG              RCC_APB1ENR_WWDGEN
 520 #define RCC_APB1Periph_SPI2              RCC_APB1ENR_SPI2EN
 521 #define RCC_APB1Periph_SPI3              RCC_APB1ENR_SPI3EN
 522 #define RCC_APB1Periph_USART2            RCC_APB1ENR_USART2EN
 523 #define RCC_APB1Periph_USART3            RCC_APB1ENR_USART3EN
 524 #define RCC_APB1Periph_UART4             RCC_APB1ENR_UART4EN
 525 #define RCC_APB1Periph_UART5             RCC_APB1ENR_UART5EN
 526 #define RCC_APB1Periph_I2C1              RCC_APB1ENR_I2C1EN
 527 #define RCC_APB1Periph_I2C2              RCC_APB1ENR_I2C2EN
 528 #define RCC_APB1Periph_USB               RCC_APB1ENR_USBEN
 529 #define RCC_APB1Periph_CAN1              RCC_APB1ENR_CAN1EN
 530 #define RCC_APB1Periph_PWR               RCC_APB1ENR_PWREN
 531 #define RCC_APB1Periph_DAC1              RCC_APB1ENR_DAC1EN
 532 #define RCC_APB1Periph_I2C3              RCC_APB1ENR_I2C3EN
 533 #define RCC_APB1Periph_DAC2              RCC_APB1ENR_DAC2EN
 534 #define RCC_APB1Periph_DAC               RCC_APB1Periph_DAC1
 535
 536
 537 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x890137C8) == 0x00) && ((PERIPH) != 0x00))
 538 /**
 539   * @}
 540   */
 541
 542 /** @defgroup RCC_MCO_Clock_Source
 543   * @{
 544   */
 545
 546 #define RCC_MCOSource_NoClock            ((uint8_t)0x00)
 547 #define RCC_MCOSource_LSI                ((uint8_t)0x02)
 548 #define RCC_MCOSource_LSE                ((uint8_t)0x03)
 549 #define RCC_MCOSource_SYSCLK             ((uint8_t)0x04)
 550 #define RCC_MCOSource_HSI                ((uint8_t)0x05)
 551 #define RCC_MCOSource_HSE                ((uint8_t)0x06)
 552 #define RCC_MCOSource_PLLCLK_Div2        ((uint8_t)0x07)
 553
 554 #define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) ||((SOURCE) == RCC_MCOSource_SYSCLK) ||\
 555                                     ((SOURCE) == RCC_MCOSource_HSI)  || ((SOURCE) == RCC_MCOSource_HSE) || \
 556                                     ((SOURCE) == RCC_MCOSource_LSI)  || ((SOURCE) == RCC_MCOSource_LSE) || \
 557                                     ((SOURCE) == RCC_MCOSource_PLLCLK_Div2))
 558 /**
 559   * @}
 560   */
 561
 562 /** @defgroup RCC_MCOPrescaler
 563   * @{
 564   */
 565
 566 #define RCC_MCOPrescaler_1            RCC_CFGR_MCO_PRE_1
 567 #define RCC_MCOPrescaler_2            RCC_CFGR_MCO_PRE_2
 568 #define RCC_MCOPrescaler_4            RCC_CFGR_MCO_PRE_4
 569 #define RCC_MCOPrescaler_8            RCC_CFGR_MCO_PRE_8
 570 #define RCC_MCOPrescaler_16           RCC_CFGR_MCO_PRE_16
 571 #define RCC_MCOPrescaler_32           RCC_CFGR_MCO_PRE_32
 572 #define RCC_MCOPrescaler_64           RCC_CFGR_MCO_PRE_64
 573 #define RCC_MCOPrescaler_128          RCC_CFGR_MCO_PRE_128
 574
 575 #define IS_RCC_MCO_PRESCALER(PRESCALER) (((PRESCALER) == RCC_MCOPrescaler_1)  || \
 576                                          ((PRESCALER) == RCC_MCOPrescaler_2)  || \
 577                                          ((PRESCALER) == RCC_MCOPrescaler_4)  || \
 578                                          ((PRESCALER) == RCC_MCOPrescaler_8)  || \
 579                                          ((PRESCALER) == RCC_MCOPrescaler_16) || \
 580                                          ((PRESCALER) == RCC_MCOPrescaler_32) || \
 581                                          ((PRESCALER) == RCC_MCOPrescaler_64) || \
 582                                          ((PRESCALER) == RCC_MCOPrescaler_128))
 583 /**
 584   * @}
 585   */
 586
 587 /** @defgroup RCC_USB_Device_clock_source
 588   * @{
 589   */
 590
 591 #define RCC_USBCLKSource_PLLCLK_1Div5   ((uint8_t)0x00)
 592 #define RCC_USBCLKSource_PLLCLK_Div1    ((uint8_t)0x01)
 593
 594 #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
 595                                       ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
 596 /**
 597   * @}
 598   */
 599
 600 /** @defgroup RCC_Flag
 601   * @{
 602   */
 603 #define RCC_FLAG_HSIRDY                  ((uint8_t)0x01)
 604 #define RCC_FLAG_HSERDY                  ((uint8_t)0x11)
 605 #define RCC_FLAG_PLLRDY                  ((uint8_t)0x19)
 606 #define RCC_FLAG_MCOF                    ((uint8_t)0x9C)
 607 #define RCC_FLAG_LSERDY                  ((uint8_t)0x21)
 608 #define RCC_FLAG_LSIRDY                  ((uint8_t)0x41)
 609 #define RCC_FLAG_OBLRST                  ((uint8_t)0x59)
 610 #define RCC_FLAG_PINRST                  ((uint8_t)0x5A)
 611 #define RCC_FLAG_PORRST                  ((uint8_t)0x5B)
 612 #define RCC_FLAG_SFTRST                  ((uint8_t)0x5C)
 613 #define RCC_FLAG_IWDGRST                 ((uint8_t)0x5D)
 614 #define RCC_FLAG_WWDGRST                 ((uint8_t)0x5E)
 615 #define RCC_FLAG_LPWRRST                 ((uint8_t)0x5F)
 616
 617 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
 618                            ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
 619                            ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_OBLRST) || \
 620                            ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
 621                            ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
 622                            ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
 623                            ((FLAG) == RCC_FLAG_MCOF))
 624
 625 #define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
 626
 627 /**
 628   * @}
 629   */
 630
 631 /**
 632   * @}
 633   */
 634
 635 /* Exported macro ------------------------------------------------------------*/
 636 /* Exported functions ------------------------------------------------------- */
 637
 638 /* Function used to set the RCC clock configuration to the default reset state */
 639 void RCC_DeInit(void);
 640
 641 /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
 642 void RCC_HSEConfig(uint8_t RCC_HSE);
 643 ErrorStatus RCC_WaitForHSEStartUp(void);
 644 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
 645 void RCC_HSICmd(FunctionalState NewState);
 646 void RCC_LSEConfig(uint32_t RCC_LSE);
 647 void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive);
 648 void RCC_LSICmd(FunctionalState NewState);
 649 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
 650 void RCC_PLLCmd(FunctionalState NewState);
 651 void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div);
 652 void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
 653 #ifdef STM32F303xC
 654  void RCC_MCOConfig(uint8_t RCC_MCOSource);
 655 #else
 656  void RCC_MCOConfig(uint8_t RCC_MCOSource,uint32_t RCC_MCOPrescaler);
 657 #endif /* STM32F303xC */
 658
 659 /* System, AHB and APB busses clocks configuration functions ******************/
 660 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
 661 uint8_t RCC_GetSYSCLKSource(void);
 662 void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
 663 void RCC_PCLK1Config(uint32_t RCC_HCLK);
 664 void RCC_PCLK2Config(uint32_t RCC_HCLK);
 665 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
 666
 667 /* Peripheral clocks configuration functions **********************************/
 668 void RCC_ADCCLKConfig(uint32_t RCC_PLLCLK);
 669 void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK);
 670 void RCC_TIMCLKConfig(uint32_t RCC_TIMCLK);
 671 void RCC_HRTIM1CLKConfig(uint32_t RCC_HRTIMCLK);
 672 void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
 673 void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK);
 674 void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
 675
 676 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
 677 void RCC_RTCCLKCmd(FunctionalState NewState);
 678 void RCC_BackupResetCmd(FunctionalState NewState);
 679
 680 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
 681 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
 682 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
 683
 684 void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
 685 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
 686 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
 687
 688 /* Interrupts and flags management functions **********************************/
 689 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
 690 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
 691 void RCC_ClearFlag(void);
 692 ITStatus RCC_GetITStatus(uint8_t RCC_IT);
 693 void RCC_ClearITPendingBit(uint8_t RCC_IT);
 694
 695 #ifdef __cplusplus
 696 }
 697 #endif
 698
 699 #endif /* __STM32F30x_RCC_H */
 700
 701 /**
 702   * @}
 703   */
 704
 705 /**
 706   * @}
 707   */
 708
 709 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/