tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_syscfg.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f30x_syscfg.c
   4   * @author  MCD Application Team
   5   * @version V1.1.0
   6   * @date    27-February-2014
   7   * @brief   This file provides firmware functions to manage the following
   8   *          functionalities of the SYSCFG peripheral:
   9   *           + Remapping the memory mapped at 0x00000000
  10   *           + Remapping the DMA channels
  11   *           + Enabling I2C fast mode plus driving capability for I2C plus
  12   *           + Remapping USB interrupt line
  13   *           + Configuring the EXTI lines connection to the GPIO port
  14   *           + Configuring the CLASSB requirements
  15   *
  16   @verbatim
  17
  18  ===============================================================================
  19                       ##### How to use this driver #####
  20  ===============================================================================
  21     [..] The SYSCFG registers can be accessed only when the SYSCFG
  22          interface APB clock is enabled.
  23     [..] To enable SYSCFG APB clock use:
  24          RCC_APBPeriphClockCmd(RCC_APBPeriph_SYSCFG, ENABLE);
  25
  26   @endverbatim
  27
  28   ******************************************************************************
  29   * @attention
  30   *
  31   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  32   *
  33   * Redistribution and use in source and binary forms, with or without modification,
  34   * are permitted provided that the following conditions are met:
  35   *   1. Redistributions of source code must retain the above copyright notice,
  36   *      this list of conditions and the following disclaimer.
  37   *   2. Redistributions in binary form must reproduce the above copyright notice,
  38   *      this list of conditions and the following disclaimer in the documentation
  39   *      and/or other materials provided with the distribution.
  40   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  41   *      may be used to endorse or promote products derived from this software
  42   *      without specific prior written permission.
  43   *
  44   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  45   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  46   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  47   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  48   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  49   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  50   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  51   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  52   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  53   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  54   *
  55   ******************************************************************************
  56   */
  57
  58 /* Includes ------------------------------------------------------------------*/
  59 #include "stm32f30x_syscfg.h"
  60
  61 /** @addtogroup STM32F30x_StdPeriph_Driver
  62   * @{
  63   */
  64
  65 /** @defgroup SYSCFG
  66   * @brief SYSCFG driver modules
  67   * @{
  68   */
  69
  70 /* Private typedef -----------------------------------------------------------*/
  71 /* Private define ------------------------------------------------------------*/
  72 /* Reset value od SYSCFG_CFGR1 register */
  73 #define CFGR1_CLEAR_MASK            ((uint32_t)0x7C000000)
  74
  75 /* ------------ SYSCFG registers bit address in the alias region -------------*/
  76 #define SYSCFG_OFFSET                (SYSCFG_BASE - PERIPH_BASE)
  77
  78 /* --- CFGR1 Register ---*/
  79 /* Alias word address of USB_IT_RMP bit */
  80 #define CFGR1_OFFSET                 (SYSCFG_OFFSET + 0x00)
  81 #define USBITRMP_BitNumber            0x05
  82 #define CFGR1_USBITRMP_BB            (PERIPH_BB_BASE + (CFGR1_OFFSET * 32) + (USBITRMP_BitNumber * 4))
  83
  84 /* --- CFGR2 Register ---*/
  85 /* Alias word address of BYP_ADDR_PAR bit */
  86 #define CFGR2_OFFSET                 (SYSCFG_OFFSET + 0x18)
  87 #define BYPADDRPAR_BitNumber          0x04
  88 #define CFGR1_BYPADDRPAR_BB          (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (BYPADDRPAR_BitNumber * 4))
  89
  90 /* Private macro -------------------------------------------------------------*/
  91 /* Private variables ---------------------------------------------------------*/
  92 /* Private function prototypes -----------------------------------------------*/
  93 /* Private functions ---------------------------------------------------------*/
  94
  95 /** @defgroup SYSCFG_Private_Functions
  96   * @{
  97   */
  98
  99 /** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions
 100  *  @brief   SYSCFG Initialization and Configuration functions
 101  *
 102 @verbatim
 103  ===============================================================================
 104          ##### SYSCFG Initialization and Configuration functions #####
 105  ===============================================================================
 106
 107 @endverbatim
 108   * @{
 109   */
 110
 111 /**
 112   * @brief  Deinitializes the SYSCFG registers to their default reset values.
 113   * @param  None
 114   * @retval None
 115   * @note   MEM_MODE bits are not affected by APB reset.
 116   *         MEM_MODE bits took the value from the user option bytes.
 117   */
 118 void SYSCFG_DeInit(void)
 119 {
 120   /* Reset SYSCFG_CFGR1 register to reset value without affecting MEM_MODE bits */
 121   SYSCFG->CFGR1 &= SYSCFG_CFGR1_MEM_MODE;
 122   /* Set FPU Interrupt Enable bits to default value */
 123   SYSCFG->CFGR1 |= 0x7C000000;
 124   /* Reset RAM Write protection bits to default value */
 125   SYSCFG->RCR = 0x00000000;
 126   /* Set EXTICRx registers to reset value */
 127   SYSCFG->EXTICR[0] = 0;
 128   SYSCFG->EXTICR[1] = 0;
 129   SYSCFG->EXTICR[2] = 0;
 130   SYSCFG->EXTICR[3] = 0;
 131   /* Set CFGR2 register to reset value */
 132   SYSCFG->CFGR2 = 0;
 133   /* Set CFGR3 register to reset value */
 134   SYSCFG->CFGR3 = 0;
 135 }
 136
 137 /**
 138   * @brief  Configures the memory mapping at address 0x00000000.
 139   * @param  SYSCFG_MemoryRemap: selects the memory remapping.
 140   *   This parameter can be one of the following values:
 141   *     @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
 142   *     @arg SYSCFG_MemoryRemap_SystemMemory: System Flash memory mapped at 0x00000000
 143   *     @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000
 144   * @retval None
 145   */
 146 void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap)
 147 {
 148   uint32_t tmpcfgr1 = 0;
 149
 150   /* Check the parameter */
 151   assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap));
 152
 153   /* Get CFGR1 register value */
 154   tmpcfgr1 = SYSCFG->CFGR1;
 155
 156   /* Clear MEM_MODE bits */
 157   tmpcfgr1 &= (uint32_t) (~SYSCFG_CFGR1_MEM_MODE);
 158
 159   /* Set the new MEM_MODE bits value */
 160   tmpcfgr1 |= (uint32_t) SYSCFG_MemoryRemap;
 161
 162   /* Set CFGR1 register with the new memory remap configuration */
 163   SYSCFG->CFGR1 = tmpcfgr1;
 164 }
 165
 166 /**
 167   * @brief  Configures the DMA channels remapping.
 168   * @param  SYSCFG_DMARemap: selects the DMA channels remap.
 169   *   This parameter can be one of the following values:
 170   *     @arg SYSCFG_DMARemap_TIM17: Remap TIM17 DMA requests from DMA1 channel1 to channel2
 171   *     @arg SYSCFG_DMARemap_TIM16: Remap TIM16 DMA requests from DMA1 channel3 to channel4
 172   *     @arg SYSCFG_DMARemap_TIM6DAC1Ch1: Remap TIM6/DAC1 DMA requests from DMA2 channel 3 to DMA1 channel 3
 173   *     @arg SYSCFG_DMARemap_TIM7DAC1Ch2: Remap TIM7/DAC2 DMA requests from DMA2 channel 4 to DMA1 channel 4
 174   *     @arg SYSCFG_DMARemap_ADC2ADC4: Remap ADC2 and ADC4 DMA requests from DMA2 channel1/channel3 to channel3/channel4
 175   *     @arg SYSCFG_DMARemap_DAC2Ch1: Remap DAC2 DMA requests to DMA1 channel5
 176   *     @arg SYSCFG_DMARemapCh2_SPI1_RX: Remap SPI1 RX DMA1 CH2 requests
 177   *     @arg SYSCFG_DMARemapCh4_SPI1_RX: Remap SPI1 RX DMA CH4 requests
 178   *     @arg SYSCFG_DMARemapCh6_SPI1_RX: Remap SPI1 RX DMA CH6 requests
 179   *     @arg SYSCFG_DMARemapCh3_SPI1_TX: Remap SPI1 TX DMA CH2 requests
 180   *     @arg SYSCFG_DMARemapCh5_SPI1_TX: Remap SPI1 TX DMA CH5 requests
 181   *     @arg SYSCFG_DMARemapCh7_SPI1_TX: Remap SPI1 TX DMA CH7 requests
 182   *     @arg SYSCFG_DMARemapCh7_I2C1_RX: Remap I2C1 RX DMA CH7 requests
 183   *     @arg SYSCFG_DMARemapCh3_I2C1_RX: Remap I2C1 RX DMA CH3 requests
 184   *     @arg SYSCFG_DMARemapCh5_I2C1_RX: Remap I2C1 RX DMA CH5 requests
 185   *     @arg SYSCFG_DMARemapCh6_I2C1_TX: Remap I2C1 TX DMA CH6 requests
 186   *     @arg SYSCFG_DMARemapCh2_I2C1_TX: Remap I2C1 TX DMA CH2 requests
 187   *     @arg SYSCFG_DMARemapCh4_I2C1_TX: Remap I2C1 TX DMA CH4 requests
 188   *     @arg SYSCFG_DMARemapCh4_ADC2: Remap ADC2 DMA1 Ch4 requests
 189   *     @arg SYSCFG_DMARemapCh2_ADC2: Remap ADC2 DMA1 Ch2 requests
 190   * @param  NewState: new state of the DMA channel remapping.
 191   *         This parameter can be: Enable or Disable.
 192   * @note   When enabled, DMA channel of the selected peripheral is remapped
 193   * @note   When disabled, Default DMA channel is mapped to the selected peripheral
 194   * @note
 195   *           By default TIM17 DMA requests is mapped to channel 1
 196   *           use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Enable)
 197   *           to remap TIM17 DMA requests to DMA1 channel 2
 198   *           use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Disable)
 199   *           to map TIM17 DMA requests to DMA1 channel 1 (default mapping)
 200   * @retval None
 201   */
 202 void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState)
 203 {
 204   /* Check the parameters */
 205   assert_param(IS_SYSCFG_DMA_REMAP(SYSCFG_DMARemap));
 206   assert_param(IS_FUNCTIONAL_STATE(NewState));
 207
 208   if ((SYSCFG_DMARemap & 0x80000000)!= 0x80000000)
 209   {
 210     if (NewState != DISABLE)
 211     {
 212       /* Remap the DMA channel */
 213       SYSCFG->CFGR1 |= (uint32_t)SYSCFG_DMARemap;
 214     }
 215     else
 216     {
 217       /* use the default DMA channel mapping */
 218       SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_DMARemap);
 219     }
 220   }
 221   else
 222   {
 223     if (NewState != DISABLE)
 224     {
 225       /* Remap the DMA channel */
 226       SYSCFG->CFGR3 |= (uint32_t)SYSCFG_DMARemap;
 227     }
 228     else
 229     {
 230       /* use the default DMA channel mapping */
 231       SYSCFG->CFGR3 &= (uint32_t)(~SYSCFG_DMARemap);
 232     }
 233   }
 234 }
 235
 236 /**
 237   * @brief  Configures the remapping capabilities of DAC/TIM triggers.
 238   * @param  SYSCFG_TriggerRemap: selects the trigger to be remapped.
 239   *   This parameter can be one of the following values:
 240   *     @arg SYSCFG_TriggerRemap_DACTIM3: Remap DAC trigger from TIM8 to TIM3
 241   *     @arg SYSCFG_TriggerRemap_TIM1TIM17: Remap TIM1 ITR3 from TIM4 TRGO to TIM17 OC
 242   *     @arg SYSCFG_TriggerRemap_DACHRTIM1_TRIG1: Remap DAC trigger to HRTIM1 TRIG1
 243   *     @arg SYSCFG_TriggerRemap_DACHRTIM1_TRIG2: Remap DAC trigger to HRTIM1 TRIG2
 244   * @param  NewState: new state of the trigger mapping.
 245   *         This parameter can be: ENABLE or DISABLE.
 246   * @note   ENABLE:  Enable fast mode plus driving capability for selected pin
 247   * @note   DISABLE: Disable fast mode plus driving capability for selected pin
 248   * @retval None
 249   */
 250 void SYSCFG_TriggerRemapConfig(uint32_t SYSCFG_TriggerRemap, FunctionalState NewState)
 251 {
 252   /* Check the parameters */
 253   assert_param(IS_SYSCFG_TRIGGER_REMAP(SYSCFG_TriggerRemap));
 254   assert_param(IS_FUNCTIONAL_STATE(NewState));
 255
 256   if ((SYSCFG_TriggerRemap & 0x80000000)!= 0x80000000)
 257   {
 258     if (NewState != DISABLE)
 259     {
 260       /* Remap the trigger */
 261       SYSCFG->CFGR1 |= (uint32_t)SYSCFG_TriggerRemap;
 262     }
 263     else
 264     {
 265       /* Use the default trigger mapping */
 266       SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_TriggerRemap);
 267     }
 268   }
 269   else
 270   {
 271     if (NewState != DISABLE)
 272     {
 273       /* Remap the trigger */
 274       SYSCFG->CFGR3 |= (uint32_t)SYSCFG_TriggerRemap;
 275     }
 276     else
 277     {
 278       /* Use the default trigger mapping */
 279       SYSCFG->CFGR3 &= (uint32_t)(~SYSCFG_TriggerRemap);
 280     }
 281   }
 282 }
 283
 284 /**
 285   * @brief  Configures the remapping capabilities of encoder mode.
 286   * @ note This feature implement the so-called M/T method for measuring speed
 287   *        and position using quadrature encoders.
 288   * @param  SYSCFG_EncoderRemap: selects the remap option for encoder mode.
 289   *   This parameter can be one of the following values:
 290   *     @arg SYSCFG_EncoderRemap_No: No remap
 291   *     @arg SYSCFG_EncoderRemap_TIM2: Timer 2 IC1 and IC2 connected to TIM15 IC1 and IC2
 292   *     @arg SYSCFG_EncoderRemap_TIM3: Timer 3 IC1 and IC2 connected to TIM15 IC1 and IC2
 293   *     @arg SYSCFG_EncoderRemap_TIM4: Timer 4 IC1 and IC2 connected to TIM15 IC1 and IC2
 294   * @retval None
 295   */
 296 void SYSCFG_EncoderRemapConfig(uint32_t SYSCFG_EncoderRemap)
 297 {
 298   /* Check the parameter */
 299   assert_param(IS_SYSCFG_ENCODER_REMAP(SYSCFG_EncoderRemap));
 300
 301   /* Reset the encoder mode remapping bits */
 302   SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_CFGR1_ENCODER_MODE);
 303
 304   /* Set the selected configuration */
 305   SYSCFG->CFGR1 |= (uint32_t)(SYSCFG_EncoderRemap);
 306 }
 307
 308 /**
 309   * @brief  Remaps the USB interrupt lines.
 310   * @param  NewState: new state of the mapping of USB interrupt lines.
 311   *         This parameter can be:
 312   * @param  ENABLE: Remap the USB interrupt line as following:
 313   *         @arg  USB Device High Priority (USB_HP) interrupt mapped to line 74.
 314   *         @arg  USB Device Low Priority (USB_LP) interrupt mapped to line 75.
 315   *         @arg  USB Wakeup Interrupt (USB_WKUP) interrupt mapped to line 76.
 316   * @param  DISABLE: Use the default USB interrupt line:
 317   *         @arg  USB Device High Priority (USB_HP) interrupt mapped to line 19.
 318   *         @arg  USB Device Low Priority (USB_LP) interrupt mapped to line 20.
 319   *         @arg  USB Wakeup Interrupt (USB_WKUP) interrupt mapped to line 42.
 320   * @retval None
 321   */
 322 void SYSCFG_USBInterruptLineRemapCmd(FunctionalState NewState)
 323 {
 324   /* Check the parameter */
 325   assert_param(IS_FUNCTIONAL_STATE(NewState));
 326
 327   /* Remap the USB interupt lines */
 328   *(__IO uint32_t *) CFGR1_USBITRMP_BB = (uint32_t)NewState;
 329 }
 330
 331 /**
 332   * @brief  Configures the I2C fast mode plus driving capability.
 333   * @param  SYSCFG_I2CFastModePlus: selects the pin.
 334   *   This parameter can be one of the following values:
 335   *     @arg SYSCFG_I2CFastModePlus_PB6: Configure fast mode plus driving capability for PB6
 336   *     @arg SYSCFG_I2CFastModePlus_PB7: Configure fast mode plus driving capability for PB7
 337   *     @arg SYSCFG_I2CFastModePlus_PB8: Configure fast mode plus driving capability for PB8
 338   *     @arg SYSCFG_I2CFastModePlus_PB9: Configure fast mode plus driving capability for PB9
 339   *     @arg SYSCFG_I2CFastModePlus_I2C1: Configure fast mode plus driving capability for I2C1 pins
 340   *     @arg SYSCFG_I2CFastModePlus_I2C2: Configure fast mode plus driving capability for I2C2 pins
 341   * @param  NewState: new state of the DMA channel remapping.
 342   *         This parameter can be:
 343   *     @arg ENABLE: Enable fast mode plus driving capability for selected I2C pin
 344   *     @arg DISABLE: Disable fast mode plus driving capability for selected I2C pin
 345   * @note  For I2C1, fast mode plus driving capability can be enabled on all selected
 346   *        I2C1 pins using SYSCFG_I2CFastModePlus_I2C1 parameter or independently
 347   *        on each one of the following pins PB6, PB7, PB8 and PB9.
 348   * @note  For remaing I2C1 pins (PA14, PA15...) fast mode plus driving capability
 349   *        can be enabled only by using SYSCFG_I2CFastModePlus_I2C1 parameter.
 350   * @note  For all I2C2 pins fast mode plus driving capability can be enabled
 351   *        only by using SYSCFG_I2CFastModePlus_I2C2 parameter.
 352   * @retval None
 353   */
 354 void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState)
 355 {
 356   /* Check the parameters */
 357   assert_param(IS_SYSCFG_I2C_FMP(SYSCFG_I2CFastModePlus));
 358   assert_param(IS_FUNCTIONAL_STATE(NewState));
 359
 360   if (NewState != DISABLE)
 361   {
 362     /* Enable fast mode plus driving capability for selected I2C pin */
 363     SYSCFG->CFGR1 |= (uint32_t)SYSCFG_I2CFastModePlus;
 364   }
 365   else
 366   {
 367     /* Disable fast mode plus driving capability for selected I2C pin */
 368     SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_I2CFastModePlus);
 369   }
 370 }
 371
 372 /**
 373   * @brief  Enables or disables the selected SYSCFG interrupts.
 374   * @param  SYSCFG_IT: specifies the SYSCFG interrupt sources to be enabled or disabled.
 375   *   This parameter can be one of the following values:
 376   *     @arg SYSCFG_IT_IXC: Inexact Interrupt
 377   *     @arg SYSCFG_IT_IDC: Input denormal Interrupt
 378   *     @arg SYSCFG_IT_OFC: Overflow Interrupt
 379   *     @arg SYSCFG_IT_UFC: Underflow Interrupt
 380   *     @arg SYSCFG_IT_DZC: Divide-by-zero Interrupt
 381   *     @arg SYSCFG_IT_IOC: Invalid operation Interrupt
 382   * @param  NewState: new state of the specified SYSCFG interrupts.
 383   *         This parameter can be: ENABLE or DISABLE.
 384   * @retval None
 385   */
 386 void SYSCFG_ITConfig(uint32_t SYSCFG_IT, FunctionalState NewState)
 387 {
 388   /* Check the parameters */
 389   assert_param(IS_FUNCTIONAL_STATE(NewState));
 390   assert_param(IS_SYSCFG_IT(SYSCFG_IT));
 391
 392   if (NewState != DISABLE)
 393   {
 394     /* Enable the selected SYSCFG interrupts */
 395     SYSCFG->CFGR1 |= SYSCFG_IT;
 396   }
 397   else
 398   {
 399     /* Disable the selected SYSCFG interrupts */
 400     SYSCFG->CFGR1 &= ((uint32_t)~SYSCFG_IT);
 401   }
 402 }
 403
 404 /**
 405   * @brief  Selects the GPIO pin used as EXTI Line.
 406   * @param  EXTI_PortSourceGPIOx : selects the GPIO port to be used as source
 407   *                                for EXTI lines where x can be (A, B, C, D, E or F).
 408   * @param  EXTI_PinSourcex: specifies the EXTI line to be configured.
 409   *         This parameter can be EXTI_PinSourcex where x can be (0..15)
 410   * @retval None
 411   */
 412 void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
 413 {
 414   uint32_t tmp = 0x00;
 415
 416   /* Check the parameters */
 417   assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
 418   assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
 419
 420   tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
 421   SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
 422   SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
 423 }
 424
 425 /**
 426   * @brief  Connects the selected parameter to the break input of TIM1.
 427   * @note   The selected configuration is locked and can be unlocked by system reset
 428   * @param  SYSCFG_Break: selects the configuration to be connected to break
 429   *         input of TIM1
 430   *   This parameter can be any combination of the following values:
 431   *     @arg SYSCFG_Break_PVD: PVD interrupt is connected to the break input of TIM1.
 432   *     @arg SYSCFG_Break_SRAMParity: SRAM Parity error is connected to the break input of TIM1.
 433   *     @arg SYSCFG_Break_HardFault: Lockup output of CortexM4 is connected to the break input of TIM1.
 434   * @retval None
 435   */
 436 void SYSCFG_BreakConfig(uint32_t SYSCFG_Break)
 437 {
 438   /* Check the parameter */
 439   assert_param(IS_SYSCFG_LOCK_CONFIG(SYSCFG_Break));
 440
 441   SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break;
 442 }
 443
 444 /**
 445   * @brief  Disables the parity check on RAM.
 446   * @note   Disabling the parity check on RAM locks the configuration bit.
 447   *         To re-enable the parity check on RAM perform a system reset.
 448   * @param  None
 449   * @retval None
 450   */
 451 void SYSCFG_BypassParityCheckDisable(void)
 452 {
 453   /* Disable the adddress parity check on RAM */
 454   *(__IO uint32_t *) CFGR1_BYPADDRPAR_BB = (uint32_t)0x00000001;
 455 }
 456
 457 /**
 458   * @brief  Enables the ICODE SRAM write protection.
 459   * @note   Enabling the ICODE SRAM write protection locks the configuration bit.
 460   *         To disable the ICODE SRAM write protection perform a system reset.
 461   * @param  None
 462   * @retval None
 463   */
 464 void SYSCFG_SRAMWRPEnable(uint32_t SYSCFG_SRAMWRP)
 465 {
 466   /* Check the parameter */
 467   assert_param(IS_SYSCFG_PAGE(SYSCFG_SRAMWRP));
 468
 469   /* Enable the write-protection on the selected ICODE SRAM page */
 470   SYSCFG->RCR |= (uint32_t)SYSCFG_SRAMWRP;
 471 }
 472
 473 /**
 474   * @brief  Checks whether the specified SYSCFG flag is set or not.
 475   * @param  SYSCFG_Flag: specifies the SYSCFG flag to check.
 476   *   This parameter can be one of the following values:
 477   *     @arg SYSCFG_FLAG_PE: SRAM parity error flag.
 478   * @retval The new state of SYSCFG_Flag (SET or RESET).
 479   */
 480 FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag)
 481 {
 482   FlagStatus bitstatus = RESET;
 483
 484   /* Check the parameter */
 485   assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));
 486
 487   /* Check the status of the specified SPI flag */
 488   if ((SYSCFG->CFGR2 & SYSCFG_CFGR2_SRAM_PE) != (uint32_t)RESET)
 489   {
 490     /* SYSCFG_Flag is set */
 491     bitstatus = SET;
 492   }
 493   else
 494   {
 495     /* SYSCFG_Flag is reset */
 496     bitstatus = RESET;
 497   }
 498   /* Return the SYSCFG_Flag status */
 499   return  bitstatus;
 500 }
 501
 502 /**
 503   * @brief  Clears the selected SYSCFG flag.
 504   * @param  SYSCFG_Flag: selects the flag to be cleared.
 505   *   This parameter can be any combination of the following values:
 506   *     @arg SYSCFG_FLAG_PE: SRAM parity error flag.
 507   * @retval None
 508   */
 509 void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag)
 510 {
 511   /* Check the parameter */
 512   assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));
 513
 514   SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Flag;
 515 }
 516
 517 /**
 518   * @}
 519   */
 520
 521 /**
 522   * @}
 523   */
 524
 525 /**
 526   * @}
 527   */
 528
 529 /**
 530   * @}
 531   */
 532 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 533