tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/TOOLCHAIN_GCC_ARM/startup_STM32F40x.s

   1 /* File: startup_STM32F40x.S
   2  * Purpose: startup file for Cortex-M4 devices. Should use with
   3  *   GCC for ARM Embedded Processors
   4  * Version: V1.4
   5  * Date: 09 July 2012
   6  *
   7  * Copyright (c) 2011, 2012, ARM Limited
   8  * All rights reserved.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions are met:
  12     * Redistributions of source code must retain the above copyright
  13       notice, this list of conditions and the following disclaimer.
  14     * Redistributions in binary form must reproduce the above copyright
  15       notice, this list of conditions and the following disclaimer in the
  16       documentation and/or other materials provided with the distribution.
  17     * Neither the name of the ARM Limited nor the
  18       names of its contributors may be used to endorse or promote products
  19       derived from this software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  23  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  24  * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
  25  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  27  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  28  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  30  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32     .syntax unified
  33     .arch armv7-m
  34
  35     .section .stack
  36     .align 3
  37 #ifdef __STACK_SIZE
  38     .equ    Stack_Size, __STACK_SIZE
  39 #else
  40     .equ    Stack_Size, 0xc00
  41 #endif
  42     .globl    __StackTop
  43     .globl    __StackLimit
  44 __StackLimit:
  45     .space    Stack_Size
  46     .size __StackLimit, . - __StackLimit
  47 __StackTop:
  48     .size __StackTop, . - __StackTop
  49
  50     .section .heap
  51     .align 3
  52 #ifdef __HEAP_SIZE
  53     .equ    Heap_Size, __HEAP_SIZE
  54 #else
  55     .equ    Heap_Size, 0
  56 #endif
  57     .globl    __HeapBase
  58     .globl    __HeapLimit
  59 __HeapBase:
  60     .if    Heap_Size
  61     .space    Heap_Size
  62     .endif
  63     .size __HeapBase, . - __HeapBase
  64 __HeapLimit:
  65     .size __HeapLimit, . - __HeapLimit
  66
  67     .section .isr_vector
  68     .align 2
  69     .globl __isr_vector
  70 __isr_vector:
  71     .long    __StackTop            /* Top of Stack */
  72     .long    Reset_Handler         /* Reset Handler */
  73     .long    NMI_Handler           /* NMI Handler */
  74     .long    HardFault_Handler     /* Hard Fault Handler */
  75     .long    MemManage_Handler     /* MPU Fault Handler */
  76     .long    BusFault_Handler      /* Bus Fault Handler */
  77     .long    UsageFault_Handler    /* Usage Fault Handler */
  78     .long    0                     /* Reserved */
  79     .long    0                     /* Reserved */
  80     .long    0                     /* Reserved */
  81     .long    0                     /* Reserved */
  82     .long    SVC_Handler           /* SVCall Handler */
  83     .long    DebugMon_Handler      /* Debug Monitor Handler */
  84     .long    0                     /* Reserved */
  85     .long    PendSV_Handler        /* PendSV Handler */
  86     .long    SysTick_Handler       /* SysTick Handler */
  87
  88     /* External interrupts */
  89     .long     WWDG_IRQHandler               /* Window WatchDog */
  90     .long     PVD_IRQHandler                /* PVD through EXTI Line detection */
  91     .long     TAMP_STAMP_IRQHandler         /* Tamper and TimeStamps through the EXTI line */
  92     .long     RTC_WKUP_IRQHandler           /* RTC Wakeup through the EXTI line */
  93     .long     FLASH_IRQHandler              /* FLASH */
  94     .long     RCC_IRQHandler                /* RCC */
  95     .long     EXTI0_IRQHandler              /* EXTI Line0 */
  96     .long     EXTI1_IRQHandler              /* EXTI Line1 */
  97     .long     EXTI2_IRQHandler              /* EXTI Line2 */
  98     .long     EXTI3_IRQHandler              /* EXTI Line3 */
  99     .long     EXTI4_IRQHandler              /* EXTI Line4 */
 100     .long     DMA1_Stream0_IRQHandler       /* DMA1 Stream 0 */
 101     .long     DMA1_Stream1_IRQHandler       /* DMA1 Stream 1 */
 102     .long     DMA1_Stream2_IRQHandler       /* DMA1 Stream 2 */
 103     .long     DMA1_Stream3_IRQHandler       /* DMA1 Stream 3 */
 104     .long     DMA1_Stream4_IRQHandler       /* DMA1 Stream 4 */
 105     .long     DMA1_Stream5_IRQHandler       /* DMA1 Stream 5 */
 106     .long     DMA1_Stream6_IRQHandler       /* DMA1 Stream 6 */
 107     .long     ADC_IRQHandler                /* ADC1, ADC2 and ADC3s */
 108     .long     CAN1_TX_IRQHandler            /* CAN1 TX */
 109     .long     CAN1_RX0_IRQHandler           /* CAN1 RX0 */
 110     .long     CAN1_RX1_IRQHandler           /* CAN1 RX1 */
 111     .long     CAN1_SCE_IRQHandler           /* CAN1 SCE */
 112     .long     EXTI9_5_IRQHandler            /* External Line[9:5]s */
 113     .long     TIM1_BRK_TIM9_IRQHandler      /* TIM1 Break and TIM9 */
 114     .long     TIM1_UP_TIM10_IRQHandler      /* TIM1 Update and TIM10 */
 115     .long     TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
 116     .long     TIM1_CC_IRQHandler            /* TIM1 Capture Compare */
 117     .long     TIM2_IRQHandler               /* TIM2 */
 118     .long     TIM3_IRQHandler               /* TIM3 */
 119     .long     TIM4_IRQHandler               /* TIM4 */
 120     .long     I2C1_EV_IRQHandler            /* I2C1 Event */
 121     .long     I2C1_ER_IRQHandler            /* I2C1 Error */
 122     .long     I2C2_EV_IRQHandler            /* I2C2 Event */
 123     .long     I2C2_ER_IRQHandler            /* I2C2 Error */
 124     .long     SPI1_IRQHandler               /* SPI1 */
 125     .long     SPI2_IRQHandler               /* SPI2 */
 126     .long     USART1_IRQHandler             /* USART1 */
 127     .long     USART2_IRQHandler             /* USART2 */
 128     .long     USART3_IRQHandler             /* USART3 */
 129     .long     EXTI15_10_IRQHandler          /* External Line[15:10]s */
 130     .long     RTC_Alarm_IRQHandler          /* RTC Alarm (A and B) through EXTI Line */
 131     .long     OTG_FS_WKUP_IRQHandler        /* USB OTG FS Wakeup through EXTI line */
 132     .long     TIM8_BRK_TIM12_IRQHandler     /* TIM8 Break and TIM12 */
 133     .long     TIM8_UP_TIM13_IRQHandler      /* TIM8 Update and TIM13 */
 134     .long     TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
 135     .long     TIM8_CC_IRQHandler            /* TIM8 Capture Compare */
 136     .long     DMA1_Stream7_IRQHandler       /* DMA1 Stream7 */
 137     .long     FSMC_IRQHandler               /* FSMC */
 138     .long     SDIO_IRQHandler               /* SDIO */
 139     .long     TIM5_IRQHandler               /* TIM5 */
 140     .long     SPI3_IRQHandler               /* SPI3 */
 141     .long     UART4_IRQHandler              /* UART4 */
 142     .long     UART5_IRQHandler              /* UART5 */
 143     .long     TIM6_DAC_IRQHandler           /* TIM6 and DAC1&2 underrun errors */
 144     .long     TIM7_IRQHandler               /* TIM7 */
 145     .long     DMA2_Stream0_IRQHandler       /* DMA2 Stream 0 */
 146     .long     DMA2_Stream1_IRQHandler       /* DMA2 Stream 1 */
 147     .long     DMA2_Stream2_IRQHandler       /* DMA2 Stream 2 */
 148     .long     DMA2_Stream3_IRQHandler       /* DMA2 Stream 3 */
 149     .long     DMA2_Stream4_IRQHandler       /* DMA2 Stream 4 */
 150     .long     0                             /* Reserved */
 151     .long     0                             /* Reserved */
 152     .long     CAN2_TX_IRQHandler            /* CAN2 TX */
 153     .long     CAN2_RX0_IRQHandler           /* CAN2 RX0 */
 154     .long     CAN2_RX1_IRQHandler           /* CAN2 RX1 */
 155     .long     CAN2_SCE_IRQHandler           /* CAN2 SCE */
 156     .long     OTG_FS_IRQHandler             /* USB OTG FS */
 157     .long     DMA2_Stream5_IRQHandler       /* DMA2 Stream 5 */
 158     .long     DMA2_Stream6_IRQHandler       /* DMA2 Stream 6 */
 159     .long     DMA2_Stream7_IRQHandler       /* DMA2 Stream 7 */
 160     .long     USART6_IRQHandler             /* USART6 */
 161     .long     I2C3_EV_IRQHandler            /* I2C3 event */
 162     .long     I2C3_ER_IRQHandler            /* I2C3 error */
 163     .long     OTG_HS_EP1_OUT_IRQHandler     /* USB OTG HS End Point 1 Out */
 164     .long     OTG_HS_EP1_IN_IRQHandler      /* USB OTG HS End Point 1 In */
 165     .long     OTG_HS_WKUP_IRQHandler        /* USB OTG HS Wakeup through EXTI */
 166     .long     OTG_HS_IRQHandler             /* USB OTG HS */
 167     .long     0                             /* Reserved */
 168     .long     0                             /* Reserved */
 169     .long     HASH_RNG_IRQHandler           /* Hash and Rng */
 170     .long     FPU_IRQHandler                /* FPU */
 171
 172     .size    __isr_vector, . - __isr_vector
 173
 174     .text
 175     .thumb
 176     .thumb_func
 177     .align 2
 178     .globl    Reset_Handler
 179     .type    Reset_Handler, %function
 180 Reset_Handler:
 181 /*     Loop to copy data from read only memory to RAM. The ranges
 182  *      of copy from/to are specified by following symbols evaluated in
 183  *      linker script.
 184  *      __etext: End of code section, i.e., begin of data sections to copy from.
 185  *      __data_start__/__data_end__: RAM address range that data should be
 186  *      copied to. Both must be aligned to 4 bytes boundary.  */
 187
 188     ldr    r1, =__etext
 189     ldr    r2, =__data_start__
 190     ldr    r3, =__data_end__
 191
 192 .LC0:
 193     cmp     r2, r3
 194     ittt    lt
 195     ldrlt   r0, [r1], #4
 196     strlt   r0, [r2], #4
 197     blt    .LC0
 198
 199     ldr    r0, =SystemInit
 200     blx    r0
 201     ldr    r0, =_start
 202     bx     r0
 203     .pool
 204     .size Reset_Handler, . - Reset_Handler
 205
 206     .text
 207 /*    Macro to define default handlers. Default handler
 208  *    will be weak symbol and just dead loops. They can be
 209  *    overwritten by other handlers */
 210     .macro    def_default_handler    handler_name
 211     .align 1
 212     .thumb_func
 213     .weak    \handler_name
 214     .type    \handler_name, %function
 215 \handler_name :
 216     b    .
 217     .size    \handler_name, . - \handler_name
 218     .endm
 219
 220     def_default_handler    NMI_Handler
 221     def_default_handler    HardFault_Handler
 222     def_default_handler    MemManage_Handler
 223     def_default_handler    BusFault_Handler
 224     def_default_handler    UsageFault_Handler
 225     def_default_handler    SVC_Handler
 226     def_default_handler    DebugMon_Handler
 227     def_default_handler    PendSV_Handler
 228     def_default_handler    SysTick_Handler
 229     def_default_handler    Default_Handler
 230
 231     .macro    def_irq_default_handler    handler_name
 232     .weak     \handler_name
 233     .set      \handler_name, Default_Handler
 234     .endm
 235
 236     def_irq_default_handler     WWDG_IRQHandler
 237     def_irq_default_handler     PVD_IRQHandler
 238     def_irq_default_handler     TAMP_STAMP_IRQHandler
 239     def_irq_default_handler     RTC_WKUP_IRQHandler
 240     def_irq_default_handler     FLASH_IRQHandler
 241     def_irq_default_handler     RCC_IRQHandler
 242     def_irq_default_handler     EXTI0_IRQHandler
 243     def_irq_default_handler     EXTI1_IRQHandler
 244     def_irq_default_handler     EXTI2_IRQHandler
 245     def_irq_default_handler     EXTI3_IRQHandler
 246     def_irq_default_handler     EXTI4_IRQHandler
 247     def_irq_default_handler     DMA1_Stream0_IRQHandler
 248     def_irq_default_handler     DMA1_Stream1_IRQHandler
 249     def_irq_default_handler     DMA1_Stream2_IRQHandler
 250     def_irq_default_handler     DMA1_Stream3_IRQHandler
 251     def_irq_default_handler     DMA1_Stream4_IRQHandler
 252     def_irq_default_handler     DMA1_Stream5_IRQHandler
 253     def_irq_default_handler     DMA1_Stream6_IRQHandler
 254     def_irq_default_handler     ADC_IRQHandler
 255     def_irq_default_handler     CAN1_TX_IRQHandler
 256     def_irq_default_handler     CAN1_RX0_IRQHandler
 257     def_irq_default_handler     CAN1_RX1_IRQHandler
 258     def_irq_default_handler     CAN1_SCE_IRQHandler
 259     def_irq_default_handler     EXTI9_5_IRQHandler
 260     def_irq_default_handler     TIM1_BRK_TIM9_IRQHandler
 261     def_irq_default_handler     TIM1_UP_TIM10_IRQHandler
 262     def_irq_default_handler     TIM1_TRG_COM_TIM11_IRQHandler
 263     def_irq_default_handler     TIM1_CC_IRQHandler
 264     def_irq_default_handler     TIM2_IRQHandler
 265     def_irq_default_handler     TIM3_IRQHandler
 266     def_irq_default_handler     TIM4_IRQHandler
 267     def_irq_default_handler     I2C1_EV_IRQHandler
 268     def_irq_default_handler     I2C1_ER_IRQHandler
 269     def_irq_default_handler     I2C2_EV_IRQHandler
 270     def_irq_default_handler     I2C2_ER_IRQHandler
 271     def_irq_default_handler     SPI1_IRQHandler
 272     def_irq_default_handler     SPI2_IRQHandler
 273     def_irq_default_handler     USART1_IRQHandler
 274     def_irq_default_handler     USART2_IRQHandler
 275     def_irq_default_handler     USART3_IRQHandler
 276     def_irq_default_handler     EXTI15_10_IRQHandler
 277     def_irq_default_handler     RTC_Alarm_IRQHandler
 278     def_irq_default_handler     OTG_FS_WKUP_IRQHandler
 279     def_irq_default_handler     TIM8_BRK_TIM12_IRQHandler
 280     def_irq_default_handler     TIM8_UP_TIM13_IRQHandler
 281     def_irq_default_handler     TIM8_TRG_COM_TIM14_IRQHandler
 282     def_irq_default_handler     TIM8_CC_IRQHandler
 283     def_irq_default_handler     DMA1_Stream7_IRQHandler
 284     def_irq_default_handler     FSMC_IRQHandler
 285     def_irq_default_handler     SDIO_IRQHandler
 286     def_irq_default_handler     TIM5_IRQHandler
 287     def_irq_default_handler     SPI3_IRQHandler
 288     def_irq_default_handler     UART4_IRQHandler
 289     def_irq_default_handler     UART5_IRQHandler
 290     def_irq_default_handler     TIM6_DAC_IRQHandler
 291     def_irq_default_handler     TIM7_IRQHandler
 292     def_irq_default_handler     DMA2_Stream0_IRQHandler
 293     def_irq_default_handler     DMA2_Stream1_IRQHandler
 294     def_irq_default_handler     DMA2_Stream2_IRQHandler
 295     def_irq_default_handler     DMA2_Stream3_IRQHandler
 296     def_irq_default_handler     DMA2_Stream4_IRQHandler
 297     def_irq_default_handler     CAN2_TX_IRQHandler
 298     def_irq_default_handler     CAN2_RX0_IRQHandler
 299     def_irq_default_handler     CAN2_RX1_IRQHandler
 300     def_irq_default_handler     CAN2_SCE_IRQHandler
 301     def_irq_default_handler     OTG_FS_IRQHandler
 302     def_irq_default_handler     DMA2_Stream5_IRQHandler
 303     def_irq_default_handler     DMA2_Stream6_IRQHandler
 304     def_irq_default_handler     DMA2_Stream7_IRQHandler
 305     def_irq_default_handler     USART6_IRQHandler
 306     def_irq_default_handler     I2C3_EV_IRQHandler
 307     def_irq_default_handler     I2C3_ER_IRQHandler
 308     def_irq_default_handler     OTG_HS_EP1_OUT_IRQHandler
 309     def_irq_default_handler     OTG_HS_EP1_IN_IRQHandler
 310     def_irq_default_handler     OTG_HS_WKUP_IRQHandler
 311     def_irq_default_handler     OTG_HS_IRQHandler
 312     def_irq_default_handler     HASH_RNG_IRQHandler
 313     def_irq_default_handler     FPU_IRQHandler
 314     def_irq_default_handler     DEF_IRQHandler
 315
 316     .end