tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_adc.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f4xx_hal_adc.h
   4   * @author  MCD Application Team
   5   * @version V1.1.0
   6   * @date    19-June-2014
   7   * @brief   Header file of ADC HAL extension module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32F4xx_ADC_H
  40 #define __STM32F4xx_ADC_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #include "stm32f4xx_hal_def.h"
  48
  49 /** @addtogroup STM32F4xx_HAL_Driver
  50   * @{
  51   */
  52
  53 /** @addtogroup ADC
  54   * @{
  55   */
  56
  57 /* Exported types ------------------------------------------------------------*/
  58
  59 /**
  60   * @brief  HAL State structures definition
  61   */
  62 typedef enum
  63 {
  64   HAL_ADC_STATE_RESET                   = 0x00,    /*!< ADC not yet initialized or disabled */
  65   HAL_ADC_STATE_READY                   = 0x01,    /*!< ADC peripheral ready for use */
  66   HAL_ADC_STATE_BUSY                    = 0x02,    /*!< An internal process is ongoing */
  67   HAL_ADC_STATE_BUSY_REG                = 0x12,    /*!< Regular conversion is ongoing */
  68   HAL_ADC_STATE_BUSY_INJ                = 0x22,    /*!< Injected conversion is ongoing */
  69   HAL_ADC_STATE_BUSY_INJ_REG            = 0x32,    /*!< Injected and regular conversion are ongoing */
  70   HAL_ADC_STATE_TIMEOUT                 = 0x03,    /*!< Timeout state */
  71   HAL_ADC_STATE_ERROR                   = 0x04,    /*!< ADC state error */
  72   HAL_ADC_STATE_EOC                     = 0x05,    /*!< Conversion is completed */
  73   HAL_ADC_STATE_EOC_REG                 = 0x15,    /*!< Regular conversion is completed */
  74   HAL_ADC_STATE_EOC_INJ                 = 0x25,    /*!< Injected conversion is completed */
  75   HAL_ADC_STATE_EOC_INJ_REG             = 0x35,    /*!< Injected and regular conversion are completed */
  76   HAL_ADC_STATE_AWD                     = 0x06    /*!< ADC state analog watchdog */
  77
  78 }HAL_ADC_StateTypeDef;
  79
  80 /**
  81   * @brief   ADC Init structure definition
  82   */
  83 typedef struct
  84 {
  85   uint32_t ClockPrescaler;        /*!< Select the frequency of the clock to the ADC. The clock is common for
  86                                        all the ADCs.
  87                                        This parameter can be a value of @ref ADC_ClockPrescaler */
  88   uint32_t Resolution;            /*!< Configures the ADC resolution dual mode.
  89                                        This parameter can be a value of @ref ADC_Resolution */
  90   uint32_t DataAlign;             /*!< Specifies whether the ADC data  alignment is left or right.
  91                                        This parameter can be a value of @ref ADC_data_align */
  92   uint32_t ScanConvMode;          /*!< Specifies whether the conversion is performed in Scan (multi channels) or
  93                                        Single (one channel) mode.
  94                                        This parameter can be set to ENABLE or DISABLE */
  95   uint32_t EOCSelection;          /*!< Specifies whether the EOC flag is set
  96                                        at the end of single channel conversion or at the end of all conversions.
  97                                        This parameter can be a value of @ref ADC_EOCSelection */
  98   uint32_t ContinuousConvMode;    /*!< Specifies whether the conversion is performed in Continuous or Single mode.
  99                                        This parameter can be set to ENABLE or DISABLE. */
 100   uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests is performed in Continuous or in Single mode.
 101                                        This parameter can be set to ENABLE or DISABLE. */
 102   uint32_t NbrOfConversion;       /*!< Specifies the number of ADC conversions that will be done using the sequencer for
 103                                        regular channel group.
 104                                        This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
 105   uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversion is performed in Discontinuous or not
 106                                        for regular channels.
 107                                        This parameter can be set to ENABLE or DISABLE. */
 108   uint32_t NbrOfDiscConversion;   /*!< Specifies the number of ADC discontinuous conversions that will be done
 109                                        using the sequencer for regular channel group.
 110                                        This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
 111   uint32_t ExternalTrigConvEdge;  /*!< Select the external trigger edge and enable the trigger of a regular group.
 112                                        This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
 113   uint32_t ExternalTrigConv;      /*!< Select the external event used to trigger the start of conversion of a regular group.
 114                                        This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
 115 }ADC_InitTypeDef;
 116
 117 /**
 118   * @brief  ADC handle Structure definition
 119   */
 120 typedef struct
 121 {
 122   ADC_TypeDef                   *Instance;                   /*!< Register base address */
 123
 124   ADC_InitTypeDef               Init;                        /*!< ADC required parameters */
 125
 126   __IO uint32_t                 NbrOfCurrentConversionRank;  /*!< ADC number of current conversion rank */
 127
 128   DMA_HandleTypeDef             *DMA_Handle;                 /*!< Pointer DMA Handler */
 129
 130   HAL_LockTypeDef               Lock;                        /*!< ADC locking object */
 131
 132   __IO HAL_ADC_StateTypeDef     State;                       /*!< ADC communication state */
 133
 134   __IO uint32_t                 ErrorCode;                   /*!< ADC Error code */
 135 }ADC_HandleTypeDef;
 136
 137 /**
 138   * @brief   ADC Configuration regular Channel structure definition
 139   */
 140 typedef struct
 141 {
 142   uint32_t Channel;        /*!< The ADC channel to configure.
 143                                 This parameter can be a value of @ref ADC_channels */
 144   uint32_t Rank;           /*!< The rank in the regular group sequencer.
 145                                 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
 146   uint32_t SamplingTime;   /*!< The sample time value to be set for the selected channel.
 147                                 This parameter can be a value of @ref ADC_sampling_times */
 148   uint32_t Offset;         /*!< Reserved for future use, can be set to 0 */
 149 }ADC_ChannelConfTypeDef;
 150
 151 /**
 152   * @brief   ADC Configuration multi-mode structure definition
 153   */
 154 typedef struct
 155 {
 156   uint32_t WatchdogMode;      /*!< Configures the ADC analog watchdog mode.
 157                                    This parameter can be a value of @ref ADC_analog_watchdog_selection */
 158   uint32_t HighThreshold;     /*!< Configures the ADC analog watchdog High threshold value.
 159                                    This parameter must be a 12-bit value. */
 160   uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog High threshold value.
 161                                    This parameter must be a 12-bit value. */
 162   uint32_t Channel;           /*!< Configures ADC channel for the analog watchdog.
 163                                    This parameter has an effect only if watchdog mode is configured on single channel
 164                                    This parameter can be a value of @ref ADC_channels */
 165   uint32_t ITMode;            /*!< Specifies whether the analog watchdog is configured
 166                                    is interrupt mode or in polling mode.
 167                                    This parameter can be set to ENABLE or DISABLE */
 168   uint32_t WatchdogNumber;    /*!< Reserved for future use, can be set to 0 */
 169 }ADC_AnalogWDGConfTypeDef;
 170
 171 /* Exported constants --------------------------------------------------------*/
 172
 173 /** @defgroup ADC_Exported_Constants
 174   * @{
 175   */
 176
 177
 178 /** @defgroup ADC_Error_Code
 179   * @{
 180   */
 181
 182 #define HAL_ADC_ERROR_NONE        ((uint32_t)0x00)   /*!< No error             */
 183 #define HAL_ADC_ERROR_OVR         ((uint32_t)0x01)   /*!< OVR error            */
 184 #define HAL_ADC_ERROR_DMA         ((uint32_t)0x02)   /*!< DMA transfer error   */
 185 /**
 186   * @}
 187   */
 188
 189
 190 /** @defgroup ADC_ClockPrescaler
 191   * @{
 192   */
 193 #define ADC_CLOCKPRESCALER_PCLK_DIV2    ((uint32_t)0x00000000)
 194 #define ADC_CLOCKPRESCALER_PCLK_DIV4    ((uint32_t)ADC_CCR_ADCPRE_0)
 195 #define ADC_CLOCKPRESCALER_PCLK_DIV6    ((uint32_t)ADC_CCR_ADCPRE_1)
 196 #define ADC_CLOCKPRESCALER_PCLK_DIV8    ((uint32_t)ADC_CCR_ADCPRE)
 197 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK)     (((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV2) || \
 198                                               ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV4) || \
 199                                               ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV6) || \
 200                                               ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV8))
 201 /**
 202   * @}
 203   */
 204
 205 /** @defgroup ADC_delay_between_2_sampling_phases
 206   * @{
 207   */
 208 #define ADC_TWOSAMPLINGDELAY_5CYCLES    ((uint32_t)0x00000000)
 209 #define ADC_TWOSAMPLINGDELAY_6CYCLES    ((uint32_t)ADC_CCR_DELAY_0)
 210 #define ADC_TWOSAMPLINGDELAY_7CYCLES    ((uint32_t)ADC_CCR_DELAY_1)
 211 #define ADC_TWOSAMPLINGDELAY_8CYCLES    ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
 212 #define ADC_TWOSAMPLINGDELAY_9CYCLES    ((uint32_t)ADC_CCR_DELAY_2)
 213 #define ADC_TWOSAMPLINGDELAY_10CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
 214 #define ADC_TWOSAMPLINGDELAY_11CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
 215 #define ADC_TWOSAMPLINGDELAY_12CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
 216 #define ADC_TWOSAMPLINGDELAY_13CYCLES   ((uint32_t)ADC_CCR_DELAY_3)
 217 #define ADC_TWOSAMPLINGDELAY_14CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
 218 #define ADC_TWOSAMPLINGDELAY_15CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
 219 #define ADC_TWOSAMPLINGDELAY_16CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
 220 #define ADC_TWOSAMPLINGDELAY_17CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
 221 #define ADC_TWOSAMPLINGDELAY_18CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
 222 #define ADC_TWOSAMPLINGDELAY_19CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
 223 #define ADC_TWOSAMPLINGDELAY_20CYCLES   ((uint32_t)ADC_CCR_DELAY)
 224
 225 #define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES)  || \
 226                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES)  || \
 227                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES)  || \
 228                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES)  || \
 229                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES)  || \
 230                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
 231                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
 232                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
 233                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
 234                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
 235                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
 236                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
 237                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
 238                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
 239                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
 240                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES))
 241 /**
 242   * @}
 243   */
 244
 245 /** @defgroup ADC_Resolution
 246   * @{
 247   */
 248 #define ADC_RESOLUTION12b  ((uint32_t)0x00000000)
 249 #define ADC_RESOLUTION10b  ((uint32_t)ADC_CR1_RES_0)
 250 #define ADC_RESOLUTION8b   ((uint32_t)ADC_CR1_RES_1)
 251 #define ADC_RESOLUTION6b   ((uint32_t)ADC_CR1_RES)
 252
 253 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION12b) || \
 254                                        ((RESOLUTION) == ADC_RESOLUTION10b) || \
 255                                        ((RESOLUTION) == ADC_RESOLUTION8b)  || \
 256                                        ((RESOLUTION) == ADC_RESOLUTION6b))
 257 /**
 258   * @}
 259   */
 260
 261 /** @defgroup ADC_External_trigger_edge_Regular
 262   * @{
 263   */
 264 #define ADC_EXTERNALTRIGCONVEDGE_NONE           ((uint32_t)0x00000000)
 265 #define ADC_EXTERNALTRIGCONVEDGE_RISING         ((uint32_t)ADC_CR2_EXTEN_0)
 266 #define ADC_EXTERNALTRIGCONVEDGE_FALLING        ((uint32_t)ADC_CR2_EXTEN_1)
 267 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CR2_EXTEN)
 268
 269 #define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE)    || \
 270                                     ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING)  || \
 271                                     ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
 272                                     ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
 273 /**
 274   * @}
 275   */
 276
 277 /** @defgroup ADC_External_trigger_Source_Regular
 278   * @{
 279   */
 280 #define ADC_EXTERNALTRIGCONV_T1_CC1    ((uint32_t)0x00000000)
 281 #define ADC_EXTERNALTRIGCONV_T1_CC2    ((uint32_t)ADC_CR2_EXTSEL_0)
 282 #define ADC_EXTERNALTRIGCONV_T1_CC3    ((uint32_t)ADC_CR2_EXTSEL_1)
 283 #define ADC_EXTERNALTRIGCONV_T2_CC2    ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
 284 #define ADC_EXTERNALTRIGCONV_T2_CC3    ((uint32_t)ADC_CR2_EXTSEL_2)
 285 #define ADC_EXTERNALTRIGCONV_T2_CC4    ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
 286 #define ADC_EXTERNALTRIGCONV_T2_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
 287 #define ADC_EXTERNALTRIGCONV_T3_CC1    ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
 288 #define ADC_EXTERNALTRIGCONV_T3_TRGO   ((uint32_t)ADC_CR2_EXTSEL_3)
 289 #define ADC_EXTERNALTRIGCONV_T4_CC4    ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
 290 #define ADC_EXTERNALTRIGCONV_T5_CC1    ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))
 291 #define ADC_EXTERNALTRIGCONV_T5_CC2    ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
 292 #define ADC_EXTERNALTRIGCONV_T5_CC3    ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))
 293 #define ADC_EXTERNALTRIGCONV_T8_CC1    ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
 294 #define ADC_EXTERNALTRIGCONV_T8_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
 295 #define ADC_EXTERNALTRIGCONV_Ext_IT11  ((uint32_t)ADC_CR2_EXTSEL)
 296
 297 #define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1)  || \
 298                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2)  || \
 299                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3)  || \
 300                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2)  || \
 301                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3)  || \
 302                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4)  || \
 303                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
 304                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1)  || \
 305                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
 306                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4)  || \
 307                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1)  || \
 308                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2)  || \
 309                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3)  || \
 310                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1)  || \
 311                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
 312                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11))
 313 /**
 314   * @}
 315   */
 316
 317 /** @defgroup ADC_data_align
 318   * @{
 319   */
 320 #define ADC_DATAALIGN_RIGHT      ((uint32_t)0x00000000)
 321 #define ADC_DATAALIGN_LEFT       ((uint32_t)ADC_CR2_ALIGN)
 322
 323 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
 324                                   ((ALIGN) == ADC_DATAALIGN_LEFT))
 325 /**
 326   * @}
 327   */
 328
 329 /** @defgroup ADC_channels
 330   * @{
 331   */
 332 #define ADC_CHANNEL_0           ((uint32_t)0x00000000)
 333 #define ADC_CHANNEL_1           ((uint32_t)ADC_CR1_AWDCH_0)
 334 #define ADC_CHANNEL_2           ((uint32_t)ADC_CR1_AWDCH_1)
 335 #define ADC_CHANNEL_3           ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
 336 #define ADC_CHANNEL_4           ((uint32_t)ADC_CR1_AWDCH_2)
 337 #define ADC_CHANNEL_5           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
 338 #define ADC_CHANNEL_6           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
 339 #define ADC_CHANNEL_7           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
 340 #define ADC_CHANNEL_8           ((uint32_t)ADC_CR1_AWDCH_3)
 341 #define ADC_CHANNEL_9           ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))
 342 #define ADC_CHANNEL_10          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))
 343 #define ADC_CHANNEL_11          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
 344 #define ADC_CHANNEL_12          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))
 345 #define ADC_CHANNEL_13          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
 346 #define ADC_CHANNEL_14          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
 347 #define ADC_CHANNEL_15          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
 348 #define ADC_CHANNEL_16          ((uint32_t)ADC_CR1_AWDCH_4)
 349 #define ADC_CHANNEL_17          ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
 350 #define ADC_CHANNEL_18          ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
 351
 352 #define ADC_CHANNEL_TEMPSENSOR  ((uint32_t)ADC_CHANNEL_16)
 353 #define ADC_CHANNEL_VREFINT     ((uint32_t)ADC_CHANNEL_17)
 354 #define ADC_CHANNEL_VBAT        ((uint32_t)ADC_CHANNEL_18)
 355
 356 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0)  || \
 357                                  ((CHANNEL) == ADC_CHANNEL_1)  || \
 358                                  ((CHANNEL) == ADC_CHANNEL_2)  || \
 359                                  ((CHANNEL) == ADC_CHANNEL_3)  || \
 360                                  ((CHANNEL) == ADC_CHANNEL_4)  || \
 361                                  ((CHANNEL) == ADC_CHANNEL_5)  || \
 362                                  ((CHANNEL) == ADC_CHANNEL_6)  || \
 363                                  ((CHANNEL) == ADC_CHANNEL_7)  || \
 364                                  ((CHANNEL) == ADC_CHANNEL_8)  || \
 365                                  ((CHANNEL) == ADC_CHANNEL_9)  || \
 366                                  ((CHANNEL) == ADC_CHANNEL_10) || \
 367                                  ((CHANNEL) == ADC_CHANNEL_11) || \
 368                                  ((CHANNEL) == ADC_CHANNEL_12) || \
 369                                  ((CHANNEL) == ADC_CHANNEL_13) || \
 370                                  ((CHANNEL) == ADC_CHANNEL_14) || \
 371                                  ((CHANNEL) == ADC_CHANNEL_15) || \
 372                                  ((CHANNEL) == ADC_CHANNEL_16) || \
 373                                  ((CHANNEL) == ADC_CHANNEL_17) || \
 374                                  ((CHANNEL) == ADC_CHANNEL_18))
 375 /**
 376   * @}
 377   */
 378
 379 /** @defgroup ADC_sampling_times
 380   * @{
 381   */
 382 #define ADC_SAMPLETIME_3CYCLES    ((uint32_t)0x00000000)
 383 #define ADC_SAMPLETIME_15CYCLES   ((uint32_t)ADC_SMPR1_SMP10_0)
 384 #define ADC_SAMPLETIME_28CYCLES   ((uint32_t)ADC_SMPR1_SMP10_1)
 385 #define ADC_SAMPLETIME_56CYCLES   ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
 386 #define ADC_SAMPLETIME_84CYCLES   ((uint32_t)ADC_SMPR1_SMP10_2)
 387 #define ADC_SAMPLETIME_112CYCLES  ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
 388 #define ADC_SAMPLETIME_144CYCLES  ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
 389 #define ADC_SAMPLETIME_480CYCLES  ((uint32_t)ADC_SMPR1_SMP10)
 390
 391 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES)   || \
 392                                   ((TIME) == ADC_SAMPLETIME_15CYCLES)  || \
 393                                   ((TIME) == ADC_SAMPLETIME_28CYCLES)  || \
 394                                   ((TIME) == ADC_SAMPLETIME_56CYCLES)  || \
 395                                   ((TIME) == ADC_SAMPLETIME_84CYCLES)  || \
 396                                   ((TIME) == ADC_SAMPLETIME_112CYCLES) || \
 397                                   ((TIME) == ADC_SAMPLETIME_144CYCLES) || \
 398                                   ((TIME) == ADC_SAMPLETIME_480CYCLES))
 399 /**
 400   * @}
 401   */
 402
 403   /** @defgroup ADC_EOCSelection
 404   * @{
 405   */
 406 #define EOC_SEQ_CONV              ((uint32_t)0x00000000)
 407 #define EOC_SINGLE_CONV           ((uint32_t)0x00000001)
 408 #define EOC_SINGLE_SEQ_CONV       ((uint32_t)0x00000002)  /*!< reserved for future use */
 409
 410 #define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == EOC_SINGLE_CONV)   || \
 411                                            ((EOCSelection) == EOC_SEQ_CONV)  || \
 412                                            ((EOCSelection) == EOC_SINGLE_SEQ_CONV))
 413 /**
 414   * @}
 415   */
 416
 417 /** @defgroup ADC_Event_type
 418   * @{
 419   */
 420 #define AWD_EVENT             ((uint32_t)ADC_FLAG_AWD)
 421 #define OVR_EVENT             ((uint32_t)ADC_FLAG_OVR)
 422
 423 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == AWD_EVENT) || \
 424                                   ((EVENT) == OVR_EVENT))
 425 /**
 426   * @}
 427   */
 428
 429 /** @defgroup ADC_analog_watchdog_selection
 430   * @{
 431   */
 432 #define ADC_ANALOGWATCHDOG_SINGLE_REG         ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
 433 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC       ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
 434 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC    ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
 435 #define ADC_ANALOGWATCHDOG_ALL_REG            ((uint32_t)ADC_CR1_AWDEN)
 436 #define ADC_ANALOGWATCHDOG_ALL_INJEC          ((uint32_t)ADC_CR1_JAWDEN)
 437 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC       ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
 438 #define ADC_ANALOGWATCHDOG_NONE               ((uint32_t)0x00000000)
 439
 440 #define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG)        || \
 441                                           ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)      || \
 442                                           ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)   || \
 443                                           ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG)           || \
 444                                           ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC)         || \
 445                                           ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)      || \
 446                                           ((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE))
 447 /**
 448   * @}
 449   */
 450
 451 /** @defgroup ADC_interrupts_definition
 452   * @{
 453   */
 454 #define ADC_IT_EOC      ((uint32_t)ADC_CR1_EOCIE)
 455 #define ADC_IT_AWD      ((uint32_t)ADC_CR1_AWDIE)
 456 #define ADC_IT_JEOC     ((uint32_t)ADC_CR1_JEOCIE)
 457 #define ADC_IT_OVR      ((uint32_t)ADC_CR1_OVRIE)
 458
 459 #define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
 460                        ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR))
 461 /**
 462   * @}
 463   */
 464
 465 /** @defgroup ADC_flags_definition
 466   * @{
 467   */
 468 #define ADC_FLAG_AWD    ((uint32_t)ADC_SR_AWD)
 469 #define ADC_FLAG_EOC    ((uint32_t)ADC_SR_EOC)
 470 #define ADC_FLAG_JEOC   ((uint32_t)ADC_SR_JEOC)
 471 #define ADC_FLAG_JSTRT  ((uint32_t)ADC_SR_JSTRT)
 472 #define ADC_FLAG_STRT   ((uint32_t)ADC_SR_STRT)
 473 #define ADC_FLAG_OVR    ((uint32_t)ADC_SR_OVR)
 474 /**
 475   * @}
 476   */
 477
 478 /** @defgroup ADC_channels_type
 479   * @{
 480   */
 481 #define ALL_CHANNELS      ((uint32_t)0x00000001)
 482 #define REGULAR_CHANNELS  ((uint32_t)0x00000002) /*!< reserved for future use */
 483 #define INJECTED_CHANNELS ((uint32_t)0x00000003) /*!< reserved for future use */
 484
 485 #define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ALL_CHANNELS) || \
 486                                             ((CHANNEL_TYPE) == REGULAR_CHANNELS) || \
 487                                             ((CHANNEL_TYPE) == INJECTED_CHANNELS))
 488 /**
 489   * @}
 490   */
 491
 492 /** @defgroup ADC_thresholds
 493   * @{
 494   */
 495 #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= ((uint32_t)0xFFF))
 496 /**
 497   * @}
 498   */
 499
 500 /** @defgroup ADC_regular_length
 501   * @{
 502   */
 503 #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
 504 /**
 505   * @}
 506   */
 507
 508 /** @defgroup ADC_regular_rank
 509   * @{
 510   */
 511 #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)16)))
 512 /**
 513   * @}
 514   */
 515
 516 /** @defgroup ADC_regular_discontinuous_mode_number
 517   * @{
 518   */
 519 #define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
 520 /**
 521   * @}
 522   */
 523
 524 /** @defgroup ADC_range_verification
 525   * @{
 526   */
 527 #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE)                                     \
 528    ((((RESOLUTION) == ADC_RESOLUTION12b) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \
 529     (((RESOLUTION) == ADC_RESOLUTION10b) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \
 530     (((RESOLUTION) == ADC_RESOLUTION8b)  && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \
 531     (((RESOLUTION) == ADC_RESOLUTION6b)  && ((ADC_VALUE) <= ((uint32_t)0x003F))))
 532 /**
 533   * @}
 534   */
 535
 536 /**
 537   * @}
 538   */
 539
 540 /* Exported macro ------------------------------------------------------------*/
 541
 542 /** @brief Reset ADC handle state
 543   * @param  __HANDLE__: ADC handle
 544   * @retval None
 545   */
 546 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
 547
 548 /**
 549   * @brief  Enable the ADC peripheral.
 550   * @param  __HANDLE__: ADC handle
 551   * @retval None
 552   */
 553 #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |=  ADC_CR2_ADON)
 554
 555 /**
 556   * @brief  Disable the ADC peripheral.
 557   * @param  __HANDLE__: ADC handle
 558   * @retval None
 559   */
 560 #define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &=  ~ADC_CR2_ADON)
 561
 562 /**
 563   * @brief  Set ADC Regular channel sequence length.
 564   * @param  _NbrOfConversion_: Regular channel sequence length.
 565   * @retval None
 566   */
 567 #define __HAL_ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20)
 568
 569 /**
 570   * @brief  Set the ADC's sample time for channel numbers between 10 and 18.
 571   * @param  _SAMPLETIME_: Sample time parameter.
 572   * @param  _CHANNELNB_: Channel number.
 573   * @retval None
 574   */
 575 #define __HAL_ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10)))
 576
 577 /**
 578   * @brief  Set the ADC's sample time for channel numbers between 0 and 9.
 579   * @param  _SAMPLETIME_: Sample time parameter.
 580   * @param  _CHANNELNB_: Channel number.
 581   * @retval None
 582   */
 583 #define __HAL_ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (_CHANNELNB_)))
 584
 585 /**
 586   * @brief  Set the selected regular channel rank for rank between 1 and 6.
 587   * @param  _CHANNELNB_: Channel number.
 588   * @param  _RANKNB_: Rank number.
 589   * @retval None
 590   */
 591 #define __HAL_ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 1)))
 592
 593 /**
 594   * @brief  Set the selected regular channel rank for rank between 7 and 12.
 595   * @param  _CHANNELNB_: Channel number.
 596   * @param  _RANKNB_: Rank number.
 597   * @retval None
 598   */
 599 #define __HAL_ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 7)))
 600
 601 /**
 602   * @brief  Set the selected regular channel rank for rank between 13 and 16.
 603   * @param  _CHANNELNB_: Channel number.
 604   * @param  _RANKNB_: Rank number.
 605   * @retval None
 606   */
 607 #define __HAL_ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 13)))
 608
 609 /**
 610   * @brief  Enable ADC continuous conversion mode.
 611   * @param  _CONTINUOUS_MODE_: Continuous mode.
 612   * @retval None
 613   */
 614 #define __HAL_ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1)
 615
 616 /**
 617   * @brief  Configures the number of discontinuous conversions for the regular group channels.
 618   * @param  _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions.
 619   * @retval None
 620   */
 621 #define __HAL_ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << 13)
 622
 623 /**
 624   * @brief  Enable ADC scan mode.
 625   * @param  _SCANCONV_MODE_: Scan conversion mode.
 626   * @retval None
 627   */
 628 #define __HAL_ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8)
 629
 630 /**
 631   * @brief  Enable the ADC end of conversion selection.
 632   * @param  _EOCSelection_MODE_: End of conversion selection mode.
 633   * @retval None
 634   */
 635 #define __HAL_ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10)
 636
 637 /**
 638   * @brief  Enable the ADC DMA continuous request.
 639   * @param  _DMAContReq_MODE_: DMA continuous request mode.
 640   * @retval None
 641   */
 642 #define __HAL_ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9)
 643
 644 /**
 645   * @brief  Enable the ADC end of conversion interrupt.
 646   * @param  __HANDLE__: specifies the ADC Handle.
 647   * @param  __INTERRUPT__: ADC Interrupt.
 648   * @retval None
 649   */
 650 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
 651
 652 /**
 653   * @brief  Disable the ADC end of conversion interrupt.
 654   * @param  __HANDLE__: specifies the ADC Handle.
 655   * @param  __INTERRUPT__: ADC interrupt.
 656   * @retval None
 657   */
 658 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
 659
 660 /** @brief  Check if the specified ADC interrupt source is enabled or disabled.
 661   * @param  __HANDLE__: specifies the ADC Handle.
 662   * @param  __INTERRUPT__: specifies the ADC interrupt source to check.
 663   * @retval The new state of __IT__ (TRUE or FALSE).
 664   */
 665 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 666
 667 /**
 668   * @brief  Clear the ADC's pending flags.
 669   * @param  __HANDLE__: specifies the ADC Handle.
 670   * @param  __FLAG__: ADC flag.
 671   * @retval None
 672   */
 673 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
 674
 675 /**
 676   * @brief  Get the selected ADC's flag status.
 677   * @param  __HANDLE__: specifies the ADC Handle.
 678   * @param  __FLAG__: ADC flag.
 679   * @retval None
 680   */
 681 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
 682
 683 /**
 684   * @brief Return resolution bits in CR1 register.
 685   * @param __HANDLE__: ADC handle
 686   * @retval None
 687   */
 688 #define __HAL_ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
 689
 690 /* Include ADC HAL Extension module */
 691 #include "stm32f4xx_hal_adc_ex.h"
 692
 693 /* Exported functions --------------------------------------------------------*/
 694 /* Initialization/de-initialization functions ***********************************/
 695 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
 696 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
 697 void       HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
 698 void       HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
 699
 700 /* I/O operation functions ******************************************************/
 701 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
 702 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
 703 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
 704
 705 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
 706
 707 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
 708 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
 709
 710 void              HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
 711
 712 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
 713 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
 714
 715 uint32_t          HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
 716
 717 void       HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
 718 void       HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
 719 void       HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
 720 void       HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
 721
 722 /* Peripheral Control functions *************************************************/
 723 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
 724 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
 725
 726 /* Peripheral State functions ***************************************************/
 727 HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
 728 uint32_t             HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
 729
 730 /**
 731   * @}
 732   */
 733
 734 /**
 735   * @}
 736   */
 737
 738 #ifdef __cplusplus
 739 }
 740 #endif
 741
 742 #endif /*__STM32F4xx_ADC_H */
 743
 744
 745 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/