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[tmk_keyboard.git] / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_STM / TARGET_STM32F4 / stm32f4xx_hal_eth.h
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_eth.h
4 * @author MCD Application Team
5 * @version V1.1.0
6 * @date 19-June-2014
7 * @brief Header file of ETH HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F4xx_HAL_ETH_H
40 #define __STM32F4xx_HAL_ETH_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
47 /* Includes ------------------------------------------------------------------*/
48 #include "stm32f4xx_hal_def.h"
49
50 /** @addtogroup STM32F4xx_HAL_Driver
51 * @{
52 */
53
54 /** @addtogroup ETH
55 * @{
56 */
57
58 /* Exported types ------------------------------------------------------------*/
59
60 /**
61 * @brief HAL State structures definition
62 */
63 typedef enum
64 {
65 HAL_ETH_STATE_RESET = 0x00, /*!< Peripheral not yet Initialized or disabled */
66 HAL_ETH_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
67 HAL_ETH_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
68 HAL_ETH_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
69 HAL_ETH_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
70 HAL_ETH_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
71 HAL_ETH_STATE_BUSY_WR = 0x42, /*!< Write process is ongoing */
72 HAL_ETH_STATE_BUSY_RD = 0x82, /*!< Read process is ongoing */
73 HAL_ETH_STATE_TIMEOUT = 0x03, /*!< Timeout state */
74 HAL_ETH_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
75 }HAL_ETH_StateTypeDef;
76
77 /**
78 * @brief ETH Init Structure definition
79 */
80
81 typedef struct
82 {
83 uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
84 The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
85 and the mode (half/full-duplex).
86 This parameter can be a value of @ref ETH_AutoNegotiation */
87
88 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
89 This parameter can be a value of @ref ETH_Speed */
90
91 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
92 This parameter can be a value of @ref ETH_Duplex_Mode */
93
94 uint16_t PhyAddress; /*!< Ethernet PHY address.
95 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
96
97 uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
98
99 uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
100 This parameter can be a value of @ref ETH_Rx_Mode */
101
102 uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
103 This parameter can be a value of @ref ETH_Checksum_Mode */
104
105 uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.
106 This parameter can be a value of @ref ETH_Media_Interface */
107
108 } ETH_InitTypeDef;
109
110
111 /**
112 * @brief ETH MAC Configuration Structure definition
113 */
114
115 typedef struct
116 {
117 uint32_t Watchdog; /*!< Selects or not the Watchdog timer
118 When enabled, the MAC allows no more then 2048 bytes to be received.
119 When disabled, the MAC can receive up to 16384 bytes.
120 This parameter can be a value of @ref ETH_watchdog */
121
122 uint32_t Jabber; /*!< Selects or not Jabber timer
123 When enabled, the MAC allows no more then 2048 bytes to be sent.
124 When disabled, the MAC can send up to 16384 bytes.
125 This parameter can be a value of @ref ETH_Jabber */
126
127 uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
128 This parameter can be a value of @ref ETH_Inter_Frame_Gap */
129
130 uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
131 This parameter can be a value of @ref ETH_Carrier_Sense */
132
133 uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
134 ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
135 in Half-Duplex mode.
136 This parameter can be a value of @ref ETH_Receive_Own */
137
138 uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
139 This parameter can be a value of @ref ETH_Loop_Back_Mode */
140
141 uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
142 This parameter can be a value of @ref ETH_Checksum_Offload */
143
144 uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
145 when a collision occurs (Half-Duplex mode).
146 This parameter can be a value of @ref ETH_Retry_Transmission */
147
148 uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
149 This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
150
151 uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
152 This parameter can be a value of @ref ETH_Back_Off_Limit */
153
154 uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
155 This parameter can be a value of @ref ETH_Deferral_Check */
156
157 uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
158 This parameter can be a value of @ref ETH_Receive_All */
159
160 uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
161 This parameter can be a value of @ref ETH_Source_Addr_Filter */
162
163 uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
164 This parameter can be a value of @ref ETH_Pass_Control_Frames */
165
166 uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
167 This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
168
169 uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
170 This parameter can be a value of @ref ETH_Destination_Addr_Filter */
171
172 uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
173 This parameter can be a value of @ref ETH_Promiscuous_Mode */
174
175 uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
176 This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
177
178 uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
179 This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
180
181 uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
182 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
183
184 uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
185 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
186
187 uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
188 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
189
190 uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
191 This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
192
193 uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
194 automatic retransmission of PAUSE Frame.
195 This parameter can be a value of @ref ETH_Pause_Low_Threshold */
196
197 uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
198 unicast address and unique multicast address).
199 This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
200
201 uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
202 disable its transmitter for a specified time (Pause Time)
203 This parameter can be a value of @ref ETH_Receive_Flow_Control */
204
205 uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
206 or the MAC back-pressure operation (Half-Duplex mode)
207 This parameter can be a value of @ref ETH_Transmit_Flow_Control */
208
209 uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
210 comparison and filtering.
211 This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
212
213 uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
214
215 } ETH_MACInitTypeDef;
216
217
218 /**
219 * @brief ETH DMA Configuration Structure definition
220 */
221
222 typedef struct
223 {
224 uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
225 This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
226
227 uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
228 This parameter can be a value of @ref ETH_Receive_Store_Forward */
229
230 uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
231 This parameter can be a value of @ref ETH_Flush_Received_Frame */
232
233 uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
234 This parameter can be a value of @ref ETH_Transmit_Store_Forward */
235
236 uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
237 This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
238
239 uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
240 This parameter can be a value of @ref ETH_Forward_Error_Frames */
241
242 uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
243 and length less than 64 bytes) including pad-bytes and CRC)
244 This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
245
246 uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
247 This parameter can be a value of @ref ETH_Receive_Threshold_Control */
248
249 uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
250 frame of Transmit data even before obtaining the status for the first frame.
251 This parameter can be a value of @ref ETH_Second_Frame_Operate */
252
253 uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
254 This parameter can be a value of @ref ETH_Address_Aligned_Beats */
255
256 uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
257 This parameter can be a value of @ref ETH_Fixed_Burst */
258
259 uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
260 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
261
262 uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
263 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
264
265 uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
266 This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
267
268 uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
269 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
270
271 uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
272 This parameter can be a value of @ref ETH_DMA_Arbitration */
273 } ETH_DMAInitTypeDef;
274
275
276 /**
277 * @brief ETH DMA Descriptors data structure definition
278 */
279
280 typedef struct
281 {
282 __IO uint32_t Status; /*!< Status */
283
284 uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
285
286 uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
287
288 uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
289
290 /*!< Enhanced ETHERNET DMA PTP Descriptors */
291 uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */
292
293 uint32_t Reserved1; /*!< Reserved */
294
295 uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */
296
297 uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */
298
299 } ETH_DMADescTypeDef;
300
301
302 /**
303 * @brief Received Frame Informations structure definition
304 */
305 typedef struct
306 {
307 ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */
308
309 ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */
310
311 uint32_t SegCount; /*!< Segment count */
312
313 uint32_t length; /*!< Frame length */
314
315 uint32_t buffer; /*!< Frame buffer */
316
317 } ETH_DMARxFrameInfos;
318
319
320 /**
321 * @brief ETH Handle Structure definition
322 */
323
324 typedef struct
325 {
326 ETH_TypeDef *Instance; /*!< Register base address */
327
328 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */
329
330 uint32_t LinkStatus; /*!< Ethernet link status */
331
332 ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */
333
334 ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */
335
336 ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */
337
338 __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */
339
340 HAL_LockTypeDef Lock; /*!< ETH Lock */
341
342 } ETH_HandleTypeDef;
343
344 /* Exported constants --------------------------------------------------------*/
345
346 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
347
348 /* Delay to wait when writing to some Ethernet registers */
349 #define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
350
351
352 /* ETHERNET Errors */
353 #define ETH_SUCCESS ((uint32_t)0)
354 #define ETH_ERROR ((uint32_t)1)
355
356 /** @defgroup ETH_Buffers_setting
357 * @{
358 */
359 #define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /*!< ETH_HEADER + ETH_EXTRA + VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */
360 #define ETH_HEADER ((uint32_t)14) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
361 #define ETH_CRC ((uint32_t)4) /*!< Ethernet CRC */
362 #define ETH_EXTRA ((uint32_t)2) /*!< Extra bytes in some cases */
363 #define VLAN_TAG ((uint32_t)4) /*!< optional 802.1q VLAN Tag */
364 #define MIN_ETH_PAYLOAD ((uint32_t)46) /*!< Minimum Ethernet payload size */
365 #define MAX_ETH_PAYLOAD ((uint32_t)1500) /*!< Maximum Ethernet payload size */
366 #define JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /*!< Jumbo frame payload size */
367
368 /* Ethernet driver receive buffers are organized in a chained linked-list, when
369 an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
370 to the driver receive buffers memory.
371
372 Depending on the size of the received ethernet packet and the size of
373 each ethernet driver receive buffer, the received packet can take one or more
374 ethernet driver receive buffer.
375
376 In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
377 and the total count of the driver receive buffers ETH_RXBUFNB.
378
379 The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
380 example, they can be reconfigured in the application layer to fit the application
381 needs */
382
383 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
384 packet */
385 #ifndef ETH_RX_BUF_SIZE
386 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
387 #endif
388
389 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
390 #ifndef ETH_RXBUFNB
391 #define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
392 #endif
393
394
395 /* Ethernet driver transmit buffers are organized in a chained linked-list, when
396 an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
397 driver transmit buffers memory to the TxFIFO.
398
399 Depending on the size of the Ethernet packet to be transmitted and the size of
400 each ethernet driver transmit buffer, the packet to be transmitted can take
401 one or more ethernet driver transmit buffer.
402
403 In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
404 and the total count of the driver transmit buffers ETH_TXBUFNB.
405
406 The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
407 example, they can be reconfigured in the application layer to fit the application
408 needs */
409
410 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
411 packet */
412 #ifndef ETH_TX_BUF_SIZE
413 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
414 #endif
415
416 /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
417 #ifndef ETH_TXBUFNB
418 #define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
419 #endif
420
421
422 /*
423 DMA Tx Desciptor
424 -----------------------------------------------------------------------------------------------
425 TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
426 -----------------------------------------------------------------------------------------------
427 TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
428 -----------------------------------------------------------------------------------------------
429 TDES2 | Buffer1 Address [31:0] |
430 -----------------------------------------------------------------------------------------------
431 TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
432 -----------------------------------------------------------------------------------------------
433 */
434
435 /**
436 * @brief Bit definition of TDES0 register: DMA Tx descriptor status register
437 */
438 #define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
439 #define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */
440 #define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /*!< Last Segment */
441 #define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /*!< First Segment */
442 #define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /*!< Disable CRC */
443 #define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /*!< Disable Padding */
444 #define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */
445 #define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */
446 #define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */
447 #define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */
448 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
449 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
450 #define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */
451 #define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */
452 #define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */
453 #define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /*!< IP Header Error */
454 #define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
455 #define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */
456 #define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
457 #define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */
458 #define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during transmission */
459 #define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the transceiver */
460 #define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */
461 #define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */
462 #define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /*!< VLAN Frame */
463 #define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /*!< Collision Count */
464 #define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */
465 #define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */
466 #define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /*!< Deferred Bit */
467
468 /**
469 * @brief Bit definition of TDES1 register
470 */
471 #define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */
472 #define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */
473
474 /**
475 * @brief Bit definition of TDES2 register
476 */
477 #define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
478
479 /**
480 * @brief Bit definition of TDES3 register
481 */
482 #define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
483
484 /*---------------------------------------------------------------------------------------------
485 TDES6 | Transmit Time Stamp Low [31:0] |
486 -----------------------------------------------------------------------------------------------
487 TDES7 | Transmit Time Stamp High [31:0] |
488 ----------------------------------------------------------------------------------------------*/
489
490 /* Bit definition of TDES6 register */
491 #define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */
492
493 /* Bit definition of TDES7 register */
494 #define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */
495
496 /**
497 * @}
498 */
499
500
501 /** @defgroup ETH_DMA_Rx_descriptor
502 * @{
503 */
504
505 /*
506 DMA Rx Descriptor
507 --------------------------------------------------------------------------------------------------------------------
508 RDES0 | OWN(31) | Status [30:0] |
509 ---------------------------------------------------------------------------------------------------------------------
510 RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
511 ---------------------------------------------------------------------------------------------------------------------
512 RDES2 | Buffer1 Address [31:0] |
513 ---------------------------------------------------------------------------------------------------------------------
514 RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
515 ---------------------------------------------------------------------------------------------------------------------
516 */
517
518 /**
519 * @brief Bit definition of RDES0 register: DMA Rx descriptor status register
520 */
521 #define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
522 #define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */
523 #define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */
524 #define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
525 #define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /*!< Descriptor error: no more descriptors for receive frame */
526 #define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */
527 #define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */
528 #define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */
529 #define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */
530 #define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */
531 #define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */
532 #define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
533 #define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */
534 #define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */
535 #define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
536 #define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */
537 #define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */
538 #define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /*!< CRC error */
539 #define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
540
541 /**
542 * @brief Bit definition of RDES1 register
543 */
544 #define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */
545 #define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */
546 #define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */
547 #define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */
548 #define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */
549
550 /**
551 * @brief Bit definition of RDES2 register
552 */
553 #define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
554
555 /**
556 * @brief Bit definition of RDES3 register
557 */
558 #define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
559
560 /*---------------------------------------------------------------------------------------------------------------------
561 RDES4 | Reserved[31:15] | Extended Status [14:0] |
562 ---------------------------------------------------------------------------------------------------------------------
563 RDES5 | Reserved[31:0] |
564 ---------------------------------------------------------------------------------------------------------------------
565 RDES6 | Receive Time Stamp Low [31:0] |
566 ---------------------------------------------------------------------------------------------------------------------
567 RDES7 | Receive Time Stamp High [31:0] |
568 --------------------------------------------------------------------------------------------------------------------*/
569
570 /* Bit definition of RDES4 register */
571 #define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000) /* PTP Version */
572 #define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */
573 #define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */
574 #define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100) /* SYNC message (all clock types) */
575 #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200) /* FollowUp message (all clock types) */
576 #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300) /* DelayReq message (all clock types) */
577 #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400) /* DelayResp message (all clock types) */
578 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
579 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
580 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
581 #define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */
582 #define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */
583 #define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */
584 #define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010) /* IP Payload Error */
585 #define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008) /* IP Header Error */
586 #define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007) /* IP Payload Type */
587 #define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */
588 #define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */
589 #define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */
590
591 /* Bit definition of RDES6 register */
592 #define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */
593
594 /* Bit definition of RDES7 register */
595 #define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */
596
597
598 /** @defgroup ETH_AutoNegotiation
599 * @{
600 */
601 #define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)
602 #define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)
603 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
604 ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
605 /**
606 * @}
607 */
608 /** @defgroup ETH_Speed
609 * @{
610 */
611 #define ETH_SPEED_10M ((uint32_t)0x00000000)
612 #define ETH_SPEED_100M ((uint32_t)0x00004000)
613 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
614 ((SPEED) == ETH_SPEED_100M))
615 /**
616 * @}
617 */
618 /** @defgroup ETH_Duplex_Mode
619 * @{
620 */
621 #define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)
622 #define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)
623 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
624 ((MODE) == ETH_MODE_HALFDUPLEX))
625 /**
626 * @}
627 */
628 /** @defgroup ETH_Rx_Mode
629 * @{
630 */
631 #define ETH_RXPOLLING_MODE ((uint32_t)0x00000000)
632 #define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)
633 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
634 ((MODE) == ETH_RXINTERRUPT_MODE))
635 /**
636 * @}
637 */
638
639 /** @defgroup ETH_Checksum_Mode
640 * @{
641 */
642 #define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)
643 #define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)
644 #define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
645 ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
646 /**
647 * @}
648 */
649
650 /** @defgroup ETH_Media_Interface
651 * @{
652 */
653 #define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)
654 #define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
655 #define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
656 ((MODE) == ETH_MEDIA_INTERFACE_RMII))
657
658 /**
659 * @}
660 */
661
662 /** @defgroup ETH_watchdog
663 * @{
664 */
665 #define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)
666 #define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)
667 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
668 ((CMD) == ETH_WATCHDOG_DISABLE))
669
670 /**
671 * @}
672 */
673
674 /** @defgroup ETH_Jabber
675 * @{
676 */
677 #define ETH_JABBER_ENABLE ((uint32_t)0x00000000)
678 #define ETH_JABBER_DISABLE ((uint32_t)0x00400000)
679 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
680 ((CMD) == ETH_JABBER_DISABLE))
681
682 /**
683 * @}
684 */
685
686 /** @defgroup ETH_Inter_Frame_Gap
687 * @{
688 */
689 #define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */
690 #define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */
691 #define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */
692 #define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */
693 #define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */
694 #define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */
695 #define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */
696 #define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */
697 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
698 ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
699 ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
700 ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
701 ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
702 ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
703 ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
704 ((GAP) == ETH_INTERFRAMEGAP_40BIT))
705
706 /**
707 * @}
708 */
709
710 /** @defgroup ETH_Carrier_Sense
711 * @{
712 */
713 #define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)
714 #define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
715 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
716 ((CMD) == ETH_CARRIERSENCE_DISABLE))
717
718 /**
719 * @}
720 */
721
722 /** @defgroup ETH_Receive_Own
723 * @{
724 */
725 #define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)
726 #define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
727 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
728 ((CMD) == ETH_RECEIVEOWN_DISABLE))
729
730 /**
731 * @}
732 */
733
734 /** @defgroup ETH_Loop_Back_Mode
735 * @{
736 */
737 #define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)
738 #define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)
739 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
740 ((CMD) == ETH_LOOPBACKMODE_DISABLE))
741
742 /**
743 * @}
744 */
745
746 /** @defgroup ETH_Checksum_Offload
747 * @{
748 */
749 #define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)
750 #define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)
751 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
752 ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
753
754 /**
755 * @}
756 */
757
758 /** @defgroup ETH_Retry_Transmission
759 * @{
760 */
761 #define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)
762 #define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)
763 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
764 ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
765
766 /**
767 * @}
768 */
769
770 /** @defgroup ETH_Automatic_Pad_CRC_Strip
771 * @{
772 */
773 #define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)
774 #define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)
775 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
776 ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
777
778 /**
779 * @}
780 */
781
782 /** @defgroup ETH_Back_Off_Limit
783 * @{
784 */
785 #define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)
786 #define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)
787 #define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)
788 #define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)
789 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
790 ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
791 ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
792 ((LIMIT) == ETH_BACKOFFLIMIT_1))
793
794 /**
795 * @}
796 */
797
798 /** @defgroup ETH_Deferral_Check
799 * @{
800 */
801 #define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)
802 #define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)
803 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
804 ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
805
806 /**
807 * @}
808 */
809
810 /** @defgroup ETH_Receive_All
811 * @{
812 */
813 #define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)
814 #define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)
815 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
816 ((CMD) == ETH_RECEIVEAll_DISABLE))
817
818 /**
819 * @}
820 */
821
822 /** @defgroup ETH_Source_Addr_Filter
823 * @{
824 */
825 #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)
826 #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)
827 #define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)
828 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
829 ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
830 ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
831
832 /**
833 * @}
834 */
835
836 /** @defgroup ETH_Pass_Control_Frames
837 * @{
838 */
839 #define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */
840 #define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */
841 #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */
842 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
843 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
844 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
845
846 /**
847 * @}
848 */
849
850 /** @defgroup ETH_Broadcast_Frames_Reception
851 * @{
852 */
853 #define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)
854 #define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)
855 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
856 ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
857
858 /**
859 * @}
860 */
861
862 /** @defgroup ETH_Destination_Addr_Filter
863 * @{
864 */
865 #define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)
866 #define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)
867 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
868 ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
869
870 /**
871 * @}
872 */
873
874 /** @defgroup ETH_Promiscuous_Mode
875 * @{
876 */
877 #define ETH_PROMISCIOUSMODE_ENABLE ((uint32_t)0x00000001)
878 #define ETH_PROMISCIOUSMODE_DISABLE ((uint32_t)0x00000000)
879 #define IS_ETH_PROMISCIOUS_MODE(CMD) (((CMD) == ETH_PROMISCIOUSMODE_ENABLE) || \
880 ((CMD) == ETH_PROMISCIOUSMODE_DISABLE))
881
882 /**
883 * @}
884 */
885
886 /** @defgroup ETH_Multicast_Frames_Filter
887 * @{
888 */
889 #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)
890 #define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)
891 #define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
892 #define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)
893 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
894 ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
895 ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
896 ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
897 /**
898 * @}
899 */
900
901 /** @defgroup ETH_Unicast_Frames_Filter
902 * @{
903 */
904 #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
905 #define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)
906 #define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
907 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
908 ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
909 ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
910 /**
911 * @}
912 */
913
914 /** @defgroup ETH_Pause_Time
915 * @{
916 */
917 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
918
919 /**
920 * @}
921 */
922
923 /** @defgroup ETH_Zero_Quanta_Pause
924 * @{
925 */
926 #define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
927 #define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)
928 #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
929 ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
930 /**
931 * @}
932 */
933
934 /** @defgroup ETH_Pause_Low_Threshold
935 * @{
936 */
937 #define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */
938 #define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */
939 #define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */
940 #define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */
941 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
942 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
943 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
944 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
945 /**
946 * @}
947 */
948
949 /** @defgroup ETH_Unicast_Pause_Frame_Detect
950 * @{
951 */
952 #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)
953 #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
954 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
955 ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
956 /**
957 * @}
958 */
959
960 /** @defgroup ETH_Receive_Flow_Control
961 * @{
962 */
963 #define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)
964 #define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
965 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
966 ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
967 /**
968 * @}
969 */
970
971 /** @defgroup ETH_Transmit_Flow_Control
972 * @{
973 */
974 #define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)
975 #define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
976 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
977 ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
978 /**
979 * @}
980 */
981
982 /** @defgroup ETH_VLAN_Tag_Comparison
983 * @{
984 */
985 #define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)
986 #define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)
987 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
988 ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
989 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
990
991 /**
992 * @}
993 */
994
995 /** @defgroup ETH_MAC_addresses
996 * @{
997 */
998 #define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)
999 #define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)
1000 #define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)
1001 #define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)
1002 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
1003 ((ADDRESS) == ETH_MAC_ADDRESS1) || \
1004 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
1005 ((ADDRESS) == ETH_MAC_ADDRESS3))
1006 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
1007 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
1008 ((ADDRESS) == ETH_MAC_ADDRESS3))
1009 /**
1010 * @}
1011 */
1012
1013 /** @defgroup ETH_MAC_addresses_filter_SA_DA_filed_of_received_frames
1014 * @{
1015 */
1016 #define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)
1017 #define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)
1018 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
1019 ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
1020 /**
1021 * @}
1022 */
1023
1024 /** @defgroup ETH_MAC_addresses_filter_Mask_bytes
1025 * @{
1026 */
1027 #define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */
1028 #define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */
1029 #define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */
1030 #define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */
1031 #define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */
1032 #define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */
1033 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
1034 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
1035 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
1036 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
1037 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
1038 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
1039
1040 /**
1041 * @}
1042 */
1043
1044 /** @defgroup ETH_MAC_Debug_flags
1045 * @{
1046 */
1047 #define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
1048
1049 #define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
1050
1051 #define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
1052
1053 #define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
1054 #define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
1055 #define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
1056 #define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
1057
1058 #define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
1059
1060 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
1061 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
1062 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
1063 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
1064
1065 #define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
1066
1067 #define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
1068 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
1069 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
1070 #define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
1071
1072 #define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000060) /* Rx FIFO read controller IDLE state */
1073 #define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame data */
1074 #define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame status (or time-stamp) */
1075 #define ETH_MAC_READCONTROLLER_ FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
1076
1077 #define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
1078
1079 #define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
1080 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
1081 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
1082 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
1083
1084 #define ETH_MAC_MII_RECEIVE_PROTOCOL_AVTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
1085
1086 /**
1087 * @}
1088 */
1089
1090 /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame
1091 * @{
1092 */
1093 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)
1094 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)
1095 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
1096 ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
1097 /**
1098 * @}
1099 */
1100
1101 /** @defgroup ETH_Receive_Store_Forward
1102 * @{
1103 */
1104 #define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)
1105 #define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)
1106 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
1107 ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
1108 /**
1109 * @}
1110 */
1111
1112 /** @defgroup ETH_Flush_Received_Frame
1113 * @{
1114 */
1115 #define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)
1116 #define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)
1117 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
1118 ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
1119 /**
1120 * @}
1121 */
1122
1123 /** @defgroup ETH_Transmit_Store_Forward
1124 * @{
1125 */
1126 #define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)
1127 #define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)
1128 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
1129 ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
1130 /**
1131 * @}
1132 */
1133
1134 /** @defgroup ETH_Transmit_Threshold_Control
1135 * @{
1136 */
1137 #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
1138 #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
1139 #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
1140 #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
1141 #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
1142 #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
1143 #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
1144 #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
1145 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
1146 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
1147 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
1148 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
1149 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
1150 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
1151 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
1152 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
1153 /**
1154 * @}
1155 */
1156
1157 /** @defgroup ETH_Forward_Error_Frames
1158 * @{
1159 */
1160 #define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)
1161 #define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)
1162 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
1163 ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
1164 /**
1165 * @}
1166 */
1167
1168 /** @defgroup ETH_Forward_Undersized_Good_Frames
1169 * @{
1170 */
1171 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)
1172 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)
1173 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
1174 ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
1175
1176 /**
1177 * @}
1178 */
1179
1180 /** @defgroup ETH_Receive_Threshold_Control
1181 * @{
1182 */
1183 #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
1184 #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
1185 #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
1186 #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
1187 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
1188 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
1189 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
1190 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
1191 /**
1192 * @}
1193 */
1194
1195 /** @defgroup ETH_Second_Frame_Operate
1196 * @{
1197 */
1198 #define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)
1199 #define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)
1200 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
1201 ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
1202
1203 /**
1204 * @}
1205 */
1206
1207 /** @defgroup ETH_Address_Aligned_Beats
1208 * @{
1209 */
1210 #define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)
1211 #define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)
1212 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
1213 ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
1214
1215 /**
1216 * @}
1217 */
1218
1219 /** @defgroup ETH_Fixed_Burst
1220 * @{
1221 */
1222 #define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)
1223 #define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)
1224 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
1225 ((CMD) == ETH_FIXEDBURST_DISABLE))
1226
1227 /**
1228 * @}
1229 */
1230
1231 /** @defgroup ETH_Rx_DMA_Burst_Length
1232 * @{
1233 */
1234 #define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
1235 #define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
1236 #define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
1237 #define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
1238 #define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
1239 #define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
1240 #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
1241 #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
1242 #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
1243 #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
1244 #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
1245 #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
1246
1247 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
1248 ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
1249 ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
1250 ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
1251 ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
1252 ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
1253 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
1254 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
1255 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
1256 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
1257 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
1258 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
1259
1260 /**
1261 * @}
1262 */
1263
1264 /** @defgroup ETH_Tx_DMA_Burst_Length
1265 * @{
1266 */
1267 #define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
1268 #define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
1269 #define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
1270 #define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
1271 #define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
1272 #define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
1273 #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
1274 #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
1275 #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
1276 #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
1277 #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
1278 #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
1279
1280 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
1281 ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
1282 ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
1283 ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
1284 ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
1285 ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
1286 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
1287 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
1288 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
1289 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
1290 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
1291 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
1292
1293 /** @defgroup ETH_DMA_Enhanced_descriptor_format
1294 * @{
1295 */
1296 #define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080)
1297 #define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000)
1298
1299 #define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
1300 ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
1301
1302 /**
1303 * @}
1304 */
1305
1306 /**
1307 * @brief ETH DMA Descriptor SkipLength
1308 */
1309 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
1310
1311
1312 /** @defgroup ETH_DMA_Arbitration
1313 * @{
1314 */
1315 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
1316 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)
1317 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
1318 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
1319 #define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)
1320 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
1321 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
1322 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
1323 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
1324 ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
1325 /**
1326 * @}
1327 */
1328
1329 /** @defgroup ETH_DMA_Tx_descriptor_flags
1330 * @{
1331 */
1332 #define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
1333 ((FLAG) == ETH_DMATXDESC_IC) || \
1334 ((FLAG) == ETH_DMATXDESC_LS) || \
1335 ((FLAG) == ETH_DMATXDESC_FS) || \
1336 ((FLAG) == ETH_DMATXDESC_DC) || \
1337 ((FLAG) == ETH_DMATXDESC_DP) || \
1338 ((FLAG) == ETH_DMATXDESC_TTSE) || \
1339 ((FLAG) == ETH_DMATXDESC_TER) || \
1340 ((FLAG) == ETH_DMATXDESC_TCH) || \
1341 ((FLAG) == ETH_DMATXDESC_TTSS) || \
1342 ((FLAG) == ETH_DMATXDESC_IHE) || \
1343 ((FLAG) == ETH_DMATXDESC_ES) || \
1344 ((FLAG) == ETH_DMATXDESC_JT) || \
1345 ((FLAG) == ETH_DMATXDESC_FF) || \
1346 ((FLAG) == ETH_DMATXDESC_PCE) || \
1347 ((FLAG) == ETH_DMATXDESC_LCA) || \
1348 ((FLAG) == ETH_DMATXDESC_NC) || \
1349 ((FLAG) == ETH_DMATXDESC_LCO) || \
1350 ((FLAG) == ETH_DMATXDESC_EC) || \
1351 ((FLAG) == ETH_DMATXDESC_VF) || \
1352 ((FLAG) == ETH_DMATXDESC_CC) || \
1353 ((FLAG) == ETH_DMATXDESC_ED) || \
1354 ((FLAG) == ETH_DMATXDESC_UF) || \
1355 ((FLAG) == ETH_DMATXDESC_DB))
1356
1357 /**
1358 * @}
1359 */
1360
1361 /** @defgroup ETH_DMA_Tx_descriptor_segment
1362 * @{
1363 */
1364 #define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /*!< Last Segment */
1365 #define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /*!< First Segment */
1366 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
1367 ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
1368
1369 /**
1370 * @}
1371 */
1372
1373 /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control
1374 * @{
1375 */
1376 #define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /*!< Checksum engine bypass */
1377 #define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */
1378 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
1379 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
1380 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
1381 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
1382 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
1383 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
1384 /**
1385 * @brief ETH DMA Tx Desciptor buffer size
1386 */
1387 #define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
1388
1389 /**
1390 * @}
1391 */
1392
1393 /** @defgroup ETH_DMA_Rx_descriptor_flags
1394 * @{
1395 */
1396 #define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
1397 ((FLAG) == ETH_DMARXDESC_AFM) || \
1398 ((FLAG) == ETH_DMARXDESC_ES) || \
1399 ((FLAG) == ETH_DMARXDESC_DE) || \
1400 ((FLAG) == ETH_DMARXDESC_SAF) || \
1401 ((FLAG) == ETH_DMARXDESC_LE) || \
1402 ((FLAG) == ETH_DMARXDESC_OE) || \
1403 ((FLAG) == ETH_DMARXDESC_VLAN) || \
1404 ((FLAG) == ETH_DMARXDESC_FS) || \
1405 ((FLAG) == ETH_DMARXDESC_LS) || \
1406 ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
1407 ((FLAG) == ETH_DMARXDESC_LC) || \
1408 ((FLAG) == ETH_DMARXDESC_FT) || \
1409 ((FLAG) == ETH_DMARXDESC_RWT) || \
1410 ((FLAG) == ETH_DMARXDESC_RE) || \
1411 ((FLAG) == ETH_DMARXDESC_DBE) || \
1412 ((FLAG) == ETH_DMARXDESC_CE) || \
1413 ((FLAG) == ETH_DMARXDESC_MAMPCE))
1414
1415 /* ETHERNET DMA PTP Rx descriptor extended flags --------------------------------*/
1416 #define IS_ETH_DMAPTPRXDESC_GET_EXTENDED_FLAG(FLAG) (((FLAG) == ETH_DMAPTPRXDESC_PTPV) || \
1417 ((FLAG) == ETH_DMAPTPRXDESC_PTPFT) || \
1418 ((FLAG) == ETH_DMAPTPRXDESC_PTPMT) || \
1419 ((FLAG) == ETH_DMAPTPRXDESC_IPV6PR) || \
1420 ((FLAG) == ETH_DMAPTPRXDESC_IPV4PR) || \
1421 ((FLAG) == ETH_DMAPTPRXDESC_IPCB) || \
1422 ((FLAG) == ETH_DMAPTPRXDESC_IPPE) || \
1423 ((FLAG) == ETH_DMAPTPRXDESC_IPHE) || \
1424 ((FLAG) == ETH_DMAPTPRXDESC_IPPT))
1425
1426 /**
1427 * @}
1428 */
1429
1430 /** @defgroup ETH_DMA_Rx_descriptor_buffers_
1431 * @{
1432 */
1433 #define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */
1434 #define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */
1435 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
1436 ((BUFFER) == ETH_DMARXDESC_BUFFER2))
1437
1438
1439 /* ETHERNET DMA Tx descriptors Collision Count Shift */
1440 #define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
1441
1442 /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
1443 #define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
1444
1445 /* ETHERNET DMA Rx descriptors Frame Length Shift */
1446 #define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
1447
1448 /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
1449 #define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
1450
1451 /* ETHERNET DMA Rx descriptors Frame length Shift */
1452 #define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
1453
1454 /**
1455 * @}
1456 */
1457
1458 /** @defgroup ETH_PMT_Flags
1459 * @{
1460 */
1461 #define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Pointer Reset */
1462 #define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */
1463 #define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */
1464 #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
1465 ((FLAG) == ETH_PMT_FLAG_MPR))
1466 /**
1467 * @}
1468 */
1469
1470 /** @defgroup ETH_MMC_Tx_Interrupts
1471 * @{
1472 */
1473 #define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */
1474 #define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */
1475 #define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */
1476
1477 /**
1478 * @}
1479 */
1480
1481 /** @defgroup ETH_MMC_Rx_Interrupts
1482 * @{
1483 */
1484 #define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */
1485 #define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */
1486 #define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */
1487 #define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
1488 ((IT) != 0x00))
1489 #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
1490 ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
1491 ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
1492 /**
1493 * @}
1494 */
1495
1496 /** @defgroup ETH_MMC_Registers
1497 * @{
1498 */
1499 #define ETH_MMCCR ((uint32_t)0x00000100) /*!< MMC CR register */
1500 #define ETH_MMCRIR ((uint32_t)0x00000104) /*!< MMC RIR register */
1501 #define ETH_MMCTIR ((uint32_t)0x00000108) /*!< MMC TIR register */
1502 #define ETH_MMCRIMR ((uint32_t)0x0000010C) /*!< MMC RIMR register */
1503 #define ETH_MMCTIMR ((uint32_t)0x00000110) /*!< MMC TIMR register */
1504 #define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /*!< MMC TGFSCCR register */
1505 #define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /*!< MMC TGFMSCCR register */
1506 #define ETH_MMCTGFCR ((uint32_t)0x00000168) /*!< MMC TGFCR register */
1507 #define ETH_MMCRFCECR ((uint32_t)0x00000194) /*!< MMC RFCECR register */
1508 #define ETH_MMCRFAECR ((uint32_t)0x00000198) /*!< MMC RFAECR register */
1509 #define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /*!< MMC RGUFCR register */
1510
1511 /**
1512 * @brief ETH MMC registers
1513 */
1514 #define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) || ((REG) == ETH_MMCRIR) || \
1515 ((REG) == ETH_MMCTIR) || ((REG) == ETH_MMCRIMR) || \
1516 ((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \
1517 ((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \
1518 ((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \
1519 ((REG) == ETH_MMCRGUFCR))
1520 /**
1521 * @}
1522 */
1523
1524 /** @defgroup ETH_MAC_Flags
1525 * @{
1526 */
1527 #define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */
1528 #define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */
1529 #define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */
1530 #define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */
1531 #define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */
1532 #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
1533 ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
1534 ((FLAG) == ETH_MAC_FLAG_PMT))
1535 /**
1536 * @}
1537 */
1538
1539 /** @defgroup ETH_DMA_Flags
1540 * @{
1541 */
1542 #define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
1543 #define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
1544 #define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
1545 #define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */
1546 #define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /*!< Error bits 0-write trnsf, 1-read transfr */
1547 #define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */
1548 #define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */
1549 #define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */
1550 #define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */
1551 #define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */
1552 #define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */
1553 #define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */
1554 #define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */
1555 #define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */
1556 #define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */
1557 #define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */
1558 #define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */
1559 #define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */
1560 #define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */
1561 #define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */
1562 #define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */
1563
1564 #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))
1565 #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
1566 ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
1567 ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
1568 ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
1569 ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
1570 ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
1571 ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
1572 ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
1573 ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
1574 ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
1575 ((FLAG) == ETH_DMA_FLAG_T))
1576 /**
1577 * @}
1578 */
1579
1580 /** @defgroup ETH_MAC_Interrupts
1581 * @{
1582 */
1583 #define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */
1584 #define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */
1585 #define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */
1586 #define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */
1587 #define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */
1588 #define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF7) == 0x00) && ((IT) != 0x00))
1589 #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
1590 ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
1591 ((IT) == ETH_MAC_IT_PMT))
1592 /**
1593 * @}
1594 */
1595
1596 /** @defgroup ETH_DMA_Interrupts
1597 * @{
1598 */
1599 #define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
1600 #define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
1601 #define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
1602 #define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */
1603 #define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */
1604 #define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */
1605 #define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */
1606 #define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */
1607 #define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */
1608 #define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */
1609 #define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */
1610 #define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */
1611 #define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */
1612 #define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */
1613 #define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */
1614 #define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */
1615 #define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */
1616 #define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */
1617
1618 #define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))
1619 #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
1620 ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
1621 ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
1622 ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
1623 ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
1624 ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
1625 ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
1626 ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
1627 ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
1628
1629 /**
1630 * @}
1631 */
1632
1633 /** @defgroup ETH_DMA_transmit_process_state_
1634 * @{
1635 */
1636 #define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */
1637 #define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */
1638 #define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /*!< Running - waiting for status */
1639 #define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */
1640 #define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /*!< Suspended - Tx Descriptor unavailable */
1641 #define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */
1642
1643 /**
1644 * @}
1645 */
1646
1647
1648 /** @defgroup ETH_DMA_receive_process_state_
1649 * @{
1650 */
1651 #define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */
1652 #define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */
1653 #define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /*!< Running - waiting for packet */
1654 #define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /*!< Suspended - Rx Descriptor unavailable */
1655 #define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /*!< Running - closing descriptor */
1656 #define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /*!< Running - queuing the receive frame into host memory */
1657
1658 /**
1659 * @}
1660 */
1661
1662 /** @defgroup ETH_DMA_overflow_
1663 * @{
1664 */
1665 #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */
1666 #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */
1667 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
1668 ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
1669 /**
1670 * @}
1671 */
1672
1673 /* ETHERNET MAC address offsets */
1674 #define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
1675 #define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
1676
1677 /* ETHERNET MACMIIAR register Mask */
1678 #define MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
1679
1680 /* ETHERNET MACCR register Mask */
1681 #define MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
1682
1683 /* ETHERNET MACFCR register Mask */
1684 #define MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
1685
1686
1687 /* ETHERNET DMAOMR register Mask */
1688 #define DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
1689
1690
1691 /* ETHERNET Remote Wake-up frame register length */
1692 #define ETH_WAKEUP_REGISTER_LENGTH 8
1693
1694 /* ETHERNET Missed frames counter Shift */
1695 #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
1696
1697 /**
1698 * @}
1699 */
1700
1701 /* Exported macro ------------------------------------------------------------*/
1702
1703 /** @brief Reset ETH handle state
1704 * @param __HANDLE__: specifies the ETH handle.
1705 * @retval None
1706 */
1707 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
1708
1709 /**
1710 * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
1711 * @param __HANDLE__: ETH Handle
1712 * @param __FLAG__: specifies the flag to check.
1713 * @retval the ETH_DMATxDescFlag (SET or RESET).
1714 */
1715 #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
1716
1717 /**
1718 * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
1719 * @param __HANDLE__: ETH Handle
1720 * @param __FLAG__: specifies the flag to check.
1721 * @retval the ETH_DMATxDescFlag (SET or RESET).
1722 */
1723 #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
1724
1725 /**
1726 * @brief Enables the specified DMA Rx Desc receive interrupt.
1727 * @param __HANDLE__: ETH Handle
1728 * @retval None
1729 */
1730 #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
1731
1732 /**
1733 * @brief Disables the specified DMA Rx Desc receive interrupt.
1734 * @param __HANDLE__: ETH Handle
1735 * @retval None
1736 */
1737 #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
1738
1739 /**
1740 * @brief Set the specified DMA Rx Desc Own bit.
1741 * @param __HANDLE__: ETH Handle
1742 * @retval None
1743 */
1744 #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
1745
1746 /**
1747 * @brief Returns the specified ETHERNET DMA Tx Desc collision count.
1748 * @param __HANDLE__: ETH Handle
1749 * @retval The Transmit descriptor collision counter value.
1750 */
1751 #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
1752
1753 /**
1754 * @brief Set the specified DMA Tx Desc Own bit.
1755 * @param __HANDLE__: ETH Handle
1756 * @retval None
1757 */
1758 #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
1759
1760 /**
1761 * @brief Enables the specified DMA Tx Desc Transmit interrupt.
1762 * @param __HANDLE__: ETH Handle
1763 * @retval None
1764 */
1765 #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
1766
1767 /**
1768 * @brief Disables the specified DMA Tx Desc Transmit interrupt.
1769 * @param __HANDLE__: ETH Handle
1770 * @retval None
1771 */
1772 #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
1773
1774 /**
1775 * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
1776 * @param __HANDLE__: ETH Handle
1777 * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
1778 * This parameter can be one of the following values:
1779 * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
1780 * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
1781 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
1782 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
1783 * @retval None
1784 */
1785 #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
1786
1787 /**
1788 * @brief Enables the DMA Tx Desc CRC.
1789 * @param __HANDLE__: ETH Handle
1790 * @retval None
1791 */
1792 #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
1793
1794 /**
1795 * @brief Disables the DMA Tx Desc CRC.
1796 * @param __HANDLE__: ETH Handle
1797 * @retval None
1798 */
1799 #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
1800
1801 /**
1802 * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
1803 * @param __HANDLE__: ETH Handle
1804 * @retval None
1805 */
1806 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
1807
1808 /**
1809 * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
1810 * @param __HANDLE__: ETH Handle
1811 * @retval None
1812 */
1813 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
1814
1815 /**
1816 * @brief Enables the specified ETHERNET MAC interrupts.
1817 * @param __HANDLE__ : ETH Handle
1818 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
1819 * enabled or disabled.
1820 * This parameter can be any combination of the following values:
1821 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
1822 * @arg ETH_MAC_IT_PMT : PMT interrupt
1823 * @retval None
1824 */
1825 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
1826
1827 /**
1828 * @brief Disables the specified ETHERNET MAC interrupts.
1829 * @param __HANDLE__ : ETH Handle
1830 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
1831 * enabled or disabled.
1832 * This parameter can be any combination of the following values:
1833 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
1834 * @arg ETH_MAC_IT_PMT : PMT interrupt
1835 * @retval None
1836 */
1837 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
1838
1839 /**
1840 * @brief Initiate a Pause Control Frame (Full-duplex only).
1841 * @param __HANDLE__: ETH Handle
1842 * @retval None
1843 */
1844 #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
1845
1846 /**
1847 * @brief Checks whether the ETHERNET flow control busy bit is set or not.
1848 * @param __HANDLE__: ETH Handle
1849 * @retval The new state of flow control busy status bit (SET or RESET).
1850 */
1851 #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
1852
1853 /**
1854 * @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
1855 * @param __HANDLE__: ETH Handle
1856 * @retval None
1857 */
1858 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
1859
1860 /**
1861 * @brief Disables the MAC BackPressure operation activation (Half-duplex only).
1862 * @param __HANDLE__: ETH Handle
1863 * @retval None
1864 */
1865 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
1866
1867 /**
1868 * @brief Checks whether the specified ETHERNET MAC flag is set or not.
1869 * @param __HANDLE__: ETH Handle
1870 * @param __FLAG__: specifies the flag to check.
1871 * This parameter can be one of the following values:
1872 * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
1873 * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
1874 * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
1875 * @arg ETH_MAC_FLAG_MMC : MMC flag
1876 * @arg ETH_MAC_FLAG_PMT : PMT flag
1877 * @retval The state of ETHERNET MAC flag.
1878 */
1879 #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
1880
1881 /**
1882 * @brief Enables the specified ETHERNET DMA interrupts.
1883 * @param __HANDLE__ : ETH Handle
1884 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
1885 * enabled @defgroup ETH_DMA_Interrupts
1886 * @retval None
1887 */
1888 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
1889
1890 /**
1891 * @brief Disables the specified ETHERNET DMA interrupts.
1892 * @param __HANDLE__ : ETH Handle
1893 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
1894 * disabled. @defgroup ETH_DMA_Interrupts
1895 * @retval None
1896 */
1897 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
1898
1899 /**
1900 * @brief Clears the ETHERNET DMA IT pending bit.
1901 * @param __HANDLE__ : ETH Handle
1902 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @defgroup ETH_DMA_Interrupts
1903 * @retval None
1904 */
1905 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
1906
1907 /**
1908 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
1909 * @param __HANDLE__: ETH Handle
1910 * @param __FLAG__: specifies the flag to check. @defgroup ETH_DMA_Flags
1911 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
1912 */
1913 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
1914
1915 /**
1916 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
1917 * @param __HANDLE__: ETH Handle
1918 * @param __FLAG__: specifies the flag to clear. @defgroup ETH_DMA_Flags
1919 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
1920 */
1921 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
1922
1923 /**
1924 * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
1925 * @param __HANDLE__: ETH Handle
1926 * @param __OVERFLOW__: specifies the DMA overflow flag to check.
1927 * This parameter can be one of the following values:
1928 * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
1929 * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
1930 * @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
1931 */
1932 #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
1933
1934 /**
1935 * @brief Set the DMA Receive status watchdog timer register value
1936 * @param __HANDLE__: ETH Handle
1937 * @param __VALUE__: DMA Receive status watchdog timer register value
1938 * @retval None
1939 */
1940 #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
1941
1942 /**
1943 * @brief Enables any unicast packet filtered by the MAC address
1944 * recognition to be a wake-up frame.
1945 * @param __HANDLE__: ETH Handle.
1946 * @retval None
1947 */
1948 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
1949
1950 /**
1951 * @brief Disables any unicast packet filtered by the MAC address
1952 * recognition to be a wake-up frame.
1953 * @param __HANDLE__: ETH Handle.
1954 * @retval None
1955 */
1956 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
1957
1958 /**
1959 * @brief Enables the MAC Wake-Up Frame Detection.
1960 * @param __HANDLE__: ETH Handle.
1961 * @retval None
1962 */
1963 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
1964
1965 /**
1966 * @brief Disables the MAC Wake-Up Frame Detection.
1967 * @param __HANDLE__: ETH Handle.
1968 * @retval None
1969 */
1970 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
1971
1972 /**
1973 * @brief Enables the MAC Magic Packet Detection.
1974 * @param __HANDLE__: ETH Handle.
1975 * @retval None
1976 */
1977 #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
1978
1979 /**
1980 * @brief Disables the MAC Magic Packet Detection.
1981 * @param __HANDLE__: ETH Handle.
1982 * @retval None
1983 */
1984 #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
1985
1986 /**
1987 * @brief Enables the MAC Power Down.
1988 * @param __HANDLE__: ETH Handle
1989 * @retval None
1990 */
1991 #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
1992
1993 /**
1994 * @brief Disables the MAC Power Down.
1995 * @param __HANDLE__: ETH Handle
1996 * @retval None
1997 */
1998 #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
1999
2000 /**
2001 * @brief Checks whether the specified ETHERNET PMT flag is set or not.
2002 * @param __HANDLE__: ETH Handle.
2003 * @param __FLAG__: specifies the flag to check.
2004 * This parameter can be one of the following values:
2005 * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
2006 * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
2007 * @arg ETH_PMT_FLAG_MPR : Magic Packet Received
2008 * @retval The new state of ETHERNET PMT Flag (SET or RESET).
2009 */
2010 #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
2011
2012 /**
2013 * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
2014 * @param __HANDLE__: ETH Handle.
2015 * @retval None
2016 */
2017 #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
2018
2019 /**
2020 * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
2021 * @param __HANDLE__: ETH Handle.
2022 * @retval None
2023 */
2024 #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
2025 (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)
2026
2027 /**
2028 * @brief Enables the MMC Counter Freeze.
2029 * @param __HANDLE__: ETH Handle.
2030 * @retval None
2031 */
2032 #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
2033
2034 /**
2035 * @brief Disables the MMC Counter Freeze.
2036 * @param __HANDLE__: ETH Handle.
2037 * @retval None
2038 */
2039 #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
2040
2041 /**
2042 * @brief Enables the MMC Reset On Read.
2043 * @param __HANDLE__: ETH Handle.
2044 * @retval None
2045 */
2046 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
2047
2048 /**
2049 * @brief Disables the MMC Reset On Read.
2050 * @param __HANDLE__: ETH Handle.
2051 * @retval None
2052 */
2053 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
2054
2055 /**
2056 * @brief Enables the MMC Counter Stop Rollover.
2057 * @param __HANDLE__: ETH Handle.
2058 * @retval None
2059 */
2060 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
2061
2062 /**
2063 * @brief Disables the MMC Counter Stop Rollover.
2064 * @param __HANDLE__: ETH Handle.
2065 * @retval None
2066 */
2067 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
2068
2069 /**
2070 * @brief Resets the MMC Counters.
2071 * @param __HANDLE__: ETH Handle.
2072 * @retval None
2073 */
2074 #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
2075
2076 /**
2077 * @brief Enables the specified ETHERNET MMC Rx interrupts.
2078 * @param __HANDLE__: ETH Handle.
2079 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
2080 * This parameter can be one of the following values:
2081 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
2082 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
2083 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
2084 * @retval None
2085 */
2086 #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
2087 /**
2088 * @brief Disables the specified ETHERNET MMC Rx interrupts.
2089 * @param __HANDLE__: ETH Handle.
2090 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
2091 * This parameter can be one of the following values:
2092 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
2093 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
2094 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
2095 * @retval None
2096 */
2097 #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)
2098 /**
2099 * @brief Enables the specified ETHERNET MMC Tx interrupts.
2100 * @param __HANDLE__: ETH Handle.
2101 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
2102 * This parameter can be one of the following values:
2103 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
2104 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
2105 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
2106 * @retval None
2107 */
2108 #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
2109
2110 /**
2111 * @brief Disables the specified ETHERNET MMC Tx interrupts.
2112 * @param __HANDLE__: ETH Handle.
2113 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
2114 * This parameter can be one of the following values:
2115 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
2116 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
2117 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
2118 * @retval None
2119 */
2120 #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
2121
2122 /** @defgroup ETH_EXTI_LINE_WAKEUP
2123 * @{
2124 */
2125 #define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the ETH EXTI Line */
2126
2127 /**
2128 * @}
2129 */
2130
2131 /**
2132 * @brief Enables the ETH External interrupt line.
2133 * @param None
2134 * @retval None
2135 */
2136 #define __HAL_ETH_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
2137
2138 /**
2139 * @brief Disables the ETH External interrupt line.
2140 * @param None
2141 * @retval None
2142 */
2143 #define __HAL_ETH_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
2144
2145 /**
2146 * @brief Get flag of the ETH External interrupt line.
2147 * @param None
2148 * @retval None
2149 */
2150 #define __HAL_ETH_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
2151
2152 /**
2153 * @brief Clear flag of the ETH External interrupt line.
2154 * @param None
2155 * @retval None
2156 */
2157 #define __HAL_ETH_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
2158
2159 /**
2160 * @brief Sets rising edge trigger to the ETH External interrupt line.
2161 * @param None
2162 * @retval None
2163 */
2164 #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
2165 EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
2166
2167 /**
2168 * @brief Sets falling edge trigger to the ETH External interrupt line.
2169 * @param None
2170 * @retval None
2171 */
2172 #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP);\
2173 EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
2174
2175 /**
2176 * @brief Sets rising/falling edge trigger to the ETH External interrupt line.
2177 * @param None
2178 * @retval None
2179 */
2180 #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
2181 EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
2182 EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
2183 EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP
2184
2185 /* Exported functions --------------------------------------------------------*/
2186
2187 /* Initialization and de-initialization functions ****************************/
2188 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
2189 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
2190 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
2191 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
2192 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
2193 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
2194
2195 /* IO operation functions ****************************************************/
2196 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
2197 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
2198
2199 /* Non-Blocking mode: Interrupt */
2200 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
2201 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
2202
2203 /* Callback in non blocking modes (Interrupt) */
2204 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
2205 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
2206 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
2207
2208 /* Cmmunication with PHY functions*/
2209 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
2210 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
2211
2212 /* Peripheral Control functions **********************************************/
2213 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
2214 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
2215
2216 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
2217 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
2218
2219 /* Peripheral State functions ************************************************/
2220 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
2221
2222 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
2223 /**
2224 * @}
2225 */
2226
2227 /**
2228 * @}
2229 */
2230
2231 #ifdef __cplusplus
2232 }
2233 #endif
2234
2235 #endif /* __STM32F4xx_HAL_ETH_H */
2236
2237
2238
2239 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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