tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_nand.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f4xx_hal_nand.h
   4   * @author  MCD Application Team
   5   * @version V1.1.0
   6   * @date    19-June-2014
   7   * @brief   Header file of NAND HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32F4xx_HAL_NAND_H
  40 #define __STM32F4xx_HAL_NAND_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
  48   #include "stm32f4xx_ll_fsmc.h"
  49 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
  50
  51 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
  52   #include "stm32f4xx_ll_fmc.h"
  53 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
  54
  55 /** @addtogroup STM32F4xx_HAL_Driver
  56   * @{
  57   */
  58
  59 /** @addtogroup NAND
  60   * @{
  61   */
  62
  63 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
  64
  65 /* Exported typedef ----------------------------------------------------------*/
  66 /* Exported types ------------------------------------------------------------*/
  67
  68 /**
  69   * @brief  HAL NAND State structures definition
  70   */
  71 typedef enum
  72 {
  73   HAL_NAND_STATE_RESET     = 0x00,  /*!< NAND not yet initialized or disabled */
  74   HAL_NAND_STATE_READY     = 0x01,  /*!< NAND initialized and ready for use   */
  75   HAL_NAND_STATE_BUSY      = 0x02,  /*!< NAND internal process is ongoing     */
  76   HAL_NAND_STATE_ERROR     = 0x03   /*!< NAND error state                     */
  77 }HAL_NAND_StateTypeDef;
  78
  79 /**
  80   * @brief  NAND Memory electronic signature Structure definition
  81   */
  82 typedef struct
  83 {
  84   /*<! NAND memory electronic signature maker and device IDs */
  85
  86   uint8_t Maker_Id;
  87
  88   uint8_t Device_Id;
  89
  90   uint8_t Third_Id;
  91
  92   uint8_t Fourth_Id;
  93 }NAND_IDTypeDef;
  94
  95 /**
  96   * @brief  NAND Memory address Structure definition
  97   */
  98 typedef struct
  99 {
 100   uint16_t Page;   /*!< NAND memory Page address  */
 101
 102   uint16_t Zone;   /*!< NAND memory Zone address  */
 103
 104   uint16_t Block;  /*!< NAND memory Block address */
 105
 106 }NAND_AddressTypedef;
 107
 108 /**
 109   * @brief  NAND Memory info Structure definition
 110   */
 111 typedef struct
 112 {
 113   uint32_t PageSize;       /*!< NAND memory page (without spare area) size measured in K. bytes */
 114
 115   uint32_t SpareAreaSize;  /*!< NAND memory spare area size measured in K. bytes                */
 116
 117   uint32_t BlockSize;      /*!< NAND memory block size number of pages                          */
 118
 119   uint32_t BlockNbr;       /*!< NAND memory number of blocks                                    */
 120
 121   uint32_t ZoneSize;       /*!< NAND memory zone size measured in number of blocks              */
 122 }NAND_InfoTypeDef;
 123
 124 /**
 125   * @brief  NAND handle Structure definition
 126   */
 127 typedef struct
 128 {
 129   FMC_NAND_TypeDef             *Instance;  /*!< Register base address                        */
 130
 131   FMC_NAND_InitTypeDef         Init;       /*!< NAND device control configuration parameters */
 132
 133   HAL_LockTypeDef              Lock;       /*!< NAND locking object                          */
 134
 135   __IO HAL_NAND_StateTypeDef   State;      /*!< NAND device access state                     */
 136
 137   NAND_InfoTypeDef             Info;       /*!< NAND characteristic information structure    */
 138 }NAND_HandleTypeDef;
 139
 140
 141 /* Exported constants --------------------------------------------------------*/
 142 /** @defgroup NAND_Exported_Constants
 143  * @{
 144  */
 145 #define NAND_DEVICE1               ((uint32_t)0x70000000)
 146 #define NAND_DEVICE2               ((uint32_t)0x80000000)
 147 #define NAND_WRITE_TIMEOUT         ((uint32_t)0x01000000)
 148
 149 #define CMD_AREA                   ((uint32_t)(1<<16))  /* A16 = CLE high */
 150 #define ADDR_AREA                  ((uint32_t)(1<<17))  /* A17 = ALE high */
 151
 152 #define NAND_CMD_AREA_A            ((uint8_t)0x00)
 153 #define NAND_CMD_AREA_B            ((uint8_t)0x01)
 154 #define NAND_CMD_AREA_C            ((uint8_t)0x50)
 155 #define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30)
 156
 157 #define NAND_CMD_WRITE0            ((uint8_t)0x80)
 158 #define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10)
 159 #define NAND_CMD_ERASE0            ((uint8_t)0x60)
 160 #define NAND_CMD_ERASE1            ((uint8_t)0xD0)
 161 #define NAND_CMD_READID            ((uint8_t)0x90)
 162 #define NAND_CMD_STATUS            ((uint8_t)0x70)
 163 #define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7A)
 164 #define NAND_CMD_RESET             ((uint8_t)0xFF)
 165
 166 /* NAND memory status */
 167 #define NAND_VALID_ADDRESS         ((uint32_t)0x00000100)
 168 #define NAND_INVALID_ADDRESS       ((uint32_t)0x00000200)
 169 #define NAND_TIMEOUT_ERROR         ((uint32_t)0x00000400)
 170 #define NAND_BUSY                  ((uint32_t)0x00000000)
 171 #define NAND_ERROR                 ((uint32_t)0x00000001)
 172 #define NAND_READY                 ((uint32_t)0x00000040)
 173
 174 /**
 175   * @}
 176   */
 177
 178 /* Exported macro ------------------------------------------------------------*/
 179
 180 /** @brief Reset NAND handle state
 181   * @param  __HANDLE__: specifies the NAND handle.
 182   * @retval None
 183   */
 184 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
 185
 186 /**
 187   * @brief  NAND memory address computation.
 188   * @param  __ADDRESS__: NAND memory address.
 189   * @param  __HANDLE__ : NAND handle.
 190   * @retval NAND Raw address value
 191   */
 192 #define __ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
 193                          (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize)))
 194
 195 /**
 196   * @brief  NAND memory address cycling.
 197   * @param  __ADDRESS__: NAND memory address.
 198   * @retval NAND address cycling value.
 199   */
 200 #define __ADDR_1st_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st addressing cycle */
 201 #define __ADDR_2nd_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd addressing cycle */
 202 #define __ADDR_3rd_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 16)      /* 3rd addressing cycle */
 203 #define __ADDR_4th_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 24)      /* 4th addressing cycle */
 204
 205 /* Exported functions --------------------------------------------------------*/
 206
 207 /* Initialization/de-initialization functions  ********************************/
 208 HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
 209 HAL_StatusTypeDef  HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
 210 void        HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
 211 void        HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
 212 void               HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
 213 void        HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
 214
 215 /* IO operation functions  ****************************************************/
 216 HAL_StatusTypeDef  HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
 217 HAL_StatusTypeDef  HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
 218 HAL_StatusTypeDef  HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
 219 HAL_StatusTypeDef  HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
 220 HAL_StatusTypeDef  HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
 221 HAL_StatusTypeDef  HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
 222 HAL_StatusTypeDef  HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress);
 223 uint32_t           HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
 224 uint32_t           HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress);
 225
 226 /* NAND Control functions  ****************************************************/
 227 HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
 228 HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
 229 HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
 230
 231 /* NAND State functions *******************************************************/
 232 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
 233 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
 234
 235 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
 236 /**
 237   * @}
 238   */
 239
 240 /**
 241   * @}
 242   */
 243
 244 #ifdef __cplusplus
 245 }
 246 #endif
 247
 248 #endif /* __STM32F4xx_HAL_NAND_H */
 249
 250 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/