2 ******************************************************************************
3 * @file stm32f4xx_hal_rcc.c
4 * @author MCD Application Team
7 * @brief RCC HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the Reset and Clock Control (RCC) peripheral:
10 * + Initialization and de-initialization functions
11 * + Peripheral Control functions
14 ==============================================================================
15 ##### RCC specific features #####
16 ==============================================================================
18 After reset the device is running from Internal High Speed oscillator
19 (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
20 and I-Cache are disabled, and all peripherals are off except internal
22 (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
23 all peripherals mapped on these busses are running at HSI speed.
24 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
25 (+) All GPIOs are in input floating state, except the JTAG pins which
26 are assigned to be used for debug purpose.
29 Once the device started from reset, the user application has to:
30 (+) Configure the clock source to be used to drive the System clock
31 (if the application needs higher frequency/performance)
32 (+) Configure the System clock frequency and Flash settings
33 (+) Configure the AHB and APB busses prescalers
34 (+) Enable the clock for the peripheral(s) to be used
35 (+) Configure the clock source(s) for peripherals which clocks are not
36 derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
39 ******************************************************************************
42 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
44 * Redistribution and use in source and binary forms, with or without modification,
45 * are permitted provided that the following conditions are met:
46 * 1. Redistributions of source code must retain the above copyright notice,
47 * this list of conditions and the following disclaimer.
48 * 2. Redistributions in binary form must reproduce the above copyright notice,
49 * this list of conditions and the following disclaimer in the documentation
50 * and/or other materials provided with the distribution.
51 * 3. Neither the name of STMicroelectronics nor the names of its contributors
52 * may be used to endorse or promote products derived from this software
53 * without specific prior written permission.
55 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
56 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
58 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
61 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
62 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
63 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
66 ******************************************************************************
69 /* Includes ------------------------------------------------------------------*/
70 #include "stm32f4xx_hal.h"
72 /** @addtogroup STM32F4xx_HAL_Driver
77 * @brief RCC HAL module driver
81 #ifdef HAL_RCC_MODULE_ENABLED
83 /* Private typedef -----------------------------------------------------------*/
84 /* Private define ------------------------------------------------------------*/
85 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
86 #define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
87 #define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
88 #define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
89 #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
91 /* Private macro -------------------------------------------------------------*/
92 #define __MCO1_CLK_ENABLE() __GPIOA_CLK_ENABLE()
93 #define MCO1_GPIO_PORT GPIOA
94 #define MCO1_PIN GPIO_PIN_8
96 #define __MCO2_CLK_ENABLE() __GPIOC_CLK_ENABLE()
97 #define MCO2_GPIO_PORT GPIOC
98 #define MCO2_PIN GPIO_PIN_9
100 /* Private variables ---------------------------------------------------------*/
101 const uint8_t APBAHBPrescTable
[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
103 /* Private function prototypes -----------------------------------------------*/
104 /* Private functions ---------------------------------------------------------*/
106 /** @defgroup RCC_Private_Functions
110 /** @defgroup RCC_Group1 Initialization and de-initialization functions
111 * @brief Initialization and Configuration functions
114 ===============================================================================
115 ##### Initialization and de-initialization functions #####
116 ===============================================================================
118 This section provides functions allowing to configure the internal/external oscillators
119 (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
122 [..] Internal/external clock and PLL configuration
123 (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
124 the PLL as System clock source.
126 (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
129 (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
130 through the PLL as System clock source. Can be used also as RTC clock source.
132 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
134 (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
135 (++) The first output is used to generate the high speed system clock (up to 168 MHz)
136 (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
137 the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
139 (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
140 and if a HSE clock failure occurs(HSE used directly or through PLL as System
141 clock source), the System clockis automatically switched to HSI and an interrupt
142 is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
143 (Non-Maskable Interrupt) exception vector.
145 (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
146 clock (through a configurable prescaler) on PA8 pin.
148 (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
149 clock (through a configurable prescaler) on PC9 pin.
151 [..] System, AHB and APB busses clocks configuration
152 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
154 The AHB clock (HCLK) is derived from System clock through configurable
155 prescaler and used to clock the CPU, memory and peripherals mapped
156 on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
157 from AHB clock through configurable prescalers and used to clock
158 the peripherals mapped on these busses. You can use
159 "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
161 -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
162 (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
163 from an external clock mapped on the I2S_CKIN pin.
164 You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
165 (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) or
166 from an external clock mapped on the I2S_CKIN pin.
167 You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
168 (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
169 divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()
170 macros to configure this clock.
171 (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
172 to work correctly, while the SDIO require a frequency equal or lower than
173 to 48. This clock is derived of the main PLL through PLLQ divider.
174 (+@) IWDG clock which is always the LSI clock.
176 (#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum
177 frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz.
178 Depending on the device voltage range, the maximum frequency should
179 be adapted accordingly (refer to the product datasheets for more details).
181 (#) For the STM32F42xxx and STM32F43xxx devices, the maximum frequency
182 of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz.
183 Depending on the device voltage range, the maximum frequency should
184 be adapted accordingly (refer to the product datasheets for more details).
186 (#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz,
187 PCLK2 84 MHz and PCLK1 42 MHz.
188 Depending on the device voltage range, the maximum frequency should
189 be adapted accordingly (refer to the product datasheets for more details).
195 * @brief Resets the RCC clock configuration to the default reset state.
196 * @note The default reset state of the clock configuration is given below:
197 * - HSI ON and used as system clock source
198 * - HSE, PLL and PLLI2S OFF
199 * - AHB, APB1 and APB2 prescaler set to 1.
200 * - CSS, MCO1 and MCO2 OFF
201 * - All interrupts disabled
202 * @note This function doesn't modify the configuration of the
203 * - Peripheral clocks
204 * - LSI, LSE and RTC clocks
208 void HAL_RCC_DeInit(void)
211 SET_BIT(RCC
->CR
, RCC_CR_HSION
| RCC_CR_HSITRIM_4
);
213 /* Reset CFGR register */
214 CLEAR_REG(RCC
->CFGR
);
216 /* Reset HSEON, CSSON, PLLON, PLLI2S */
217 CLEAR_BIT(RCC
->CR
, RCC_CR_HSEON
| RCC_CR_CSSON
| RCC_CR_PLLON
| RCC_CR_PLLI2SON
);
219 /* Reset PLLCFGR register */
220 CLEAR_REG(RCC
->PLLCFGR
);
221 SET_BIT(RCC
->PLLCFGR
, RCC_PLLCFGR_PLLM_4
| RCC_PLLCFGR_PLLN_6
| RCC_PLLCFGR_PLLN_7
| RCC_PLLCFGR_PLLQ_2
);
223 /* Reset PLLI2SCFGR register */
224 CLEAR_REG(RCC
->PLLI2SCFGR
);
225 SET_BIT(RCC
->PLLI2SCFGR
, RCC_PLLI2SCFGR_PLLI2SN_6
| RCC_PLLI2SCFGR_PLLI2SN_7
| RCC_PLLI2SCFGR_PLLI2SR_1
);
227 /* Reset HSEBYP bit */
228 CLEAR_BIT(RCC
->CR
, RCC_CR_HSEBYP
);
230 /* Disable all interrupts */
235 * @brief Initializes the RCC Oscillators according to the specified parameters in the
236 * RCC_OscInitTypeDef.
237 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
238 * contains the configuration information for the RCC Oscillators.
239 * @note The PLL is not disabled when used as system clock.
242 HAL_StatusTypeDef
HAL_RCC_OscConfig(RCC_OscInitTypeDef
*RCC_OscInitStruct
)
244 uint32_t tickstart
= 0;
246 /* Check the parameters */
247 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct
->OscillatorType
));
248 /*------------------------------- HSE Configuration ------------------------*/
249 if(((RCC_OscInitStruct
->OscillatorType
) & RCC_OSCILLATORTYPE_HSE
) == RCC_OSCILLATORTYPE_HSE
)
251 /* Check the parameters */
252 assert_param(IS_RCC_HSE(RCC_OscInitStruct
->HSEState
));
253 /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
254 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE
) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL
) && ((RCC
->PLLCFGR
& RCC_PLLCFGR_PLLSRC
) == RCC_PLLCFGR_PLLSRC_HSE
)))
256 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY
) != RESET
) && (RCC_OscInitStruct
->HSEState
!= RCC_HSE_ON
))
263 /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
264 __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF
);
267 tickstart
= HAL_GetTick();
269 /* Wait till HSE is disabled */
270 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY
) != RESET
)
272 if((HAL_GetTick() - tickstart
) > HSE_TIMEOUT_VALUE
)
278 /* Set the new HSE configuration ---------------------------------------*/
279 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct
->HSEState
);
281 /* Check the HSE State */
282 if((RCC_OscInitStruct
->HSEState
) == RCC_HSE_ON
)
285 tickstart
= HAL_GetTick();
287 /* Wait till HSE is ready */
288 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY
) == RESET
)
290 if((HAL_GetTick() - tickstart
) > HSE_TIMEOUT_VALUE
)
299 tickstart
= HAL_GetTick();
301 /* Wait till HSE is bypassed or disabled */
302 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY
) != RESET
)
304 if((HAL_GetTick() - tickstart
) > HSE_TIMEOUT_VALUE
)
312 /*----------------------------- HSI Configuration --------------------------*/
313 if(((RCC_OscInitStruct
->OscillatorType
) & RCC_OSCILLATORTYPE_HSI
) == RCC_OSCILLATORTYPE_HSI
)
315 /* Check the parameters */
316 assert_param(IS_RCC_HSI(RCC_OscInitStruct
->HSIState
));
317 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct
->HSICalibrationValue
));
319 /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
320 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI
) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL
) && ((RCC
->PLLCFGR
& RCC_PLLCFGR_PLLSRC
) == RCC_PLLCFGR_PLLSRC_HSI
)))
322 /* When HSI is used as system clock it will not disabled */
323 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY
) != RESET
) && (RCC_OscInitStruct
->HSIState
!= RCC_HSI_ON
))
327 /* Otherwise, just the calibration is allowed */
330 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
331 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct
->HSICalibrationValue
);
336 /* Check the HSI State */
337 if((RCC_OscInitStruct
->HSIState
)!= RCC_HSI_OFF
)
339 /* Enable the Internal High Speed oscillator (HSI). */
340 __HAL_RCC_HSI_ENABLE();
343 tickstart
= HAL_GetTick();
345 /* Wait till HSI is ready */
346 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY
) == RESET
)
348 if((HAL_GetTick() - tickstart
) > HSI_TIMEOUT_VALUE
)
354 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
355 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct
->HSICalibrationValue
);
359 /* Disable the Internal High Speed oscillator (HSI). */
360 __HAL_RCC_HSI_DISABLE();
363 tickstart
= HAL_GetTick();
365 /* Wait till HSI is ready */
366 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY
) != RESET
)
368 if((HAL_GetTick() - tickstart
) > HSI_TIMEOUT_VALUE
)
376 /*------------------------------ LSI Configuration -------------------------*/
377 if(((RCC_OscInitStruct
->OscillatorType
) & RCC_OSCILLATORTYPE_LSI
) == RCC_OSCILLATORTYPE_LSI
)
379 /* Check the parameters */
380 assert_param(IS_RCC_LSI(RCC_OscInitStruct
->LSIState
));
382 /* Check the LSI State */
383 if((RCC_OscInitStruct
->LSIState
)!= RCC_LSI_OFF
)
385 /* Enable the Internal Low Speed oscillator (LSI). */
386 __HAL_RCC_LSI_ENABLE();
389 tickstart
= HAL_GetTick();
391 /* Wait till LSI is ready */
392 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY
) == RESET
)
394 if((HAL_GetTick() - tickstart
) > LSI_TIMEOUT_VALUE
)
402 /* Disable the Internal Low Speed oscillator (LSI). */
403 __HAL_RCC_LSI_DISABLE();
406 tickstart
= HAL_GetTick();
408 /* Wait till LSI is ready */
409 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY
) != RESET
)
411 if((HAL_GetTick() - tickstart
) > LSI_TIMEOUT_VALUE
)
418 /*------------------------------ LSE Configuration -------------------------*/
419 if(((RCC_OscInitStruct
->OscillatorType
) & RCC_OSCILLATORTYPE_LSE
) == RCC_OSCILLATORTYPE_LSE
)
421 /* Check the parameters */
422 assert_param(IS_RCC_LSE(RCC_OscInitStruct
->LSEState
));
424 /* Enable Power Clock*/
427 /* Enable write access to Backup domain */
428 PWR
->CR
|= PWR_CR_DBP
;
430 /* Wait for Backup domain Write protection disable */
431 tickstart
= HAL_GetTick();
433 while((PWR
->CR
& PWR_CR_DBP
) == RESET
)
435 if((HAL_GetTick() - tickstart
) > DBP_TIMEOUT_VALUE
)
441 /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
442 __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF
);
445 tickstart
= HAL_GetTick();
447 /* Wait till LSE is ready */
448 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY
) != RESET
)
450 if((HAL_GetTick() - tickstart
) > LSE_TIMEOUT_VALUE
)
456 /* Set the new LSE configuration -----------------------------------------*/
457 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct
->LSEState
);
458 /* Check the LSE State */
459 if((RCC_OscInitStruct
->LSEState
) == RCC_LSE_ON
)
462 tickstart
= HAL_GetTick();
464 /* Wait till LSE is ready */
465 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY
) == RESET
)
467 if((HAL_GetTick() - tickstart
) > LSE_TIMEOUT_VALUE
)
476 tickstart
= HAL_GetTick();
478 /* Wait till LSE is ready */
479 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY
) != RESET
)
481 if((HAL_GetTick() - tickstart
) > LSE_TIMEOUT_VALUE
)
488 /*-------------------------------- PLL Configuration -----------------------*/
489 /* Check the parameters */
490 assert_param(IS_RCC_PLL(RCC_OscInitStruct
->PLL
.PLLState
));
491 if ((RCC_OscInitStruct
->PLL
.PLLState
) != RCC_PLL_NONE
)
493 /* Check if the PLL is used as system clock or not */
494 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL
)
496 if((RCC_OscInitStruct
->PLL
.PLLState
) == RCC_PLL_ON
)
498 /* Check the parameters */
499 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct
->PLL
.PLLSource
));
500 assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct
->PLL
.PLLM
));
501 assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct
->PLL
.PLLN
));
502 assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct
->PLL
.PLLP
));
503 assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct
->PLL
.PLLQ
));
505 /* Disable the main PLL. */
506 __HAL_RCC_PLL_DISABLE();
509 tickstart
= HAL_GetTick();
511 /* Wait till PLL is ready */
512 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY
) != RESET
)
514 if((HAL_GetTick() - tickstart
) > PLL_TIMEOUT_VALUE
)
520 /* Configure the main PLL clock source, multiplication and division factors. */
521 __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct
->PLL
.PLLSource
,
522 RCC_OscInitStruct
->PLL
.PLLM
,
523 RCC_OscInitStruct
->PLL
.PLLN
,
524 RCC_OscInitStruct
->PLL
.PLLP
,
525 RCC_OscInitStruct
->PLL
.PLLQ
);
526 /* Enable the main PLL. */
527 __HAL_RCC_PLL_ENABLE();
530 tickstart
= HAL_GetTick();
532 /* Wait till PLL is ready */
533 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY
) == RESET
)
535 if((HAL_GetTick() - tickstart
) > PLL_TIMEOUT_VALUE
)
543 /* Disable the main PLL. */
544 __HAL_RCC_PLL_DISABLE();
547 tickstart
= HAL_GetTick();
549 /* Wait till PLL is ready */
550 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY
) != RESET
)
552 if((HAL_GetTick() - tickstart
) > PLL_TIMEOUT_VALUE
)
568 * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
569 * parameters in the RCC_ClkInitStruct.
570 * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
571 * contains the configuration information for the RCC peripheral.
572 * @param FLatency: FLASH Latency, this parameter depend on device selected
574 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
575 * and updated by HAL_RCC_GetHCLKFreq() function called within this function
577 * @note The HSI is used (enabled by hardware) as system clock source after
578 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
579 * of failure of the HSE used directly or indirectly as system clock
580 * (if the Clock Security System CSS is enabled).
582 * @note A switch from one clock source to another occurs only if the target
583 * clock source is ready (clock stable after startup delay or PLL locked).
584 * If a clock source which is not yet ready is selected, the switch will
585 * occur when the clock source will be ready.
587 * @note Depending on the device voltage range, the software has to set correctly
588 * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
589 * (for more details refer to section above "Initialization/de-initialization functions")
592 HAL_StatusTypeDef
HAL_RCC_ClockConfig(RCC_ClkInitTypeDef
*RCC_ClkInitStruct
, uint32_t FLatency
)
594 uint32_t tickstart
= 0;
596 /* Check the parameters */
597 assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct
->ClockType
));
598 assert_param(IS_FLASH_LATENCY(FLatency
));
600 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
601 must be correctly programmed according to the frequency of the CPU clock
602 (HCLK) and the supply voltage of the device. */
604 /* Increasing the CPU frequency */
605 if(FLatency
> (FLASH
->ACR
& FLASH_ACR_LATENCY
))
607 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
608 __HAL_FLASH_SET_LATENCY(FLatency
);
610 /* Check that the new number of wait states is taken into account to access the Flash
611 memory by reading the FLASH_ACR register */
612 if((FLASH
->ACR
& FLASH_ACR_LATENCY
) != FLatency
)
617 /*-------------------------- HCLK Configuration --------------------------*/
618 if(((RCC_ClkInitStruct
->ClockType
) & RCC_CLOCKTYPE_HCLK
) == RCC_CLOCKTYPE_HCLK
)
620 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct
->AHBCLKDivider
));
621 MODIFY_REG(RCC
->CFGR
, RCC_CFGR_HPRE
, RCC_ClkInitStruct
->AHBCLKDivider
);
624 /*------------------------- SYSCLK Configuration ---------------------------*/
625 if(((RCC_ClkInitStruct
->ClockType
) & RCC_CLOCKTYPE_SYSCLK
) == RCC_CLOCKTYPE_SYSCLK
)
627 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct
->SYSCLKSource
));
629 /* HSE is selected as System Clock Source */
630 if(RCC_ClkInitStruct
->SYSCLKSource
== RCC_SYSCLKSOURCE_HSE
)
632 /* Check the HSE ready flag */
633 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY
) == RESET
)
638 /* PLL is selected as System Clock Source */
639 else if(RCC_ClkInitStruct
->SYSCLKSource
== RCC_SYSCLKSOURCE_PLLCLK
)
641 /* Check the PLL ready flag */
642 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY
) == RESET
)
647 /* HSI is selected as System Clock Source */
650 /* Check the HSI ready flag */
651 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY
) == RESET
)
656 MODIFY_REG(RCC
->CFGR
, RCC_CFGR_SW
, RCC_ClkInitStruct
->SYSCLKSource
);
659 tickstart
= HAL_GetTick();
661 if(RCC_ClkInitStruct
->SYSCLKSource
== RCC_SYSCLKSOURCE_HSE
)
663 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE
)
665 if((HAL_GetTick() - tickstart
) > CLOCKSWITCH_TIMEOUT_VALUE
)
671 else if(RCC_ClkInitStruct
->SYSCLKSource
== RCC_SYSCLKSOURCE_PLLCLK
)
673 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL
)
675 if((HAL_GetTick() - tickstart
) > CLOCKSWITCH_TIMEOUT_VALUE
)
683 while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI
)
685 if((HAL_GetTick() - tickstart
) > CLOCKSWITCH_TIMEOUT_VALUE
)
693 /* Decreasing the CPU frequency */
696 /*-------------------------- HCLK Configuration --------------------------*/
697 if(((RCC_ClkInitStruct
->ClockType
) & RCC_CLOCKTYPE_HCLK
) == RCC_CLOCKTYPE_HCLK
)
699 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct
->AHBCLKDivider
));
700 MODIFY_REG(RCC
->CFGR
, RCC_CFGR_HPRE
, RCC_ClkInitStruct
->AHBCLKDivider
);
703 /*------------------------- SYSCLK Configuration -------------------------*/
704 if(((RCC_ClkInitStruct
->ClockType
) & RCC_CLOCKTYPE_SYSCLK
) == RCC_CLOCKTYPE_SYSCLK
)
706 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct
->SYSCLKSource
));
708 /* HSE is selected as System Clock Source */
709 if(RCC_ClkInitStruct
->SYSCLKSource
== RCC_SYSCLKSOURCE_HSE
)
711 /* Check the HSE ready flag */
712 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY
) == RESET
)
717 /* PLL is selected as System Clock Source */
718 else if(RCC_ClkInitStruct
->SYSCLKSource
== RCC_SYSCLKSOURCE_PLLCLK
)
720 /* Check the PLL ready flag */
721 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY
) == RESET
)
726 /* HSI is selected as System Clock Source */
729 /* Check the HSI ready flag */
730 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY
) == RESET
)
735 MODIFY_REG(RCC
->CFGR
, RCC_CFGR_SW
, RCC_ClkInitStruct
->SYSCLKSource
);
738 tickstart
= HAL_GetTick();
740 if(RCC_ClkInitStruct
->SYSCLKSource
== RCC_SYSCLKSOURCE_HSE
)
742 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE
)
744 if((HAL_GetTick() - tickstart
) > CLOCKSWITCH_TIMEOUT_VALUE
)
750 else if(RCC_ClkInitStruct
->SYSCLKSource
== RCC_SYSCLKSOURCE_PLLCLK
)
752 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL
)
754 if((HAL_GetTick() - tickstart
) > CLOCKSWITCH_TIMEOUT_VALUE
)
762 while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI
)
764 if((HAL_GetTick() - tickstart
) > CLOCKSWITCH_TIMEOUT_VALUE
)
772 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
773 __HAL_FLASH_SET_LATENCY(FLatency
);
775 /* Check that the new number of wait states is taken into account to access the Flash
776 memory by reading the FLASH_ACR register */
777 if((FLASH
->ACR
& FLASH_ACR_LATENCY
) != FLatency
)
783 /*-------------------------- PCLK1 Configuration ---------------------------*/
784 if(((RCC_ClkInitStruct
->ClockType
) & RCC_CLOCKTYPE_PCLK1
) == RCC_CLOCKTYPE_PCLK1
)
786 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct
->APB1CLKDivider
));
787 MODIFY_REG(RCC
->CFGR
, RCC_CFGR_PPRE1
, RCC_ClkInitStruct
->APB1CLKDivider
);
790 /*-------------------------- PCLK2 Configuration ---------------------------*/
791 if(((RCC_ClkInitStruct
->ClockType
) & RCC_CLOCKTYPE_PCLK2
) == RCC_CLOCKTYPE_PCLK2
)
793 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct
->APB2CLKDivider
));
794 MODIFY_REG(RCC
->CFGR
, RCC_CFGR_PPRE2
, ((RCC_ClkInitStruct
->APB2CLKDivider
) << 3));
797 /* Configure the source of time base considering new system clocks settings*/
798 HAL_InitTick (TICK_INT_PRIORITY
);
807 /** @defgroup RCC_Group2 Peripheral Control functions
808 * @brief RCC clocks control functions
811 ===============================================================================
812 ##### Peripheral Control functions #####
813 ===============================================================================
815 This subsection provides a set of functions allowing to control the RCC Clocks
823 * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
824 * @note PA8/PC9 should be configured in alternate function mode.
825 * @param RCC_MCOx: specifies the output direction for the clock source.
826 * This parameter can be one of the following values:
827 * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
828 * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
829 * @param RCC_MCOSource: specifies the clock source to output.
830 * This parameter can be one of the following values:
831 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
832 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
833 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
834 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
835 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
836 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
837 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
838 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
839 * @param RCC_MCODiv: specifies the MCOx prescaler.
840 * This parameter can be one of the following values:
841 * @arg RCC_MCODIV_1: no division applied to MCOx clock
842 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
843 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
844 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
845 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
848 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx
, uint32_t RCC_MCOSource
, uint32_t RCC_MCODiv
)
850 GPIO_InitTypeDef GPIO_InitStruct
;
851 /* Check the parameters */
852 assert_param(IS_RCC_MCO(RCC_MCOx
));
853 assert_param(IS_RCC_MCODIV(RCC_MCODiv
));
855 if(RCC_MCOx
== RCC_MCO1
)
857 assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource
));
859 /* MCO1 Clock Enable */
862 /* Configue the MCO1 pin in alternate function mode */
863 GPIO_InitStruct
.Pin
= MCO1_PIN
;
864 GPIO_InitStruct
.Mode
= GPIO_MODE_AF_PP
;
865 GPIO_InitStruct
.Speed
= GPIO_SPEED_HIGH
;
866 GPIO_InitStruct
.Pull
= GPIO_NOPULL
;
867 GPIO_InitStruct
.Alternate
= GPIO_AF0_MCO
;
868 HAL_GPIO_Init(MCO1_GPIO_PORT
, &GPIO_InitStruct
);
870 /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
871 MODIFY_REG(RCC
->CFGR
, (RCC_CFGR_MCO1
| RCC_CFGR_MCO1PRE
), (RCC_MCOSource
| RCC_MCODiv
));
875 assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource
));
877 /* MCO2 Clock Enable */
880 /* Configue the MCO2 pin in alternate function mode */
881 GPIO_InitStruct
.Pin
= MCO2_PIN
;
882 GPIO_InitStruct
.Mode
= GPIO_MODE_AF_PP
;
883 GPIO_InitStruct
.Speed
= GPIO_SPEED_HIGH
;
884 GPIO_InitStruct
.Pull
= GPIO_NOPULL
;
885 GPIO_InitStruct
.Alternate
= GPIO_AF0_MCO
;
886 HAL_GPIO_Init(MCO2_GPIO_PORT
, &GPIO_InitStruct
);
888 /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
889 MODIFY_REG(RCC
->CFGR
, (RCC_CFGR_MCO2
| RCC_CFGR_MCO2PRE
), (RCC_MCOSource
| (RCC_MCODiv
<< 3)));
894 * @brief Enables the Clock Security System.
895 * @note If a failure is detected on the HSE oscillator clock, this oscillator
896 * is automatically disabled and an interrupt is generated to inform the
897 * software about the failure (Clock Security System Interrupt, CSSI),
898 * allowing the MCU to perform rescue operations. The CSSI is linked to
899 * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
903 void HAL_RCC_EnableCSS(void)
905 *(__IO
uint32_t *) CR_CSSON_BB
= (uint32_t)ENABLE
;
909 * @brief Disables the Clock Security System.
913 void HAL_RCC_DisableCSS(void)
915 *(__IO
uint32_t *) CR_CSSON_BB
= (uint32_t)DISABLE
;
919 * @brief Returns the SYSCLK frequency
921 * @note The system frequency computed by this function is not the real
922 * frequency in the chip. It is calculated based on the predefined
923 * constant and the selected clock source:
924 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
925 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
926 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
927 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
928 * @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
929 * 16 MHz) but the real value may vary depending on the variations
930 * in voltage and temperature.
931 * @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
932 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
933 * frequency of the crystal used. Otherwise, this function may
936 * @note The result of this function could be not correct when using fractional
937 * value for HSE crystal.
939 * @note This function can be used by the user application to compute the
940 * baudrate for the communication peripherals or configure other parameters.
942 * @note Each time SYSCLK changes, this function must be called to update the
943 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
947 * @retval SYSCLK frequency
949 uint32_t HAL_RCC_GetSysClockFreq(void)
951 uint32_t pllm
= 0, pllvco
= 0, pllp
= 0;
952 uint32_t sysclockfreq
= 0;
954 /* Get SYSCLK source -------------------------------------------------------*/
955 switch (RCC
->CFGR
& RCC_CFGR_SWS
)
957 case RCC_CFGR_SWS_HSI
: /* HSI used as system clock source */
959 sysclockfreq
= HSI_VALUE
;
962 case RCC_CFGR_SWS_HSE
: /* HSE used as system clock source */
964 sysclockfreq
= HSE_VALUE
;
967 case RCC_CFGR_SWS_PLL
: /* PLL used as system clock source */
969 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
970 SYSCLK = PLL_VCO / PLLP */
971 pllm
= RCC
->PLLCFGR
& RCC_PLLCFGR_PLLM
;
972 if (__RCC_PLLSRC() != 0)
974 /* HSE used as PLL clock source */
975 pllvco
= ((HSE_VALUE
/ pllm
) * ((RCC
->PLLCFGR
& RCC_PLLCFGR_PLLN
) >> POSITION_VAL(RCC_PLLCFGR_PLLN
)));
979 /* HSI used as PLL clock source */
980 pllvco
= ((HSI_VALUE
/ pllm
) * ((RCC
->PLLCFGR
& RCC_PLLCFGR_PLLN
) >> POSITION_VAL(RCC_PLLCFGR_PLLN
)));
982 pllp
= ((((RCC
->PLLCFGR
& RCC_PLLCFGR_PLLP
) >> POSITION_VAL(RCC_PLLCFGR_PLLP
)) + 1 ) *2);
984 sysclockfreq
= pllvco
/pllp
;
989 sysclockfreq
= HSI_VALUE
;
997 * @brief Returns the HCLK frequency
998 * @note Each time HCLK changes, this function must be called to update the
999 * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
1001 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
1002 * and updated within this function
1004 * @retval HCLK frequency
1006 uint32_t HAL_RCC_GetHCLKFreq(void)
1008 SystemCoreClock
= HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable
[(RCC
->CFGR
& RCC_CFGR_HPRE
)>> POSITION_VAL(RCC_CFGR_HPRE
)];
1009 return SystemCoreClock
;
1013 * @brief Returns the PCLK1 frequency
1014 * @note Each time PCLK1 changes, this function must be called to update the
1015 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
1017 * @retval PCLK1 frequency
1019 uint32_t HAL_RCC_GetPCLK1Freq(void)
1021 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
1022 return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable
[(RCC
->CFGR
& RCC_CFGR_PPRE1
)>> POSITION_VAL(RCC_CFGR_PPRE1
)]);
1026 * @brief Returns the PCLK2 frequency
1027 * @note Each time PCLK2 changes, this function must be called to update the
1028 * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
1030 * @retval PCLK2 frequency
1032 uint32_t HAL_RCC_GetPCLK2Freq(void)
1034 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
1035 return (HAL_RCC_GetHCLKFreq()>> APBAHBPrescTable
[(RCC
->CFGR
& RCC_CFGR_PPRE2
)>> POSITION_VAL(RCC_CFGR_PPRE2
)]);
1039 * @brief Configures the RCC_OscInitStruct according to the internal
1040 * RCC configuration registers.
1041 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
1042 * will be configured.
1045 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef
*RCC_OscInitStruct
)
1047 /* Set all possible values for the Oscillator type parameter ---------------*/
1048 RCC_OscInitStruct
->OscillatorType
= RCC_OSCILLATORTYPE_HSE
| RCC_OSCILLATORTYPE_HSI
| RCC_OSCILLATORTYPE_LSE
| RCC_OSCILLATORTYPE_LSI
;
1050 /* Get the HSE configuration -----------------------------------------------*/
1051 if((RCC
->CR
&RCC_CR_HSEBYP
) == RCC_CR_HSEBYP
)
1053 RCC_OscInitStruct
->HSEState
= RCC_HSE_BYPASS
;
1055 else if((RCC
->CR
&RCC_CR_HSEON
) == RCC_CR_HSEON
)
1057 RCC_OscInitStruct
->HSEState
= RCC_HSE_ON
;
1061 RCC_OscInitStruct
->HSEState
= RCC_HSE_OFF
;
1064 /* Get the HSI configuration -----------------------------------------------*/
1065 if((RCC
->CR
&RCC_CR_HSION
) == RCC_CR_HSION
)
1067 RCC_OscInitStruct
->HSIState
= RCC_HSI_ON
;
1071 RCC_OscInitStruct
->HSIState
= RCC_HSI_OFF
;
1074 RCC_OscInitStruct
->HSICalibrationValue
= (uint32_t)((RCC
->CR
&RCC_CR_HSITRIM
) >> POSITION_VAL(RCC_CR_HSITRIM
));
1076 /* Get the LSE configuration -----------------------------------------------*/
1077 if((RCC
->BDCR
&RCC_BDCR_LSEBYP
) == RCC_BDCR_LSEBYP
)
1079 RCC_OscInitStruct
->LSEState
= RCC_LSE_BYPASS
;
1081 else if((RCC
->BDCR
&RCC_BDCR_LSEON
) == RCC_BDCR_LSEON
)
1083 RCC_OscInitStruct
->LSEState
= RCC_LSE_ON
;
1087 RCC_OscInitStruct
->LSEState
= RCC_LSE_OFF
;
1090 /* Get the LSI configuration -----------------------------------------------*/
1091 if((RCC
->CSR
&RCC_CSR_LSION
) == RCC_CSR_LSION
)
1093 RCC_OscInitStruct
->LSIState
= RCC_LSI_ON
;
1097 RCC_OscInitStruct
->LSIState
= RCC_LSI_OFF
;
1100 /* Get the PLL configuration -----------------------------------------------*/
1101 if((RCC
->CR
&RCC_CR_PLLON
) == RCC_CR_PLLON
)
1103 RCC_OscInitStruct
->PLL
.PLLState
= RCC_PLL_ON
;
1107 RCC_OscInitStruct
->PLL
.PLLState
= RCC_PLL_OFF
;
1109 RCC_OscInitStruct
->PLL
.PLLSource
= (uint32_t)(RCC
->PLLCFGR
& RCC_PLLCFGR_PLLSRC
);
1110 RCC_OscInitStruct
->PLL
.PLLM
= (uint32_t)(RCC
->PLLCFGR
& RCC_PLLCFGR_PLLM
);
1111 RCC_OscInitStruct
->PLL
.PLLN
= (uint32_t)((RCC
->PLLCFGR
& RCC_PLLCFGR_PLLN
) >> POSITION_VAL(RCC_PLLCFGR_PLLN
));
1112 RCC_OscInitStruct
->PLL
.PLLP
= (uint32_t)((((RCC
->PLLCFGR
& RCC_PLLCFGR_PLLP
) + RCC_PLLCFGR_PLLP_0
) << 1) >> POSITION_VAL(RCC_PLLCFGR_PLLP
));
1113 RCC_OscInitStruct
->PLL
.PLLQ
= (uint32_t)((RCC
->PLLCFGR
& RCC_PLLCFGR_PLLQ
) >> POSITION_VAL(RCC_PLLCFGR_PLLQ
));
1117 * @brief Configures the RCC_ClkInitStruct according to the internal
1118 * RCC configuration registers.
1119 * @param RCC_OscInitStruct: pointer to an RCC_ClkInitTypeDef structure that
1120 * will be configured.
1121 * @param pFLatency: Pointer on the Flash Latency.
1124 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef
*RCC_ClkInitStruct
, uint32_t *pFLatency
)
1126 /* Set all possible values for the Clock type parameter --------------------*/
1127 RCC_ClkInitStruct
->ClockType
= RCC_CLOCKTYPE_SYSCLK
| RCC_CLOCKTYPE_HCLK
| RCC_CLOCKTYPE_PCLK1
| RCC_CLOCKTYPE_PCLK2
;
1129 /* Get the SYSCLK configuration --------------------------------------------*/
1130 RCC_ClkInitStruct
->SYSCLKSource
= (uint32_t)(RCC
->CFGR
& RCC_CFGR_SW
);
1132 /* Get the HCLK configuration ----------------------------------------------*/
1133 RCC_ClkInitStruct
->AHBCLKDivider
= (uint32_t)(RCC
->CFGR
& RCC_CFGR_HPRE
);
1135 /* Get the APB1 configuration ----------------------------------------------*/
1136 RCC_ClkInitStruct
->APB1CLKDivider
= (uint32_t)(RCC
->CFGR
& RCC_CFGR_PPRE1
);
1138 /* Get the APB2 configuration ----------------------------------------------*/
1139 RCC_ClkInitStruct
->APB2CLKDivider
= (uint32_t)((RCC
->CFGR
& RCC_CFGR_PPRE2
) >> 3);
1141 /* Get the Flash Wait State (Latency) configuration ------------------------*/
1142 *pFLatency
= (uint32_t)(FLASH
->ACR
& FLASH_ACR_LATENCY
);
1146 * @brief This function handles the RCC CSS interrupt request.
1147 * @note This API should be called under the NMI_Handler().
1151 void HAL_RCC_NMI_IRQHandler(void)
1153 /* Check RCC CSSF flag */
1154 if(__HAL_RCC_GET_IT(RCC_IT_CSS
))
1156 /* RCC Clock Security System interrupt user callback */
1157 HAL_RCC_CCSCallback();
1159 /* Clear RCC CSS pending bit */
1160 __HAL_RCC_CLEAR_IT(RCC_IT_CSS
);
1165 * @brief RCC Clock Security System interrupt callback
1169 __weak
void HAL_RCC_CCSCallback(void)
1171 /* NOTE : This function Should not be modified, when the callback is needed,
1172 the HAL_RCC_CCSCallback could be implemented in the user file
1184 #endif /* HAL_RCC_MODULE_ENABLED */
1193 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/